A double-sided alignment method for small die substrates

Abstract

The application discloses a double-face alignment method of small-substrate, and relates to the field of photoetching.The alignment method comprises the following steps: 1) drawing a plurality of coordinate system alignment marks on a wafer substrate and recording the marks in a set S; 2) continuing to draw a plurality of front-face cutting marks and recording the marks in a set T; 3) drawing a plurality of small-substrate front-face alignment marks on a small-substrate and recording the marks in a set P; 4) turning over the wafer substrate, re-reading the coordinate system alignment marks and recording the marks in a set X; 5) automatically adjusting a photoetching machine to eliminate the offset in the set X; 6) inputting the set T into the photoetching machine to draw a plurality of back-face cutting marks; and 7) inputting the set P into the photoetching machine to draw a plurality of small-substrate back-face alignment marks.After the above steps, the small-substrate front-face alignment marks and the small-substrate back-face marks are drawn at the same positions of the front face and the back face of the small-substrate, and the patterns are drawn at the same positions of the front face and the back face of the small-substrate.

Description

Technical Field

[0001] This invention relates to the field of photolithography, and in particular to a method for double-sided alignment of a small substrate. Background Technology

[0002] Micro-nano fabrication technology refers to the optimized design, processing, assembly, system integration, and application of components and systems at the sub-millimeter, micrometer, and nanometer scales. It is a crucial component of advanced manufacturing and a key indicator of a nation's high-end manufacturing level. Characterized by multidisciplinary collaboration and extreme manufacturing factors, it plays a vital role in driving technological progress, promoting industrial development, and safeguarding national defense. In laboratory-level microfabrication exploration, patterns need to be fabricated on both the front and back sides of the substrate, with high precision requirements (μm or even nm scale) for the relative positions of the patterns. This necessitates the use of double-sided alignment fabrication processes.

[0003] In the laboratory research and development stage, when the wafer substrate is made of very expensive materials such as silicon-on-insulator (SOI) or gallium arsenide (GaAs), to save costs, the wafer substrate is usually cut into small substrates with a size of 10mm*10mm or smaller. Currently, existing photolithography equipment can perform front-side patterning when the small substrate is facing up; however, when the small substrate is flipped to face down to process the back-side pattern, the small substrate will shift during the flipping process, so it is impossible to draw the pattern on the back side of the small substrate in the same position as when it was facing up.

[0004] Therefore, this application aims to develop a method that can achieve double-sided alignment of a small substrate, using commercially available lithography machines to eliminate the offset caused by flipping the small substrate, and to achieve pattern fabrication at the same position on both sides of the small substrate. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, the present invention provides a method for double-sided alignment of a small substrate. This alignment method allows for the alignment of the same positions on both the front and back sides of the small substrate. The method for double-sided alignment of a small substrate includes the following steps:

[0006] 1) Place the wafer substrate face up on the lithography machine stage, draw multiple coordinate system alignment marks on the front of the wafer substrate, and ensure that the positions of the coordinate system alignment marks do not overlap. The lithography machine records the coordinate positions of the coordinate system alignment marks in set S.

[0007] 2) Draw multiple front-side cutting marks on the front side of the wafer substrate; wherein, at least three front-side cutting marks form a closable region, the closable region being the small substrate to be cut, and record the coordinate position of each front-side cutting mark in set T;

[0008] 3) Draw multiple small substrate front alignment marks on the front side of each small substrate. The positions of the small substrate front alignment marks do not overlap, and record the coordinate positions of the small substrate front alignment marks in set P.

[0009] 4) Flip the wafer substrate so that the back side is facing up and place it on the lithography machine operating table. All coordinate system alignment marks are within the recognition range of the lithography machine's recognition window. The lithography machine reads the coordinate system alignment marks on the front side of the wafer substrate from below through the recognition window and records the coordinate positions of each coordinate system alignment mark in set X.

[0010] 5) The lithography machine performs automatic adjustments to eliminate coordinate offsets in set X caused by flipping the wafer substrate;

[0011] 6) Input the coordinate positions in set T sequentially into the lithography machine to draw multiple back-side cutting marks on the back of the wafer substrate that are the same as the positions of the front-side cutting marks;

[0012] 7) Input the coordinate positions in set P sequentially into the lithography machine to draw multiple small substrate back alignment marks on the back of each small substrate, which are in the same position as the front alignment marks of each small substrate.

[0013] In one specific embodiment, in step 1), when drawing the alignment marks 11 of each coordinate system, the position of each alignment mark 11 is within the range of the lithography machine recognition window.

[0014] In one specific embodiment, in step 1), adjacent front cutting marks 21 form front cutting lines 211.

[0015] In one specific embodiment, in step 3), a small substrate front marking 31 is drawn on the front side of each small substrate 3, and a small substrate front alignment marking 32 and a small substrate front marking 31 are drawn on the edge area of ​​the small substrate 3.

[0016] In one specific embodiment, in step 5), the lithography machine performs automatic adjustment by rotating the wafer substrate 1 or re-establishing the coordinate system to eliminate the coordinate offset in set X caused by flipping the wafer substrate.

[0017] This invention provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the following method for double-sided alignment of a small substrate:

[0018] S1) Establish a set S to record the coordinate positions of each coordinate system alignment mark on the front side of the wafer substrate, wherein the positions of each coordinate system alignment mark do not overlap.

[0019] Establish a set T to record the coordinate positions of each front-side cutting mark on the front side of the wafer substrate, wherein at least three front-side cutting marks form a closable region, and the closable region is a small substrate to be cut;

[0020] Establish a set P to record the coordinate positions of the alignment marks of each small substrate on the front side of the wafer substrate, wherein the positions of the alignment marks of each small substrate do not overlap.

[0021] S2) Establish a set X to record the coordinate positions of each coordinate system aligned with the marker on the front side of the wafer substrate after the wafer substrate is flipped.

[0022] S3) Compare the coordinate positions of set S and set X to see if there is a deviation. If at least one coordinate position is deviated, send an instruction to adjust the position of the wafer substrate or re-establish the lithography machine coordinate system so that set X = S. If there is no deviation in all coordinate positions, read the coordinate positions in set T and send an instruction to draw the back cut mark, and read the coordinate positions in set P and send an instruction to draw the back alignment mark of the small substrate.

[0023] The present invention provides an electronic terminal, characterized in that it includes: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the terminal performs the above-described method for double-sided alignment of a small substrate.

[0024] In one specific embodiment, a wafer substrate including double-sided alignment marks is prepared by the double-sided alignment method of the small substrate described in any of the above claims.

[0025] In one specific embodiment, at least one of the following technical features is included: 1) the size of the wafer substrate 1 is 2 to 8 inches; 2) the thickness of the wafer substrate 1 is 300 μm to 2 mm; 3) the shape of each coordinate system alignment mark, each front cutting mark 21, each small substrate front mark 31, each small substrate front alignment mark 32, each back cutting mark 41, each small substrate back mark 33, and each small substrate back alignment mark 34 is any one or more combinations of cross shape, circle, and square; 4) the material of the wafer substrate 1 is any one of silicon, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, gallium arsenide, lithium niobate, and metal; 5) the shape of the small substrate 3 is rectangular; 6) the size of the small substrate 3 is less than 25 mm * 25 mm.

[0026] In one specific embodiment, the process of creating the mark consists of two steps: first, photolithography; second, etching or metal stripping; wherein the depth of the etching material is 50–300 nm; and the thickness of the metal stripping is 50–200 nm.

[0027] Beneficial effects

[0028] 1) This invention eliminates the offset caused by flipping the wafer substrate by drawing coordinate system alignment marks on the front side of the wafer substrate. Simultaneously, front-side cutting marks are drawn on the wafer substrate to delineate the areas of small substrates, and front-side alignment marks are drawn on each small substrate. After eliminating the offset using coordinate system alignment marks, back-side alignment marks are drawn on the back side of the small substrate at the same position as the front side. Since the front-side and back-side alignment marks are in the same position, it achieves the ability to draw patterns at the same location on both the front and back sides of the small substrate.

[0029] 2) A front marking is drawn on the front side of the small substrate, and a back marking is drawn on the back side of the small substrate to distinguish the front and back sides of the small substrate. This allows subsequent drawing processes to identify the front and back sides of the small substrate by recognizing the markings, so that different patterns can be drawn on the front and back sides of the small substrate. Attached Figure Description

[0030] Figure 1 This is a schematic diagram showing the positional relationship between the lithography machine's operating stage, recognition window, and wafer substrate.

[0031] Figure 2 This is a schematic diagram showing the positional relationship between the lithography machine's operating stage, recognition window, and small substrate.

[0032] Figure 3 This diagram illustrates the positions of the coordinate system alignment mark, front cutting mark, front cutting line, small substrate front mark, and small substrate front alignment mark on the wafer substrate.

[0033] Figure 4 This diagram illustrates the positions of the small substrate back-side marking, small substrate back-side alignment marking, back-side cutting marking, and back-side cutting line on the wafer substrate.

[0034] Figure 5 The position marked on the front of the small substrate in sets X and S.

[0035] Figure 6 A step in the execution of a computer program.

[0036] Figure 7 A step in the execution of a computer program.

[0037] Figure 8This is a schematic diagram of the alignment terminal of the double-sided alignment method of the present invention applied to small substrates.

[0038] The attached diagram is labeled with wafer substrate 1 and coordinate system alignment mark 11.

[0039] Front cutting mark 21, front cutting line 211;

[0040] Small substrate 3, small substrate front side mark 31, small substrate front side alignment mark 32, small substrate back side mark 33, small substrate back side alignment mark 34;

[0041] Back cut mark 41, back cut line 411;

[0042] Photolithography machine operating table 51, recognition window 52;

[0043] The system includes a terminal 200, a processor 201, a memory 202, an operating system 2021, an application program 2022, a network interface 203, a user interface 204, and a bus system 205. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "left side", "right side", "upper side", "lower side", "above", "below", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0047] First, let me briefly explain the identification process of the lithography machine involved in this application: The lithography machine can identify the markings on the wafer substrate 1 placed on the lithography machine operating stage 51 from both top and bottom directions. The first identification method involves identifying the markings on the wafer substrate 1 from above the lithography machine, such as... Figure 1 As shown, when reading the mark from above the lithography machine stage 51, the reading range can cover the entire wafer substrate 1. The second identification method involves reading the mark from below the lithography machine stage 51, as shown... Figure 1 As shown, when reading a mark from below the lithography machine operating table 51, the mark can only be identified through the recognition window 52 opened below the lithography machine operating table 51. The size of the recognition window 52 is strictly limited by the lithography machine process. Therefore, when reading a mark from below the lithography machine operating table 51, as... Figure 1 As shown, the lithography machine can only read a portion of the wafer substrate 1 located on the recognition window 52. Furthermore, it should be noted that the number of recognition windows 52 is not necessarily as specified. Figure 1 As shown, there are usually two. The number of recognition windows 52 varies depending on the model of the lithography machine. There is no particular limit to the number. A single recognition window 52 or multiple recognition windows 52 are allowed.

[0048] In addition, in various embodiments of the present invention, in order to illustrate the double-sided alignment method of the present invention in detail and clearly, the specific coordinates of the important marks involved in the double-sided alignment process are given.

[0049] Example 1

[0050] This embodiment provides a method for double-sided alignment of a small substrate. Based on the identification process of the lithography machine described above, the specific steps of the double-sided alignment method for the wafer substrate and the small substrate are as follows:

[0051] 1) such as Figure 1 As shown, the wafer substrate 1 is placed face up on the lithography machine stage 51. Multiple coordinate system alignment marks 11 (multiple means at least two) are drawn on the face of the wafer substrate 1. The positions of each coordinate system alignment mark 11 do not overlap. The lithography machine records the coordinate positions of each coordinate system alignment mark 11 in a set S. It is worth noting that the lithography machine coordinate system is a built-in coordinate system within the lithography machine system, and the initial setting of the lithography machine coordinate system varies depending on the lithography machine model. In this invention, regardless of the initial setting of the lithography machine coordinate system, it does not affect the double-sided alignment method for the wafer substrate and the small substrate.

[0052] Furthermore, set S can contain any number of coordinate system alignment marks 11, and set S can be expressed as S = {S n ,n∈N *}, where n represents the number of coordinate system alignment marks 11, Sn This represents the coordinates of the nth coordinate system alignment mark 11. However, it should be noted that the meaning of "the positions of the alignment marks 11 of each coordinate system do not overlap" is that the coordinate positions of one coordinate system alignment mark 11 are not exactly the same as those of any other coordinate system alignment mark 11. For a detailed explanation of the specific explanation of the coordinate positions not being exactly the same, please refer to the specific embodiment below.

[0053] In one specific embodiment, a Cartesian coordinate system XOY is used. Two coordinate alignment marks 11 are drawn on the front side of the wafer substrate 1, named Mark_A and Mark_B respectively. The coordinate position of Mark_A in the lithography machine coordinate system is... The coordinate position of Mark_B in the lithography machine coordinate system is: It is important to emphasize that the coordinates of Mark_A and Mark_B cannot be exactly the same. Specifically, if but

[0054] In a preferred embodiment, when drawing each coordinate system alignment mark 11 on the front side of the wafer substrate 1, the position of each coordinate system alignment mark 11 falls within the recognition window 52, ​​so as to save the need to adjust each coordinate system alignment mark 11 to the recognition range of the recognition window 52 later.

[0055] Furthermore, as a supplementary explanation, the shape of the aforementioned coordinate system alignment mark 11 is not particularly limited, but is preferably cross-shaped, circular, square, etc. It is also worth noting that the thickness of the wafer substrate 1 used in this method is 300μm to 2mm, for example 300μm to 600μm, 600μm to 800μm, 800μm to 1mm, or 1mm to 2mm. The material of the wafer substrate 1 is silicon, silicon carbide, gallium arsenide, lithium niobate, or metal, etc., and the size of the wafer substrate 1 is 2 to 8 inches, for example 2 inches, 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, etc.

[0056] 2) such as Figure 3 As shown, multiple front-side dicing marks 21 are drawn on the front side of the wafer substrate 1. At least three front-side dicing marks 21 form a closable region, which is the small substrate 3 to be diced. The coordinate positions of each front-side dicing mark 21 are recorded in a set T. Furthermore, the set T can contain any number of front-side dicing marks 21, and the set T can be expressed as T = {T...} n ,n∈N *}, where n represents the number of front-side cutting marks 21, T n This represents the coordinates of the nth frontal cutting mark 21. However, it should be noted that the positions of each frontal cutting mark 21 do not overlap. The meaning of non-overlapping positions can be found in the relevant explanation of step S1), which will not be repeated here.

[0057] In a preferred embodiment, to enable researchers to more intuitively and clearly observe the specific extent and shape of each small substrate 3, front-side cutting marks 11 can be paired to form front-side cutting lines 211 as needed, such as... Figure 3 As shown, generally speaking, the front cutting line 211 is a straight line.

[0058] Taking a wafer substrate 1 with front-side dicing lines 211 drawn as an example, such as Figure 3 As shown, the closed area formed by the intersection of each front-side cutting line 211 on the front side of the wafer substrate 1 is the front side of each small substrate 3. Generally, when the wafer substrate 1 is cut into small substrates 3, the cutting is performed perpendicular to the wafer substrate 1. Therefore, the overall shape of the small substrate 3 is the shape of the front side of the small substrate 3 stretched in a direction perpendicular to the back side of the wafer substrate 1. Specifically, the shape of the front side of the small substrate 3 can be any polygon. Preferably, the shape of the front side of the small substrate 3 is a rectangle or a square.

[0059] In one specific embodiment, four front-side cutting marks 11 are drawn on the front side of the wafer substrate 1, namely FCut1, FCut2, FCut3 and FCut4, and the coordinates of the above four front-side cutting marks 11 in the lithography machine coordinate system are (x, y, y) respectively. cut1 ,y cut1 ), (x cut2 ,y cut2 ), (x cut3 ,y cut3 ) and (x cut4 ,y cut4 It should be emphasized that the positions of FCut1, FCut2, FCut3, and FCut4 do not overlap. The meaning of non-overlapping positions can be found in the relevant explanation of step S1), which will not be repeated here.

[0060] 3) Draw multiple small substrate front alignment marks 32 on the front side of each small substrate 3. The positions of each small substrate front alignment mark 32 do not overlap, and record the coordinate positions of each small substrate front alignment mark 32 in a set P. Furthermore, the set P can contain any number of small substrate front alignment marks 32, and the set P can be expressed as P = {P...} n ,n∈N *}, where n represents the number of small substrate front alignment marks 32, P n This represents the coordinates of the nth small substrate's front-side alignment with mark 32. However, it should be noted that the positions of the front-side alignment marks 32 of each small substrate do not overlap. The meaning of the non-overlapping positions can be found in the relevant explanation in step 1), which will not be repeated here.

[0061] In one specific embodiment, taking a small substrate 3 (hereinafter referred to as Sub_1) as an example, Sub_1 is provided with two small substrate front alignment marks 32, namely sMark A and sMark B sMark A The coordinate position in the lithography machine coordinate system is sMark B The coordinate position in the lithography machine coordinate system is It should be emphasized that the positions of sMark_A and sMark_B do not overlap. The meaning of non-overlapping positions can be found in the relevant explanation in step 1), and will not be repeated here.

[0062] In a preferred embodiment, a front-side marking 31 is drawn on the front side of each small substrate 3. This marking 31 identifies the front side of the small substrate 3. Specifically, during subsequent pattern drawing, it may be necessary to strictly distinguish between the front and back sides of the small substrate 3 and draw different shapes on each side. Since the size of the small substrate 3 after being cut from the wafer substrate 3 is generally less than 25mm*25mm, manually distinguishing the front and back sides is almost impossible. Therefore, this embodiment draws a front-side marking 31 on the front side of the small substrate 3 so that the lithography machine can read the front-side marking 31 to determine that the small substrate 3 is facing upwards. More preferably, a back-side marking 33 may be drawn on the back side of the small substrate 3. Furthermore, the front-side marking 31 and each small substrate front alignment mark 32 are preferably drawn at the edge of each small substrate 3 to prevent interference with the area where patterns need to be drawn.

[0063] 4) The wafer substrate 1 is flipped so that its back side faces upward and placed on the lithography machine stage 51, with all the coordinate system alignment marks 11 located within the recognition range of the recognition window 52. The lithography machine reads each of the coordinate system alignment marks 11 on the front side of the wafer substrate 1 from below through the recognition window 52, ​​and simultaneously records the coordinate positions of each coordinate system alignment mark 11 in set X. Furthermore, set X can contain any number of coordinate system alignment marks 11, and set X can be expressed as X = {X...} n ,n∈N * Where n represents the number of coordinate system alignment marks 11, X n This represents the coordinates of the nth coordinate system alignment mark 11. However, it should be noted that the positions of the alignment marks 11 in each coordinate system do not overlap. The meaning of non-overlapping positions can be found in the relevant explanation in step 1), which will not be repeated here.

[0064] To elaborate on the above explanation: In step 1), alignment marks 11 of each coordinate system are drawn, and the coordinate positions of each alignment mark 11 are recorded for the first time, with the coordinate positions recorded in set S; in step 4), the coordinate positions of each alignment mark 11 are recorded for the second time, with the coordinate positions recorded in set X. During the process of flipping the wafer substrate 1 from front-side up to back-side up, the position of the wafer substrate 1 on the lithography machine stage 51 will inevitably shift (or rotate, or displace). When the position of the wafer substrate 1 shifts, for the lithography machine coordinate system, as... Figure 5 As shown, the coordinate system alignment marks 11 on the wafer substrate 1 will also be offset. That is to say, although both set S and set X record coordinate system alignment marks 11, their coordinate positions are not the same, which requires calibration in step 5).

[0065] 5) The lithography machine performs automatic adjustments to eliminate the coordinate offset in set X caused by flipping the wafer substrate 1.

[0066] In one specific embodiment, when the wafer substrate 1 is flipped from the front side to the back side, the position of the wafer substrate 1 on the lithography machine stage 51 will shift to a certain extent. Furthermore, as... Figure 5 As shown, each mark will have a certain offset relative to the lithography machine coordinate system, and the amount of offset caused by the flipping of each mark may be different. Therefore, when the back side of the wafer substrate 1 is facing up, and the lithography machine recognizes the Mark_A and Mark_B marks from the recognition window 52, ​​the positions of the Mark_A and Mark_B marks in the current lithography machine coordinate system are respectively... and in, The offset generated by Mark_A on the x-axis of the lithography machine coordinate system when flipping wafer substrate 1. Mark_A represents the offset generated on the y-axis of the lithography machine coordinate system when flipping wafer substrate 1. and Similarly, the same logic applies, so I will not elaborate further.

[0067] When the lithography machine detects that the coordinate positions of Mark_A and Mark_B read in two separate readings are not exactly the same, it will automatically calibrate the coordinate positions of Mark_A and Mark_B. It's important to note that "not exactly the same coordinate positions" here refers to any difference between Mark_A and Mark_B. For example, if the coordinate position of Mark_A read from the lithography machine's recognition window 52 is unchanged compared to the position of Mark_A read from the front, but the coordinate position of Mark_B read from the lithography machine's recognition window 52 has changed compared to the position of Mark_B read from the front, then the lithography machine still needs to perform calibration.

[0068] Currently, there are two methods for coordinate calibration of lithography machines, as described below: 1) The lithography machine operating stage automatically performs rotation and movement operations, causing the wafer substrate 1 to rotate and move on the lithography machine operating stage, and reads the Mark_A and Mark_B coordinates from the back side. and Adjusted to and 2) The lithography machine automatically adjusts the position of the lithography machine coordinate system and establishes a new lithography machine coordinate system, so that the coordinate positions of Mark_A and Mark_B read from the back side are located relative to the new lithography machine coordinate system. and In this embodiment, for ease of explanation, the coordinates are calibrated using the first method.

[0069] 6) Input the coordinate positions in set T sequentially into the lithography machine to draw multiple back-side cutting marks 41 at the same positions as the front-side cutting marks 21 on the back side of the wafer substrate 1. Draw an equal number of back-side cutting marks 41 at the same positions as the front-side cutting marks 21 on the back side of the wafer substrate 1. Since multiple front-side cutting marks 21 were drawn and their positions were recorded in step 2), after the wafer substrate 1 is flipped from front-side up to back-side up and the coordinates are calibrated in step 4), inputting the coordinate positions of each front-side cutting mark 21 sequentially will draw an equal number of back-side cutting marks 41 at the same positions as the front-side cutting marks 21 on the back side of the wafer substrate 1.

[0070] In a preferred embodiment, the back-side cutting marks 41 can be selectively paired to form back-side cutting lines 411, as needed. Figure 4 As shown, generally speaking, the back cutting line 411 is a straight line.

[0071] It is worth noting that when actually dicing the wafer substrate 1, only the dicing marks on one side of the wafer substrate 1 need to be used. The specific method depends on the type of lithography machine. Some lithography machines can only diced from the front side, so the front dicing marks 11 are used; others can only diced from the back side, so the back dicing marks 41 are used. The drawing of the back dicing marks 41 improves the applicability of the double-sided alignment method of this invention to different types of lithography machines.

[0072] 7) Input the coordinate positions in set P sequentially into the lithography machine to draw multiple small substrate back-side alignment marks 34 on the back side of each small substrate 3, which are in the same position as the small substrate front-side alignment marks 32. In step 3), the coordinate positions of each small substrate front-side mark 31 and each small substrate front-side alignment mark 32 on each small substrate 3 are recorded in the lithography machine system. Therefore, by inputting the same coordinate positions as each small substrate front-side mark 31 and each small substrate front-side alignment mark 32, an equal number of small substrate back-side alignment marks 34 can be drawn at the same position as the front side of the small substrate 3.

[0073] It is worth noting that the wafer substrate 1 only needs to have coordinate system alignment marks 11 drawn on its front side, while the small substrate 3 needs to have small substrate front alignment marks 32 drawn on its front side and small substrate back alignment marks 34 drawn on its back side. This is because the size of the small substrate 3 is too small (generally less than 20mm*20mm, such as 15mm*15mm, 10mm*10mm or 5mm*5mm), and the current recognition window 52 is much larger than the size of the small substrate 3. Therefore, it is impossible to recognize the marks on the small substrate 3 from below the lithography machine stage 52. If multiple small substrate back alignment marks 34 are not drawn, after the small substrate 3 is flipped from the front-facing state to the back-facing state, the lithography machine cannot recognize the small substrate front alignment marks 32 of the small substrate 3 from below, and therefore cannot perform fabrication at the same position on the back side.

[0074] Specifically, in step 4), when the wafer substrate 1 is flipped from a front-facing state to a back-facing state, the position of the wafer substrate 1 in the lithography machine will be deviated, thus affecting the sMark read from the back side. A and sMark B The coordinates from the original and Change to and and The explanation is the same as the explanation in step 5), and will not be repeated here.

[0075] After the calibration process described in step 4), the sMark read from the back side A and sMarkB The resulting offset is corrected, thus making the sMark read from the back side... A and sMark B The position in the lithography machine coordinate system was recalibrated to... and At this time, wafer substrate 1 is in a back-side-up position, and sMark is input into the lithography machine. A and sMark B At the same coordinate position, it can be located on the back side of wafer substrate 1 and sMark A and sMark B Draw sMark at the same position A and sMark B .

[0076] The marking steps in the double-sided alignment method for small substrates described in this invention are divided into: first step, photolithography; second step, etching or metal stripping; wherein, the depth of the etching material is 50-300 nm; and the thickness of the metal stripping is 50-200 nm.

[0077] Example 2

[0078] This embodiment provides a computer-readable storage medium on which a computer program is stored, see reference. Figure 6 and Figure 7 When the computer program is executed by the processor, it implements the following method for double-sided alignment of a small substrate:

[0079] S1) Establish a set S to record the coordinate positions of each coordinate system alignment mark 11 on the front side of the wafer substrate 1, wherein the positions of each coordinate system alignment mark 11 do not overlap.

[0080] Establish a set T to record the coordinate positions of each front-side cutting mark 21 on the front side of the wafer substrate 1, wherein at least three front-side cutting marks 21 form a closable region, and the closable region is the small substrate 3 to be cut;

[0081] Establish a set P to record the coordinate positions of the front alignment marks 32 of each small substrate on the front side of the wafer substrate 1, wherein the positions of the front alignment marks 32 of each small substrate do not overlap.

[0082] S2) Establish set X to record the coordinate positions of each coordinate system aligned with marker 11 after the wafer substrate 1 is flipped;

[0083] S3) Compare the coordinate positions of set S and set X to see if there is a deviation. If at least one coordinate position is deviated, send an instruction to adjust the position of wafer substrate 1 or re-establish the lithography machine coordinate system so that set X = S. If there is no deviation in all coordinate positions, read the coordinate positions in set T and send an instruction to draw the back cut mark 41, and read the coordinate positions in set P and send an instruction to draw the back alignment mark 34 of the small substrate.

[0084] For instructions on adjusting the position of wafer substrate 1, please refer to [link / reference]. Figure 6 When set X ≠ S, a command is sent to adjust the position of wafer substrate 1; and the position of coordinate system alignment mark 11 is reread and re-recorded in set X. Subsequently, the condition is checked again until the condition of set X = S is met.

[0085] For instructions on how to re-establish the lithography machine coordinate system, please refer to [link / reference]. Figure 7 When set X ≠ S, a new lithography machine coordinate system is established; the coordinate position of set X in the new lithography machine coordinate system is recalculated, and the original coordinate position is overwritten. Subsequently, the condition is checked again until the condition X = S is met.

[0086] Example 3

[0087] This embodiment provides an electronic terminal, including a processor and a memory. The memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory, so that the terminal executes the double-sided alignment method of the small substrate in Embodiment 2.

[0088] See Figure 8 The diagram illustrates an optional hardware structure of terminal 200, which may be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. Terminal 200 includes: at least one processor 201, memory 202, at least one network interface 203, and user interface 204. The various components in the device are coupled together via a bus system 205. It is understood that the bus system 205 is used to implement communication between these components. In addition to a data bus, the bus system 205 also includes a power bus, a control bus, and a status signal bus.

[0089] The user interface 204 may include a display, keyboard, mouse, trackball, clicker, buttons, a touchpad, or a touchscreen. It is understood that the memory 202 may be volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in this embodiment are intended to include, but are not limited to, these and any other suitable categories of memory.

[0090] In this embodiment of the invention, the memory 202 is used to store various types of data for aligning the operation of the terminal 100. Examples of this data include: any executable program for operation on the bi-alignment method terminal 200, such as the operating system 2021 and application program 2022; the operating system 2021 includes various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 2022 may include various applications, such as a media player, browser, etc., for implementing various application services. The bi-alignment method for small substrates provided in this embodiment of the invention can be included in the application program 2022.

[0091] The methods disclosed in the above embodiments of the present invention can be applied to processor 201, or implemented by processor 201. Processor 201 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 201 or by instructions in software form. The processor 201 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 201 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 201 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0092] In an exemplary embodiment, the alignment terminal 200 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to perform the aforementioned method.

[0093] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A method for double-sided alignment of a small substrate, characterized in that, Includes the following steps: 1) Place the wafer substrate (1) face up on the lithography machine operating table, draw multiple coordinate system alignment marks (11) on the front of the wafer substrate (1), the positions of each coordinate system alignment mark (11) do not overlap, and the lithography machine records the coordinate positions of each coordinate system alignment mark (11) in set S. 2) Draw multiple front cutting marks (21) on the front side of the wafer substrate (1); wherein, at least three front cutting marks (21) form a closable region, the closable region being a small substrate (3) to be cut, and record the coordinate position of each front cutting mark (21) in set T; 3) Draw multiple small substrate front alignment marks (32) on the front side of each small substrate (3), the positions of each small substrate front alignment mark (32) do not overlap, and record the coordinate position of each small substrate front alignment mark (32) in set P; 4) Flip the wafer substrate (1) so that the back side faces up and place it on the lithography machine operating table, and all the coordinate system alignment marks (11) are within the recognition range of the lithography machine recognition window. The lithography machine reads the coordinate system alignment marks (11) on the front side of the wafer substrate (1) from below through the recognition window, and records the coordinate position of each coordinate system alignment mark (11) in set X at the same time. 5) The lithography machine performs automatic adjustments to eliminate the coordinate offset in set X caused by flipping the wafer substrate (1); 6) Input the coordinate positions in set T sequentially in the lithography machine to draw multiple back cut marks (41) on the back of the wafer substrate (1) with the same positions as the front cut marks (21); 7) Input the coordinate positions in set P sequentially in the lithography machine to draw multiple small substrate back alignment marks (34) on the back of each small substrate (3) with the same position as the front alignment marks (32) of each small substrate.

2. The method for double-sided alignment of a small substrate according to claim 1, characterized in that, In step 1), when drawing each of the coordinate system alignment marks (11), the position of each of the coordinate system alignment marks (11) is within the range of the lithography machine recognition window.

3. The method for double-sided alignment of a small substrate according to claim 1, characterized in that, In step 1): adjacent front cutting marks (21) form a front cutting line (211).

4. The method for double-sided alignment of a small substrate according to claim 1, characterized in that, In step 3): a small substrate front marking (31) is drawn on the front side of each small substrate (3), and the small substrate front alignment marking (32) and the small substrate front marking (31) are drawn on the edge area of ​​the small substrate (3).

5. The method for double-sided alignment of a small substrate according to claim 1, characterized in that, In step 5): The lithography machine performs automatic adjustment by rotating the wafer substrate (1) or re-establishing the coordinate system to eliminate the coordinate offset in set X caused by flipping the wafer substrate (1).

6. The method for double-sided alignment of a small substrate according to claim 1, characterized in that, The process of creating a marker involves two steps: The first step, photolithography; The second step is etching or metal stripping. The depth of the etching material is 50–300 nm; the thickness of the metal stripping is 50–200 nm.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the following method for double-sided alignment of a small substrate: S1) Establish a set S to record the coordinate positions of each coordinate system alignment mark (11) on the front side of the wafer substrate (1), and the positions of each coordinate system alignment mark (11) do not overlap. Establish a set T to record the coordinate positions of each front cutting mark (21) on the front side of the wafer substrate (1), wherein at least three front cutting marks (21) form a closable region, the closable region being a small substrate (3) to be cut; Establish a set P to record the coordinate positions of the front alignment marks (32) of each small substrate on the front side of the wafer substrate (1), wherein the positions of the front alignment marks (32) of each small substrate do not overlap. S2) Establish set X to record the coordinate positions of each coordinate system alignment mark (11) after the wafer substrate (1) is flipped; S3) Compare the coordinate positions of set S and set X to see if there is a deviation. If at least one coordinate position is deviated, send an instruction to adjust the position of the wafer substrate (1) or re-establish the lithography machine coordinate system so that set X = S. If there is no deviation of all coordinate positions, read the coordinate positions of set T and send an instruction to draw the back cut mark (41) and read the coordinate positions of set P and send an instruction to draw the back alignment mark (34) of the small substrate.

8. An electronic terminal, characterized in that, include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory to cause the terminal to perform the double-sided alignment method of the small substrate as described in claim 7.

9. A wafer substrate comprising double-sided alignment marks, prepared by the double-sided alignment method of a small substrate according to any one of claims 1 to 6.

10. The wafer substrate comprising double-sided alignment marks according to claim 9, characterized in that: Includes at least one of the following technical features: 1) The size of the wafer substrate (1) is 2 to 8 inches; 2) The thickness of the wafer substrate (1) is 300 μm to 2 mm; 3) The shape of each of the coordinate system alignment marks, the front cutting mark (21), the front mark (31) of the small substrate, the front alignment mark (32) of each of the small substrates, the back cutting mark (41), the back mark (33) of the small substrates, and the back alignment mark (34) of each of the small substrates is any one or more combinations of cross, circle, and square; 4) The material of the wafer substrate (1) is any one of silicon, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, gallium arsenide, lithium niobate, and metal; 5) The small substrate (3) is rectangular in shape; 6) The size of the small substrate (3) is less than (25) mm * (25) mm.

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