An industrial control chip

Abstract

The application discloses an industrial control chip, which is applied to the chip manufacturing field. In the chip, the chip assembly is hung on a high-speed bus matrix; the first end of a first slave logic interface is hung on the high-speed bus matrix through a special high-speed bus, and the second end of the first slave logic interface is connected with an optoelectronic conversion interface; the first end of a universal asynchronous receiver-transmitter is hung on the high-speed bus matrix through a low-speed bus, and the second end of the universal asynchronous receiver-transmitter is connected with the optoelectronic conversion interface; the optoelectronic conversion interface is hung on the high-speed bus matrix through the special high-speed bus and is connected with external chip pins. The first slave logic interface and the universal asynchronous receiver-transmitter are redundant to each other in the application, which increases the guarantee for the signal transmission process. Meanwhile, the first slave logic interface is an interface integrated with specific demand circuits, protocols and the like, and meets the demand for optoelectronic conversion in different scenes, and the chip structure is simple.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing, and in particular to an industrial control chip. Background Technology

[0002] In recent years, industrial chips have become a fundamental part of the entire industrial system architecture, solving basic and execution problems such as sensing, interconnection, computing, and storage, and playing a vital role in industrial production. While the industrial chips sold on the market are often diverse, based on market demands, industrially produced chips are often standardized products with basic functions. Standardized products can achieve basic functions, but in some companies or specific scenarios, they are often not the optimal solution to meet various product requirements. In some scenarios, it is necessary to convert light energy into electrical energy for human use, but this requires connecting external hardware circuits to the industrial chip. The more complex the requirements, the more cumbersome the hardware circuit connections become. Therefore, industrial chip research and development needs to be closely integrated with application, and development should be tailored to specific application scenarios.

[0003] Given the aforementioned technologies, finding an industrial control chip is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide an industrial control chip to solve the problem that the development of industrial chips in the above-mentioned technologies cannot be closely integrated with applications.

[0005] To address the aforementioned technical problems, this application provides an industrial control chip, including a chip assembly, a first slave logic interface, a universal asynchronous transceiver, and a photoelectric conversion interface; The chip components are connected to a high-speed bus matrix; The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the universal asynchronous transceiver is connected to a high-speed bus matrix via a low-speed bus, and the second end of the universal asynchronous transceiver is connected to an optoelectronic conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus and is connected to the pins of an external chip.

[0006] Preferably, the photoelectric conversion interface includes: a universal asynchronous transceiver interface processing logic device, a selector, and a signal encoder; The first end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the high-speed bus matrix via a dedicated high-speed bus; the second end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the second end of the Universal Asynchronous Receiver / Transmitter. The first end of the selector is connected to the second end of the first slave logic interface, and the second end of the selector is connected to the third end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device. The first end of the signal encoder is connected to the third end of the selector, and the second end of the signal encoder is connected to the pin of an external chip.

[0007] Preferably, it also includes a first controller pin switch; The first terminal of the first controller pin switch is connected to the second terminal of the first slave logic interface via wireless technology; the second terminal of the first controller pin switch is connected to the first terminal of the selector via wireless technology; and the third terminal of the first controller pin switch is connected to the pin of an external chip. The second logic interface can be selectively connected to the first terminal of the selector or to the pins of an external chip via the first controller pin switch.

[0008] Preferably, it also includes a second controller pin switch; The first terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver, the second terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver interface processing logic device, and the third terminal of the second controller pin switch is connected to the pin of an external chip. The Universal Asynchronous Receiver / Transmitter (UART) can be selectively connected to the second terminal of the UART interface processing logic device or to the pins of an external chip via a second controller pin switch.

[0009] Preferably, the universal asynchronous transceiver includes at least a first universal asynchronous transceiver and a second universal asynchronous transceiver.

[0010] Preferably, the chip assembly includes a central processing unit, memory, communication equipment, functional devices, slow peripherals, and industrial communication interfaces; The central processing unit and memory are connected to a high-speed bus matrix; The communication equipment is connected to the high-speed bus matrix via the first high-speed bus; Functional devices are connected to the high-speed bus matrix via a second high-speed bus; Slow-speed peripherals are connected to the high-speed bus matrix sequentially via a low-speed bus and a third high-speed bus. The industrial communication interface is connected to a high-speed bus matrix via a dedicated high-speed bus.

[0011] Preferably, the slow peripheral includes: The first group of slow peripherals includes at least three components. The first group of slow peripherals is connected to the high-speed bus matrix in sequence through the first low-speed bus and the third high-speed bus. The second group of slow peripherals includes at least three components, which are connected to the high-speed bus matrix in sequence via a second low-speed bus and a third high-speed bus.

[0012] Preferably, The first group of slow peripherals includes at least three of the following: chip communication interface, analog-to-digital converter, watchdog device, DWA configuration device, pin multiplexing configuration device, and first standard timer; The second group of slow peripherals includes at least three of the following: a universal asynchronous transmitter, a bus device, a serial peripheral interface, a second standard timer, a third standard timer, and a fourth standard timer.

[0013] Preferably, the industrial communication interface includes: A first communication interface with 100 Mbps link layer functionality, wherein the first communication interface is connected to a high-speed bus matrix via a first dedicated high-speed bus; At least one second communication interface, wherein the second communication interface, the first slave logic interface, and the photoelectric conversion interface are connected to a high-speed bus matrix via a second dedicated high-speed bus.

[0014] Preferably, the first communication interface is a second slave logic interface, and the second communication interface is an LED control interface, a link switching interface, an independent watchdog interface, a module redundancy switching interface, a signal processing interface, or a frequency measurement and counting interface.

[0015] This application provides an industrial control chip, comprising a chip assembly, a first slave logic interface, a universal asynchronous transceiver (UAST), and a photoelectric conversion interface. The chip assembly is connected to a high-speed bus matrix. The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the UAST is connected to the high-speed bus matrix via a low-speed bus, and the second end of the UAST is connected to the photoelectric conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus and is connected to the pins of an external chip. The first slave logic interface and the UAST in this industrial control chip are redundant, providing added protection during the photoelectric conversion transmission process. Furthermore, the first slave logic interface integrates specific circuits and protocols, meeting the photoelectric conversion needs of different scenarios and companies, without requiring external circuitry, resulting in a simple chip structure. Attached Figure Description

[0016] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an industrial control chip provided in an embodiment of this application; Figure 2 A schematic diagram of the photoelectric conversion interface provided in an embodiment of this application; Figure 3 A detailed schematic diagram of the industrial control chip provided in the embodiments of this application; Figure 4 This is a structural diagram of the chip assembly provided in an embodiment of this application; Figure 5 This is a detailed architecture diagram of the industrial control chip provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0019] The core of this application is to provide an industrial control chip.

[0020] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] To address the aforementioned technical problems, this application provides an industrial control chip, including a chip assembly, a first slave logic interface, a universal asynchronous transceiver, and a photoelectric conversion interface; The chip components are connected to a high-speed bus matrix; The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the universal asynchronous transceiver is connected to a high-speed bus matrix via a low-speed bus, and the second end of the universal asynchronous transceiver is connected to an optoelectronic conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus and is connected to the pins of an external chip.

[0022] In specific embodiments, such as Figure 1As shown, the chip assembly includes 1, a first slave logic interface 2, a universal asynchronous transceiver 3, an optoelectronic conversion interface 4, and chip pins 6. Chip assembly 1 is connected to a high-speed bus matrix to implement the specific functions of its internal structure. The first end of the first slave logic interface 2 is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface 2 is connected to the optoelectronic conversion interface 4 via wireless technology, serving as a signal transmission channel to transmit signals from the optoelectronic conversion interface 4 to chip assembly 1, or vice versa. The first end of the universal asynchronous transceiver 3 is connected to the high-speed bus matrix via a low-speed bus, and the second end of the universal asynchronous transceiver 3 is connected to the optoelectronic conversion interface 4 via wireless technology, also serving as a signal transmission channel to transmit signals from the optoelectronic conversion interface 4 to chip assembly 1, or vice versa. The optoelectronic conversion interface 4 is also connected to external chip pins 6, used to transmit signals to external chip pins 6, or receive signals sent by external chip pins 6.

[0023] The first logic interface 2 is an interface for integrating circuits, protocols, etc., with no limitation on its internal structure in this application. The Universal Asynchronous Receiver / Transmitter (UART) is part of the computer hardware used to convert data transmission between serial and parallel communication.

[0024] In this application, the first slave logic interface 2 and the universal asynchronous transceiver 3 serve as transmission channels in the photoelectric conversion process, and the two are redundant. When the initial signal sent by the chip component 1 needs to be photoelectric converted, the photoelectric conversion interface 4 can receive data transmitted wirelessly by the first slave logic interface 2 and perform photoelectric conversion, or it can receive data transmitted by the universal asynchronous transceiver 3 and perform photoelectric conversion, and then send the signal to the external chip pin 6. Similarly, when the signal from the external chip pin 6 needs to be transmitted to the chip component 1, it can be transmitted through the first slave logic interface 2 or the universal asynchronous transceiver 3, adding protection to the photoelectric conversion transmission process.

[0025] The photoelectric conversion interface 4 implements the photoelectric conversion function, but the specific devices within the photoelectric conversion interface 4 are not limited in this application and can be set according to the user's needs.

[0026] Meanwhile, as a preferred option, the high-speed bus adopts AHB (Advanced High performance Bus), and the low-speed bus adopts APB (Advanced Peripheral Bus). Chip 1 uses a 32-bit Cortex-M3 core central processing unit, where the M3 core frequency supports 96MHz.

[0027] This application provides an industrial control chip, comprising a chip assembly, a first slave logic interface, a universal asynchronous transceiver (UAST), and a photoelectric conversion interface. The chip assembly is connected to a high-speed bus matrix. The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the UAST is connected to the high-speed bus matrix via a low-speed bus, and the second end of the UAST is connected to the photoelectric conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus and is connected to the pins of an external chip. The first slave logic interface and the UAST in this industrial control chip are redundant, providing added protection during the photoelectric conversion transmission process. Furthermore, the first slave logic interface integrates specific circuits and protocols, meeting the photoelectric conversion needs of different scenarios and companies, without requiring external circuitry, resulting in a simple chip structure.

[0028] Based on the above embodiments, as a preferred embodiment, the photoelectric conversion interface includes: a universal asynchronous transceiver interface processing logic device, a selector, and a signal encoder; The first end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the high-speed bus matrix via a dedicated high-speed bus; the second end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the second end of the Universal Asynchronous Receiver / Transmitter. The first end of the selector is connected to the second end of the first slave logic interface, and the second end of the selector is connected to the third end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device. The first end of the signal encoder is connected to the third end of the selector, and the second end of the signal encoder is connected to the pin of an external chip.

[0029] In a specific embodiment, as a preferred option, such as Figure 2As shown, the photoelectric conversion interface 4 includes: a universal asynchronous transceiver interface processing logic device 7, a selector 8, and a signal encoder 9. The first end of the universal asynchronous transceiver interface processing logic device 7 is connected to a high-speed bus matrix via a dedicated high-speed bus; the second end of the universal asynchronous transceiver interface processing logic device 7 is connected to the second end of the universal asynchronous transceiver 3; the first end of the selector 8 is connected to the second end of the first slave logic interface 2, and the second end of the selector 8 is connected to the third end of the universal asynchronous transceiver interface processing logic device 7; the first end of the signal encoder 9 is connected to the third end of the selector 8, and the second end of the signal encoder 9 is connected to pin 6 of an external chip. The universal asynchronous transceiver interface processing logic device 7 is used to perform preliminary processing on the received or transmitted signals for transmission to the selector 8 or to the slave logic interface 2 and the universal asynchronous transceiver 3. In practical applications, the first slave logic interface 2 and the universal asynchronous transceiver 3 are a redundant pair of devices; therefore, a 2-to-1 selector is needed to select the signal so that the signal encoder 9 can select the corresponding signal for photoelectric conversion.

[0030] It should be noted that when the initial signal sent by chip component 1 is transmitted to external chip pin 6 through the first slave logic interface 2 and the universal asynchronous transceiver 3, it is equivalent to two signals. The selector 8 selects one signal from the first slave logic interface 2 and the universal asynchronous transceiver 3 for photoelectric conversion. When a signal needs to be transmitted from external chip pin 6 to chip component 1, it is also two signals, but these two signals are selected in the selector 8. Only one signal will be sent to the first slave logic interface 2 or the universal asynchronous transceiver 3, and they will not be sent simultaneously.

[0031] Since the signal transmission during the photoelectric conversion process is bidirectional, when the chip component needs to send a signal to the external chip pin 6, the signal reaches the first end of the first slave logic interface 2 (at this time, the first end of the first slave logic interface 2 is the input) via a dedicated high-speed bus. Simultaneously, the signal reaches the first end of the universal asynchronous transceiver 3 (at this time, the first end of the universal asynchronous transceiver 3 is the input) via a low-speed bus. The second end of the first slave logic interface 2 (at this time, the second end of the first slave logic interface 2 is the output) then transmits the signal wirelessly to the first end of the selector 8 (at this time, the first end of the selector 8 is the first input). Simultaneously, the second end of the universal asynchronous transceiver 3 (at this time, the second end of the universal asynchronous transceiver 3 is the output) transmits the signal wirelessly to the second end of the universal asynchronous transceiver interface processing logic device 7 (at this time, the universal asynchronous...). The second end of the transceiver interface processing logic device 7 is the input end, and the signal is transmitted to the second end of the selector 8 (the second end of the selector 8 is the second input end) through the third end of the universal asynchronous transceiver interface processing logic device 7 (at this time, the third end of the universal asynchronous transceiver interface processing logic device 7 is the output end). Finally, the selector 8 selects the signal transmitted from the first logic interface 2 and the signal transmitted from the universal asynchronous transceiver 3, selects one signal, and transmits it to the first end of the signal encoder 9 (the first end of the signal encoder 9 is the input end) through the third end of the selector 8 (at this time, the third end of the selector 8 is the output end), so that the signal encoder 9 performs photoelectric conversion processing on the signal sent by the selector 8, and sends it to the external chip pin 6 through the second end of the signal encoder 9 (the second end of the signal encoder 9 is the output end).

[0032] Therefore, when a signal from external chip pin 6 needs to be sent to chip assembly 1, the second end of signal encoder 9 (which is the input end at this time) first receives the signal from external chip pin 6, and sends the signal to the third end of selector 8 (which is the input end at this time) through the first end of signal encoder 9 (which is the output end at this time). At this time, selector 8 has two selection methods: First, the first end of selector 8 (which is the first output end at this time) sends the signal wirelessly to the second end of the first slave logic interface 2 (which is the input end at this time), and then the first end of the first slave logic interface 2 (which is the output end at this time) sends the signal via a dedicated high-speed bus. The signal is transmitted to chip assembly 1; or: the second terminal of the select controller 8 (which is the second output terminal) sends the signal to the third terminal of the universal asynchronous transceiver interface processing logic device 7 (which is the input terminal), and then wirelessly transmits the signal to the second terminal of universal asynchronous transceiver 3 (which is the input terminal) through the second terminal of universal asynchronous transceiver interface processing logic device 7 (which is the output terminal). Finally, the signal is transmitted to chip assembly 1 through a low-speed bus via the first terminal of universal asynchronous transceiver 3 (which is the output terminal).

[0033] It should be noted that the device included in the photoelectric conversion interface 4 in this application is only one possible implementation method, but is not limited to this one implementation method. Users can configure it according to their needs. Furthermore, as a preferred option, the selector is a 2-to-1 selector, but this application is not limited to this; it can also be a 3-to-1 selector or a 4-to-1 selector, etc.

[0034] This application provides a specific implementation of a photoelectric conversion interface. The received signal undergoes preliminary processing via a universal asynchronous transceiver interface processing logic device. A selector then selects which signal path will be photoelectric converted. Finally, a signal encoder performs the photoelectric conversion. The overall structure is simple, and it is a dual-path photoelectric conversion interface.

[0035] Based on the above embodiments, as a preferred real-time method, a first controller pin switch is also included; The first terminal of the first controller pin switch is connected to the second terminal of the first slave logic interface via wireless technology; the second terminal of the first controller pin switch is connected to the first terminal of the selector via wireless technology; and the third terminal of the first controller pin switch is connected to the pin of an external chip. The second logic interface can be selectively connected to the first terminal of the selector or to the pins of an external chip via the first controller pin switch.

[0036] It also includes the second controller pin switch; The first terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver, the second terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver interface processing logic device, and the third terminal of the second controller pin switch is connected to the pin of an external chip. The Universal Asynchronous Receiver / Transmitter (UART) can be selectively connected to the second terminal of the UART interface processing logic device or to the pins of an external chip via a second controller pin switch.

[0037] As a preferred embodiment, the universal asynchronous transceiver includes at least a first universal asynchronous transceiver and a second universal asynchronous transceiver.

[0038] In specific embodiments, such as Figure 3 As shown, the chip assembly includes 1, a first slave logic interface 2, an external chip pin 6, a universal asynchronous transceiver interface processing logic device 7, a selector 8, a signal encoder 9, a first universal asynchronous transceiver 10, a second universal asynchronous transceiver 11, a first controller pin switch 12, and a second controller pin switch 13.

[0039] When the industrial control chip includes a first controller pin switch 12, the first controller pin switch 12 is located between the first slave logic interface 2 and the selector 8, both using wireless technology. Specifically, the first end of the first controller pin switch 12 is wirelessly connected to the second end of the first slave logic interface 2, the second end of the first controller pin switch 12 is wirelessly connected to the first end of the selector 8, and the third end of the first controller pin switch 12 is connected to the external chip pin 6. The function of the first controller pin switch 12 is to selectively connect to either the first end of the selector 8 or the external chip pin 6. In other words, the signal emitted by the chip component 1 can be selectively converted to photoelectric signals. When the signal emitted by the chip component 1 needs to reach the external chip pin 6, and the entire process does not require photoelectric conversion, the signal transmission channel is: chip component 1 - first slave logic interface 2 - first controller pin switch 12 - external chip pin 6. In this case, the first end of the first controller pin switch 12 is the input end, the second end is the first output end, and the third end is the second output end. Similarly, when the signal sent by the external chip pin 6 needs to reach the chip component 1, and the whole process does not require photoelectric conversion, the signal transmission channel is: external chip pin 6 - first controller pin switch 12 - first slave logic interface 2 - chip component 1. At this time, the third end of the first controller pin switch 12 is the input end, the second end of the first controller pin switch 12 is the first input end, and the first end of the first controller pin switch 12 is the second input end.

[0040] When the industrial control chip includes a second controller pin switch 13, the first terminal of the second controller pin switch 13 is connected to the second terminal of the universal asynchronous transceiver 3, the second terminal of the second controller pin switch 13 is connected to the second terminal of the universal asynchronous transceiver interface processing logic device 7, and the third terminal of the second controller pin switch 13 is connected to the external chip pin 6. The universal asynchronous transceiver 3 (the first universal asynchronous transceiver 10 and the second universal asynchronous transceiver 11) can be selectively connected to the second terminal of the universal asynchronous transceiver interface processing logic device 7 or to the external chip pin 6 via the second controller pin switch 13. In other words, the signal emitted by the chip component 1 can be selectively converted into photoelectric signals. The signal emitted by chip component 1 needs to reach the external chip pin 6, and the whole process does not require photoelectric conversion. At this time, the signal transmission channel is: chip component 1 - universal asynchronous transceiver 3 (first universal asynchronous transceiver 10 and second universal asynchronous transceiver 11) - second controller pin switch 13 - external chip pin 6. At this time, the first end of the second controller pin switch 13 is the input end, the second end of the second controller pin switch 13 is the first output end, and the third end of the second controller pin switch 13 is the second output end.

[0041] Among them, the universal asynchronous transceiver 3 includes a first universal asynchronous transceiver 10 and a second universal asynchronous transceiver 11, which are also a redundant device used to ensure signal transmission.

[0042] As can be seen from the above embodiments, the first slave logic interface in this application supports a preset slave protocol, implements a 100Mbps slave link layer function, and the interface connected to the chip component is a dedicated AHB bus. The chip component accesses the registers and interface RAM inside the first slave logic interface through the dedicated AHB bus to complete data reception and transmission, supporting bus redundancy communication. The photoelectric conversion interface provided in this application supports dual-channel optical interfaces, which can support optical signal encoding and decoding (photoelectric signal mutual conversion). Through a selector (2-to-1), it can be used in conjunction with a preset slave protocol or with the chip and the universal asynchronous transceiver interface processing logic device, ultimately adapting to the preset slave protocol or running on the chip's general protocol stack for optical transmission applications. Among them, the AHB high-speed bus and the universal asynchronous transceiver interface processing logic device realize the mutual transmission of control signals, the first controller pin switch and the selector realize the transmission of dual-channel transmit and receive signals, the universal asynchronous transceiver interface processing logic device and the selector realize the transmission of dual-channel transmit and receive signals, and the selector and the signal encoder realize the transmission of data stream. The chip component configures the photoelectric conversion interface by setting the following registers, and the specific implementation of its functions is shown in Table 2.

[0043] Table 2

[0044] This application provides an industrial control chip, comprising a chip assembly, a first slave logic interface, a universal asynchronous transceiver (UAST), and a photoelectric conversion interface. The chip assembly is connected to a high-speed bus matrix. The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the UAST is connected to the high-speed bus matrix via a low-speed bus, and the second end of the UAST is connected to the photoelectric conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus. The first slave logic interface and the UAST in this industrial control chip are redundant, adding protection during the photoelectric conversion transmission process. Furthermore, the first slave logic interface integrates specific circuits and protocols, meeting the photoelectric conversion needs of different scenarios and companies, without requiring external circuitry, resulting in a simple surrounding structure.

[0045] Based on the above embodiments, as a preferred embodiment, the chip assembly includes a central processing unit, a memory, a communication device, a functional device, a slow peripheral device, and an industrial communication interface; The central processing unit and memory are connected to a high-speed bus matrix; The communication equipment is connected to the high-speed bus matrix via the first high-speed bus; Functional devices are connected to the high-speed bus matrix via a second high-speed bus; Slow-speed peripherals are connected to the high-speed bus matrix sequentially via a low-speed bus and a third high-speed bus. The industrial communication interface is connected to a high-speed bus matrix via a dedicated high-speed bus.

[0046] In specific embodiments, such as Figure 4 As shown, the chip assembly includes a central processing unit 21, a memory 22, a communication device 23, a functional device 24, a slow peripheral device 25, and an industrial communication interface 26. The central processing unit 21 and the memory 22 are connected to a high-speed bus matrix; the communication device 23 is connected to the high-speed bus matrix via a first high-speed bus; the functional device 24 is connected to the high-speed bus matrix via a second high-speed bus; the slow peripheral device is connected to the high-speed bus matrix sequentially via a low-speed bus and a third high-speed bus; and the industrial communication interface 26 is connected to the high-speed bus matrix via a dedicated high-speed bus.

[0047] As a preferred option, the high-speed bus uses AHB (Advanced High performance Bus), and the low-speed bus uses APB (Advanced Peripheral Bus).

[0048] Furthermore, in this application, the slow peripheral 25 is connected to the high-speed bus matrix through a low-speed bus and a third high-speed bus, which reduces the burden on the high-speed bus and also meets the common functional requirements of the chip.

[0049] As a preferred embodiment, the central processing unit 21 adopts a 32-bit Cortex-M3 core central processing unit, wherein the M3 core frequency supports 96MHz and supports MPU (Menory Protection Unit) to improve chip performance; the memory 22 includes SRAM (Static Random-Access Memory), FLASH (Encoded Flash Memory) and DMA (Direct Memory Access), wherein the FLASH uses 2MB Byte FLASH, which supports OTP (One-time Password); the SRAM uses 256K Byte SRAM, which supports ECC (Error Correcting Code).

[0050] Communication device 23 includes EBI (Extension Bus) and QSPI (Quad SPI, 6-wire SPI interface). The EBI is 8 / 16 bit and expandable to external storage (SRAM, NOR_FLASH, etc.). QSPI implements master-slave mode, and the clock frequency supports up to 32MHz during chip operation. Functional device 4 includes: SYSCFG (System Configuration), CMU (Clock Management Unit), GPIO (General Purpose Input Output, Port Expander), RMU (Reset Manager), MSC (Memory Management Unit), CRC (Security and Acceleration Unit), and CALC (Arithmetic Accelerator). The chip operates at a voltage range of 3V-5V. It features Power-On Reset (POR), Undervoltage Reset (BOR), and the RMU for power monitoring. The chip uses an external high-speed crystal oscillator (24MHz) and an internal low-speed RC oscillator to implement the CMU. It should also be noted that the CMU uses a PLL (Phase Locked Loop). The phase-locked loop (PLL) can be multiplied up to 96MHz; it has up to 169 general-purpose I / Os; CRC supports CRC-CCITT, CRC-8, CRC-16, CRC-32 polynomials and square roots; CALC supports firmware encryption and is traceable to prevent theft.

[0051] Slow peripherals 25 include IIC (In-Chips Interface), ADC (Analog-to-Digital Converter), WDT (Watchdog Timer), UART (Universal Asynchronous Receiver / Transmitter), CAN (CAN bus), and SPI (Serial Peripheral Interface). Interface (serial peripheral interface), timers, pin multiplexing configuration device, DMA configuration device, among which the DMA configuration device supports 12 multiplexed channels; WDT includes independent watchdog timer IWDT and window watchdog timer WWDT, ADC uses 1MSPS, 8 external analog channels, its internal switch can be switched to acquire internal power supply voltage and chip temperature; timers use 2 16-bit advanced timers: supporting 4 input capture and output compare channels, supporting 3 dead-time programmable PWM complementary output channels, supporting braking function; 2 16-bit general-purpose timers: supporting 4 independent input capture and output compare channels; 2 32-bit general-purpose timers: supporting 4 independent input capture and output compare channels; also includes 2 basic timers, IIC uses 2 IIC interfaces, supports multi-master mode and bus arbitration, supports 16-level deep FIFO; SPI uses 5 SPI interfaces, master-slave mode, supports 16-level deep FIFO; UART uses 6 UARTs: with 16-level deep FIFO, supports 12Mbps; CAN uses 2 CAN, supports CAN2.0B, supports 1Mbps.

[0052] It should be noted that the specific internal structure and chip selection of the central processing unit 21, memory 22, communication device 23, functional device 24, and slow peripheral 25 provided in this application embodiment are only a preferred embodiment, but are not limited to this implementation method. Users can set them themselves according to their needs.

[0053] It should also be noted that the industrial communication interface 26 is an interface for integrating the circuits corresponding to the other functions required by the chip in a specific scenario. By connecting the industrial communication interface 26 to the high-speed bus matrix, the chip can realize the function of the industrial chip interface 26, so that no external hard-wired circuit is required in the scenario in which the chip is used.

[0054] However, it should be noted that the required functions of the chip may vary slightly depending on the scenario. Therefore, this application does not limit the specific type of the industrial communication interface 26, including the type of interface and the type of function to be implemented. Users can set it themselves according to their needs.

[0055] The chip assembly provided in this application includes a central processing unit (CPU), a memory, a communication device, functional devices, and slow peripherals, as well as an industrial communication interface. The CPU and memory are connected to a high-speed bus matrix. The communication device is connected to the high-speed bus matrix via a first high-speed bus. The functional devices are connected to the high-speed bus matrix via a second high-speed bus. The slow peripherals are connected to the high-speed bus matrix sequentially via a low-speed bus and a third high-speed bus. The industrial communication interface is connected to the high-speed bus matrix via a dedicated high-speed bus. The industrial communication interface in this application is an interface integrating hardware circuits corresponding to specific functions, meeting the needs of different scenarios and requiring no external hardware circuits. Therefore, based on the above structure of the chip assembly, the industrial control chip provided in this application is a highly functional, reliable, simple peripheral circuit, professional, and versatile industrial control chip.

[0056] Based on the above embodiments, as a preferred embodiment, the slow peripheral includes: The first group of slow peripherals includes at least three components. The first group of slow peripherals is connected to the high-speed bus matrix in sequence through the first low-speed bus and the third high-speed bus. The second group of slow peripherals comprises at least three components, which are sequentially connected to the high-speed bus matrix via a second low-speed bus and a third high-speed bus. In a specific embodiment, since there are many slow peripheral devices 25 during chip fabrication, they are divided into two groups, which are respectively connected to the high-speed bus matrix via a first low-speed bus, a second low-speed bus, and a third high-speed bus. Both the first group and the second group of slow peripherals include at least three components. The purpose of this is to ensure that the chip can perform some of the most basic functions, but it is not limited to including at least three components; it can also include at least two components.

[0057] As a preferred embodiment, the first group of slow peripherals includes: IIC (chip communication interface), ADC (analog-to-digital converter), WDT (watchdog device), DMA configuration device, pin multiplexing configuration device, and two basic 16-bit timers (first standard timers) among the timers. The second group of slow peripherals includes: UART (universal asynchronous transceiver), CAN (bus device), SPI (serial peripheral interface), and two advanced 16-bit timers (second standard timers), two general-purpose 16-bit timers (third standard timers), and two general-purpose 32-bit timers (fourth standard timers).

[0058] It should be noted that this application is only one possible method, but it is not limited to this method. Users can set their own methods according to their needs.

[0059] This application divides slow peripherals into two groups, reducing the burden on one group of low-speed buses and improving the performance of chip components.

[0060] Based on the above embodiments, as a preferred embodiment, the industrial communication interface includes: a first communication interface with a 100 Mbps link layer function, wherein the first communication interface is connected to a high-speed bus matrix via a first dedicated high-speed bus; and at least one second communication interface, wherein the second communication interface, the first slave logic interface, and the photoelectric conversion interface are connected to the high-speed bus matrix via a second dedicated high-speed bus.

[0061] Accordingly, as a preferred option, and in summary of the above embodiments, such as Figure 5 As shown, the first communication interface is the second slave logic interface. The second communication interface includes an LED control interface, a link switching interface, an independent watchdog interface, a module redundancy switching interface, a signal processing interface, or a frequency measurement and counting interface. The second slave logic interface can implement 100Mbps slave link layer functions and has high bandwidth requirements for interaction with M3. Therefore, it communicates with M3 via a dedicated high-speed bus connected to the high-speed bus matrix. The remaining industrial communication interfaces communicate with M3 via the dedicated high-speed bus connected to the high-speed bus matrix.

[0062] It should also be noted that the industrial communication interface 26 provided in this application embodiment is only one possible method, but it is not limited to this method. Users can choose the type of industrial communication interface according to their needs.

[0063] This application provides an industrial control chip, comprising a chip assembly, a first slave logic interface, a universal asynchronous transceiver (UAST), and a photoelectric conversion interface. The chip assembly is connected to a high-speed bus matrix. The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface via wireless technology. The first end of the UAST is connected to the high-speed bus matrix via a low-speed bus, and the second end of the UAST is connected to the photoelectric conversion interface via wireless technology. The photoelectric conversion interface is connected to the high-speed bus matrix via a dedicated high-speed bus and is connected to the pins of an external chip. The first slave logic interface and the UAST in this industrial control chip are redundant, adding protection during the photoelectric conversion transmission process. Furthermore, the first slave logic interface is an integrated interface for specific circuit requirements and protocols, meeting the photoelectric conversion needs of different scenarios and companies, without requiring external circuitry, resulting in a simple surrounding structure. Meanwhile, the chip assembly, including a central processing unit, memory, communication equipment, functional devices, and slow peripherals, also includes an industrial communication interface. The central processing unit and memory are connected to a high-speed bus matrix; the communication equipment is connected to the high-speed bus matrix via a first high-speed bus; the functional devices are connected to the high-speed bus matrix via a second high-speed bus; the slow peripherals are connected to the high-speed bus matrix sequentially via a low-speed bus and a third high-speed bus; and the industrial communication interface is connected to the high-speed bus matrix via a dedicated high-speed bus. Its industrial communication interface is an interface integrating hardware circuits corresponding to specific functions, meeting the needs of different scenarios and requiring no external hardware circuits. Therefore, based on the above structure of the chip assembly, the industrial control chip provided in this application is an industrial control chip with rich overall functions, high reliability, simple peripheral circuits, professional features, and a certain degree of versatility.

[0064] The industrial control chip provided in this application has been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0065] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. An industrial control chip, characterized in that, Includes chip components, a first slave logic interface, a universal asynchronous transceiver, and an optoelectronic conversion interface; The chip assembly is connected to a high-speed bus matrix; The first end of the first slave logic interface is connected to the high-speed bus matrix via a dedicated high-speed bus, and the second end of the first slave logic interface is connected to the photoelectric conversion interface. The first end of the universal asynchronous transceiver is connected to the high-speed bus matrix via a low-speed bus, and the second end of the universal asynchronous transceiver is connected to the photoelectric conversion interface. The photoelectric conversion interface is connected to the high-speed bus matrix via the dedicated high-speed bus and is connected to the pins of an external chip. The photoelectric conversion interface includes: a universal asynchronous transceiver interface processing logic device, a selector, and a signal encoder; The first end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the High-Speed ​​Bus Matrix via the Dedicated High-Speed ​​Bus; the second end of the Universal Asynchronous Receiver / Transmitter Interface Processing Logic Device is connected to the second end of the Universal Asynchronous Receiver / Transmitter. The first end of the selector is connected to the second end of the first slave logic interface, and the second end of the selector is connected to the third end of the universal asynchronous transceiver interface processing logic device. The first end of the signal encoder is connected to the third end of the selector, and the second end of the signal encoder is connected to the pin of the external chip. It also includes the first controller pin switch; The first terminal of the first controller pin switch is connected to the second terminal of the first slave logic interface, the second terminal of the first controller pin switch is connected to the first terminal of the selector, and the third terminal of the first controller pin switch is connected to the pin of the external chip. The second logic interface can be selectively connected to the first terminal of the selector or to the pin of the external chip via the first controller pin switch.

2. The industrial control chip according to claim 1, characterized in that, It also includes the second controller pin switch; The first terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver, the second terminal of the second controller pin switch is connected to the second terminal of the universal asynchronous transceiver interface processing logic device, and the third terminal of the second controller pin switch is connected to the pin of the external chip. The universal asynchronous transceiver can be selectively connected to the second terminal of the universal asynchronous transceiver interface processing logic device or to the pin of the external chip via the second controller pin switch.

3. The industrial control chip according to claim 2, characterized in that, The general asynchronous transceiver includes at least a first general asynchronous transceiver and a second general asynchronous transceiver.

4. The industrial control chip according to any one of claims 1 to 3, characterized in that, The chip assembly includes a central processing unit, memory, communication equipment, functional devices, slow peripherals, and industrial communication interfaces. The central processing unit and the memory are connected to a high-speed bus matrix; The communication device is connected to the high-speed bus matrix via a first high-speed bus; The functional device is connected to the high-speed bus matrix via a second high-speed bus; The slow peripheral is connected to the high-speed bus matrix in sequence via a low-speed bus and a third high-speed bus. The industrial communication interface is connected to the high-speed bus matrix via the dedicated high-speed bus.

5. The industrial control chip according to claim 4, characterized in that, The slow peripherals include: The first group of slow peripherals includes at least three components, and the first group of slow peripherals is connected to the high-speed bus matrix in sequence through a first low-speed bus and the third high-speed bus. The second group of slow peripherals includes at least three components, and the second group of slow peripherals is connected to the high-speed bus matrix in sequence through the second low-speed bus and the third high-speed bus.

6. The industrial control chip according to claim 5, characterized in that, The first group of slow peripherals includes at least three of the following: a chip communication interface, an analog-to-digital converter, a watchdog device, a DWA configuration device, a pin multiplexing configuration device, and a first standard timer. The second group of slow peripherals includes at least three of the following: a universal asynchronous transceiver, a bus device, a serial peripheral interface, a second standard timer, a third standard timer, and a fourth standard timer.

7. The industrial control chip according to claim 4, characterized in that, The industrial communication interface includes: A first communication interface with 100 Mbps link layer functionality, wherein the first communication interface is connected to the high-speed bus matrix via a first dedicated high-speed bus; At least one second communication interface, wherein the second communication interface, the first slave logic interface and the photoelectric conversion interface are connected to the high-speed bus matrix via a second dedicated high-speed bus.

8. The industrial control chip according to claim 7, characterized in that, The first communication interface is a second slave logic interface, which can be an LED control interface, a link switching interface, an independent watchdog interface, a module redundancy switching interface, a signal processing interface, or a frequency measurement and counting interface.

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