A vector processor based on multi-core and resource reuse

Abstract

The application provides a vector processor based on multi-core and resource multiplexing, comprising one processing core M and one to multiple processing cores S, which can execute scalar instructions simultaneously. The processing core M is used for decoding vector instructions, dispatching the vector instructions to the processing cores S for execution, and tracking the execution status of the dispatched vector instructions. The processing cores S receive the vector instructions dispatched by the core M and execute the instructions on a part of vector registers on the basis of multiplexing the existing calculation logic. The application also provides a method for executing vector instructions based on the above vector processor. On the basis of multiplexing the existing execution units in the multi-core processor architecture, the application realizes efficient execution of vector instructions by additionally adding a group of vector registers and a small amount of control logic related to vector instructions, while ensuring low hardware overhead.

Description

Technical Field

[0001] This invention relates to the field of data processing, and in particular to a vector processor that achieves low hardware overhead by reusing resources on the basis of a multi-core processor. Background Technology

[0002] In recent years, with the rapid development of mobile internet and IoT technologies, the scale of data that terminal devices can acquire and collect has gradually increased. This growth in data volume has posed challenges to the real-time performance and availability of the previously mainstream cloud computing model. Edge computing, by providing intelligent services on terminal devices closer to the data source, effectively addresses issues that cloud computing models struggle to resolve, such as cloud center load, data transmission, and user privacy protection, in the era of big data processing. Therefore, with the rise of edge computing, the shift of data processing from the cloud to terminal devices is an inevitable trend. The computing demands of terminal devices are increasing accordingly, requiring them to provide more computing power within limited hardware resources.

[0003] On the other hand, modern processors have begun to introduce vector operation instructions to further accelerate computation. Vector operation instructions are those that instruct the processor to perform operations on vectors, including vector addition, subtraction, and inner product operations. These instructions, by sharing hardware control logic, develop data-level parallelism capabilities, achieving high data throughput computing power. This characteristic makes vector operation instructions a promising area for application in edge computing.

[0004] Currently, edge computing devices on the market typically achieve a certain degree of task-level parallelism through multi-core processors, but few devices incorporate vector computing capabilities into the processor. This is because implementing vector computing instructions requires significant hardware overhead, placing a heavy cost burden on chip design and manufacturing. Based on this, this invention proposes a vector processor that achieves low hardware overhead by utilizing resource reuse on top of a multi-core processor. Summary of the Invention

[0005] This invention provides a vector processor with low hardware overhead based on a multi-core processor and through resource reuse, in order to solve the problem that existing processors are limited by large hardware overhead and cannot introduce vector processing instructions to accelerate computation in edge computing scenarios.

[0006] In a first aspect, the present invention provides a processing core M, which is used to decode vector instructions and track their execution state, and can also execute scalar instructions. The processing core includes: a memory, an instruction decoding unit, an instruction execution unit, a vector instruction tracking unit, and a register unit.

[0007] The memory is used to store the data and instructions involved in the calculation;

[0008] The instruction decoding unit is used to retrieve scalar instructions or vector instructions from memory, and decode the operations to be performed and the corresponding parameters from the instructions; the scalar instructions and vector instructions are relative, representing instructions that perform operations on a single piece of data;

[0009] The instruction execution unit is used to obtain the data to be operated on from the register unit according to the instruction decoded by the instruction decoding unit, perform the operation on scalar instructions and store the operation result in the register unit, and dispatch the operation to the vector instruction tracking unit for execution on vector instructions.

[0010] The vector instruction tracking unit is used to dispatch vector instructions to the processing core S described in the second aspect, and track the instruction execution status to ensure that the vector instructions are successfully executed by all processing cores S.

[0011] The register unit is used to store data that participates in the execution of scalar instructions.

[0012] In a second aspect, the present invention provides a processing core S, which is used to perform operations according to the vector instructions decoded by the processing core M described in the first aspect above. At the same time, the processing core can also execute scalar instructions. The processing core includes: a memory, a scalar instruction decoding unit, an instruction selection unit, an instruction execution unit, a scalar register unit, and a vector register unit.

[0013] The memory is used to store the data involved in the calculation and scalar instructions;

[0014] The scalar instruction decoding unit is used to retrieve scalar instructions from memory, and decode the operations to be performed and the corresponding parameters from the instructions.

[0015] The instruction selection unit is used to select the instruction to be executed from the decoded scalar instruction and the vector instruction dispatched by the vector instruction tracking unit in the processing core M described in the first aspect above.

[0016] The instruction execution unit is used to obtain data for computation from a scalar register unit or a vector register unit according to the instruction selected by the instruction selection unit, perform computation, and store the computation result in the scalar register unit or the vector register unit.

[0017] The scalar register unit is used to store data that participates in the execution of scalar instructions;

[0018] The vector register unit is used to store data involved in the execution of vector instructions. The vector register unit and the scalar register unit reuse the same set of bypass logic when acquiring data.

[0019] Thirdly, the present invention provides a vector processor comprising a processing core M as described in the first aspect above, and one or more processing cores S as described in the second aspect above.

[0020] Fourthly, the present invention provides a method for executing vector instructions, based on the vector processor described in the third aspect above, comprising:

[0021] The processing core M described in the first aspect above retrieves the vector instruction I from memory and decodes it;

[0022] The instruction execution unit of the core M dispatches the decoded vector instruction I to the vector instruction tracing unit;

[0023] The vector instruction tracking unit dispatches the decoded vector instruction I to all the processing cores S1 to Sn described in the second aspect above.

[0024] Each instruction selection unit of the processing core S1 to Sn selects the decoded vector instruction I and begins execution;

[0025] The processing core M described in the first aspect above confirms that all processing cores S1 to Sn described in the second aspect above have started executing vector instruction I, and the vector instruction execution status tracking unit starts tracking the execution status of vector instruction I of S1 to Sn;

[0026] The processing cores S1 to Sn described in the second aspect above execute vector instruction I respectively, obtain the data required for the operation from the vector register, and perform the operation;

[0027] The processing core M described in the first aspect above confirms that all processing cores S1 to Sn described in the second aspect above have completed the execution of vector instruction I, and submits the execution status of vector instruction I. The purpose of this is to mark the instruction as successfully executed.

[0028] As can be seen, the vector processor provided by this invention can reduce most of the hardware overhead by adding an extra set of vector registers and a small amount of vector instruction-related control logic, based on the reuse of the existing instruction execution units in the multi-core processor architecture. Attached Figure Description

[0029] The following description will detail some specific embodiments of the invention by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art will understand that these drawings are not necessarily drawn to scale. The objectives and features of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 The present invention provides a schematic diagram of the structure of a vector processor, which includes a processing core M and two processing cores S, labeled S1 and S2 respectively.

[0031] Figure 2 This is a schematic diagram of the structure of the scalar register unit and the vector register unit in the processing core S provided by the present invention.

[0032] Figure 3 This is a schematic diagram of the composition structure of the vector register in a vector processor provided by the present invention.

[0033] Figure 4 A flowchart of a method for executing vector instructions provided by the present invention. Detailed Implementation

[0034] To make the key points of this invention more apparent and understandable, the invention will be further described below with reference to the accompanying drawings and examples. Many details and specific examples are set forth in the following description. These examples are provided to enable a more thorough understanding of the invention and to fully and vividly convey its contents to those skilled in the art. Although the invention can be implemented in many other ways different from those described herein, those skilled in the art can make corresponding extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific examples and drawings disclosed below.

[0035] While the present invention has been described with reference to specific illustrative embodiments, it is not limited to these embodiments but only to the appended claims. Those skilled in the art will understand that modifications and alterations can be made to the embodiments of the invention without departing from the scope and spirit of the invention.

[0036] Modern processors typically consist of an instruction decoding unit, an instruction execution unit, register units, and memory. The instruction decoding unit fetches the instructions from memory and decodes them. The instruction execution unit retrieves the data to be executed from registers based on the decoded instructions, performs the computation, and stores the result in register units. Register units temporarily store the data and results used in the computation. Memory stores the instructions and data used in the computation. To provide some task-level parallelism, current edge computing devices often implement multi-core processors, meaning that by introducing multiple independent processing cores into the processor, multiple task loads can be run simultaneously. However, due to circuit resource limitations, processors designed for edge computing scenarios typically do not implement vector instruction processing.

[0037] This invention provides a vector processor based on multi-core and resource reuse. By introducing a set of vector registers and a small amount of control logic into the existing multi-core processor architecture, and reusing existing components, it solves the problem that existing processors are limited by large circuit overhead and cannot introduce vector processing instructions to accelerate computation in edge computing scenarios.

[0038] like Figure 1 The diagram shown is a schematic representation of the structure of a vector processor provided by the present invention. Figure 1 It includes a processing core M and two processing cores S, named S1 and S2 respectively.

[0039] The processing core M includes:

[0040] The instruction decoding unit is used to retrieve scalar instructions or vector instructions from memory, and decode the operations to be performed and the corresponding parameters from the instructions; the scalar instructions and vector instructions are relative to each other and represent instructions that perform operations on a single piece of data;

[0041] The instruction execution unit is used to obtain the data to be operated on from the register unit according to the instruction decoded by the instruction decoder unit. For scalar instructions, it performs the operation and stores the result in the register unit. For vector instructions, it dispatches the operation to the vector instruction tracing unit for execution.

[0042] The vector instruction tracking unit is used to dispatch vector instructions to the processing core S and track the execution status of the instructions to ensure that the vector instructions are successfully executed by all processing cores S.

[0043] The register unit is used to store data that participates in the execution of scalar instructions.

[0044] The processing core S includes:

[0045] The instruction decoding unit is used to retrieve scalar instructions from memory, decode the operations to be performed and the corresponding parameters from the instructions;

[0046] The instruction selection unit is used to select the instruction to be executed next from the decoded scalar instructions and the vector instructions dispatched by the vector instruction tracing unit of the processing core M.

[0047] The instruction execution unit is used to obtain the data to be operated on from the scalar register unit or the vector register unit according to the instruction selected by the instruction selection unit, perform the operation, and store the operation result in the scalar register unit or the vector register unit.

[0048] The scalar register unit is used to store data that participates in the execution of scalar instructions;

[0049] The vector register unit is used to store data involved in the execution of vector instructions. The vector register unit has the same length as a single register in the scalar register unit.

[0050] It should be noted that, in Figure 1 In this vector processor, there are two processing cores S. This application does not impose a specific limit on the number of processing cores S, which can be set by those skilled in the art based on actual processing core requirements, data processing needs, and hardware overhead. The more processing cores S there are, the more elements a single vector instruction can process, ultimately improving data processing efficiency.

[0051] Based on the embodiments described above, to reduce the hardware overhead caused by the register bypass network, the scalar register unit and the vector register unit can be merged and share the register index number. In this case, the vector register unit will share the bypass network of the scalar register unit. For example, in... Figure 2 In the architecture shown, the vector processor provides 32 scalar registers x0 to x31 and 32 vector registers v0 to v31. The scalar registers are 64 bits long, and the vector registers are 128 bits long. At this time, there are 64 registers x0 to x63 in the processing core S, where x0 to x31 are used as scalar registers, and x32 to x63 are used as part of the vector registers. Specifically, as... Figure 3 As shown, registers x32 to x63 of processing core S1 are used as the lower 64 bits of vector registers v0 to v31, and registers x32 to x63 of processing core S2 are used as the higher 64 bits of vector registers v0 to v31.

[0052] For example, such as Figure 4The diagram shows a flowchart of a method for executing vector instructions provided by the present invention. The specific instruction executed is `vadd.vi v3,v2,32`, where the element length is pre-set to 8 bits. Specifically, this means that each element in register v2 is incremented by 32 every 8 bits, and the result is saved to register v3. Those skilled in the art should understand that the execution flow of other vector instructions is similar. Figure 4 The flowcharts are similar, differing only in the types of operations performed and the length of the operands. For example... Figure 4 As shown, the method includes:

[0053] To process core M, the following steps are involved:

[0054] Step S101: Retrieve vector instructions from memory and decode them;

[0055] In step S102, the vector instruction enters the instruction execution unit and is ready to begin execution;

[0056] In step S103, the vector instruction is dispatched to the processing core S by the vector instruction tracking unit, and waits for all processing cores S to select the vector instruction and start execution.

[0057] Step S104: Wait for all processing cores S to finish executing;

[0058] Step S105: Submit instruction. At this time, the processor's external status will show that the vector instruction has been executed.

[0059] For the secondary processor, the following steps are involved:

[0060] Step S201: Obtain the data to be used in the operation from the vector register unit;

[0061] Step S202: Perform the calculation. In this example, the actual operation is to add 32 to each element.

[0062] Step S203: Write the calculation result into the destination register, and at the same time notify the processing core M that the vector instruction has been executed on the processing core S.

Claims

1. A vector processor based on multi-core and resource multiplexing, used to provide a set of vector registers and perform operations on this set of vector registers, characterized in that, include: A processing core M is used to decode vector instructions, dispatch vector instructions to processing core S for execution, and track the execution status of dispatched vector instructions; the processing core M can also execute regular scalar instructions. One or more processing cores S are used to receive vector instructions dispatched by processing core M and execute the instructions on a portion of a vector register; the processing core S can also execute regular scalar instructions. A vector instruction tracking unit is used to dispatch vector instructions to processing core S and track the execution status of all dispatched vector instructions on processing core S. An instruction selection unit is used to select the instruction to be executed next from scalar instructions obtained locally from processing core S and vector instructions dispatched by processing core M. A vector register unit is used to store a portion of the contents of the vector registers provided by the vector processor; An instruction execution unit is configured to execute vector instructions that target a portion of the data stored in the vector register unit that falls within the processing core S; the instruction execution unit may also execute regular scalar instructions. To process core M, the following steps are involved: Step S101: Retrieve vector instructions from memory and decode them; In step S102, the vector instruction enters the instruction execution unit and is ready to begin execution; In step S103, the vector instruction is dispatched to the processing core S by the vector instruction tracking unit, and waits for all processing cores S to select the vector instruction and start execution. Step S104: Wait for all processing cores S to finish executing; Step S105: Submit the instruction. At this time, the vector processor displays the status of the vector instruction as having been executed. To process core S, the following steps are involved: Step S201: Obtain the data to be used in the operation from the vector register unit; Step S202: Perform the operation on each element of the vector; Step S203: Write the calculation result into the destination vector register unit, and at the same time notify the processing core M that the vector instruction has been executed on this processing core S. By merging the scalar register unit and the vector register unit and sharing the register index number, the vector register unit will share the bypass network of the scalar register unit.

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