A USB data decoding circuit, method, chip and system

Abstract

The application discloses a USB data decoding circuit, method, chip and system, and relates to the technical field of USB data decoding, in particular to a USB data decoding circuit, which comprises a high-low speed switching receiving module, a speed selector, a reverse non-return-to-zero decoder, a bit elimination module, a shift register and a static random access memory; wherein, the input port of the high-low speed switching receiving module is used as the input port of the USB data decoding circuit, the output port of the high-low speed switching receiving module is connected with the input port of the speed selector, the input end of the reverse non-return-to-zero decoder is connected with the output port of the speed selector, the output port of the reverse non-return-to-zero decoder is connected with the input port of the bit elimination module, the output port of the bit elimination module is connected with the input port of the shift register, and the output port of the shift register is connected with the input port of the static random access memory. The application realizes the technical effect that high-speed USB protocol data packets can be decoded without increasing the clock frequency, reduces the circuit cost and the difficulty of circuit design.

Description

Technical Field

[0001] This invention relates to the field of USB data decoding, and specifically to a USB data decoding circuit, method, chip, and system. Background Technology

[0002] Currently, the USB protocol is the most commonly used communication protocol and is widely used in various fields. With the development of technology, the requirements for the communication speed of the USB protocol are getting higher and higher. Based on Shannon's sampling theorem, in order to recover the analog signal without distortion, the sampling frequency should be no less than twice the highest frequency in the analog signal spectrum. When the communication speed requirement of the USB protocol is higher, the sampling frequency also needs to be increased accordingly to recover the analog signal without distortion. This high-speed sampling frequency has an impact on the chip and receiving device and increases the design cost. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a USB data decoding circuit, method, chip, and system. By designing a USB data decoding circuit, it completes the decoding of USB protocol data packets. Based on the high-low speed switching receiver module within the USB data decoding circuit, it achieves high-speed USB protocol data packet decoding without increasing the clock frequency, thus reducing circuit cost and design complexity. The specific technical solution of this invention is as follows: A USB data decoding circuit includes: a high-low speed switching receiving module, a speed selector, a non-return-to-zero decoder, a bit rejection module, a shift register, and a static random access memory (SRAM); wherein, the input port of the high-low speed switching receiving module serves as the input port of the USB data decoding circuit, the output port of the high-low speed switching receiving module is connected to the input port of the speed selector, the input of the non-return-to-zero decoder is connected to the output port of the speed selector, the output port of the non-return-to-zero decoder is connected to the input port of the bit rejection module, the output port of the bit rejection module is connected to the input port of the shift register, and the output port of the shift register is connected to the input port of the SRAM.

[0004] Furthermore, the high-speed / low-speed switching receiving module includes a high-speed receiving module and a low-speed receiving module; the speed selector includes a first input port and a second input port; wherein, the output port of the high-speed receiving module is connected to the first input port of the speed selector, and the output port of the low-speed receiving module is connected to the second input port of the speed selector.

[0005] Furthermore, the high-speed receiving module includes: a high-speed receiver, a high-speed delay phase-locked loop, and a flexible buffer; wherein, the input port of the high-speed receiver serves as the input port of the high-speed receiving module, the output port of the high-speed receiver is connected to the first input port of the high-speed delay phase-locked loop, the output port of the high-speed delay phase-locked loop is connected to the input port of the flexible buffer, and the first output port of the flexible buffer serves as the output port of the high-speed receiving module and is connected to the first input port of the speed selector.

[0006] Furthermore, the high-speed receiver includes: a first differential amplifier, a second differential amplifier, and a current mirror; wherein, the input ports of the first differential amplifier and the second differential amplifier serve as input ports of the high-speed receiver, the output port of the first differential amplifier is connected to the first input port of the current mirror, the output port of the second differential amplifier is connected to the second input port of the current mirror, and the output port of the current mirror serves as the output port of the high-speed receiver and is connected to the first input port of the high-speed delay phase-locked loop.

[0007] Furthermore, the low-speed receiving module includes: a low-speed receiver and a low-speed data recovery circuit; wherein, the input port of the low-speed receiver serves as the input port of the low-speed receiving module, the output port of the low-speed receiver is connected to the first input port of the low-speed data recovery circuit, and the first output port of the low-speed data recovery circuit serves as the output port of the low-speed receiving module and is connected to the second input port of the speed selector.

[0008] Furthermore, the low-speed receiver includes an open-loop amplifier and a Schmitt trigger; wherein, the input port of the open-loop amplifier serves as the input port of the low-speed receiver, the output port of the open-loop amplifier is connected to the input port of the Schmitt trigger, and the output port of the Schmitt trigger serves as the output port of the low-speed receiver and is connected to the first input port of the low-speed data recovery circuit.

[0009] Furthermore, the USB data decoding circuit further includes a phase-locked loop (PLL); wherein the first output port of the PLL is connected to the second input port of the high-speed delay PLL, and the second output port of the PLL is connected to the second input port of the low-speed data recovery circuit.

[0010] Furthermore, the USB data decoding circuit further includes a logic control module; wherein the logic control module is connected to the elastic buffer, the low-speed data recovery circuit, the bit rejection module, and the shift register, respectively.

[0011] This invention also provides a USB data decoding method, which is implemented based on the USB data decoding circuit described above. The USB data decoding method includes: a high-speed receiving module and a low-speed receiving module synchronously receiving externally input USB protocol data packets and performing high-speed data processing and low-speed data processing respectively; the high-speed receiving module transmitting the USB protocol data packets processed by high-speed data to a speed selector, and the low-speed receiving module transmitting the USB protocol data packets processed by low-speed data to the speed selector; the speed selector selecting a processed USB protocol data packet from the high-speed and low-speed processed USB protocol data packets based on a specified selection signal and transmitting it to a reverse non-return-to-zero decoder; the reverse non-return-to-zero decoder performing reverse non-return-to-zero decoding on the processed USB protocol data packet, obtaining the decoded data and transmitting it to a bit removal module; the bit removal module removing data conforming to the bit filling rules from the received decoded data, and transmitting data that does not conform to the bit filling rules to a shift register; the shift register parallelizing the received data and transmitting the parallelized data as the final decoded data to a static random access memory for storage; wherein, the data processing includes high-speed data processing and low-speed data processing.

[0012] Furthermore, the high-speed data processing described in the USB data decoding method specifically includes: a high-speed receiver in the high-speed receiving module acquiring high-speed data from the USB protocol data packet and transmitting it to a high-speed delay-locked loop in the high-speed receiving module; the high-speed delay-locked loop in the high-speed receiving module performing spatial oversampling on the high-speed data, acquiring the sampling clock signal and the data signal of the high-speed data, and transmitting them to a flexible buffer in the high-speed receiving module; the flexible buffer in the high-speed receiving module adjusting the local clock signal based on the frequency difference and phase difference between the sampling clock signal of the high-speed data and the local clock signal, and transmitting the data signal of the high-speed data to the speed selector.

[0013] Furthermore, the low-speed data processing described in the USB data decoding method specifically includes: the low-speed receiver in the low-speed receiving module acquiring low-speed data in the USB protocol data packet and transmitting it to the low-speed data recovery circuit in the low-speed receiving module; the low-speed data recovery circuit in the low-speed receiving module sampling the low-speed data, acquiring the data signal of the low-speed data, and transmitting it to the speed selector.

[0014] Furthermore, the USB data decoding method further includes: a flexible buffer module in the high-speed data processing module transmitting the high-speed data signal back to the logic control module; a low-speed data recovery circuit transmitting the low-speed data signal back to the logic control module; and the logic control module obtaining the parsing information of the USB protocol data packet based on the received high-speed data signal and low-speed data signal.

[0015] Furthermore, the USB data decoding method further includes: the logic control module transmitting a specified bit stuffing rule to the bit culling module.

[0016] Furthermore, the USB data decoding method further includes: the logic control module controlling the shift register to perform parallel processing on data of a specified type.

[0017] The present invention also provides a USB data decoding chip, including the USB data decoding circuit as described above.

[0018] The present invention also provides a USB data decoding system, comprising: a USB host, a USB device, and a USB data decoding chip as described above; wherein, the output port of the USB host is connected to the input port of the USB data decoding chip, and the output port of the USB data decoding chip is connected to the input port of the USB device.

[0019] The beneficial effects of this invention are as follows: the high-speed delay phase-locked loop based on the high-speed receiver in the high-speed and low-speed switching receiver module enables the parsing of USB data packets without increasing the clock frequency, which greatly reduces the cost and design difficulty of the decoding circuit. By implementing the logic control module in the USB data decoding circuit to adjust the parsing of different USB data packets according to the requirements, the flexibility of the USB data decoding circuit is improved. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a USB data decoding circuit according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of a high-low speed switching module according to an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of a high-speed receiving module and a low-speed receiving module according to an embodiment of the present invention.

[0023] Figure 4 This is a circuit diagram of a high-speed receiver according to an embodiment of the present invention.

[0024] Figure 5 This is a circuit diagram of a low-speed receiver according to an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of a USB data decoding circuit including a phase-locked loop according to an embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram of a USB data decoding circuit including a logic control module according to an embodiment of the present invention.

[0027] Figure 8 This is a schematic diagram of the logic control module according to one embodiment of the present invention.

[0028] Figure 9 This is a flowchart illustrating a USB data decoding method according to an embodiment of the present invention.

[0029] Figure 10 This is a schematic diagram of a USB data decoding system according to an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0031] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any creative effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to the design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0032] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may represent singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or units but may also include steps or units not listed, or may include other steps or units inherent to such processes, methods, products, or apparatus. The terms “first,” “second,” and “third” used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects.

[0033] As a preferred embodiment of the present invention, the first embodiment provides a USB data decoding circuit, aiming to solve the current difficulties in parsing high-speed USB protocols. Figure 1 As shown, the USB data decoding circuit includes: a high-low speed switching receiver module, a speed selector, a non-return-to-zero decoder, a bit rejection module, a shift register, and a static random access memory.

[0034] Specifically, the high-speed / low-speed switching receiving module is used to switch and set high-speed or low-speed reception through the high and low levels of external pins. The speed selector is used to select the recovery data and recovery clock of the USB protocol data packet according to the external pins. The reverse non-return-to-zero decoder is used to perform reverse non-return-to-zero decoding on the data. Its decoding rule can be understood as "high level remains unchanged, low level toggles". During decoding, if the current data is XORed with the value of the previous frame data, the decoded current data can be obtained. The bit rejection module is used to reject data that conforms to the bit filling rule. The bit filling rule can be, but is not limited to, counting consecutive high levels. When the count reaches a specified value, the bit is rejected. It should be noted that when the count of consecutive high levels reaches the specified value, it indicates that the data packet has an error. The specified value can be, but is not limited to, integer values ​​such as 6, 7, 8, 10, 15, etc. The shift register is used to parallelize the serialized data, that is, to convert the serial data into parallel data. The static random access memory is used to store the data output by the shift register, so that external software can read the stored data; the storage space of the static random access memory can be configured according to the actual application requirements.

[0035] like Figure 1 As shown, the connection relationship of each module component in the USB data decoding circuit is as follows: the input port of the high-low speed switching receiving module serves as the input port of the USB data decoding circuit; the output port of the high-low speed switching receiving module is connected to the input port of the speed selector; the input of the inverted non-return-to-zero decoder is connected to the output port of the speed selector; the output port of the inverted non-return-to-zero decoder is connected to the input port of the bit rejection module; the output port of the bit rejection module is connected to the input port of the shift register; and the output port of the shift register is connected to the input port of the static random access memory. The USB data decoding circuit provided in this embodiment, based on the high-low speed receiving switching module, enables the parsing of USB protocol data packets without increasing the clock frequency, reducing circuit cost and design complexity.

[0036] Based on the above embodiments, as a preferred embodiment of this application, the high-low speed reception switching module in the USB data decoding circuit provided in the second embodiment of this application specifically includes: a high-speed reception module and a low-speed reception module. Specifically, the high-speed reception module refers to a module with a relatively high operating frequency, used to receive and process high-speed data to obtain sampled data signals; conversely, the low-speed reception module refers to a module with a relatively low operating frequency, used to receive and process low-speed or full-speed data to obtain sampled data signals. Figure 2 As shown, the speed selector includes a first input port and a second input port. The connection relationship between the high-speed receiving module and the low-speed receiving module and the remaining components in the USB data decoding circuit is as follows: the input ports of the high-speed receiving module and the low-speed receiving module together serve as the input ports of the high-low speed receiving switching module; the output port of the high-speed receiving module is connected to the first input port of the speed selector; and the output port of the low-speed receiving module is connected to the second input port of the speed selector. In this embodiment, the high-low speed switching receiving module is configured as a high-speed receiving module and a low-speed receiving module, enabling the USB data decoding circuit to receive data in modules according to the data speed of the input USB protocol data packets, and perform different processing based on the data speed, thereby obtaining a more reliable sampled data signal.

[0037] Based on the above embodiments, as a preferred embodiment of this application, the third embodiment of this application configures the high-speed receiving module to specifically include: a high-speed receiver, a high-speed delay-locked loop (PLL), and a flexible buffer. Specifically, the high-speed receiver is used to receive high-speed data from externally input USB protocol data packets. The high-speed delay-locked loop is used to spatially oversample the high-speed data received by the high-speed receiver, thereby recovering the sampled clock signal and data signal. The flexible buffer is used to compensate for the frequency difference and phase difference between the clock signal recovered by the high-speed delay-locked loop and the local transmission clock. The flexible buffer may be, but is not limited to, a FIFO buffer with dual clocks.

[0038] like Figure 3As shown, the connection relationship of each component in the high-speed receiving module is as follows: the input port of the high-speed receiver serves as the input port of the high-speed receiving module; the output port of the high-speed receiver is connected to the first input port of the high-speed delay-locked loop (PLL); the output port of the high-speed delay-locked loop is connected to the input port of the elastic buffer; and the first output port of the elastic buffer serves as the output port of the high-speed receiving module and is connected to the first input port of the speed selector. In this embodiment, the high-speed delay-locked loop in the USB data decoding circuit performs targeted spatial oversampling on the high-speed data in the USB protocol data packets, enabling the USB data decoding circuit to complete the parsing of high-speed USB protocol data packets without requiring an additional clock frequency, significantly reducing the design difficulty and cost of the USB data decoding circuit.

[0039] In some preferred embodiments of this application, the high-speed receiver may be implemented, but is not limited to, using the input terminal of a differential amplifier with two-stage resistors as loads as the input port of the high-speed receiver, and then using the output terminal of a differential amplifier with a current mirror as the load as the output port of the high-speed receiver. Specifically, the high-speed receivers described in various embodiments of this application are implemented by digital circuits, and in some embodiments of this application, the high-speed receiver includes at least a differential amplifier and a current mirror.

[0040] like Figure 4 As shown, in a preferred embodiment of this application, the high-speed receiver includes: a first differential amplifier diff1, a second differential amplifier diff2, and a current mirror CM0; wherein, the input ports of the first differential amplifier diff1 and the second differential amplifier diff2 serve as the input ports of the high-speed receiver, the output port of the first differential amplifier diff1 is connected to the first input port N1 of the current mirror CM0, the output port of the second differential amplifier diff2 is connected to the second input port N2 of the current mirror CM0, and the output port N0 of the current mirror CM0 serves as the output port of the high-speed receiver and is connected to the first input port of the high-speed delay-locked loop. Specifically, the first differential amplifier and the second differential amplifier process the signal of the externally input USB protocol data packet in a differential form to reduce noise interference. The current mirror is used to reduce the signal's sensitivity to ground and power supply, thereby improving signal stability. That is, the signal processing in the high-speed receiver reduces signal noise interference while improving signal stability.

[0041] Based on the above embodiments, as a preferred embodiment of this application, the fourth embodiment of this application configures the low-speed receiving module to specifically include: a low-speed receiver and a low-speed data recovery circuit. Specifically, the low-speed receiver is used to receive low-speed and / or full-speed data of externally input USB protocol data packets. The low-speed data recovery circuit is used to sample the low-speed and / or full-speed data received by the low-speed receiver to recover the sampled clock signal and data signal. Figure 3 As shown, the connection relationship of each component in the low-speed receiving module is as follows: the input port of the low-speed receiver serves as the input port of the low-speed receiving module; the output port of the low-speed receiver is connected to the first input port of the low-speed data recovery circuit; and the first output port of the low-speed data recovery circuit serves as the output port of the low-speed receiving module and is connected to the second input port of the speed selector. The low-speed receiving module provided in this embodiment can parse low-speed data in USB protocol data packets and obtain the recovered data signal. It uses different receivers to process the data according to the speed, improving the data decoding flexibility of the USB data decoding circuit.

[0042] Based on the above embodiments, as a preferred embodiment of this application, in the fifth embodiment of this application, the low-speed receiver is configured to include an open-loop amplifier and a Schmitt trigger, wherein the open-loop amplifier is used to implement the function of receiving and filtering low-speed data by the low-speed receiver, and the Schmitt trigger is used to increase the noise immunity of the low-speed receiver. Figure 5 As shown, the positive and negative terminals of the open-loop amplifier are the input ports of the open-loop amplifier, which serve as the input ports of the low-speed receiver. The output port of the open-loop amplifier is connected to the input port of the Schmitt trigger, and the output port of the Schmitt trigger serves as the output port of the low-speed receiver and is connected to the first input port of the low-speed data recovery circuit. Here, DP and DM refer to the positive and negative signals of the externally input USB protocol data packets.

[0043] Based on the above embodiments, as a preferred embodiment of this application, the USB data decoding circuit in the sixth embodiment of this application is configured to further include a phase-locked loop (PLL). Specifically, the PLL uses an external crystal oscillator or an internal RC circuit as a clock source to generate a high-speed clock signal and a low-speed clock signal; wherein, the PLL applies the high-speed clock signal to the high-speed delay PLL of the high-speed receiving module to enable the high-speed delay PLL to perform spatial oversampling of high-speed data in the USB protocol data packet based on the high-speed clock signal, thereby obtaining the sampling data signal and clock signal recovered from the high-speed data. The PLL applies the low-speed clock signal to the low-speed data recovery circuit of the low-speed receiving module to enable the low-speed data recovery circuit to sample low-speed data in the USB protocol data packet based on the low-speed clock signal, thereby obtaining the sampling data signal recovered from the low-speed data. Specifically, as... Figure 6 As shown, the connection relationship between the phase-locked loop (PLL) and the other modules in the USB data decoding circuit is as follows: the first output port of the PLL is connected to the second input port of the high-speed delay PLL, and the second output port of the PLL is connected to the second input port of the low-speed data recovery circuit. This embodiment, by configuring a PLL in the USB data decoding circuit, provides corresponding high-speed and low-speed clock signals to the high-speed and low-speed receiving modules, thereby guiding the sampling frequency of the USB protocol data by the high-speed and low-speed receiving modules.

[0044] In some preferred embodiments of this application, the high-speed clock signal generated by the phase-locked loop may be, but is not limited to, a 480MHz clock signal with 16 phases, and the low-speed clock signal generated by the phase-locked loop may be, but is not limited to, a 48MHz clock signal or a 60MHz clock signal, etc.

[0045] Based on the above embodiments, as a preferred embodiment of this application, the USB data decoding circuit in the seventh embodiment of this application is configured to further include a logic control module. Specifically, the logic control module is used to detect the type of data packets and the decoding status of the data packets in the USB data decoding circuit, and can be used to receive configuration information from the chip CPU via the AHB bus for the logic control module. The configuration content may include, but is not limited to: controlling the USB data decoding circuit to store only data packets of a specified type, or controlling the USB data decoding circuit to remove data of a specified type (i.e., equivalent to configuring the logic control module to control the bit filling rules or bit removal conditions of the bit removal module), etc. Specifically, as shown... Figure 7As shown, the connection relationship between the logic control module and the other modules in the USB data decoding module is as follows: the logic control module is connected to the elastic buffer, the low-speed data recovery circuit, the bit removal module, and the shift register. Through its connection with the elastic buffer and the low-speed data recovery circuit, the logic control module monitors the operating status of the high-speed and low-speed receiving modules and their data packet parsing information, allowing external systems to read the circuit operating status of the USB data decoding circuit. Through its connection with the bit removal module, the logic control module controls the enabling of the bit removal module and specifies the bit stuffing rules and / or bit removal conditions, enabling more flexible filtering and removal of decoded content from data packets. Through its connection with the shift register, the logic control module controls the shift register to store only specified data packet information according to the chip CPU's configuration information, so that the static random access memory can only read and write to specified data packets. Here, the chip CPU refers to the CPU containing the USB data decoding circuit. This embodiment, by configuring a logic control module in the USB data decoding circuit, enables the USB data decoding circuit, in conjunction with the chip CPU, to adjust the parsing of different USB protocol data packets according to actual needs, effectively improving the flexibility and application range of the USB data decoding circuit. In some embodiments of this application, the logic control module is composed of, for example... Figure 8 The digital circuit implementation shown is as follows: Figure 8 In this context, AHB refers to the AHB bus; CSR module refers to the controller dedicated register, used to store information of the logic control module; the full-speed and low-speed logic control is the logic control unit used to instruct the low-speed data recovery circuit; the SOP and EOP identification is the unit used to enable the logic controller to identify whether the received data is the start data or the end data of a data packet; and the external signal refers to the signal transmitted from the other modules in the USB data decoding circuit to the logic control module.

[0046] It should be noted that the "low speed" mentioned in the modules or circuits such as the low-speed receiving module, low-speed receiver, low-speed data recovery circuit, and low-speed data mentioned in the various embodiments of this application actually includes both full speed and low speed in the USB protocol. It can be understood that the above modules or circuits can also be referred to as: low-speed full-speed receiving module, low-speed full-speed receiver, low-speed data full-speed data recovery circuit, low-speed data, and full-speed data.

[0047] Based on the USB data decoding circuit provided in the above embodiments, as a preferred embodiment of this application, the eighth embodiment of this application provides a USB data decoding method, such as... Figure 9As shown, the USB data decoding method specifically includes: a high-speed receiving module and a low-speed receiving module synchronously receive externally input USB protocol data packets and perform high-speed data processing and low-speed data processing respectively; the high-speed receiving module transmits the USB protocol data packets after high-speed data processing to a speed selector, and the low-speed receiving module transmits the USB protocol data packets after low-speed data processing to a speed selector; the speed selector selects a processed USB protocol data packet from the high-speed and low-speed processed USB protocol data packets based on a specified selection signal and transmits it to a reverse non-return-to-zero decoder; the reverse non-return-to-zero decoder performs reverse non-return-to-zero decoding on the processed USB protocol data packet, obtains the decoded data, and transmits it to a bit removal module; the bit removal module removes data that conforms to the bit filling rule from the received decoded data, and transmits data that does not conform to the bit filling rule to a shift register; the shift register parallelizes the received data and transmits the parallelized data as the final decoded data to a static random access memory for storage; wherein, the data processing includes high-speed data processing and low-speed data processing. This embodiment uses a high-speed receiving module and a low-speed receiving module to achieve more accurate processing of data in USB protocol data packets based on speed.

[0048] Specifically, the high-speed data processing described in the USB data decoding method includes: a high-speed receiver in the high-speed receiving module acquiring high-speed data from the USB protocol data packet and transmitting it to a high-speed delay-locked loop (PLL) in the high-speed receiving module; the high-speed PLL in the high-speed receiving module performing spatial oversampling on the high-speed data to acquire the sampling clock signal and the data signal of the high-speed data and transmitting them to a flexible buffer in the high-speed receiving module; and the flexible buffer in the high-speed receiving module adjusting the local clock signal based on the frequency difference and phase difference between the sampling clock signal of the high-speed data and the local clock signal, and transmitting the data signal of the high-speed data to the speed selector.

[0049] Specifically, the low-speed data processing in the USB data decoding method includes: the low-speed receiver in the low-speed receiving module acquiring low-speed data in the USB protocol data packet and transmitting it to the low-speed data recovery circuit in the low-speed receiving module; the low-speed data recovery circuit in the low-speed receiving module sampling the low-speed data, acquiring the data signal of the low-speed data, and transmitting it to the speed selector.

[0050] In some embodiments of this application, the USB data decoding method further includes: a flexible buffer module in the high-speed data processing module transmitting the high-speed data signal back to the logic control module; a low-speed data recovery circuit transmitting the low-speed data signal back to the logic control module; and the logic control module obtaining the parsing information of the USB protocol data packet based on the received high-speed and low-speed data signals. By setting up the logic control module, external systems can monitor the operating status information of the high-speed and low-speed data processing modules in the USB data decoding circuit, as well as the data packet parsing information, in real time.

[0051] In some embodiments of this application, the USB data decoding method further includes: a logic control module transmitting a specified bit stuffing rule to a bit culling module. By setting the logic control module, the external system can specify the bit stuffing rule used by the bit culling module, which is equivalent to enabling the bit culling module to perform culling, thereby improving the controllability of the USB data decoding method.

[0052] In some embodiments of this application, the USB data decoding method further includes: a logic control module controlling a shift register to perform parallel processing on data of a specified type. By setting the logic control module, the external system can specify that the shift register should only perform parallel processing on data of a specified type, so that the USB data decoding method can decode only specific types of data, thus meeting the user's specific needs.

[0053] In some preferred embodiments of this application, a USB data decoding chip is provided, the USB decoding chip including the USB data decoding circuit as described in any of the foregoing embodiments.

[0054] In some preferred embodiments of this application, a USB data decoding system is provided, such as... Figure 10 As shown, the USB system includes: a USB host, a USB device, and a USB data decoding chip as described in the previous embodiment; wherein, the output port of the USB host is connected to the input port of the USB decoding chip, and the output port of the USB decoding chip is connected to the input port of the USB device. Specifically, in the USB data decoding system, the USB host transmits USB protocol data packets to the USB data decoding chip, the USB data decoding chip transmits the USB protocol data packets to its internal USB data decoding circuit for data packet parsing, and the USB device can retrieve the content of the parsed USB protocol data packets from the USB data decoding chip. The USB data decoding system provided in this embodiment can decode the USB protocol data packets output by the USB host, enabling the USB device to flexibly retrieve the parsed USB protocol data packets.

[0055] It should be noted that the circuits and modules mentioned in the above embodiments can all be implemented using corresponding digital circuits and electronic components. The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural transformations made based on the description and drawings of this invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this invention.

Claims

1. A USB data decoding circuit, characterized by comprising: The USB data decoding circuit includes: a high-low speed switching receiving module, a speed selector, a non-return-to-zero decoder, a bit rejection module, a shift register, and a static random access memory (SRAM); wherein, the high-low speed switching receiving module includes a high-speed receiving module and a low-speed receiving module; the input port of the high-low speed switching receiving module serves as the input port of the USB data decoding circuit, the output port of the high-low speed switching receiving module is connected to the input port of the speed selector, the input of the non-return-to-zero decoder is connected to the output port of the speed selector, the output port of the non-return-to-zero decoder is connected to the input port of the bit rejection module, the output port of the bit rejection module is connected to the input port of the shift register, and the output port of the shift register is connected to the input port of the SRAM; The system comprises two modules: a high-speed receiving module and a low-speed receiving module, which synchronously receive externally input USB protocol data packets and perform high-speed and low-speed data processing respectively; a speed selector, which selects a processed USB protocol data packet from the high-speed and low-speed processed USB protocol data packets based on a specified selection signal and transmits it to the inverted non-return-to-zero decoder; an inverted non-return-to-zero decoder, which performs inverted non-return-to-zero decoding on the processed USB protocol data packets, obtains the decoded data, and transmits it to the bit removal module; a bit removal module, which removes data that conforms to the bit stuffing rules from the received decoded data, and transmits data that does not conform to the bit stuffing rules to a shift register; and a shift register, which parallelizes the received data and transmits the parallelized data as the final decoded data to a static random access memory for storage. The high-speed receiving module includes a high-speed receiver, a high-speed delay-locked loop (PLL), and a flexible buffer. The high-speed receiver acquires high-speed data from USB protocol data packets and transmits it to the PLL within the high-speed receiving module. The PLL performs spatial oversampling on the high-speed data to acquire a sampling clock signal and a data signal, which are then transmitted to the flexible buffer in the high-speed receiving module. The flexible buffer adjusts the local clock signal based on the frequency and phase differences between the sampling clock signal and the local clock signal, and transmits the high-speed data signal to a speed selector. The input port of the high-speed receiver serves as the input port of the high-speed receiving module. The output port of the high-speed receiver is connected to the first input port of the PLL, the output port of the PLL is connected to the input port of the flexible buffer, and the first output port of the flexible buffer serves as the output port of the high-speed receiving module and is connected to the first input port of the speed selector.

2. The USB data decoding circuit according to claim 1, characterized in that, The speed selector includes a first input port and a second input port; wherein, the output port of the high-speed receiving module is connected to the first input port of the speed selector, and the output port of the low-speed receiving module is connected to the second input port of the speed selector.

3. The USB data decoding circuit according to claim 2, characterized in that, The high-speed receiver includes a first differential amplifier, a second differential amplifier, and a current mirror; wherein the input ports of the first differential amplifier and the second differential amplifier serve as input ports of the high-speed receiver, the output port of the first differential amplifier is connected to the first input port of the current mirror, the output port of the second differential amplifier is connected to the second input port of the current mirror, and the output port of the current mirror serves as the output port of the high-speed receiver and is connected to the first input port of the high-speed delay phase-locked loop.

4. The USB data decoding circuit according to claim 2, characterized in that, The low-speed receiving module includes a low-speed receiver and a low-speed data recovery circuit; wherein, the input port of the low-speed receiver serves as the input port of the low-speed receiving module, the output port of the low-speed receiver is connected to the first input port of the low-speed data recovery circuit, and the first output port of the low-speed data recovery circuit serves as the output port of the low-speed receiving module and is connected to the second input port of the speed selector.

5. The USB data decoding circuit according to claim 4, characterized in that, The low-speed receiver includes an open-loop amplifier and a Schmitt trigger; wherein, the input port of the open-loop amplifier serves as the input port of the low-speed receiver, the output port of the open-loop amplifier is connected to the input port of the Schmitt trigger, and the output port of the Schmitt trigger serves as the output port of the low-speed receiver and is connected to the first input port of the low-speed data recovery circuit.

6. The USB data decoding circuit according to claim 4, characterized in that, The USB data decoding circuit further includes a phase-locked loop (PLL); wherein the first output port of the PLL is connected to the second input port of the high-speed delay PLL, and the second output port of the PLL is connected to the second input port of the low-speed data recovery circuit.

7. The USB data decoding circuit according to claim 6, characterized in that, The USB data decoding circuit further includes a logic control module; wherein the logic control module is connected to the elastic buffer, the low-speed data recovery circuit, the bit rejection module and the shift register respectively.

8. A USB data decoding method, characterized in that, The USB data decoding method is implemented based on the USB data decoding circuit as described in any one of claims 1 to 7, and the USB data decoding method includes: The high-speed receiving module and the low-speed receiving module synchronously receive externally input USB protocol data packets and perform high-speed data processing and low-speed data processing respectively; The high-speed receiving module transmits the USB protocol data packets after high-speed data processing to the speed selector, while the low-speed receiving module transmits the USB protocol data packets after low-speed data processing to the speed selector. The speed selector selects a processed USB protocol data packet from the high-speed and low-speed processed USB protocol data packets based on a specified selection signal and transmits it to the inverted non-return-to-zero decoder. The reverse non-return-to-zero decoder performs reverse non-return-to-zero decoding on the USB protocol data packets after data processing, obtains the decoded data, and transmits it to the bit removal module. The bit removal module removes data that conforms to the bit stuffing rules from the received decoded data, and transmits data that does not conform to the bit stuffing rules to the shift register; The shift register parallelizes the received data and then transmits the parallelized data as the final decoded data to the static random access memory for storage. Data processing includes high-speed data processing and low-speed data processing.

9. The USB data decoding method according to claim 8, characterized in that, The high-speed data processing described in the USB data decoding method specifically includes: The high-speed receiver in the high-speed receiving module acquires high-speed data from the USB protocol data packets and transmits it to the high-speed delay phase-locked loop in the high-speed receiving module. The high-speed delay phase-locked loop in the high-speed receiving module performs spatial oversampling on the high-speed data, obtains the sampling clock signal and the data signal of the high-speed data, and transmits them to the elastic buffer in the high-speed receiving module. The elastic buffer in the high-speed receiving module adjusts the local clock signal based on the frequency difference and phase difference between the sampling clock signal of the high-speed data and the local clock signal, and transmits the high-speed data signal to the speed selector.

10. The USB data decoding method according to claim 9, characterized in that, The low-speed data processing described in the USB data decoding method specifically includes: The low-speed receiver in the low-speed receiving module acquires low-speed data from the USB protocol data packet and transmits it to the low-speed data recovery circuit in the low-speed receiving module. The low-speed data recovery circuit in the low-speed receiving module samples the low-speed data, acquires the data signal of the low-speed data, and transmits it to the speed selector.

11. The USB data decoding method according to claim 10, characterized in that, The USB data decoding method further includes: The elastic buffer module in the high-speed data processing module also transmits the high-speed data signal to the logic control module; The low-speed data recovery circuit transmits the low-speed data signal back to the logic control module; The logic control module obtains the parsing information of the USB protocol data packets based on the data signals of the received high-speed data and low-speed data.

12. The USB data decoding method according to claim 11, characterized in that, The USB data decoding method further includes: the logic control module transmitting a specified bit stuffing rule to the bit culling module.

13. The USB data decoding method according to claim 12, characterized in that, The USB data decoding method further includes: a logic control module controlling a shift register to perform parallel processing on data of a specified type.

14. A USB data decoding chip, characterized in that, The USB data decoding chip includes the USB data decoding circuit as described in any one of claims 1 to 7.

15. A USB data decoding system, characterized in that, The USB data decoding system includes: a USB host, a USB device, and a USB data decoding chip as described in claim 14; wherein the output port of the USB host is connected to the input port of the USB data decoding chip, and the output port of the USB data decoding chip is connected to the input port of the USB device.

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