Display device

Abstract

Embodiments of this disclosure relate to a display device, comprising: a display panel including pixels for displaying images; a display panel driving circuit outputting a driving signal for driving the display panel; and a compensation signal generator sensing a noise signal generated by the display panel or the display panel driving circuit, and generating a noise compensation signal corresponding to the noise signal. The compensation signal generator includes: a detection unit detecting a phase-shifted signal generated by synthesizing a target signal; and an inversion unit generating an inverted signal by inverting the phase of the phase-shifted signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0083345, filed on July 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Display devices include liquid crystal displays (LCDs), electroluminescent displays, etc. Based on the material of the light-emitting layer, electroluminescent displays can be divided into inorganic light-emitting displays and organic light-emitting diode (OLED) displays.

[0005] As the resolution of display devices gradually increases, higher frequencies and more signals are required to drive the display devices, resulting in signal distortion and electromagnetic interference (EMI) noise.

[0006] To address these issues, phase cancellation methods are employed, which use an inverse signal with the same amplitude and opposite polarity as the target signal (e.g., an electromagnetic wave signal) as a noise compensation signal. However, in general phase cancellation methods, the phase cannot be completely eliminated due to the delay between the target signal and the inverse signal. In particular, the noise reduction effect is significantly reduced in the high-frequency domain, causing further problems. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device that has improved noise (e.g., EMI) cancellation within the display panel.

[0008] Embodiments of this disclosure provide a display device that uses a phase-shifted signal extracted by synthesizing a target signal to achieve zero delay in a noise-compensated signal.

[0009] One embodiment is a display device, comprising: a display panel including pixels for displaying an image; a display panel driving circuit outputting a driving signal for driving the display panel; and a compensation signal generator sensing a noise signal generated by the display panel or the display panel driving circuit, and generating a noise compensation signal corresponding to the noise signal. The compensation signal generator may include: a detection unit detecting a phase-shifted signal generated by synthesizing a target signal; and an inversion unit generating an inverted signal by inverting the phase of the phase-shifted signal.

[0010] The target signal may include: a first signal sensed from the display panel via a sensing line; and a second signal generated by inverting the phase of the first signal. The detection unit can detect the phase-shifted signal generated by synthesizing the first signal and the second signal. The second signal may have a phase-shifted component relative to the inverse signal of the noise signal.

[0011] The inverted signal output from the inverting unit can be combined with the second signal to generate the noise compensation signal, and the noise compensation signal can be provided to the display panel.

[0012] The noise compensation signal may have the same frequency and amplitude as the noise signal, and have an inverted phase relative to the noise signal.

[0013] The compensation signal generator may further include an amplification unit that amplifies or attenuates the inverted signal output from the inverting unit.

[0014] The display panel may include touch electrodes for detecting touch input. The display panel driving circuit may apply a common voltage to the touch electrodes during the display period and may apply a touch driving signal to the touch electrodes during the touch sensing period.

[0015] The first signal may be an electromagnetic interference (EMI) noise signal sensed from the display panel when a pulsed touch drive signal is applied to the touch electrode.

[0016] The display device may further include a level shifter that sequentially outputs multiple clock signals to a clock line. A detection unit can detect the phase-shift signal generated by synthesizing the multiple clock signals.

[0017] The inverted signal output from the inversion unit can be provided to the display panel as the noise compensation signal, and can be combined with the noise signal generated by the plurality of clock signals to eliminate the phase of the noise signal.

[0018] Multiple clock signals can be n pulse signals, which have the same pulse width and a phase delayed by 1 / n periods.

[0019] The rising and falling edges of adjacent clock signals in a plurality of clock signals can be delayed or advanced relative to each other at random times.

[0020] The display panel driving circuit may include: a gate driver that applies a gate signal to a pixel via a gate line; a data driver that applies a data signal to the pixel via a data line; and a demultiplexer array disposed between the data driver and the data line. A clock signal is provided to at least one of the gate driver and the demultiplexer array.

[0021] Another embodiment is a display device comprising: a display panel including pixels and touch electrodes formed by slabifying the electrodes of the pixels into predetermined sizes; a touch driver applying a drive signal to the touch electrodes during a touch sensing period and detecting touch input based on a sensing signal received in response to the drive signal; and a compensation signal generator detecting a noise signal generated by the display panel and generating a noise compensation signal corresponding to the noise signal. The compensation signal generator may include: a detection unit detecting a phase-shifted signal generated by synthesizing a sensed noise signal and a first inverted signal, the first inverted signal being the inverted phase of the sensed noise signal; and an inversion unit generating a second inverted signal by inverting the phase of the phase-shifted signal.

[0022] The detection unit can sense the noise signal from the display panel via a sensing line.

[0023] The first inverted signal may have a phase-shifted component relative to the inverted signal of the noise signal generated by the display panel.

[0024] The second inverted signal output from the inversion unit can be combined with the first inverted signal to generate the noise compensation signal, and the noise compensation signal can be output to the display panel.

[0025] Another embodiment is a display device comprising: a display panel having pixels disposed thereon; a level shifter that sequentially outputs a plurality of clock signals to clock lines; a gate driver that generates gate signals based on the plurality of clock signals and applies the gate signals to the pixels via gate lines; a data driver that applies data signals to the pixels via data lines; and a compensation signal generator that senses noise signals generated by the level shifter and generates a noise compensation signal corresponding to the noise signals. The compensation signal generator may include: a detection unit that detects a phase-shifted signal generated by synthesizing the plurality of clock signals; and an inversion unit that generates an inverted signal by inverting the phase of the phase-shifted signal.

[0026] Multiple clock signals can be n pulse signals, which have the same pulse width and a phase delayed by 1 / n periods.

[0027] The rising and falling edges of adjacent clock signals among the plurality of clock signals may be delayed or advanced relative to each other at random times. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment;

[0029] Figure 2 This is a block diagram illustrating the configuration of a compensation signal generator for a display device according to an embodiment;

[0030] Figure 3 This is a view showing the circuit configuration of a compensation signal generator according to an embodiment;

[0031] Figure 4 It is shown Figure 3 The waveform diagram of the noise signal shown in the example is shown.

[0032] Figure 5 It is shown Figure 3 Waveform diagram of an embodiment of the first inverted signal shown;

[0033] Figure 6 It is shown Figure 3 Waveform diagram of an embodiment of the phase-shifted signal shown;

[0034] Figure 7 It is shown Figure 3 Waveform diagram of an embodiment of the second inverted signal shown;

[0035] Figure 8 It is shown Figure 3 The waveform diagram of an embodiment of the noise compensation signal shown;

[0036] Figure 9 It is shown Figure 3 Waveform diagrams of the noise signal and noise compensation signal shown in the embodiments;

[0037] Figure 10 This is a view showing the circuit configuration of a compensation signal generator according to another embodiment;

[0038] Figure 11 It is shown Figure 10 The waveform diagram of an embodiment of the clock signal shown;

[0039] Figure 12 It is shown Figure 10 Waveform diagram of an embodiment of the phase-shifted signal shown;

[0040] Figure 13 It is shown Figure 10 Waveform diagram of an embodiment of the inverted signal shown;

[0041] Figure 14 It is shown Figure 10 The waveform diagram of the synthesized signal of the noise signal and the noise compensation signal shown in the example;

[0042] Figure 15 and 16 It shows the basis Figure 10 The graph shows the noise reduction effect of the embodiment. Detailed Implementation

[0043] Further details of the embodiments are included in the detailed description and the accompanying drawings.

[0044] The features, advantages, and methods for implementing the invention will become more apparent from the detailed embodiments described below and the accompanying drawings. However, the invention is not limited to the embodiments disclosed below, but is implemented in different and various forms. In the following description, when reference is made to a part being “connected” to another part, it includes not only a “direct connection” but also an “electrical connection” via another element placed therebetween. Furthermore, in the accompanying drawings, parts unrelated to the invention will be omitted for clarity of description. Throughout this patent document, similar reference numerals will be assigned to similar parts.

[0045] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment.

[0046] refer to Figure 1 The display device 1 includes a display panel 100 and a display panel driving circuit.

[0047] The display panel 100 includes a pixel array AA for displaying pixel data of an input image. The pixel data of the input image is displayed on the pixels of the pixel array AA. The pixel array AA includes multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and pixels P arranged in a matrix. The arrangement of the pixels can include not only a matrix arrangement, but also a arrangement of pixels sharing the same emission color, a stripe arrangement, a diamond arrangement, etc.

[0048] When the resolution of the pixel array AA is n×m, the pixel array AA consists of n pixel columns and m pixel rows intersecting the pixel columns. A pixel column consists of pixels arranged along the column direction. A pixel row consists of pixels arranged along the row direction. A horizontal time period is the time obtained by dividing a frame time period by the total number of pixel rows. During a horizontal time period, pixel data is written to the pixels of one pixel row simultaneously.

[0049] Each pixel may include red, green, and blue sub-pixels to achieve color. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry. Pixel circuitry includes pixel electrodes, multiple thin-film transistors (TFTs), and capacitors. Pixel circuitry is connected to corresponding data lines DL and gate lines GL.

[0050] The display panel driving circuit generates and outputs driving signals for driving the display panel 100. The display panel driving circuit includes a gate driver 110, a data driver 120, and a timing controller 130 for controlling its operation timing. Under the control of the timing controller 130, the display panel driving circuit writes input image data into the pixels of the display panel 100.

[0051] Gate driver 110 applies a gate signal to pixel P via gate line GL. The gate signal applied to gate line GL turns on the switching TFTs located in the sub-pixel and sequentially selects the pixel row to be charged with the data voltage.

[0052] In an embodiment, the gate driver 110 can generate a gate signal based on a gate timing control signal received from a level shifter 140 disposed in the display device 1. The level shifter 140 converts a logic high voltage (or high-potential input voltage) of an input signal received from the timing controller 130 to a gate high voltage and converts a logic low voltage (or low-potential input voltage) of the input signal to a gate low voltage. The level shifter 140 can output a clock signal that swings between the gate high voltage and the gate low voltage. The output signal of the level shifter 140 can be transmitted to at least one of the demultiplexer array 121 and the gate driver 110.

[0053] The gate driver 110 can generate a gate signal by sequentially shifting the gate timing control signal output from the level shifter 140, and then sequentially output the gate signal to the gate line GL. The generated gate signal can be a pulse signal that oscillates between a gate high voltage and a gate low voltage.

[0054] In an embodiment, the gate driver 110 may be implemented as a gate in panel (GIP) disposed in the bezel area of ​​the display panel 100.

[0055] Data driver 120 provides the data voltage of the input image to pixel P via data line DL. Data driver 120 converts the pixel data DATA of the input image, received as a digital signal from timing controller 130, into an analog gamma-compensated voltage per frame and outputs a data signal. Data driver 120 can generate the data signal using a digital-to-analog converter (DAC) that converts the digital signal into an analog gamma-compensated voltage. The data signal is provided to data line DL.

[0056] The data driver 120 can be mounted on the chip-on-film (COF) in the form of a data driver IC (DIC) and can be connected between an external device and the display panel 100.

[0057] The display panel driving circuit may also include a demultiplexer array 121 disposed between the data driver 120 and the data line DL.

[0058] The demultiplexer array 121 sequentially connects one channel of the data driver 120 to multiple data lines DL, and then distributes the data signal output from one channel of the data driver 120 to the data lines DL in a time-division manner. As a result, the number of channels of the data driver 120 can be reduced.

[0059] The timing controller 130 receives pixel data of the input image and timing signals synchronized with it from an external host system. The timing controller 130 transmits the pixel data of the input image to the data driver 120. The timing signals include the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal DCLK, and the data enable signal DE, etc.

[0060] The timing controller 130 can output data timing control signals for controlling the data driver 120, gate timing control signals for controlling the gate driver 110, and MUX control signals for controlling the switching elements of the demultiplexer array 121, based on timing signals received from the host system. The gate timing control signals may include a start pulse, a shift clock, etc. The start pulse defines the start timing of the gate driver 110 in each frame period. The shift clock defines the shift timing of the gate signal output from the gate driver 110. The timing controller 130 can also output control signals for controlling the level shifter 140.

[0061] The timing controller 130 is provided in the form of a flexible printed circuit board (FPCB) and can be connected to a COF on which a DIC is mounted. The timing controller 130 can be electrically connected to the DIC and the display panel 100 via wires formed on the COF. Other components, such as a level shifter 140, can be mounted together on the flexible printed circuit board on which the timing controller 130 is disposed.

[0062] In an embodiment, the display device 1 may include a touch screen to detect touch input occurring on the display panel 100. In an embodiment, the display device 1 may be an external type (on-cell or add-on type) where the touch panel is separately disposed from the display panel 100, or it may be an internal type (in-cell type) where a touch sensor is disposed within the display panel 100.

[0063] When the display device 1 is implemented as having an embedded touchscreen, the display panel driving circuit may further include a touch driver 150, which is connected to the touch sensor via a touch sensing line to drive the touch sensor during the touch sensing period. The touch driver 150 may be integrally formed within the data driver 130 or formed separately. The touch driver 150 may apply a touch driving signal to the touch sensor during the touch sensing period and may detect touch input based on the touch sensing signal sensed in response to the touch driving signal.

[0064] The following will describe in more detail an example of implementing display device 1 as having a touch screen.

[0065] In this embodiment, the display device 1 further includes a compensation signal generator 160. The compensation signal generator 160 generates a noise compensation signal to remove noise generated in the display device 1 and applies the noise compensation signal to the display panel 100 or the display panel driving circuit. The noise can be signal distortion and / or EMI noise generated by drive signals applied to the display panel 100 or the display panel driving circuit. The drive signal can be, for example, a touch drive signal output from the touch driver 150 or a clock signal output from the level shifter 140.

[0066] In one embodiment, the compensation signal generator 160 can eliminate the phase of the target signal by using the inverted signal of the target signal (e.g., a noise signal) as a noise compensation signal, according to a phase cancellation method. In another embodiment, if a delay occurs between the target signal and the inverted signal, the phase of the target signal is not completely eliminated, and a differential signal remains between the target signal and the inverted signal, thus reducing the phase cancellation efficiency.

[0067] To address this problem, the compensation signal generator 160 is configured to effectively eliminate the target signal by generating an inverted signal with zero delay relative to the target signal. The specific structure of the compensation signal generator 160 will be described below.

[0068] Figure 2 This is a block diagram illustrating the configuration of a compensation signal generator for a display device according to an embodiment.

[0069] refer to Figure 1 and 2 The compensation signal generator 160 generates a noise compensation signal, which can be applied to the display panel 100 or the display panel driving circuit. In an embodiment, the noise compensation signal may be a signal used to compensate for the effects of EMI noise generated by a drive signal applied to the display panel 100 from the data driver 120. The drive signal may be, for example, a touch drive signal output from the touch driver 150 or a clock signal output from the level shifter 140.

[0070] In an embodiment, the compensation signal generator 160 includes a detection unit 161 and an inversion unit 162. The detection unit 161 detects the phase shift signal of the target signal, and the inversion unit 162 inverts the detected phase shift signal.

[0071] In one embodiment, the detection unit 161 can detect a phase-shifted signal generated by synthesizing two or more target signals. In another embodiment, the two or more target signals include a first signal and a second signal, where the first signal may be a noise signal sensed from the display panel 100, and the second signal may be the inverse of the sensed noise signal. In yet another embodiment, the two or more target signals may be clock signals output from the level shifter 140.

[0072] The phase-shifted signal is a residual signal generated by synthesizing the target signal, and may include time delay components between the target signals.

[0073] The inverting unit 162 generates an inverted signal by inverting the phase of the phase-shifted signal detected by the detection unit 161. For this purpose, the inverting unit 162 may include an inverting circuit, and the inverting circuit may include, for example, an inverter.

[0074] In an embodiment, the compensation signal generator 160 may further include an amplification unit 163. The amplification unit 163 may amplify the inverted signal generated by the inverting unit 162. The amplification unit 163 may include an amplifier that amplifies the signal amplitude and may amplify the signal to have a predetermined gain.

[0075] The inverted signal generated by the inverting unit 162 or the inverted signal amplified by the amplifying unit 163 is combined with at least one of the target signal to generate a noise compensation signal, thereby eliminating the phase of the target signal.

[0076] The specific circuit configuration of the compensation signal generator 160 and the method of compensation therethrough will be described below.

[0077] Figure 3 This is a view showing the circuit configuration of a compensation signal generator according to an embodiment. Figures 4 to 9 The following is illustrated according to an embodiment: Figure 3 The waveform of the signal generated by the compensation signal generator is shown.

[0078] refer to Figure 3 The display device 2 according to the embodiment can be implemented as having an embedded touchscreen. In the embodiment, the display panel 200 may include a plurality of touch electrodes TE. The touch electrodes TE can be connected to the data driver 220 and / or the touch driver 250 via touch sensing lines TSL.

[0079] In an embodiment, the touch electrode TE can be formed by grouping (blocking) the electrodes of a pixel into predetermined sizes. That is, the touch electrode TE can be used for touch sensing and display driving. Therefore, the touch electrode TE can receive a common voltage Vcom to display image data during the display period, and can receive a touch drive signal TDS to form a capacitance during the touch sensing period.

[0080] The drive signal applied to the touch electrode TE (e.g., touch drive signal TDS) can be a pulse signal that oscillates between high and low voltages. When the drive signal is a pulse signal, it can have various signal waveforms, such as sine waves, triangle waves, or square waves.

[0081] As pulsed drive signals are sequentially applied to multiple touch electrodes TE, EMI noise may be generated in the display panel 200. To address this issue, a compensation signal generator 260 provides the display panel 200 with a noise compensation signal corresponding to the EMI noise signal, thereby effectively improving the EMI level.

[0082] In an embodiment, the compensation signal generator 260 includes a detection unit 261 and an inversion unit 262.

[0083] The detection unit 261 can sense a noise signal ① generated by the display panel 200 as a first signal, which is a target signal. For example, the detection unit 261 can receive the noise signal ① generated by the display panel 200 via a sensing line SL electrically connected to at least one area of ​​the display panel 100. The noise signal ① detected by the sensing line SL can be... Figure 4 The sine wave shown.

[0084] The detection unit 261 can reverse the phase of the sensed noise signal ① to generate Figure 5 The first inverted signal ② shown serves as the second signal of the target signal. For example, the detection unit 261 includes an inverter as an inverting circuit and can generate the first inverted signal ②, which has the same frequency and amplitude as the noise signal ① and has an inverted phase relative to the noise signal ①. Specifically, the noise signal ① is input to the inverting terminal (-) of the first inverting amplifier OP1 that constitutes the inverter, and then the first inverted signal ②, obtained by inverting the phase of the noise signal ① by 180°, is output to the output terminal of the first inverting amplifier OP1.

[0085] Here, due to the delay that occurs in actual signal processing, the first inverted signal can have a phase shift component of up to α relative to the ideal inverted signal of the noise signal.

[0086] The target signal detected by the detection unit 261 can be synthesized. That is, the first inverted signal ② can be synthesized with the noise signal ①. Specifically, the first inverted signal ② output from the first inverting amplifier OP1 is synthesized with the noise signal ① applied to the output terminal of the first inverting amplifier OP1.

[0087] Ideally, when synthesizing the noise signal ① and the first inverted signal ②, the noise signal ① can be completely eliminated. However, as mentioned above, since the first inverted signal ② has a time delay, it retains... Figure 6 The residual signal ③ shown is a phase-shifted signal that reflects the phase delay of the first inverted signal ②. The residual signal can be sinusoidal.

[0088] The detection unit 261 can output a phase shift signal ③ based on the synthesis of the noise signal ① and the first inverted signal ②.

[0089] The inversion unit 262 inverts the phase of the phase-shift signal ③ output from the detection unit 261 and generates... Figure 7 The second inverted signal ④ is shown. For example, the inverting unit 262 includes an inverter as an inverting circuit and can generate a second inverted signal ④, which has the same waveform as the phase-shifted signal ③ and has an inverted phase relative to the phase-shifted signal ③. Specifically, the phase-shifted signal ③ is input to the inverting terminal (-) of the second inverting amplifier OP2 that constitutes the inverter, and then the second inverted signal ④, obtained by inverting the phase of the phase-shifted signal ③ by 180°, is output from the output terminal of the second inverting amplifier OP2.

[0090] In an embodiment, the compensation signal generator 260 may further include an amplifier (not shown) for amplifying or attenuating the phase of the second inverted signal ④ output from the inverting unit 262.

[0091] The second inverted signal ④ output from the inverting unit 262 can be combined with the first inverted signal ②. Specifically, the second inverted signal ④ output from the second inverting amplifier OP2 is combined with the first inverted signal ② output from the first inverting amplifier OP1 to the output terminal of the second inverting amplifier OP2.

[0092] like Figure 8 As shown, the signal obtained by synthesizing the second inverted signal ④ and the first inverted signal ② has an inverted signal waveform with no phase delay (zero delay) relative to the noise signal ①. That is, the synthesized signal of the second inverted signal ④ and the first inverted signal ② has the shape of an ideal inverted signal, has the same frequency and the same amplitude as the noise signal ①, and has an inverted phase relative to the noise signal ①.

[0093] In an embodiment, the compensation signal generator 260 may further include an amplifier OP3 for amplifying or attenuating the phase of the second inverted signal ④. The second inverted signal ④ is input to the non-inverting terminal of the amplifier OP3, amplified or attenuated by the amplifier OP3 by a predetermined gain, and then output. The compensation signal generator 260 outputs the combined signal ⑤ of the first inverted signal ② and the second inverted signal ④ as a noise compensation signal to the display panel 200. Specifically, the second inverted signal ④ output from the second inverting amplifier OP2 or amplifier OP3 is combined with the first inverted signal ② output from the first inverting amplifier OP1 to the output terminal of the second inverting amplifier OP2 or amplifier OP3. In an embodiment, the compensation signal generator 260 may output the noise compensation signal ⑤ to the display panel 200 via the data driver 220.

[0094] like Figure 9 As shown, the noise compensation signal ⑤ generated thereby is an inverted signal with near-zero delay relative to the noise signal ①. When the noise compensation signal ⑤ is output to the display panel 200, the noise signal ① generated by EMI and the like in the display panel 200 is combined with the noise compensation signal ⑤, thus effectively eliminating phase. As a result, the display device 2 according to the embodiment can effectively attenuate noise caused by EMI and the like through the compensation signal generator 260.

[0095] Figure 10 This is a view showing the circuit configuration of a compensation signal generator according to another embodiment. Figures 11 to 14 The following is illustrated according to an embodiment: Figure 10 The waveform of the signal generated by the compensation signal generator is shown.

[0096] refer to Figure 10 The display device 3 according to an embodiment may include a level shifter 340. The level shifter 340 may be provided as a separate component. However, in another embodiment, the level shifter 340 may be one of the components of the gate driver 310.

[0097] The level shifter 340 can be based on... Figure 1 The timing controller 130 shown receives a gate timing control signal to output gate clock signals GCLK1 to GCLK3. The gate clock signals GCLK1 to GCLK3 can be, for example, pulse signals that output a gate high voltage (or gate low voltage) pulse at a timing indicated by the gate timing control signal. For example, as... Figure 11As shown, the gate clock signals GCLK1 to GCLK3 can be three 3-phase gate clock signals GCLK1 to GCLK3, which have the same pulse width and a phase delay of 1 / 3 period. However, the embodiment is not limited to this. For example, the gate clock signal can be n pulse signals (n is a natural number), which have the same pulse width and a phase delay of 1 / n period. However, the embodiment is not limited to this.

[0098] Level shifter 340 can output gate clock signals GCLK1 to GCLK3 sequentially to clock lines CL1 to CL3. The gate clock signals GCLK1 to GCLK3 output from level shifter 340 can be transmitted to the shift register of demultiplexer array 321 and / or gate driver 310.

[0099] As pulsed gate clock signals GCLK1 to GCLK3 are sequentially applied to clock lines CL1 to CL3, EMI noise may occur. In this case, the smooth output state of the level shifter 340 cannot be guaranteed, and the reliability of the gate clock signals GCLK1 to GCLK3 may be reduced.

[0100] To remove noise, a method can be used to eliminate noise phase by overlapping the rising and falling edges of adjacent gate clock signals GCLK1 to GCLK3. For example, the second gate clock signal GCLK2 can rise synchronously with the falling edge of the first gate clock signal GCLK1, and the third gate clock signal GCLK3 can rise synchronously with the falling edge of the second gate clock signal GCLK2. In this case, electromagnetic wave cancellation occurs between adjacent gate clock signals GCLK1 to GCLK3, thereby overcoming or compensating for the noise problem.

[0101] Ideally, the rising and falling edges of adjacent gate clock signals GCLK1 to GCLK3 can be perfectly synchronized. However, signal delays may occur in real-world operating environments. That is, the rising and falling edges of adjacent gate clock signals GCLK1 to GCLK3 may be randomly delayed or advanced relative to each other. Therefore, when synchronization is lost between the rising and falling edges of adjacent gate clock signals GCLK1 to GCLK3, noise is not completely eliminated, and [the remaining issues] are not fully resolved. Figure 12 The residual signal shown is a phase-shifted signal that reflects the phase delay between the gate clock signals GCLK1 and GCLK3. This phase-shifted signal can be applied as a noise signal to the display panel 300.

[0102] The compensation signal generator 360 provides the display panel 300 with a noise compensation signal corresponding to the noise signal generated between the gate clock signals GCLK1 and GCLK3, thereby effectively improving the EMI level.

[0103] In an embodiment, the compensation signal generator 360 includes a detection unit 361 and a reversal unit 362.

[0104] The detection unit 361 can detect noise signals① generated by the gate clock signals GCLK1 to GCLK3. For example, the detection unit 361 can be connected to clock lines CL1 to CL3, and can synthesize the gate clock signals GCLK1 to GCLK3 output through clock lines CL1 to CL3 as target signals, and can detect them. Figure 12 The phase shift signal shown is ①.

[0105] The inversion unit 362 inverts the phase of the phase-shift signal ① output from the detection unit 361 and generates... Figure 13 The inverted signal ② is shown. For example, the inverting unit 362 includes an inverter as an inverting circuit and can generate an inverted signal having the same waveform as the phase-shifted signal but with an inverted phase relative to the phase-shifted signal. Specifically, the phase-shifted signal ① is input to the inverting terminal (-) of the inverting amplifier OP1 that constitutes the inverter, and then the inverted signal ② obtained by reversing the phase of the phase-shifted signal ① by 180° is output to the output terminal of the inverting amplifier OP1.

[0106] The compensation signal generator 360 outputs the inverted signal ② generated by the inverting unit 362 as a noise compensation signal to the display panel 300. For example, the compensation signal generator 360 can output the noise compensation signal ② to the display panel 300 through the gate driver 310 or the demultiplexer array 321.

[0107] like Figure 14 As shown, the noise compensation signal ② provided to the display panel 300 is combined with the noise signal ① applied to the display panel 300 by the level shifter 340, thus effectively eliminating the noise signal ①. As a result, the display device 3 according to the embodiment can effectively attenuate noise caused by EMI, etc., through the compensation signal generator 360.

[0108] Figure 15 and 16 It shows the basis Figure 10 The graph shows the noise reduction effect of the embodiment.

[0109] Figure 15 The noise reduction effect at low frequencies is shown.

[0110] refer to Figure 15 In the phase cancellation method 1501, which simply synthesizes the inverted signal with the noise signal without considering the delay of the inverted signal, the average peak noise is approximately -95.526 V / Hz.

[0111] On the other hand, according to the above embodiment, in method 1502, which detects the phase delay signal from the target signal and uses the inverted signal of the phase delay signal as a noise compensation signal, the average peak noise is approximately -110.39 V / Hz. Therefore, the embodiment demonstrates an EMI improvement effect of approximately 15 dB.

[0112] Figure 16 The noise reduction effect at high frequencies is shown.

[0113] refer to Figure 16 In phase cancellation method 1601, which does not consider the delay of the inverted signal, the average peak noise is approximately -104.19 V / Hz.

[0114] On the other hand, according to the above embodiment, in method 1602, which detects the phase delay signal from the target signal and uses the inverted signal of the phase delay signal as a noise compensation signal, the average peak noise is approximately -110.78 V / Hz. Therefore, the embodiment demonstrates an EMI improvement effect of approximately 2 to 5 dB.

[0115] Even in the high-frequency region of 10MHz or higher, the above embodiments can improve noise reduction.

[0116] Those skilled in the art will understand that embodiments may be embodied in other specific forms without departing from their spirit or essential characteristics. Therefore, the foregoing embodiments and advantages are merely exemplary and should not be construed as limiting the invention. The scope of the embodiments is described by the scope of the appended claims rather than by the foregoing detailed descriptions. All modifications, substitutions, and variations derived from the scope and meaning of the claims and their equivalents should be interpreted as being included within the scope of the embodiments.

[0117] The display device according to the embodiment can use an inverted signal with zero delay relative to the target signal as a noise compensation signal to effectively attenuate noise caused by EMI, etc.

[0118] The display device according to the embodiment effectively removes noise generated by the display panel, thereby improving the resolution of the display device and improving the reliability of the system.

[0119] The embodiments can improve noise reduction in the high-frequency region of 10MHz or higher.

Claims

1. A display device, comprising: A display panel, the display panel including pixels for displaying images; Display panel driving circuit, wherein the display panel driving circuit outputs driving signals for driving the display panel; and A compensation signal generator senses a noise signal generated by the display panel or the display panel driving circuit, and generates a noise compensation signal corresponding to the noise signal. The compensation signal generator includes: A detection unit detects a phase-shifted signal generated by synthesizing a sensed noise signal and a first inverted signal, wherein the first inverted signal is generated by reversing the phase of the sensed noise signal; and The inversion unit generates a second inverted signal by inverting the phase of the phase-shifted signal. The second inverted signal output from the inversion unit is combined with the first inverted signal to generate the noise compensation signal.

2. The display device according to claim 1, in, The compensation signal generator senses the noise signal from the display panel via a sensing line. The first inverted signal has a phase shift component relative to the inverted signal of the noise signal.

3. The display device according to claim 2, wherein, The noise compensation signal is provided to the display panel.

4. The display device according to claim 3, wherein, The noise compensation signal has the same frequency and amplitude as the noise signal, and has an inverted phase relative to the noise signal.

5. The display device according to claim 3, wherein, The compensation signal generator further includes an amplification unit that amplifies or attenuates the second inverted signal output from the inverting unit.

6. The display device according to claim 3, in, The display panel includes touch electrodes for detecting touch input. The display panel driving circuit applies a common voltage to the touch electrode during the display period and applies a touch driving signal to the touch electrode during the touch sensing period.

7. The display device according to claim 6, wherein, The noise signal is an electromagnetic interference (EMI) noise signal sensed from the display panel when a pulsed touch drive signal is applied to the touch electrode.

8. A display device, comprising: A display panel, the display panel including pixels for displaying images; Display panel driving circuit, wherein the display panel driving circuit outputs driving signals for driving the display panel; A level shifter that sequentially outputs multiple clock signals to a clock line; and A compensation signal generator senses a noise signal generated by the plurality of clock signals and generates a noise compensation signal corresponding to the noise signal. The compensation signal generator includes: A detection unit that detects a phase-shift signal generated by synthesizing the plurality of clock signals; and The inversion unit generates the noise compensation signal by inverting the phase of the phase-shifted signal.

9. The display device according to claim 8, wherein, The noise compensation signal is provided to the display panel and combined with the noise signal generated by the plurality of clock signals to eliminate the phase of the noise signal.

10. The display device according to claim 9, wherein, The plurality of clock signals are n pulse signals, which have the same pulse width and a phase delayed by 1 / n periods.

11. The display device according to claim 10, wherein, The rising and falling edges of adjacent clock signals in the plurality of clock signals are delayed or advanced relative to each other at random times.

12. The display device according to claim 9, in, The display panel driving circuit includes: A gate driver that applies a gate signal to the pixel via a gate line; A data driver that applies data signals to the pixel via a data line; and A demultiplexer array, disposed between the data driver and the data line. The clock signal is provided to at least one of the gate driver and the demultiplexer array.

13. A display device, comprising: The display panel includes pixels and touch electrodes formed by slabifying the electrodes of the pixels into a predetermined size; A touch driver that applies a drive signal to the touch electrode during a touch sensing period and detects touch input based on a sensing signal received in response to the drive signal; and A compensation signal generator senses a noise signal generated by the display panel and generates a noise compensation signal corresponding to the noise signal. The compensation signal generator includes: A detection unit detects a phase-shift signal generated by synthesizing a sensed noise signal and a first inverted signal, wherein the first inverted signal is the inverted signal of the sensed noise signal; and The inversion unit generates a second inverted signal by inverting the phase of the phase-shifted signal. The second inverted signal output from the inversion unit is combined with the first inverted signal to generate the noise compensation signal.

14. The display device according to claim 13, wherein, The detection unit senses the noise signal from the display panel via a sensing line.

15. The display device according to claim 13, wherein, The first inverted signal has a phase shift component relative to the inverted signal of the noise signal generated by the display panel.

16. The display device according to claim 13, wherein, The noise compensation signal is output to the display panel.

17. A display device, comprising: A display panel, wherein pixels are provided on the display panel; A level shifter that sequentially outputs multiple clock signals to a clock line; A gate driver that generates a gate signal based on the plurality of clock signals and applies the gate signal to the pixel through a gate line; A data driver that applies data signals to the pixel via a data line; and A compensation signal generator senses a noise signal generated by the plurality of clock signals and generates a noise compensation signal corresponding to the noise signal. The compensation signal generator includes: A detection unit that detects a phase-shift signal generated by synthesizing the plurality of clock signals; and The inversion unit generates the noise compensation signal by inverting the phase of the phase-shifted signal.

18. The display device according to claim 17, wherein, The plurality of clock signals are n pulse signals, which have the same pulse width and a phase delayed by 1 / n periods.

19. The display device according to claim 18, wherein, The rising and falling edges of adjacent clock signals in the plurality of clock signals are delayed or advanced relative to each other at random times.

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