Display panel, driving method thereof, and display device

Abstract

Embodiments of the present application provide a display panel and a driving method thereof and a display device, and relate to the field of display, and reduce power consumption when displaying in partitions. The display panel comprises a shift register circuit comprising a shift unit, the shift unit comprising a first output module and a control module; a first mode, the display area comprising a first partition refreshed at a first frequency and a second partition refreshed at a second frequency, the first frequency being greater than the second frequency, the shift register circuit comprising a first unit group and a second unit group; in the first mode, in a partial frame, the first unit group and the second unit group output a scanning active level, in the partial frame, the control module of the first shift unit provides a non-enable level to the first node at least after the first unit group outputs the scanning active level, the first shift unit is located in the second unit group and adjacent to the first unit group; the time length of one frame is t, and f is a reference frequency, the reference frequency being greater than or equal to the first frequency and being in an integer multiple relationship with the first frequency and the second frequency.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. [Background Technology]

[0002] In some application scenarios, the display panel needs to display different images in sections. For example, when a user is watching a short video, often only the top third to half of the screen is used to display the video, while the bottom screen is used to display comments. Since the video and comment images have different refresh rate requirements, maintaining a high refresh rate for the entire display panel would result in wasted power consumption. [Summary of the Invention]

[0003] In view of this, embodiments of the present invention provide a display panel and a display device for reducing power consumption when displaying in partitioned mode.

[0004] On one hand, embodiments of the present invention provide a display panel, including:

[0005] Display area and non-display area;

[0006] Pixel circuitry is located in the display area;

[0007] A shift register circuit, located in the non-display area, includes multiple cascaded shift units. Each shift unit includes a first output module and a control module. The first output module is used to output a scan valid level or a scan invalid level in response to the enable level of the first node. The control module is used to provide an invalid level to the first node.

[0008] The display panel has a first mode. In the first mode, the display area includes a first partition and a second partition adjacent in a first direction. The first partition refreshes data at a first frequency, and the second partition refreshes data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit includes a first unit group and a second unit group. The first unit group is electrically connected to the pixel circuit in the first partition, and the second unit group is electrically connected to the pixel circuit in the second partition. The shift unit adjacent to the first unit group in the second unit group is a first shift unit.

[0009] In the first mode, in some frames, the first unit group and the second unit group output the scan valid level in sequence, and in some frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level;

[0010] The duration of one frame is t. f is a reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of both the first frequency and the second frequency.

[0011] On the other hand, embodiments of the present invention provide a driving method for a display panel.

[0012] The display panel includes:

[0013] Display area and non-display area;

[0014] Pixel circuitry is located in the display area;

[0015] A shift register circuit, located in the non-display area, includes multiple cascaded shift units. Each shift unit includes a first output module and a control module. The first output module is used to output a scan valid level or a scan invalid level in response to the enable level of the first node. The control module is used to provide an invalid level to the first node.

[0016] The display panel has a first mode. In the first mode, the display area includes a first partition and a second partition adjacent in a first direction. The first partition refreshes data at a first frequency, and the second partition refreshes data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit includes a first unit group and a second unit group. The first unit group is electrically connected to the pixel circuit in the first partition, and the second unit group is electrically connected to the pixel circuit in the second partition. The shift unit adjacent to the first unit group in the second unit group is a first shift unit.

[0017] The driving method includes: in the first mode, in some frames, controlling the first unit group and the second unit group to output the scan valid level sequentially; in some frames, controlling the control module in the first shift unit to provide the disabled level to the first node at least after the first unit group outputs the scan valid level.

[0018] The duration of one frame is t. f is a reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of both the first frequency and the second frequency.

[0019] In another aspect, embodiments of the present invention provide a display device including the aforementioned display panel.

[0020] One of the above technical solutions has the following beneficial effects:

[0021] Based on the display panel provided in the embodiments of the present invention, in the first mode where the display panel needs to perform partitioned display, in a portion of the frames, the shift units in the first unit group and the second unit group sequentially output scan valid levels to control both the first partition and the second partition to perform data refresh. In another portion of the frames, after the shift unit in the first unit group outputs the scan valid level, the control module in the first shift unit provides a non-enable level to the first node, which prevents the first output module of the first shift unit from continuing to output the scan valid level. This is equivalent to cutting off the shift path from the first unit group to the second unit group. In this way, this portion of the frames will serve as a blank period for the second partition to lengthen the data refresh cycle of the second partition, thereby reducing the data refresh frequency of the second partition and enabling the second partition to achieve low-frequency drive.

[0022] In summary, by incorporating a control module within the shift unit, this embodiment of the invention can cut off the shift path from the first unit group to the second unit group in certain frames of the first mode. This prevents the second unit group from outputting a valid scan level during these frames, thereby preventing the second partition from refreshing data and reducing its refresh rate. Consequently, when different screens need to be displayed in different partitions, the data refresh rate can be adjusted according to the content displayed in each partition, avoiding high-frequency driving of the entire screen and thus preventing power consumption waste.

[0023] Furthermore, the display panel provided in this embodiment of the invention does not require changes to the overall architecture and driving timing of the original shift register circuit when implementing segmented frequency display. It only requires adding a control module capable of providing a non-enable level to the first node in the shift unit, and correspondingly increasing the signal timing for driving the control module. The control method is simple and easy to implement. In addition, this embodiment of the invention can flexibly adjust the frequency magnitude of the first and second partitions and the position of their boundary line. For example, regardless of how the boundary line position changes, it is only necessary to have the correspondingly adjusted first shift unit cut off the shift path of the first unit group and the second unit group within a portion of the frame. [Attached Image Description]

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0026] Figure 2This is a schematic diagram of a shift register circuit provided in an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of a circuit structure of a shift unit provided in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a partition of a display panel in a first mode provided in an embodiment of the present invention;

[0029] Figure 5 for Figure 4 A corresponding timing diagram;

[0030] Figure 6 This is a schematic diagram of a partition of a display panel provided in an embodiment of the present invention under a first type of first sub-mode;

[0031] Figure 7 for Figure 6 A corresponding timing diagram;

[0032] Figure 8 This is a schematic diagram of another partition of the display panel in the first sub-mode provided in an embodiment of the present invention;

[0033] Figure 9 for Figure 8 A corresponding timing diagram;

[0034] Figure 10 This is a schematic diagram of a partitioning of a display panel in the third type of first sub-mode provided in an embodiment of the present invention;

[0035] Figure 11 for Figure 10 A corresponding timing diagram;

[0036] Figure 12 This is a schematic diagram of a partitioning of a display panel in the fourth category, first sub-mode, provided in an embodiment of the present invention.

[0037] Figure 13 for Figure 12 A corresponding timing diagram;

[0038] Figure 14 This is a schematic diagram of a partition of the display panel provided in the second sub-mode according to an embodiment of the present invention;

[0039] Figure 15 for Figure 14 A corresponding timing diagram;

[0040] Figure 16 This is a schematic diagram of a partition of a display panel provided in an embodiment of the present invention;

[0041] Figure 17 This is another schematic diagram of the partitioning of the display panel provided in an embodiment of the present invention;

[0042] Figure 18 This is a schematic diagram of another structure of the shift register circuit provided in an embodiment of the present invention;

[0043] Figure 19 This is a schematic diagram of another circuit structure of the shifting unit provided in an embodiment of the present invention;

[0044] Figure 20 for Figure 18 A corresponding timing diagram;

[0045] Figure 21 for Figure 16 A corresponding timing diagram;

[0046] Figure 22 for Figure 17 A corresponding timing diagram;

[0047] Figure 23 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0048] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0050] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0051] It should be understood that although the terms "first" and "second" may be used to describe partitions in embodiments of the present invention, these partitions should not be limited to these terms. These terms are only used to distinguish partitions from each other. For example, without departing from the scope of embodiments of the present invention, a first partition may also be referred to as a second partition, and similarly, a second partition may also be referred to as a first partition.

[0052] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0053] This invention provides a display panel, such as... Figures 1-3 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a shift register circuit 2 provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a circuit structure of a shift unit 3 provided in an embodiment of the present invention. The display panel includes a display area DA and a non-display area NA. The display area DA is the screen display area, and the non-display area NA is the border area surrounding the display area DA. The display panel also includes a pixel circuit 1 and a shift register circuit 2. The pixel circuit 1 is located in the display area DA, and the shift register circuit 2 is located in the non-display area NA. The shift register circuit 2 includes multiple cascaded shift units 3. The shift unit 3 includes a first output module 4 and a control module 5. The first output module 4 is used to output a scan valid level or a scan invalid level in response to the enable level of the first node N1, and the control module 5 is used to provide an invalid level to the first node N1.

[0054] It should be noted that the scan active level refers to the level that controls the data writing transistor in pixel circuit 1 to conduct. When the data writing transistor is conducting, if there is data voltage transmitted on the data line, the data voltage can be written to the driving transistor, causing pixel circuit 1 to refresh the data. Taking the example that both the transistors in pixel circuit 1 and shift unit 3 are N-type transistors, in this case, the enable level and scan active level are both high, and the disable level and scan inactive level are both low. The first output module 4 is used to output a high level or a low level in response to the high level of the first node N1; the control module 5 is used to provide a low level to the first node N1. When the control module 5 provides a low level to the first node N1, the first output module 4 cannot output a high level.

[0055] like Figure 4 As shown, Figure 4This is a schematic diagram of a display panel in a first mode FM provided in an embodiment of the present invention. The display panel has a first mode FM. In the first mode FM, the display area DA includes a first partition DA1 and a second partition DA2 that are adjacent in a first direction x. The first partition DA1 refreshes data at a first frequency, and the second partition DA2 refreshes data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit 2 includes a first unit group 6 and a second unit group 7. The shift unit 3 in the first unit group 6 is electrically connected to the pixel circuit 1 in the first partition DA1. Figure 4 (Not shown in the diagram), the shifting unit 3 in the second unit group 7 is electrically connected to the pixel circuit 1 in the second partition DA2. Figure 4 (Not shown in the diagram), the shift unit 3 in the second unit group 7 that is adjacent to the first unit group 6 is the first shift unit 8.

[0056] That is, in the first mode FM, the display area DA of the display panel is divided vertically into at least a first partition DA1 and a second partition DA2. The first partition DA1 is driven at a higher frequency, and the second partition DA2 is driven at a lower frequency. Correspondingly, the shift register circuit 2 is also divided into at least a first unit group 6 and a second unit group 7. The first unit group 6 is used to output a scan valid level to the pixel circuit 1 in the first partition DA1, and the second unit group 7 is used to output a scan valid level to the pixel circuit 1 in the second partition DA2.

[0057] In the first mode FM, in some frames, the first unit group 6 and the second unit group 7 sequentially output scan valid levels. In other frames, the control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level. The duration of one frame is t. f is a reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of both the first and second frequencies. For example, if the first frequency is 120Hz and the second frequency is 60Hz, the reference frequency can be set to 120Hz; or if the first frequency is 120Hz and the second frequency is 80Hz, the reference frequency can be set to 240Hz.

[0058] It should be noted that the control module 5 in the first shift unit 8 providing a disabled level to the first node N1 after the first unit group 6 outputs a valid scan level includes at least the following two cases: First, after the first unit group 6 outputs a valid scan level, the control module 5 in the first shift unit 8 starts providing a disabled level to the first node N1; Second, before the first unit group 6 outputs a valid scan level, the control module 5 in the first shift unit 8 starts providing a disabled level to the first node N1, and the process of the control module 5 providing a disabled level to the first node N1 continues until after the first unit group 6 outputs a valid scan level.

[0059] Based on the display panel provided in this embodiment of the invention, in the first mode FM where the display panel needs to perform partitioned display, in some frames, the shift units 3 in the first unit group 6 and the second unit group 7 sequentially output scan valid levels, controlling the first partition DA1 and the second partition DA2 to perform data refresh. In other frames, after the shift unit 3 in the first unit group 6 outputs the scan valid level, the control module 5 in the first shift unit 8 provides a non-enable level to the first node N1, which prevents the first output module 4 of the first shift unit 8 from continuing to output the scan valid level. This is equivalent to cutting off the shift path from the first unit group 6 to the second unit group 7. In this way, this part of the frame will be used as a blank period for the second partition DA2 to lengthen the data refresh cycle of the second partition DA2, thereby reducing the data refresh frequency of the second partition DA2 and enabling the second partition DA2 to achieve low-frequency drive.

[0060] The embodiments of this invention will be described using the example of enabling and scanning active levels being high. For example, assuming the reference frequency and the first frequency are 120Hz and the second frequency is 60Hz, then one frame time is 8.33ms. In odd-numbered frames, the first unit group 6 and the second unit group 7 output high levels sequentially, controlling the first partition DA1 and the second partition DA2 to refresh data sequentially. In even-numbered frames, the first unit group 6 outputs high levels, and the second unit group 7 does not output high levels, only controlling the first partition DA1 to refresh data, while the second partition DA2 does not refresh data. Thus, the first partition DA1 refreshes data once every 8.33ms, while the second partition DA2 refreshes data only once every 16.88ms.

[0061] In summary, by incorporating a control module 5 within the shift unit 3, this embodiment of the invention can utilize the control module 5 in the first shift unit 8 to cut off the shift path from the first unit group 6 to the second unit group 7 in certain frames under the first mode FM. This prevents the second unit group 7 from outputting a valid scan level during these frames, thereby preventing the second partition DA2 from refreshing data and lowering its refresh rate. In this way, when different screens need to be displayed in different partitions, the data refresh rate can be adjusted according to the content displayed in each partition, avoiding high-frequency driving of the entire screen and thus preventing power consumption waste.

[0062] Furthermore, the display panel provided in this embodiment of the invention does not require changes to the overall architecture and driving timing of the original shift register circuit 2 when implementing segmented frequency display. It only requires adding a control module 5 capable of providing a non-enable level to the first node N1 in the shift unit 3, and correspondingly increasing the signal timing for driving the control module 5. The control method is simple and easy to implement. In addition, this embodiment of the invention can flexibly adjust the frequency magnitude of the first partition DA1 and the second partition DA2, as well as the position of their boundary line. For example, combining... Figures 2-5 When the control module 5 in multiple shift units 3 is electrically connected to a control signal line Greset, regardless of how the boundary line position changes, that is, how the position of the first shift unit 8 changes, it is only necessary to adjust the time when the control signal line Greset provides the conduction level so that the first shift unit 8 can cut off the shift path of the first unit group 6 and the second unit group 7 within a certain frame.

[0063] Furthermore, the inventors verified the technical solution of the embodiments of the present invention. When the first partition DA1 and the second partition DA2 each occupy half of the screen, and the first frequency is 120Hz and the second frequency is 30Hz, the prior art requires full-screen data refresh at 120Hz, while the embodiments of the present invention can refresh the first partition DA1 and the second partition DA2 at 120Hz and 30Hz respectively. When displaying a white screen, the prior art generates a digital power consumption (image processing power consumption generated by internal IC calculations) of 85mW and an analog power consumption (power consumption output by the IC), totaling 190mW, while the present invention generates a digital power consumption of 62.6mW, an analog power consumption of 77.4mW, and a total power consumption of 140mW, reducing power consumption by 26.3%. When displaying a color bar image, the existing technology generates 100.2mW of digital power consumption, 133.5mW of analog power consumption, and a total power consumption of 233.7mW. In contrast, the present invention generates 72.1mW of digital power consumption, 95mW of analog power consumption, and a total power consumption of 167.1mW, representing a power consumption reduction of 28.5%. When displaying a color image image, the existing technology generates 144.7mW of digital power consumption, 119.4mW of analog power consumption, and a total power consumption of 264mW. In contrast, the present invention generates 99.8mW of digital power consumption, 86.3mW of analog power consumption, and a total power consumption of 186.1mW, representing a power consumption reduction of 29.5%. It is evident that by employing the technical solution provided in the embodiments of the present invention, the power consumption generated by the display panel can be significantly reduced.

[0064] In one feasible implementation, combined with Figure 4 and Figure 5 The first mode FM includes at least one first sub-mode FM1. In the first sub-mode FM1, f1 = x1 × f2, where f1 is the first frequency, f2 is the second frequency, x1 is an integer and x1 ≥ 2, and the reference frequency is the first frequency. That is, in the first sub-mode FM1, the first frequency is an integer multiple of the second frequency, and the reference frequency is set to be the same as the first frequency. For example, the reference frequency and the first frequency are 120Hz, and the second frequency is 60Hz, 30Hz, 15Hz, etc., with corresponding x1 values ​​of 2, 4, 8, etc.

[0065] In the first sub-mode FM1, the scanning direction of the display area DA is from the first partition DA1 to the second partition DA2. For each adjacent x1 frame, in one of the frames, the first unit group 6 and the second unit group 7 sequentially output the scan valid level. In the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides the first node N1 with the disabled level at least after the first unit group 6 outputs the scan valid level.

[0066] Taking a reference frequency and a first frequency of 120Hz, and a second frequency of 60Hz (x1=2) as an example, combined with... Figure 4and Figure 5 , Figure 5 for Figure 4 One corresponding timing diagram shows that for every two adjacent frames, in one frame, the shift units 3 (corresponding to Gout_1 to Gout_z) in the first unit group 6 and the second unit group 7 output high levels in sequence. In the other frame, the shift units 3 (corresponding to Gout_1 to Gout_i) in the first unit group 6 output high levels in sequence. The first shift unit 8 (corresponding to Gout_i+1) cuts off the shift path from the first unit group 6 to the second unit group 7, so that the shift units 3 (corresponding to Gout_i+1 to Gout_z) in the second unit group 7 do not continue to output high levels.

[0067] It should be noted that the nth frame F_n shown in the accompanying drawings of the embodiments of the present invention can be either an odd-numbered frame or an even-numbered frame, and the present invention does not impose any restrictions on this.

[0068] In the first sub-mode FM1, when the first frequency and the second frequency are set to be integer multiples of each other, compared to setting the reference frequency to be two or three times the first frequency, directly setting the reference frequency to be the same as the first frequency can avoid the reference frequency being too high, thereby avoiding excessive demands on the frequency design of the display panel.

[0069] In one feasible implementation, combined with Figure 6 and Figure 7 At least one first sub-mode FM1 includes a first type of first sub-mode FM1-1. Under the first type of first sub-mode FM1-1, the display area DA also includes a third partition DA3 adjacent to the second partition DA2 in the first direction x. The first partition DA1 and the third partition DA3 are located on opposite sides of the second partition DA2. The scanning direction of the display area DA is from the first partition DA1 to the third partition DA3. The third partition DA3 refreshes data at a third frequency, f1 = k1 × x1 × f3, where f3 is the third frequency, k1 is an integer and k1 ≥ 2. That is, the third frequency is less than the second frequency, and the second frequency and the third frequency are also integer multiples of each other. The shift register circuit 2 also includes a third unit group 9, which is electrically connected to the pixel circuit 1 in the third partition DA3. Figure 6 (Not shown in the diagram), the shift unit 3 in the third unit group 9, which is adjacent to the second unit group 7, is the second shift unit 10.

[0070] In the first sub-mode FM1-1 of the first type, for each adjacent k1×x1 frame, within one of those frames, after the second unit group 7 outputs the scan valid level, the third unit group 9 sequentially outputs the scan valid level. Within one of those k1-1 frames, the control module 5 in the second shift unit 10 provides an enable level to the first node N1 at least after the second unit group 7 outputs the scan valid level.

[0071] It should be noted that the control module 5 in the second shift unit 10 providing a disabled level to the first node N1 after the second unit group 7 outputs a valid scan level includes at least the following two cases: First, after the second unit group 7 outputs a valid scan level, the control module 5 in the second shift unit 10 starts providing a disabled level to the first node N1; Second, before the second unit group 7 outputs a valid scan level, the control module 5 in the second shift unit 10 starts providing a disabled level to the first node N1, and the process of the control module 5 providing a disabled level to the first node N1 continues until after the second unit group 7 outputs a valid scan level.

[0072] It is understandable that, since the first frequency is x1 times the second frequency, in every adjacent k1×x1 frames, after the first unit group 6 outputs a scan valid level, the second unit group 7 will sequentially output a scan valid level. In one of these k1 frames, after the second unit group 7 outputs a scan valid level, the third unit group 9 continues to output a scan valid level. In the remaining k1-1 frames of this k1 frame, the control module 5 in the second shift unit 10 cuts off the shift path from the second unit group 7 to the third unit group 9, so that the third unit group 9 no longer outputs a scan valid level.

[0073] Taking a first frequency and reference frequency of 120Hz, a second frequency of 60Hz, and a third frequency of 30Hz (x1=2, k1=2) as an example, Figure 6 and Figure 7 As shown, Figure 6 This is a schematic diagram of a partition of the display panel provided in an embodiment of the present invention under the first sub-mode FM1-1 of the first type. Figure 7 for Figure 6A corresponding timing diagram, under the first sub-mode FM1-1 of the first type, for the four adjacent frames n-th frame F_n, (n+1)-th frame F_n+1, (n+2)-th frame F_n+2, and (n+3)-th frame F_n+3, in frames n-th frame F_n and (n+2)-th frame F_n+2, the shift units 3 (corresponding to Gout_1 to Gout_p) in the first unit group 6 and the second unit group 7 sequentially output high levels. Specifically, in frame n-th frame F_n, the shift units 3 (corresponding to Gout_1 to Gout_p) in the first unit group 6 and the second unit group 7 sequentially output high levels. After the leveling is completed, shift unit 3 (corresponding to Gout_p+1 to Gout_z) in the third unit group 9 continues to output high level sequentially. In frame n+2 F_n+2, after shift unit 3 (corresponding to Gout_1 to Gout_p) in the first unit group 6 and the second unit group 7 output high level sequentially, the second shift unit 10 (corresponding to Gout_p+1) will cut off the shift path from the second unit group 7 to the third unit group 9, so that shift unit 3 (corresponding to Gout_p+1 to Gout_z) in the third unit group 9 will no longer output scan valid level. In frames n+1 (F_n+1) and n+3 (F_n+3), shift units 3 (corresponding to Gout_1 to Gout_i) in the first unit group 6 output high levels sequentially. However, the first shift unit 8 (corresponding to Gout_i+1) cuts off the shift path from the first unit group 6 to the second unit group 7, causing shift units 3 (corresponding to Gout_i+1 to Gout_p) in the second unit group 7 to stop outputting high levels. Consequently, shift units 3 (corresponding to Gout_p+1 to Gout_z) in the third unit group 9 also do not output scan valid levels.

[0074] That is, in these four adjacent frames, the first partition DA1 was refreshed four times, the second partition DA2 was refreshed twice, and the third partition DA3 was refreshed only once, thus making the frequency of the first partition DA1 twice that of the second partition DA2 and four times that of the third partition DA3.

[0075] The above configuration allows the display panel to perform at least three-zone frequency display in the first sub-mode FM1-1 of the first category. In this mode, the frequency of each of the three zones decreases progressively. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of applications. For example, one zone can display video at a high frequency, another at a low frequency to display commentary, and yet another at an ultra-low frequency to display static images such as black borders. Furthermore, this display mode allows for more precise control over the frequency at different locations on the display area DA, thereby minimizing power consumption.

[0076] In one feasible implementation, combined with Figure 8 and Figure 9At least one first sub-mode FM1 includes a second type of first sub-mode FM1-2. In the second type of first sub-mode FM1-2, the display area DA also includes a fourth partition DA4 adjacent to the first partition DA1 in the first direction x. The fourth partition DA4 and the second partition DA2 are located on opposite sides of the first partition DA1. The scanning direction of the display area DA is from the fourth partition DA4 to the second partition DA2. The fourth partition DA4 refreshes data at a fourth frequency, f1 = k2 × x1 × f4, where f4 is the fourth frequency, k2 is an integer and k2 ≥ 2. That is, the fourth frequency is less than the second frequency, and the second frequency and the fourth frequency are integer multiples of each other. The shift register circuit 2 also includes a fourth unit group 11. The shift unit 3 in the fourth unit group 11 is electrically connected to the pixel circuit 1 in the fourth partition DA4. Figure 8 (Not shown in the image).

[0077] In the second type of first sub-mode FM1-2, for each adjacent k2×x1 frame, in each frame, the fourth unit group 11 and the first unit group 6 sequentially output scan valid levels. In the x1 frame, after the first unit group 6 outputs the scan valid level, the second unit group 7 sequentially outputs the scan valid level. In the remaining (k2-1)×x1 frames, the control module 5 in the first shift unit 8 provides an enable level to the first node N1 at least after the first unit group 6 outputs the scan valid level. Furthermore, for each adjacent k2×x1 frame, the fourth partition DA4 is written with a data voltage in one of the frames, and the fourth partition DA4 is not written with a data voltage in the remaining k2×x1-1 frames.

[0078] It should be noted that, in the embodiments of the present invention, the fact that a certain partition does not write data voltage in a certain frame means that, in this part of the frame, although the unit group corresponding to the partition outputs a scan valid level to the pixel circuit 1 in the partition and controls the data writing transistor to be turned on, the data line Data does not provide data voltage to this part of the pixel circuit 1. Therefore, the driving transistor of the pixel circuit 1 in the partition cannot write data voltage, and the partition will not be refreshed.

[0079] Taking a first frequency and reference frequency of 120Hz, a second frequency of 60Hz, and a fourth frequency of 30Hz (x1=2, k2=2) as an example, Figure 8 and Figure 9 As shown, Figure 8 This is a schematic diagram of another partition of the display panel provided in the first sub-mode FM1 according to an embodiment of the present invention. Figure 9 for Figure 8A corresponding timing diagram shows that, under the second type of first sub-mode FM1-2, for the four adjacent frames n-th frame F_n, (n+1)-th frame F_n+1, (n+2)-th frame F_n+2, and (n+3)-th frame F_n+3, in each frame, the shift units 3 (corresponding to Gout_1 to Gout_p) in the fourth unit group 11 and the first unit group 6 sequentially output a high level. Specifically, in frames n-th frame F_n and (n+2)-th frame F_n+2, after the shift units 3 (corresponding to Gout_1 to Gout_p) in the fourth unit group 11 and the first unit group 6 output a high level... In the second unit group 7, shift unit 3 (corresponding to Gout_p+1 to Gout_z) continues to output high level sequentially. In the (n+1)th frame F_n+1 and the (n+3)th frame F_n+3, after shift unit 3 (corresponding to Gout_1 to Gout_p) in the fourth unit group 11 and the first unit group 6 output high level, the first shift unit 8 (corresponding to Gout_p+1) cuts off the shift path from the first unit group 6 to the second unit group 7, so that shift unit 3 (corresponding to Gout_p+1 to Gout_z) in the second unit group 7 no longer outputs high level. Furthermore, in the four adjacent frames—the nth frame F_n, the (n+1)th frame F_n+1, the (n+2)th frame F_n+2, and the (n+3)th frame F_n+3—although the shift unit 3 (corresponding to Gout_1 to Gout_i) in the fourth unit group 11 of each frame outputs a high level to the pixel circuit 1 in the fourth partition DA4, only in one frame does the data line Data provide data voltage to the pixel circuit 1 in the fourth partition DA4, enabling the fourth partition DA4 to perform data refresh. In the other three frames, the data line Data does not provide data voltage to the pixel circuit 1 in the fourth partition DA4. In these three frames, the pixel circuit 1 in the fourth partition DA4 cannot write data voltage, and the fourth partition DA4 cannot perform data refresh. For example, see... Figure 9 The fourth partition DA4 can write data voltage in frame n F_n, but not in frames n+1 F_n+1, n+2 F_n+2, and n+3 F_n+3. Alternatively, the fourth partition DA4 can also write data voltage in frame n+1 F_n+1, but not in frames n F_n, n+2 F_n+2, and n+3 F_n+3.

[0080] That is, in these four adjacent frames, the first partition DA1 was refreshed four times, the second partition DA2 was refreshed twice, and the third partition DA3 was refreshed only once, thus making the frequency of the first partition DA1 twice that of the second partition DA2 and four times that of the fourth partition DA4.

[0081] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the second sub-mode FM1-2. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of applications. For example, the central high-frequency zone can display video footage, the upper low-frequency zone can display static images such as black borders, and the lower low-frequency zone can display commentary. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the DA array in the display area, thereby minimizing power consumption.

[0082] In one feasible implementation, combined with Figure 10 and Figure 11 At least one first sub-mode FM1 includes a third type of first sub-mode FM1-3. In the third type of first sub-mode FM1-3, the display area DA also includes a fifth partition DA5 adjacent to the first partition DA1 in the first direction x. The fifth partition DA5 and the second partition DA2 are located on opposite sides of the first partition DA1. The scanning direction of the display area DA is from the fifth partition DA5 to the second partition DA2. The fifth partition DA5 is refreshed with a fifth frequency, f5 = k3 × f2, where f5 is the fifth frequency, k3 is an integer and k3 ≥ 2. That is, the fifth frequency is greater than the second frequency and the fifth frequency is an integer multiple of the second frequency. The shift register circuit 2 also includes a fifth unit group 12. The shift unit 3 in the fifth unit group 12 is electrically connected to the pixel circuit 1 in the fifth partition DA5. Figure 10 (Not shown in the image).

[0083] In the third type, first sub-mode FM1-3, for each adjacent x1 frame, in each frame, the fifth unit group 12 and the first unit group 6 sequentially output scan valid levels. In one of these frames, after the first unit group 6 outputs the scan valid level, the second unit group 7 sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level. Furthermore, for each adjacent x1 frame, in any k3 adjacent frames, data voltage is written to the fifth partition DA5 in one of these frames, and no data voltage is written to the fifth partition DA5 in the remaining k3-1 frames.

[0084] Taking a first frequency and reference frequency of 120Hz, a second frequency of 30Hz, and a fifth frequency of 60Hz (x1=4, k3=2) as an example, Figure 10 and Figure 11 As shown, Figure 10 This is a schematic diagram of a display panel in the third type of first sub-mode FM1-3 provided in an embodiment of the present invention. Figure 11 for Figure 10A corresponding timing diagram shows that, under the third type of first sub-mode FM1-3, for the four adjacent frames n-th frame F_n, (n+1)-th frame F_n+1, (n+2)-th frame F_n+2, and (n+3)-th frame F_n+3, in each frame, the shift units 3 (corresponding to Gout_1 to Gout_p) in the fifth unit group 12 and the first unit group 6 sequentially output high levels. Specifically, in frame n-th frame F_n, after the shift units 3 (corresponding to Gout_1 to Gout_p) in the fifth unit group 12 and the first unit group 6 sequentially output high levels, the shift unit in the second unit group 7... 3 (corresponding to Gout_p+1 to Gout_z) continues to output the scan valid level. In frames (n+1), (n+2), and (n+3), after the shift units 3 (corresponding to Gout_1 to Gout_p) in the fifth unit group 12 and the first unit group 6 sequentially output high levels, the first shift unit 8 (corresponding to Gout_p+1) cuts off the shift path between the first unit group 6 and the second unit group 7, and the shift units 3 (corresponding to Gout_p+1 to Gout_z) in the second unit group 7 no longer output high levels. Furthermore, for the four adjacent frames (n-th frame F_n, (n+1), (n+2), and (n+3), although the shift units 3 (corresponding to Gout_1 to Gout_i) in the fifth unit group 12 output high levels to the pixel circuit 1 in the fifth partition DA5 within each frame, see... Figure 11 Data line Data in frame n (F_n) and frame n+2 (F_n+2) provides data voltage to pixel circuit 1 in the fifth partition DA5, enabling data refresh in the fifth partition DA5. Data line Data in frame n+1 (F_n+1) and frame n+3 (F_n+3) does not provide data voltage to pixel circuit 1 in the fifth partition DA5, preventing data refresh in the fifth partition DA5. Alternatively, data line Data in frame n (F_n+1) and frame n+3 (F_n+3) provides data voltage to pixel circuit 1 in the fifth partition DA5, enabling data refresh in the fifth partition DA5. Data line Data in frame n (F_n) and frame n+2 (F_n) does not provide data voltage to pixel circuit 1 in the fifth partition DA5, preventing data refresh in the fifth partition DA5.

[0085] That is, in these four adjacent frames, the first partition DA1 was refreshed four times, the second partition DA2 was refreshed once, and the third partition DA3 was refreshed twice, thus making the frequency of the first partition DA1 four times that of the second partition DA2 and twice that of the fifth partition DA5.

[0086] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the third category, first sub-mode FM1-3. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of application scenarios. For example, the central zone can display video footage at high frequency, the upper zone can display commentary at low frequency, and the lower zone can display static images such as black borders at ultra-low frequency. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the display area's DA, thereby minimizing power consumption.

[0087] In one feasible implementation, combined with Figure 12 and Figure 13 At least one first sub-mode FM1 includes a fourth type of first sub-mode FM1-4. In the fourth type of first sub-mode FM1-4, the display area DA also includes a sixth partition DA6 adjacent to the first partition DA1 in the first direction x. The sixth partition DA6 and the second partition DA2 are located on opposite sides of the first partition DA1, and the scanning direction of the display area DA is from the sixth partition DA6 to the second partition DA2. The sixth partition DA6 is refreshed with data at a second frequency. The shift register circuit 2 also includes a sixth unit group 13. The shift unit 3 in the sixth unit group 13 is electrically connected to the pixel circuit 1 in the sixth partition DA6. Figure 12 (Not shown in the image).

[0088] In the fourth category, first sub-mode FM1-4, for each adjacent x1 frame, in each frame, the sixth unit group 13 and the first unit group 6 sequentially output scan valid levels. In one of these frames, after the first unit group 6 outputs the scan valid level, the second unit group 7 sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides an enable level to the first node N1 at least after the first unit group 6 outputs the scan valid level. Furthermore, for each adjacent x1 frame, data voltage is written to the sixth partition DA6 in one of these frames, and no data voltage is written to the sixth partition DA6 in the remaining x1-1 frames.

[0089] Taking a first frequency and a reference frequency of 120Hz, and a second frequency of 60Hz (x1=2) as an example, Figure 12 and Figure 13 As shown, Figure 12 This is a schematic diagram of a display panel in the fourth category, first sub-mode FM1-4, provided in an embodiment of the present invention. Figure 13 for Figure 12A corresponding timing diagram, under the fourth type first sub-mode FM1-4, taking the two adjacent frames n-th frame F_n and n+1-th frame F_n+1 as examples, in frame n-th frame F_n and frame n+1-th frame F_n+1, the shift units 3 (corresponding to Gout_1~Gout_p) in the sixth unit group 13 and the first unit group 6 sequentially output high levels. Specifically, after the shift units 3 (corresponding to Gout_1~Gout_p) in the sixth unit group 13 and the first unit group 6 sequentially output high levels in frame n-th frame F_n, the second unit... In group 7, shift unit 3 (corresponding to Gout_p+1 to Gout_z) continues to output a scan valid level. In frame (n+1) F_n+1, after shift units 3 (corresponding to Gout_1 to Gout_p) in the sixth unit group 13 and the first unit group 6 sequentially output high levels, the first shift unit 8 (corresponding to Gout_p+1) cuts off the shift path between the first unit group 6 and the second unit group 7, and shift units 3 (corresponding to Gout_p+1 to Gout_z) in the second unit group 7 no longer output high levels. Furthermore, for adjacent frames (n-th frame) F_n and (n+1) F_n+1, although shift units 3 (corresponding to Gout_1 to Gout_i) in the sixth unit group 13 output high levels to pixel circuit 1 in the sixth partition DA6 in each frame, see... Figure 13 In frame n, data line Data provides data voltage to pixel circuit 1 in the sixth partition DA6 only within frame n_n, enabling the sixth partition DA6 to perform data refresh. In frame n+1, data line Data does not provide data voltage to pixel circuit 1 in the sixth partition DA6, preventing the sixth partition DA6 from performing data refresh. Alternatively, data line Data provides data voltage to pixel circuit 1 in the sixth partition DA6 only within frame n+1, enabling the sixth partition DA6 to perform data refresh. In frame n, data line Data does not provide data voltage to pixel circuit 1 in the sixth partition DA6, preventing the sixth partition DA6 from performing data refresh.

[0090] That is, in two adjacent frames, the first partition DA1 is refreshed twice, while the second partition DA2 and the sixth partition DA6 are refreshed once each, thus making the frequency of the first partition DA1 twice that of the second partition DA2 and the sixth partition DA6.

[0091] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the fourth category, first sub-mode FM1-4. Compared to two-zone frequency display, this partitioned display method is more flexible and suitable for a wider range of application scenarios. For example, the central zone can display video footage at a high frequency, while the upper and lower zones can display commentary and static images such as black borders at the same low frequency, respectively. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the display area's DA, thereby minimizing power consumption.

[0092] In one feasible implementation, combined with Figure 14 and Figure 15 The first mode FM includes a second sub-mode FM2. In the second sub-mode FM2, the first frequency is a non-integer multiple of the second frequency, the reference frequency is m1 times the first frequency, and the reference frequency is m2 times the second frequency. For example, the reference frequency is 240Hz, the first frequency is 120Hz, the second frequency is 80Hz, m1 = 2, and m2 = 3.

[0093] In the second sub-mode FM2, each adjacent m1×m2 frame includes m1 first frames F1, m2-1 second frames F2, and m1×m2-m1-(m2-1) third frames F3. In the first frame F1, the first unit group 6 and the second unit group 7 sequentially output scan valid levels. Within the m1-1 first frames F1, the first partition DA1 does not write data voltage. In the second frame F2, the first unit group 6 outputs scan valid levels, and the control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level. In the third frame F3, the control module 5 in the third shift unit 14 provides a disabled level to the first node N1. The third shift unit 14 is the shift unit 3 in the first unit group 6 that is furthest from the second unit group 7.

[0094] Taking a reference frequency of 240Hz, a first frequency of 120Hz, and a second frequency of 80Hz (m1=2, m2=3) as an example, Figure 14 and Figure 15 As shown, Figure 14 This is a schematic diagram of a partition of the display panel under the second sub-mode FM2 provided in an embodiment of the present invention. Figure 15 for Figure 14 A corresponding timing diagram shows that, under the second sub-mode FM2, for the six adjacent frames (n-th frame F_n, n+1-th frame F_n+1, n+2-th frame F_n+2, n+3-th frame F_n+3, n+4-th frame, and n+5-th frame), the n-th frame F_n and the n+3-th frame F_n+3 are the first frame F1, the n+2-th frame F_n+2 and the n+4-th frame F2 are the second frame F2, and the n+1-th frame F_n+1 and the n+5-th frame F3 are the third frame F3.

[0095] Specifically, in frames n-n and (n+3)-f(n+3) (first frame F1), shift units 3 (corresponding to Gout_1 to Gout_z) in the first unit group 6 and the second unit group 7 sequentially output scan valid levels. In frame (n+3)-f(n+3), no data voltage is written to the first partition DA1. In frames (n+2)-f(n+2) and (n+4)-f(n+4) (second frame F2), shift units 3 (corresponding to Gout_1 to Gout_i) in the first unit group 6 output high levels. The first shift unit 8 (corresponding to Gout_i+1) cuts off the shift path from the first unit group 6 to the second unit group 7, so that the shift units 3 (corresponding to Gout_i+1 to Gout_z) in the second unit group 7 no longer output a high level. In the (n+1)th frame F_n+1 and the (n+5)th frame F_n+5 (the third frame F3), the third shift unit 14 controls the shift units 3 (corresponding to Gout_1 to Gout_z) in the first unit group 6 and the second unit group 7 to not output a high level.

[0096] That is, in these 6 adjacent frames, the first partition DA1 was refreshed 3 times and the second partition DA2 was refreshed 2 times, thus making the frequencies of the first partition DA1 and the second partition DA2 not integer multiples of each other.

[0097] Under the above configuration, the frequencies of the first partition DA1 and the second partition DA2 do not have to be integer multiples of each other, which reduces the restrictions on the frequency design of the two partitions and makes the frequency design of the two partitions more flexible.

[0098] When the first frequency is a non-integer multiple of the second frequency, the reference frequency can be the least common multiple of the first and second frequencies to avoid setting the reference frequency too high and reduce the frequency requirement of the display panel.

[0099] In one feasible implementation, such as Figure 16 and Figure 17 As shown, Figure 16 This is a schematic diagram of a partition of a display panel provided in an embodiment of the present invention. Figure 17 This is another schematic diagram of the partitioning of the display panel provided in an embodiment of the present invention. The non-display area NA includes a lower step 15, which is typically provided with structures such as bonding pins. The scanning direction of the display area DA is from the first partition DA1 to the second partition DA2. See [link to relevant documentation]. Figure 16 The first section DA1 is located on the side of the second section DA2 away from the lower step 15, or, see... Figure 17 The first section DA1 is located on the side of the second section DA2 near the lower step 15.

[0100] In this embodiment of the invention, the high-frequency first partition DA1 can be flexibly selected to be placed on the top or bottom of the screen by the forward and reverse scanning of the shift register circuit 2. For example, by controlling the forward scanning of the shift register circuit 2, the high-frequency first partition DA1 can be placed on the top of the screen, so that dynamic images such as games and videos can be displayed on the top of the screen. Alternatively, by controlling the reverse scanning of the shift register circuit 2, the high-frequency first partition DA1 can be placed on the bottom of the screen, so that dynamic images such as games and videos can be displayed on the bottom of the screen. In this way, the position of the high-frequency partition within the entire display area DA will be more flexible.

[0101] In one feasible implementation, combined with Figure 2 and Figure 3 The control module 5 in the multiple shift units 3 is electrically connected to the control signal line Greset. The control module 5 is used to provide a de-enabled level to the first node N1 in response to the on level provided by the control signal line Greset. In the first mode FM, the control signal line Greset provides a de-enabled level in some frames, and provides an on level in others after the first unit group 6 outputs a scan valid level.

[0102] In this structure, the control module 5 of all shift units 3 in the shift register circuit 2 is connected to only one control signal line, Greset, resulting in a smaller number of additional signal lines. Based on this structure, in some frames, when it is necessary to use the first shift unit 8 to cut off the shift path from the first unit group 6 to the second unit group 7, it is only necessary to provide an on level to the control signal line Greset after the first unit group 6 outputs a scan valid level. At this time, although the control module 5 in all shift units 3 will perform the operation of providing an inactive level to the first node N1, since the shift units 3 in the first unit group 6 have already completed the output of the scan valid level, it will not affect the normal operation of the first unit group 6.

[0103] Alternatively, in another feasible implementation, such as Figures 18-20 As shown, Figure 18 This is a schematic diagram of another structure of the shift register circuit 2 provided in an embodiment of the present invention. Figure 19 This is a schematic diagram of another circuit structure of the shift unit 3 provided in an embodiment of the present invention. Figure 20 for Figure 18In one corresponding timing diagram, the control module 5 of the shift unit 3 in the first unit group 6 is electrically connected to the first control signal line Greset1, and the control module 5 of the shift unit 3 in the second unit group 7 is electrically connected to the second control signal line Greset2. The control module 5 is used to provide a non-enable level to the first node N1 in response to the conduction level provided by the first control signal line Greset1 or the second control signal line Greset2. In the first mode FM, the first control signal line Greset1 provides a non-enable level. In some frames, the second control signal line Greset2 provides a non-enable level. In some frames, the second control signal line Greset2 provides an enable level at least after the first unit group 6 outputs a scan valid level. For example, in some frames, the second control signal line Greset2 starts to provide an enable level after the first unit group 6 outputs a scan valid level. Or, see [link to relevant documentation]. Figure 20 At the start of the frame, the second control signal line Greset2 is always on.

[0104] In this structure, the shift units 3 in the first unit group 6 and the second unit group 7 are connected to different control signal lines Greset, thus allowing for individual control of the first unit group 6 and the second unit group 7 using these two control signal lines Greset. Specifically, in certain frames, when it is necessary to use the first shift unit 8 to cut off the shift path from the first unit group 6 to the second unit group 7, the second control signal line Greset2 can provide an on-level at the beginning of the frame, so that the first shift unit 8 maintains the cut-off of the shift path from the first unit group 6 to the second unit group 7 throughout the entire frame without affecting the normal operation of the first unit group 6. In this way, the control modules 5 in the first unit group 6 and the second unit group 7 are controlled independently, resulting in higher circuit reliability.

[0105] It should be noted that this structure is applicable to the first mode FM where the positions of the first partition DA1 and the second partition DA2 are fixed. In this first mode FM, the ranges of the first unit group 6 and the second unit group 7 are also fixed. By connecting the first unit group 6 and the second unit group 7 to different control signal lines, the first unit group 6 and the second unit group 7 can be controlled to have different working states in some frames.

[0106] In one feasible implementation, see again Figure 3 and Figure 19 The control module 5 includes a control transistor T0, which is electrically connected between the first signal line S and the first node N1. The first signal line S is used to provide a non-enable level.

[0107] The control transistor T0 is turned on in response to the conduction level provided by the control signal line Greset (or the first control signal line Greset1, or the second control signal line Greset2), so that the inactive level provided by the first signal line S is written into the first node N1, and the first output module 4 is prevented from outputting the scan valid level.

[0108] In one setup method, see Figure 2 The shift unit 3 includes a forward DC scan control signal terminal U2D, a reverse DC scan control signal terminal D2U, a forward scan reset control signal terminal RSTF, a reverse scan reset control signal terminal RSTB, and a drive signal terminal OUT. The forward DC scan control signal terminal U2D is electrically connected to the forward scan signal line U2D1, the reverse DC scan control signal terminal D2U is electrically connected to the reverse scan signal line D2U1, and the forward scan reset control signal terminal RSTF, the reverse scan reset control signal terminal RSTB, and the drive signal terminal OUT are connected to three of the following clock signal lines: the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4.

[0109] In addition, the shift unit 3 also includes a forward shift control terminal INF and a reverse shift control terminal INB. Along the direction from the first partition DA1 to the second partition DA2, the forward shift control terminal INF of the first shift unit 3 is electrically connected to the first frame start signal STV1, and the reverse shift control terminal INB of the last shift unit 3 is electrically connected to the second frame start signal STV2. For two adjacent shift units 3, the forward shift control terminal INF of the latter shift unit 3 is electrically connected to the output terminal Gout of the former shift unit 3, and the reverse shift control terminal INB of the former shift unit 3 is electrically connected to the output terminal Gout of the latter shift unit 3, so that the shift register circuit 2 has forward and reverse scan functions.

[0110] Among them, see Figure 2For the 4q+1th shift unit, the reverse scan reset control signal RSTB is electrically connected to the first clock signal line CK1, the drive signal OUT is electrically connected to the second clock signal line CK2, and the forward scan reset control signal RSTF is electrically connected to the third clock signal line CK3; for the 4q+2nd shift unit, the reverse scan reset control signal RSTB is electrically connected to the second clock signal line CK2, the drive signal OUT is electrically connected to the third clock signal line CK3, and the forward scan reset control signal RSTF is electrically connected to the fourth clock signal line CK4; for the 4q+3rd shift unit... For each shift unit, the reverse scan reset control signal RSTB is electrically connected to the third clock signal line CK3, the drive signal OUT is electrically connected to the fourth clock signal line CK4, and the forward scan reset control signal RSTF is electrically connected to the first clock signal line CK1. For the 4q+4th shift unit, the reverse scan reset control signal RSTB is electrically connected to the fourth clock signal line CK4, the drive signal OUT is electrically connected to the first clock signal line CK1, and the forward scan reset control signal RSTF is electrically connected to the second clock signal line CK2. The values ​​of q are 0, 1, 2, 3, 4, etc. in sequence.

[0111] Combination Figure 16 When the first high-frequency partition DA1 is located above the screen, the shift register circuit 2 performs a forward scan, such as... Figure 21 As shown, Figure 21 for Figure 16 In one timing diagram, taking a first frequency that is twice the second frequency as an example, in the first mode FM, the forward scan signal line U2D1 provides a high level, and the reverse scan signal line D2U1 provides a low level. In the nth frame F_n, the shift units 3 (corresponding to Gout_1~Gout_z) in the first unit group 6 and the second unit group 7 sequentially output high levels, and the control signal line Greset provides a low level. In the (n+1)th frame F_n+1, after the shift units 3 (corresponding to Gout_1~Gout_i) in the first unit group 6 output high levels, the control signal line Greset provides a high level, causing the control module 5 in the first shift unit 8 to provide a low level to the first node N1, thereby causing the shift units 3 (corresponding to Gout_i+1~Gout_z) in the second unit group 7 to stop outputting high levels.

[0112] Combination Figure 17 When the first high-frequency partition DA1 is located below the screen, the shift register circuit 2 performs a reverse scan, such as... Figure 22 As shown, Figure 22 for Figure 17In one timing diagram, taking a first frequency that is twice the second frequency as an example, in the first mode FM, the forward scan signal line U2D1 provides a low level, and the reverse scan signal line D2U1 provides a high level. In frame nF_n, the shift units 3 (corresponding to Gout_z~Gout_1) in the first unit group 6 and the second unit group 7 sequentially output high levels, and the control signal line Greset provides a low level. In frame n+1F_n+1, after the shift units 3 (corresponding to Gout_z~Gout_i+1) in the first unit group 6 output high levels, the control signal line Greset provides a high level, causing the control module 5 in the first shift unit 8 to provide a low level to the first node N1, thereby causing the shift units 3 (corresponding to Gout_i~Gout_1) in the second unit group 7 to stop outputting high levels.

[0113] In one feasible implementation, see again Figure 2 The shift unit 3 is electrically connected to the clock signal lines, which may specifically include the aforementioned first clock signal line CK1, second clock signal line CK2, third clock signal line CK3, and fourth clock signal line CK4. In the first mode FM, during a partial frame, after the first unit group 6 outputs a scan valid level, the control module 5 in the first shift unit 8 provides a disabled level to the first node N1, and the clock signal lines stop providing signals to further reduce power consumption.

[0114] In one feasible implementation, see again Figure 3 and Figure 19 The shift unit 3 also includes a drive module 16 and a second output module 17. The drive module 16 is used to provide an enable level or a disable level to the first node N1 and to the second node N2, and the second output module 17 is used to output a scan invalid level in response to the enable level of the second node N2.

[0115] In one configuration, the drive module 16 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2. The first output module 4 includes a ninth transistor T9, and the second output module 17 includes a tenth transistor T10.

[0116] In this configuration, the gate of the first transistor T1 is electrically connected to the forward shift control terminal INF, the first terminal of the first transistor T1 is electrically connected to the forward DC scan control signal terminal U2D, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0117] The gate of the second transistor T2 is electrically connected to the reverse shift control INB, the first terminal of the second transistor T2 is electrically connected to the reverse DC scan control signal terminal D2U, and the second terminal of the second transistor T2 is electrically connected to the third node N3.

[0118] The gate of the third transistor T3 is electrically connected to the forward DC scan control signal terminal U2D, the first terminal of the third transistor T3 is electrically connected to the forward scan reset control signal terminal RSTF, and the second terminal of the third transistor T3 is electrically connected to the gate of the seventh transistor T7.

[0119] The gate of the fourth transistor T4 is electrically connected to the reverse DC scan control signal terminal D2U, the first terminal of the fourth transistor T4 is electrically connected to the reverse scan reset control signal terminal RSTB, and the second terminal of the fourth transistor T4 is electrically connected to the gate of the seventh transistor T7.

[0120] The gate of the fifth transistor T5 is electrically connected to the second node N2, the first terminal of the fifth transistor T5 is electrically connected to the first potential signal line VGL, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3.

[0121] The gate of the sixth transistor T6 is electrically connected to the third node N3, the first terminal of the sixth transistor T6 is electrically connected to the first potential signal line VGL, and the second terminal of the sixth transistor T6 is electrically connected to the second terminal of the seventh transistor T7.

[0122] The first terminal of the seventh transistor T7 is electrically connected to the second potential signal line VGH, which is used to provide the effective scanning level.

[0123] The gate of the eighth transistor T8 is electrically connected to the second potential signal line VGH, the first terminal of the eighth transistor T8 is electrically connected to the third node N3, and the second terminal of the eighth transistor T8 is electrically connected to the first node N1.

[0124] The first plate of the first capacitor C1 is electrically connected to the first potential signal line VGL, and the second plate of the first capacitor C1 is electrically connected to the second node N2. The first potential signal line VGL is used to provide a scan inactive level. When the scan inactive level is the same as the inactive level, the aforementioned first signal line S can be multiplexed with the first potential signal line VGL.

[0125] The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the output signal terminal Gout.

[0126] The gate of the ninth transistor T9 is electrically connected to the first node N1, the first terminal of the ninth transistor T9 is electrically connected to the drive signal terminal OUT, and the second terminal of the ninth transistor T9 is electrically connected to the output signal terminal Gout.

[0127] The gate of the tenth transistor T10 is electrically connected to the second node N2, the first terminal of the tenth transistor T10 is electrically connected to the first potential signal line VGL, and the second terminal of the ninth transistor T9 is electrically connected to the output signal terminal Gout.

[0128] Combination Figure 3 , Figure 16 and Figure 21 Taking the forward scan of the shift register circuit 2 as an example, after the i-th shift unit 3 outputs a high level in frame n+1 F_n+1, the control signal line Greset provides a high level, pulling the potential of the first node N1 in each shift unit 3 low. At this time, the first node N1 in the first shift unit 8 controls the ninth transistor T9 to turn off. At the same time, the low level of the first node N1 is transmitted to the third node N3 through the eighth transistor T8, the sixth transistor T6 is turned off, and the potential of the second node N2 remains at the low level of the previous period, so that the fifth transistor T5 and the tenth transistor T10 remain in the off state of the previous period.

[0129] The working principle of multiple shift units 3 sequentially outputting scan effective levels is explained below:

[0130] Combination Figure 2 , Figure 3 and Figure 21 In each frame, the forward scan signal line U2D1 provides a high level to the forward DC scan control signal terminal U2D of each shift unit 3, and the reverse scan signal line D2U1 provides a low level to the reverse DC scan control signal terminal D2U of each shift unit 3, thereby controlling the third transistor T3 of each shift unit 3 to be continuously turned on and the fourth transistor T4 to be continuously turned off.

[0131] In the first sub-period t1 within a frame, the forward shift control terminal INF of the first shift unit 3 receives a high level provided by the first frame start signal line STV1, the reverse scan reset control signal terminal RSTB receives a high level provided by the first clock signal line CK1, the drive signal terminal OUT receives a low level provided by the second clock signal line CK2, and the forward scan reset control signal terminal RSTF receives a low level provided by the third clock signal line CK3.

[0132] During this sub-period, in the first shift unit 3, the first transistor T1 is turned on, writing the high level received at the forward DC scan control signal terminal U2D into the third node N3. The high level at the third node N3 is then written into the first node N1 via the turned-on eighth transistor T8, controlling the ninth transistor T9 to turn on. The ninth transistor T9 outputs the low level received at the drive signal terminal OUT to the output signal terminal Gout. Simultaneously, the high level at the third node N3 controls the sixth transistor T6 to turn on, writing the low level provided by the second fixed potential signal line VGL into the second node N2. The tenth transistor T10 is turned off. During this sub-period, the output signal terminal Gout of the first shift unit 3 outputs a low level.

[0133] In the second sub-period t2 within a frame, the forward shift control terminal INF of the first shift unit 3 receives a low level provided by the first frame start signal line STV1, the reverse scan reset control signal terminal RSTB receives a low level provided by the first clock signal line CK1, the drive signal terminal OUT receives a high level provided by the second clock signal line CK2, and the forward scan reset control signal terminal RSTF receives a low level provided by the third clock signal line CK3.

[0134] During this sub-period, in the first shift unit 3, the third node N3 remains high, and the ninth transistor T9 remains on, outputting the high level received at the drive signal terminal OUT to the output signal terminal Gout. During this sub-period, the output signal terminal Gout of the first shift unit 3 outputs a high level.

[0135] In the third sub-time period t3 within a frame, the forward shift control terminal INF of the second shift unit 3 receives the high level output by the output signal terminal Gout of the first shift unit 3, the reverse scan reset control signal terminal RSTB receives the low level provided by the second clock signal line CK2, the drive signal terminal OUT receives the high level provided by the third clock signal line CK3, and the forward scan reset control signal terminal RSTF receives the low level provided by the fourth clock signal line CK4.

[0136] During this sub-period, in the second shift unit 3, the first transistor T1 is turned on, writing the high level received at the forward DC scan control signal terminal U2D into the third node N3. The high level at the third node N3 is then written into the first node N1 via the turned-on eighth transistor T8, controlling the ninth transistor T9 to turn on. The ninth transistor T9 outputs the high level received at the drive signal terminal OUT to the output signal terminal Gout. Simultaneously, the high level at the third node N3 controls the sixth transistor T6 to turn on, writing the low level provided by the second fixed potential signal line VGL into the second node N2. The tenth transistor T10 is turned off. During this sub-period, the output signal terminal Gout of the second shift unit 3 outputs a high level.

[0137] Similarly, in the fourth sub-period, the positive shift control terminal INF of the third shift unit 3 receives the high level output by the output signal terminal Gout of the second shift unit 3, the drive signal terminal OUT receives the high level provided by the fourth clock signal line CK4, the ninth transistor T9 is turned on, and the high level received by the drive signal terminal OUT is output to the output signal terminal Gout. In the fifth sub-period, the positive shift control terminal INF of the fourth shift unit 3 receives the high level output by the output signal terminal Gout of the third shift unit 3, the drive signal terminal OUT receives the high level provided by the first clock signal line CK1, the ninth transistor T9 is turned on, and the high level received by the drive signal terminal OUT is output to the output signal terminal Gout, ..., so as to realize that multiple shift units output high levels in sequence.

[0138] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel, combined with Figures 1-4 The display panel includes a display area DA and a non-display area NA. The display panel also includes a pixel circuit 1 and a shift register circuit 2. The pixel circuit 1 is located in the display area DA, and the shift register circuit 2 is located in the non-display area NA. It includes multiple cascaded shift units 3. Each shift unit 3 includes a first output module 4 and a control module 5. The first output module 4 is used to output a scan active level or a scan inactive level in response to the enable level of the first node N1. The control module 5 is used to provide an inactive level to the first node N1.

[0139] The display panel has a first mode FM. In the first mode FM, the display area DA includes a first partition DA1 and a second partition DA2 that are adjacent in the first direction x. The first partition DA1 is refreshed with data at a first frequency, and the second partition DA2 is refreshed with data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit 2 includes a first unit group 6 and a second unit group 7. The first unit group 6 is electrically connected to the pixel circuit 1 in the first partition DA1, and the second unit group 7 is electrically connected to the pixel circuit 1 in the second partition DA2. The shift unit 3 in the second unit group 7 that is adjacent to the first unit group 6 is the first shift unit 8.

[0140] The driving method includes: in the first mode FM, in some frames, controlling the first unit group 6 and the second unit group 7 to sequentially output scan valid levels; and in some frames, controlling the control module 5 in the first shift unit 8 to provide an enable level to the first node N1 at least after the first unit group 6 outputs the scan valid level. The duration of one frame is t. f is the reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of the first and second frequencies.

[0141] Based on the foregoing analysis, this embodiment of the invention, by incorporating a control module 5 within the shift unit 3, can utilize the control module 5 in the first shift unit 8 to cut off the shift path from the first unit group 6 to the second unit group 7 in certain frames under the first mode FM. This prevents the second unit group 7 from outputting a valid scan level during these frames, thereby preventing the second partition DA2 from refreshing data and reducing its refresh rate. In this way, when different screens need to be displayed in different partitions, the data refresh rate can be adjusted according to the content to be displayed in each partition, avoiding high-frequency driving of the entire screen and resulting in wasted power.

[0142] In one feasible implementation, combined with Figure 4 and Figure 5 The first mode FM includes at least one first sub-mode FM1. In the first sub-mode FM1, f1 = x1 × f2, f1 is the first frequency, f2 is the second frequency, x1 is an integer and x1≥2, and the reference frequency is the first frequency.

[0143] In the first mode FM, the process of controlling the first unit group 6 and the second unit group 7 to sequentially output scan valid levels in some frames, and controlling the control module 5 in the first shift unit 8 to provide a de-enabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level in some frames, includes: In the first sub-mode FM1, the scanning direction of the display area DA is from the first partition DA1 to the second partition DA2. For each adjacent x1 frame, in one frame, the first unit group 6 and the second unit group 7 sequentially output scan valid levels. In the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides a de-enabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level.

[0144] For a detailed analysis of the first sub-mode FM1, please refer to the aforementioned embodiments, which will not be repeated here.

[0145] In the first sub-mode FM1, when the first frequency and the second frequency are set to be integer multiples of each other, compared to setting the reference frequency to be two or three times the first frequency, directly setting the reference frequency to be the same as the first frequency can avoid the reference frequency being too high, thereby avoiding excessive demands on the frequency design of the display panel.

[0146] In one feasible implementation, combined with Figure 6 and Figure 7At least one first sub-mode FM1 includes a first type of first sub-mode FM1-1. Under the first type of first sub-mode FM1-1, the display area DA also includes a third partition DA3 adjacent to the second partition DA2 in the first direction x. The scanning direction of the display area DA is from the first partition DA1 to the third partition DA3. The third partition DA3 refreshes data at a third frequency, f1 = k1 × x1 × f3, where f3 is the third frequency, k1 is an integer and k1 ≥ 2. The shift register circuit 2 also includes a third unit group 9. The third unit group 9 is electrically connected to the pixel circuit 1 in the third partition DA3. The shift unit 3 adjacent to the second unit group 7 in the third unit group 9 is the second shift unit 10.

[0147] In the first sub-mode FM1-1 of the first type, the driving method further includes: in the first sub-mode FM1, for each adjacent k1×x1 frame, in one of the frames, after the second unit group 7 outputs the scan valid level, the third unit group 9 sequentially outputs the scan valid level, and in the k1-1 frames, the control module 5 in the second shift unit 10 provides an enable level to the first node N1 at least after the second unit group 7 outputs the scan valid level.

[0148] For a detailed analysis of the first sub-mode FM1-1 of the first category, please refer to the aforementioned embodiments, which will not be repeated here.

[0149] The above configuration allows the display panel to perform at least three-zone frequency display in the first sub-mode FM1-1 of the first category. In this mode, the frequency of each of the three zones decreases progressively. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of applications. For example, one zone can display video at a high frequency, another at a low frequency to display commentary, and yet another at an ultra-low frequency to display static images such as black borders. Furthermore, this display mode allows for more precise control over the frequency at different locations on the display area DA, thereby minimizing power consumption.

[0150] In one feasible implementation, combined with Figure 8 and Figure 9 At least one first sub-mode FM1 includes a second type of first sub-mode FM1-2. Under the second type of first sub-mode FM1-2, the display area DA also includes a fourth partition DA4 adjacent to the first partition DA1 in the first direction x. The fourth partition DA4 and the second partition DA2 are located on opposite sides of the first partition DA1. The scanning direction of the display area DA is from the fourth partition DA4 to the second partition DA2. The fourth partition DA4 refreshes data at a fourth frequency, f1 = k2 × x1 × f4, where f4 is the fourth frequency, k2 is an integer and k2 ≥ 2. The shift register circuit 2 also includes a fourth unit group 11. The shift unit 3 in the fourth unit group 11 is electrically connected to the pixel circuit 1 in the fourth partition DA4.

[0151] Under the first sub-mode FM1-1 of the first type, the driving method further includes: for each adjacent k2×x1 frame, in each frame, the fourth unit group 11 and the first unit group 6 sequentially output scan valid levels, wherein in the x1 frame, after the first unit group 6 outputs scan valid levels, the second unit group 7 sequentially outputs scan valid levels, and in the remaining (k2-1)×x1 frames, the control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs scan valid levels; and, for each adjacent k2×x1 frame, the fourth partition DA4 writes data voltage in one of the frames, and does not write data voltage in the fourth partition DA4 in the remaining k2×x1-1 frames.

[0152] For a detailed analysis of the first sub-mode FM1-2 of the second category, please refer to the aforementioned embodiments, which will not be repeated here.

[0153] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the second sub-mode FM1-2. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of applications. For example, the central high-frequency zone can display video footage, the upper low-frequency zone can display static images such as black borders, and the lower low-frequency zone can display commentary. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the DA array in the display area, thereby minimizing power consumption.

[0154] In one feasible implementation, combined with Figure 10 and Figure 11 At least one first sub-mode FM1 includes a third type of first sub-mode FM1-3. In the third type of first sub-mode FM1-3, the display area DA also includes a fifth partition DA5 adjacent to the first partition DA1 in the first direction x. The fifth partition DA5 and the second partition DA2 are located on opposite sides of the first partition DA1. The scanning direction of the display area DA is from the fifth partition DA5 to the second partition DA2. The fifth partition DA5 refreshes data at a fifth frequency, f5 = k3 × f2, where f5 is the fifth frequency, k3 is an integer and k3 ≥ 2. The shift register circuit 2 also includes a fifth unit group 12. The shift unit 3 in the fifth unit group 12 is electrically connected to the pixel circuit 1 in the fifth partition DA5.

[0155] Under the third type first sub-mode FM1-3, the driving method further includes: for each adjacent x1 frame, in each frame, the fifth unit group 12 and the first unit group 6 sequentially output scan valid levels, in one of the frames, after the first unit group 6 outputs scan valid levels, the second unit group 7 sequentially outputs scan valid levels, and in the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs scan valid levels; and for each adjacent x1 frame, in any adjacent k3 frames, the fifth partition DA5 is written with data voltage in one of the frames, and the fifth partition DA5 is not written with data voltage in the remaining k3-1 frames.

[0156] For a detailed analysis of the first sub-mode FM1-3 of the third category, please refer to the aforementioned embodiments, which will not be repeated here.

[0157] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the third category, first sub-mode FM1-3. Compared to two-zone frequency display, this zoned display method is more flexible and suitable for a wider range of application scenarios. For example, the central zone can display video footage at high frequency, the upper zone can display commentary at low frequency, and the lower zone can display static images such as black borders at ultra-low frequency. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the display area's DA, thereby minimizing power consumption.

[0158] In one feasible implementation, combined with Figure 12 and Figure 13 At least one first sub-mode FM1 includes a fourth type of first sub-mode FM1-4. In the fourth type of first sub-mode FM1-4, the display area DA also includes a sixth partition DA6 adjacent to the first partition DA1 in the first direction x. The sixth partition DA6 and the second partition DA2 are located on opposite sides of the first partition DA1, respectively. The scanning direction of the display area DA is from the sixth partition DA6 to the second partition DA2. The sixth partition DA6 refreshes data at a second frequency. The shift register circuit 2 also includes a sixth unit group 13. The shift unit 3 in the sixth unit group 13 is electrically connected to the pixel circuit 1 in the sixth partition DA6.

[0159] Under the fourth category first sub-mode FM1-4, the driving method further includes: for each adjacent x1 frame, in each frame, the sixth unit group 13 and the first unit group 6 sequentially output scan valid levels, in one of the frames, after the first unit group 6 outputs scan valid levels, the second unit group 7 sequentially outputs scan valid levels, and in the remaining x1-1 frames, the control module 5 in the first shift unit 8 provides an enable level to the first node N1 at least after the first unit group 6 outputs scan valid levels; and, for each adjacent x1 frame, the sixth partition DA6 is written with data voltage in one of the frames, and the sixth partition DA6 is not written with data voltage in the remaining x1-1 frames.

[0160] For a detailed analysis of the first sub-mode FM1-4 of the fourth category, please refer to the aforementioned embodiments, which will not be repeated here.

[0161] The above configuration allows the display panel to perform three-zone frequency display (central high frequency, side low frequencies) in the fourth category, first sub-mode FM1-4. Compared to two-zone frequency display, this partitioned display method is more flexible and suitable for a wider range of application scenarios. For example, the central zone can display video footage at a high frequency, while the upper and lower zones can display commentary and static images such as black borders at the same low frequency, respectively. Furthermore, this display mode allows for more precise control of the frequencies at different positions of the display area's DA, thereby minimizing power consumption.

[0162] In one feasible implementation, combined with Figure 14 and Figure 15 The first mode FM includes a second sub-mode FM2. In the second sub-mode FM2, the first frequency is a non-integer multiple of the second frequency, the reference frequency is m1 times the first frequency, and the reference frequency is m2 times the second frequency.

[0163] In the first mode FM, the process of controlling the first unit group 6 and the second unit group 7 to sequentially output scan valid levels in some frames, and controlling the control module 5 in the first shift unit 8 to provide a disabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level in some frames, includes: In the second sub-mode FM2, each adjacent m1×m2 frame includes m1 first frames F1, m2-1 second frames F2, and m1×m2-m1-(m2-1) third frames F3; wherein, in the first frame F1, the first unit group 6 and the second unit group 7 The scan valid level is output sequentially, and in the first frame F1 of m1-1, the first partition DA1 does not write data voltage. In the second frame F2, the first unit group 6 outputs the scan valid level. The control module 5 in the first shift unit 8 provides a disabled level to the first node N1 at least after the first unit group 6 outputs the scan valid level. In the third frame F3, the control module 5 in the third shift unit 14 provides a disabled level to the first node N1. The third shift unit 14 is the shift unit 3 in the first unit group 6 that is farthest from the second unit group 7.

[0164] For a detailed analysis of the second sub-mode FM2, please refer to the aforementioned embodiments, which will not be repeated here.

[0165] Under the above configuration, the frequencies of the first partition DA1 and the second partition DA2 do not have to be integer multiples of each other, which reduces the restrictions on the frequency design of the two partitions and makes the frequency design of the two partitions more flexible.

[0166] In one feasible implementation, see again Figure 2 The shift unit 3 is electrically connected to the clock signal line, which may specifically include the aforementioned first clock signal line CK1, second clock signal line CK2, third clock signal line CK3, and fourth clock signal line CK4.

[0167] In the first mode FM, during a partial frame, after the first unit group 6 outputs a scan valid level, the control module 5 in the first shift unit 8 provides an enable level to the first node N1, and the clock signal line stops providing signals to further reduce power consumption.

[0168] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 23 As shown, Figure 23 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 23 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0169] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Display area and non-display area; Pixel circuitry is located in the display area; A shift register circuit, located in the non-display area, includes multiple cascaded shift units. Each shift unit includes a first output module and a control module. The first output module is used to output a scan valid level or a scan invalid level in response to the enable level of the first node. The control module is used to provide an invalid level to the first node. The control module includes a control transistor electrically connected between a first signal line and the first node, the first signal line being used to provide the disabled level. The display panel has a first mode. In the first mode, the display area includes a first partition and a second partition adjacent in a first direction. The first partition refreshes data at a first frequency, and the second partition refreshes data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit includes a first unit group and a second unit group. The first unit group is electrically connected to the pixel circuit in the first partition, and the second unit group is electrically connected to the pixel circuit in the second partition. The shift unit adjacent to the first unit group in the second unit group is a first shift unit. In the first mode, in some frames, the first unit group and the second unit group output the scan valid level in sequence, and in some frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level; The duration of one frame is t. f is a reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of both the first frequency and the second frequency.

2. The display panel according to claim 1, characterized in that, The first mode includes at least one first sub-mode; In the first sub-mode f1 is the first frequency, f2 is the second frequency, x1 is an integer and x1≥2, and the reference frequency is the first frequency; In the first sub-mode, the scanning direction of the display area is from the first partition to the second partition. For each adjacent x1 frame, within one frame, the first unit group and the second unit group output the scan valid level in sequence. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level.

3. The display panel according to claim 2, characterized in that, The at least one first sub-mode includes a first type of first sub-mode. In the first type of first sub-mode, the display area further includes a third partition adjacent to the second partition in the first direction. The scanning direction of the display area is from the first partition to the third partition, and the third partition refreshes data at a third frequency. f3 is the third frequency, k1 is an integer and k1≥2, the shift register circuit further includes a third unit group, the third unit group is electrically connected to the pixel circuit in the third partition, and the shift unit in the third unit group that is adjacent to the second unit group is the second shift unit; In the first sub-pattern of the first type, for each adjacent In one of the frames, after the second unit group outputs the scan valid level, the third unit group sequentially outputs the scan valid level. In frames k1-1, the control module in the second shift unit provides the disabled level to the first node at least after the second unit group outputs the scan valid level.

4. The display panel according to claim 2, characterized in that, The at least one first sub-mode includes a second type of first sub-mode. In the second type of first sub-mode, the display area further includes a fourth partition adjacent to the first partition in the first direction. The fourth partition and the second partition are located on opposite sides of the first partition. The scanning direction of the display area is from the fourth partition to the second partition. The fourth partition refreshes data at a fourth frequency. f4 is the fourth frequency, k2 is an integer and k2≥2, the shift register circuit further includes a fourth unit group, the shift unit in the fourth unit group is electrically connected to the pixel circuit in the fourth partition; In the second type of first sub-pattern, for each adjacent In each frame, the fourth unit group and the first unit group sequentially output the scan valid level, wherein... In the frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level, and in the remaining frames... The control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level; Furthermore, for each adjacent Frame, in which the fourth partition is written with data voltage in one frame, in the rest The fourth partition within the frame does not write the data voltage.

5. The display panel according to claim 2, characterized in that, The at least one first sub-mode includes a third type of first sub-mode, in which the display area further includes a fifth sub-mode adjacent to the first sub-mode in the first direction, the fifth sub-mode and the second sub-mode are respectively located on opposite sides of the first sub-mode, the scanning direction of the display area is from the fifth sub-mode to the second sub-mode, and the fifth sub-mode refreshes data at a fifth frequency. f5 is the fifth frequency, k3 is an integer and k3≥2, the shift register circuit further includes a fifth unit group, the shift unit in the fifth unit group is electrically connected to the pixel circuit in the fifth partition; In the third type of first sub-pattern, for each adjacent In each frame, the fifth unit group and the first unit group sequentially output the scan valid level. In one frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level. Furthermore, for each adjacent In any k3 consecutive frames, the fifth partition is written with data voltage in one of the frames, and the fifth partition is not written with data voltage in the remaining k3-1 frames.

6. The display panel according to claim 2, characterized in that, The at least one first sub-mode includes a fourth type of first sub-mode. In the fourth type of first sub-mode, the display area further includes a sixth partition adjacent to the first partition in the first direction. The sixth partition and the second partition are located on opposite sides of the first partition. The scanning direction of the display area is from the sixth partition to the second partition. The sixth partition is refreshed with data at the second frequency. The shift register circuit further includes a sixth unit group. The shift unit in the sixth unit group is electrically connected to the pixel circuit in the sixth partition. In the fourth category of the first sub-pattern, for each adjacent In each frame, the sixth unit group and the first unit group sequentially output the scan valid level. In one frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level. Furthermore, for each adjacent The sixth partition is written with data voltage in one of the frames, and not written with data voltage in the remaining x1-1 frames.

7. The display panel according to claim 1, characterized in that, The first mode includes a second sub-mode; In the second sub-mode, the first frequency is a non-integer multiple of the second frequency, the reference frequency is m1 times the first frequency, and the reference frequency is m2 times the second frequency; In the second sub-pattern, each adjacent The frame consists of m1 first frames, m2-1 second frames, and A third frame; wherein, in the first frame, the first unit group and the second unit group sequentially output the scan valid level, and, in m1-1 of the first frames, the first partition does not write data voltage, in the second frame, the first unit group outputs the scan valid level, and the control module in the first shift unit provides the disable level to the first node at least after the first unit group outputs the scan valid level, in the third frame, the control module in the third shift unit provides the disable level to the first node, and the third shift unit is the shift unit in the first unit group that is furthest from the second unit group.

8. The display panel according to claim 7, characterized in that, The reference frequency is the least common multiple of the first frequency and the second frequency.

9. The display panel according to claim 1, characterized in that, The non-display area includes a lower step; The scanning direction of the display area is from the first partition to the second partition, and the first partition is located on the side of the second partition away from the lower step, or the first partition is located on the side of the second partition closer to the lower step.

10. The display panel according to claim 1, characterized in that, The control module in the plurality of shifting units is electrically connected to the control signal line, and the control module is used to provide the disable level to the first node in response to the conduction level provided by the control signal line. In the first mode, the control signal line provides a non-conducting level in some frames, and provides the conducting level in other frames after the first unit group outputs the scan valid level.

11. The display panel according to claim 1, characterized in that, The control module of the shift unit in the first unit group is electrically connected to the first control signal line, and the control module of the shift unit in the second unit group is electrically connected to the second control signal line. The control module is used to provide the disabled level to the first node in response to the conduction level provided by the first control signal line or the second control signal line. In the first mode, the first control signal line provides a non-conducting level, and in some frames, the second control signal line provides the non-conducting level; in some frames, the second control signal line provides the conducting level at least after the first unit group outputs the scan valid level.

12. The display panel according to claim 1, characterized in that, The shifting unit is electrically connected to the clock signal line; In the first mode, in a partial frame, after the first unit group outputs the scan valid level, the control module in the first shift unit provides the disabled level to the first node, and the clock signal line stops providing signals.

13. The display panel according to claim 1, characterized in that, The shifting unit further includes: The driving module is used to provide the enable level or the disable level to the first node and to the second node; The second output module is used to output the scan inactive level in response to the enable level of the second node.

14. A driving method for a display panel, characterized in that, The display panel includes: Display area and non-display area; Pixel circuitry is located in the display area; A shift register circuit, located in the non-display area, includes multiple cascaded shift units. Each shift unit includes a first output module and a control module. The first output module is used to output a scan valid level or a scan invalid level in response to the enable level of the first node. The control module is used to provide an invalid level to the first node. The control module includes a control transistor electrically connected between a first signal line and the first node, the first signal line being used to provide the disabled level. The display panel has a first mode. In the first mode, the display area includes a first partition and a second partition adjacent in a first direction. The first partition refreshes data at a first frequency, and the second partition refreshes data at a second frequency. The first frequency is greater than the second frequency. The shift register circuit includes a first unit group and a second unit group. The first unit group is electrically connected to the pixel circuit in the first partition, and the second unit group is electrically connected to the pixel circuit in the second partition. The shift unit adjacent to the first unit group in the second unit group is a first shift unit. The driving method includes: in the first mode, in some frames, controlling the first unit group and the second unit group to output the scan valid level sequentially; in some frames, controlling the control module in the first shift unit to provide the disabled level to the first node at least after the first unit group outputs the scan valid level. The duration of one frame is t. f is a reference frequency, which is greater than or equal to the first frequency, and the reference frequency is an integer multiple of both the first frequency and the second frequency.

15. The driving method according to claim 14, characterized in that, The first mode includes at least one first sub-mode, in which, f1 is the first frequency, f2 is the second frequency, x1 is an integer and x1≥2, and the reference frequency is the first frequency; In the first mode, in some frames, controlling the first unit group and the second unit group to sequentially output the scan valid level, and in some frames, controlling the control module in the first shift unit to provide the disabled level to the first node at least after the first unit group outputs the scan valid level, includes the following process: In the first sub-mode, the scanning direction of the display area is from the first partition to the second partition. For each adjacent x1 frame, within one frame, the first unit group and the second unit group output the scan valid level in sequence. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level.

16. The driving method according to claim 15, characterized in that, The at least one first sub-mode includes a first type of first sub-mode. In the first type of first sub-mode, the display area further includes a third partition adjacent to the second partition in the first direction. The scanning direction of the display area is from the first partition to the third partition, and the third partition refreshes data at a third frequency. f3 is the third frequency, k1 is an integer and k1≥2, the shift register circuit further includes a third unit group, the third unit group is electrically connected to the pixel circuit in the third partition, and the shift unit in the third unit group that is adjacent to the second unit group is the second shift unit; In the first sub-mode of the first type, the driving method further includes: in the first sub-mode, for each adjacent In one of the frames, after the second unit group outputs the scan valid level, the third unit group sequentially outputs the scan valid level. In frames k1-1, the control module in the second shift unit provides the disabled level to the first node at least after the second unit group outputs the scan valid level.

17. The driving method according to claim 15, characterized in that, The at least one first sub-mode includes a second type of first sub-mode. In the second type of first sub-mode, the display area further includes a fourth partition adjacent to the first partition in the first direction. The fourth partition and the second partition are located on opposite sides of the first partition. The scanning direction of the display area is from the fourth partition to the second partition. The fourth partition refreshes data at a fourth frequency. f4 is the fourth frequency, k2 is an integer and k2≥2, the shift register circuit further includes a fourth unit group, the shift unit in the fourth unit group is electrically connected to the pixel circuit in the fourth partition; In the second type of first sub-mode, the driving method further includes: for each adjacent In each frame, the fourth unit group and the first unit group sequentially output the scan valid level, wherein... In the frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level, and in the remaining frames... The control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level; Furthermore, for each adjacent Frame, in one of which the fourth partition is written with data voltage, in the remaining frames The fourth partition within the frame does not write the data voltage.

18. The driving method according to claim 15, characterized in that, The at least one first sub-mode includes a third type of first sub-mode, in which the display area further includes a fifth sub-mode adjacent to the first sub-mode in the first direction, the fifth sub-mode and the second sub-mode are respectively located on opposite sides of the first sub-mode, the scanning direction of the display area is from the fifth sub-mode to the second sub-mode, and the fifth sub-mode refreshes data at a fifth frequency. f5 is the fifth frequency, k3 is an integer and k3≥2, the shift register circuit further includes a fifth unit group, the shift unit in the fifth unit group is electrically connected to the pixel circuit in the fifth partition; In the third type of first sub-mode, the driving method further includes: for each adjacent In each frame, the fifth unit group and the first unit group sequentially output the scan valid level. In one frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level. Furthermore, for each adjacent In any k3 consecutive frames, the fifth partition is written with data voltage in one of the frames, and the fifth partition is not written with data voltage in the remaining k3-1 frames.

19. The driving method according to claim 15, characterized in that, The at least one first sub-mode includes a fourth type of first sub-mode. In the fourth type of first sub-mode, the display area further includes a sixth partition adjacent to the first partition in the first direction. The sixth partition and the second partition are located on opposite sides of the first partition. The scanning direction of the display area is from the sixth partition to the second partition. The sixth partition is refreshed with data at the second frequency. The shift register circuit further includes a sixth unit group. The shift unit in the sixth unit group is electrically connected to the pixel circuit in the sixth partition. In the fourth type of first sub-mode, the driving method further includes: for each adjacent In each frame, the sixth unit group and the first unit group sequentially output the scan valid level. In one frame, after the first unit group outputs the scan valid level, the second unit group sequentially outputs the scan valid level. In the remaining x1-1 frames, the control module in the first shift unit provides the disabled level to the first node at least after the first unit group outputs the scan valid level. Furthermore, for each adjacent The sixth partition is written with data voltage in one of the frames, and not written with data voltage in the remaining x1-1 frames.

20. The driving method according to claim 14, characterized in that, The first mode includes a second sub-mode, in which the first frequency is a non-integer multiple of the second frequency, the reference frequency is m1 times the first frequency, and the reference frequency is m2 times the second frequency; In the first mode, in some frames, controlling the first unit group and the second unit group to sequentially output the scan valid level, and in some frames, controlling the control module in the first shift unit to provide the disabled level to the first node at least after the first unit group outputs the scan valid level, includes the following process: In the second sub-pattern, each adjacent The frame consists of m1 first frames, m2-1 second frames, and The third frame; wherein, in the first frame, the first unit group and the second unit group sequentially output the scan valid level, and, in the m1-1 first frames, the first partition does not write data voltage, in the second frame, the first unit group outputs the scan valid level, and the control module in the first shift unit provides the disable level to the first node at least after the first unit group outputs the scan valid level, in the third frame, the control module in the third shift unit provides the disable level to the first node, and the third shift unit is the shift unit in the first unit group that is furthest from the second unit group.

21. The driving method according to claim 14, characterized in that, The shifting unit is electrically connected to the clock signal line; In the first mode, in a partial frame, after the first unit group outputs the scan valid level, the control module in the first shift unit provides the disabled level to the first node, and the clock signal line stops providing signals.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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