Video signal processing circuit, display panel and electronic device
By recombining a single data input signal into a synchronization signal for four sub-pixels through a video signal processing circuit, the problem of excessive I/O ports in monochrome high-resolution applications of OLED displays is solved, and the miniaturization and integration of the system are realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI GREATECH MICROELECTRONICS TECH CO LTD
- Filing Date
- 2023-11-17
- Publication Date
- 2026-07-21
AI Technical Summary
In monochrome high-resolution applications, OLED displays require the simultaneous output of four sub-pixel signals, resulting in an excessive number of I/O ports, which hinders miniaturization and integration.
The video signal processing circuit, including column counter, odd-even row counter, odd row controller, even row controller and synchronization signal controller, processes the input signal and reassembles the single data input signal into a synchronization signal for four sub-pixels.
This reduces the number of external video input signal ports required by the display driver, improving the miniaturization and integration of the OLED display system.
Smart Images
Figure CN117373391B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to a video signal processing circuit, a display panel, and an electronic device. Background Technology
[0002] In some OLED displays, a pixel unit typically contains four subpixels (e.g., red, green, blue, and white subpixels), arranged in two rows and two columns. With this architecture, when all four subpixels are monochrome pixels, the display can be used as a high-resolution monochrome OLED display.
[0003] However, since these OLED displays are originally driven by full pixels, in monochrome high-resolution applications, the OLED driver chip also needs to output four sub-pixel signals simultaneously for display output. In many applications, too many input / output I / O ports can significantly hinder the miniaturization and integration of the OLED display system. Summary of the Invention
[0004] To overcome the aforementioned shortcomings in the prior art, the purpose of this application is to provide a video signal processing circuit, the video signal processing circuit comprising:
[0005] The column counter is used to count and output the column count signal hcnt for each row of video signal based on the input row synchronization input signal hsy and the data valid input signal de. When the data valid input signal de is valid, the column count signal hcnt is based on the clock input signal clk.
[0006] The odd / even line counter is used to count the input line synchronization signal hsy, so as to output different odd / even line counting signals vcnt for odd and even lines in the video signal;
[0007] An odd-row controller is configured to convert the single-channel serial signal of each odd-row in the data input signal din into a first intermediate sub-signal and a second intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The first intermediate sub-signal is the serial signal of each 2i+1 column sub-pixels in the odd-row, and the second intermediate sub-signal is the serial signal of each 2i+2 column sub-pixels in the odd-row, where i is a natural number.
[0008] An even-row controller is configured to convert the serial signal of each even-row single channel in the data input signal din into a third intermediate sub-signal and a fourth intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The third intermediate sub-signal is the serial signal of each 2i+1 column sub-pixel in the even-row, and the fourth intermediate sub-signal is the serial signal of each 2i+2 column sub-pixel in the even-row.
[0009] A synchronization signal controller is used to synchronize the first intermediate sub-signal, the second intermediate sub-signal, the third intermediate sub-signal, and the fourth intermediate sub-signal to obtain a first output sub-signal, a second output sub-signal, a third output sub-signal, and a fourth output sub-signal. The data of the sub-pixels in the 2j+1th row and 2n+1th column of the data input signal din, the sub-pixels in the 2j+1th row and 2n+2th column of the data input signal din, and the sub-pixels in the 2j+2th row and 2n+2th column of the data input signal din are synchronously output in the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal, respectively, where j is a natural number.
[0010] In one possible implementation, the input of the column counter receives a row synchronization input signal hsy and a data valid input signal de, respectively.
[0011] The column counter is used to count according to the clock input signal clk when the data valid input signal de is valid, and to output the column count signal hcnt. When the row synchronization input signal hsy is valid, the column count signal hcnt is cleared.
[0012] In one possible implementation, the input terminals of the odd / even row counter receive the row synchronization input signal hsy and the field synchronization input signal vsy, respectively.
[0013] The odd / even row counter flips and counts to output the odd / even row count signal vcnt when the row synchronization input signal hsy is valid, and clears the odd / even row count signal vcnt when the field synchronization input signal vsy is valid.
[0014] In one possible implementation, the odd-row controller includes a first NOT gate, a second NOT gate, a first AND gate, a second AND gate, a row memory, a first data signal register group, and a second data signal register group;
[0015] The odd-row controller is used to save the current sub-pixel row when an odd-row input occurs, and to read and output odd-row data when an even-row input occurs, wherein:
[0016] The two inputs of the first AND gate receive the data valid input signal de and the odd / even row count signal vcnt, respectively.
[0017] The input of the first NOT gate receives the parity row counting signal vcnt;
[0018] The two inputs of the second AND gate receive the data valid input signal de and the output signal of the first NOT gate, respectively.
[0019] The clock input terminals of the first data signal register group and the second data signal register group of the row memory respectively receive the clock input signal clk.
[0020] The write signal input terminal of the row memory receives the signal output by the first logic AND gate;
[0021] The read signal input terminal of the row memory receives the signal output by the second logic AND gate;
[0022] The address input terminal of the row memory receives the column counting signal hcnt;
[0023] The data input terminal of the row memory receives the data input signal din;
[0024] The data input terminals of the first data signal register group and the second data signal register group respectively receive the signals output by the row memory;
[0025] The input of the second NOT gate receives the least significant bit of the column counting signal hcnt;
[0026] The enable terminal of the first data signal register group receives the signal output by the second logic NOT gate. The first data signal register group is used to obtain the signal of the sub-pixel in the 2i+1th column of the current row, so as to output the first intermediate sub-signal.
[0027] The enable terminal of the second data signal register group receives the least significant bit of the column count signal hcnt. The second data signal register group is used to obtain the signal of the sub-pixel of the 2i+2th column in the current row, so as to output the second intermediate sub-signal.
[0028] In one possible implementation, the even-row controller includes a third AND gate, a fourth AND gate, a fifth AND gate, a third NOT gate, a fourth NOT gate, a third data signal register group, and a fourth data signal register group.
[0029] The even-row controller is used to output even-row data when an even-row input occurs, wherein:
[0030] The clock input terminals of the third data signal register group and the fourth data signal register group respectively receive the clock input signal clk;
[0031] The data input terminals of the third data signal register group and the fourth data signal register group respectively receive the data input signal din;
[0032] The input terminal of the fourth NOT gate receives the parity row counting signal vcnt;
[0033] The two inputs of the third AND gate receive the data valid input signal de and the signal output by the fourth NOT gate, respectively. The input of the third NOT gate receives the least significant bit of the column count signal hcnt.
[0034] The two inputs of the fourth AND gate receive the signal output by the third AND gate and the least significant bit of the column counting signal hcnt, respectively.
[0035] The two inputs of the fifth AND gate receive the signals output by the third AND gate and the third NOT gate, respectively.
[0036] The enable terminal of the third data signal register group receives the signal output by the fifth logic AND gate. The third data signal register group is used to obtain the signal of the sub-pixel in the 2i+1th column of the current row, so as to output the third intermediate sub-signal.
[0037] The enable terminal of the fourth data signal register group receives the signal output by the fourth logic AND gate. The fourth data signal register group is used to obtain the signal of the sub-pixel in the 2i+2th column of the current row, so as to output the fourth intermediate sub-signal.
[0038] In one possible implementation, the synchronization signal controller is further configured to perform synchronization processing on the line synchronization input signal hsy, the field synchronization input signal vsy, the data valid input signal de, and the clock input signal clk, and output a line synchronization valid signal HSYNC, a field synchronization valid signal VSYNC, a data valid signal VALID, and a pixel clock output signal PCLK that are synchronized with the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal.
[0039] In one possible implementation, the synchronization signal controller includes a clock divider, a fifth data signal register group, a sixth data signal register group, a seventh data signal register group, an eighth data signal register group, a first field synchronization input signal register, a second field synchronization input signal register, a first row synchronization input signal register, a second row synchronization input signal register, a first data valid input signal register, and a second data valid input signal register.
[0040] The clock input terminals of the clock divider, the first field synchronization input signal register, the second field synchronization input signal register, the first row synchronization input signal register, the second row synchronization input signal register, the first data valid input signal register, and the second data valid input signal register respectively receive the clock input signal clk;
[0041] The input terminal of the clock divider receives the signal output by the clock divider, and the clock divider also outputs a synchronized pixel clock output signal PCLK.
[0042] The clock input terminals of the fifth, sixth, seventh, and eighth data signal register groups respectively receive the signals output by the clock divider.
[0043] The data input terminals of the fifth data signal register group, the sixth data signal register group, the seventh data signal register group, and the eighth data signal register group respectively receive the signals output by the first data signal register group, the second data signal register group, the third data signal register group, and the fourth data signal register group;
[0044] The data input terminal of the first field synchronization input signal register receives the field synchronization input signal vsy;
[0045] The data input terminal of the second field synchronization input signal register receives the signal output from the data output terminal of the first field synchronization input signal register, and the data output terminal of the second field synchronization input signal register outputs the re-synchronized field synchronization valid signal VSYNC;
[0046] The data input terminal of the first row synchronization input signal register receives the row synchronization input signal hsy;
[0047] The data input terminal of the second row synchronization input signal register receives the signal output from the data output terminal of the first row synchronization input signal register, and the data output terminal of the second row synchronization input signal register outputs the re-synchronized row synchronization valid signal HSYNC.
[0048] The data input terminal of the first valid data input signal register receives the valid data input signal de;
[0049] The data input terminal of the second valid data input signal register receives the signal output from the data output terminal of the first valid data input signal register, and the data output terminal of the second valid data input signal register outputs the reassembled and synchronized valid data signal VALID.
[0050] This application also provides a display panel, which includes the video signal processing circuit provided in this application.
[0051] In one possible implementation, the display panel includes a monochrome high-resolution display panel, wherein the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal are used to synchronously drive four sub-pixels in the same pixel.
[0052] This application also provides an electronic device, which includes the display panel provided in this application.
[0053] Compared with the prior art, this application has the following beneficial effects:
[0054] This application provides a video signal processing circuit, a display panel, and an electronic device. The video signal processing circuit can reassemble a single-channel data input signal din into synchronized first intermediate sub-signals, second intermediate sub-signals, third intermediate sub-signals, and fourth intermediate sub-signals corresponding to four sub-pixels of a pixel unit. Thus, only one data input signal din is needed in the input signal, significantly reducing the display driver's requirements for the number of external video input signal ports. Attached Figure Description
[0055] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1 This is a schematic diagram of the sub-pixels of the display panel provided in this embodiment;
[0057] Figure 2 This is a schematic diagram of the video signal processing circuit provided in this embodiment;
[0058] Figure 3 This is one of the signal timing relationship diagrams provided in this embodiment;
[0059] Figure 4 This is the second schematic diagram of the signal timing relationship provided in this embodiment;
[0060] Figure 5 This is the third schematic diagram of the signal timing relationship provided in this embodiment;
[0061] Figure 6 A schematic diagram of the odd-row controller provided in this embodiment;
[0062] Figure 7 This is the fourth schematic diagram of the signal timing relationship provided in this embodiment;
[0063] Figure 8 A schematic diagram of the even-row controller provided in this embodiment;
[0064] Figure 9 This is the fifth schematic diagram of the signal timing relationship provided in this embodiment;
[0065] Figure 10 A schematic diagram of the synchronization signal controller provided in this embodiment;
[0066] Figure 11 This is the sixth schematic diagram of the signal timing relationship provided in this embodiment. Detailed Implementation
[0067] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0068] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0069] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0070] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0071] The inventors discovered that in some display panels, a pixel unit typically contains four sub-pixels, arranged in two rows and two columns adjacent to each other. For example, please see... Figure 1 In a display panel with X columns and Y rows of subpixels, subpixels 1-1 in the first row and first column, 1-2 in the first row and second column, 2-1 in the second row and first column, and 2-2 in the second row and second column are four subpixels belonging to the same pixel unit. When the display is originally driven by full pixels, the OLED driver chip typically outputs four subpixel signals simultaneously per pixel unit, resulting in excessive input / output and hindering the miniaturization and integration of the display system.
[0072] In view of this, this embodiment provides a solution that can reduce the number of external video input signal ports. The solution provided in this embodiment will be described in detail below.
[0073] Please see Figure 2 , Figure 2 This is a schematic diagram of a video signal processing circuit provided in this embodiment. The video signal processing circuit may include a column counter, an odd-even row counter, an odd-row controller, an even-row controller, and a synchronization signal controller.
[0074] Please refer to Figure 3 In this embodiment, the input signals of the video signal processing circuit may include a clock input signal clk, a vertical synchronization input signal vsy, a horizontal synchronization input signal hsy, a data valid input signal de, and a single-channel data input signal din.
[0075] The clock input signal clk is a pulse signal that jumps regularly at a fixed frequency. The field synchronization input signal vsy is used to achieve screen synchronization, and the line synchronization input signal hsy pulses once when a new frame of image is about to be transmitted to mark the start of a frame.
[0076] The line synchronization input signal hsy is used to realize line signal synchronization. The line synchronization input signal hsy can pulse once when a new line in a frame of image is about to be transmitted to mark the start of a line.
[0077] The valid data input signal de is used to identify the validity of the data input signal din, that is, during the period when the valid data input signal de is valid, the transition signal on the data input signal din is considered valid.
[0078] The data input signal din is used for serial transmission of data for each sub-pixel in one frame of an image, for example, from... Figure 1The data of sub-pixels 1-1 to 1-X, and from row 1 to row Y, are transmitted sequentially.
[0079] The column counter is used to count and output the column count signal hcnt for each row of video signal according to the input row synchronization input signal hsy and the data valid input signal de, when the data valid input signal de is valid and according to the clock input signal clk.
[0080] Alternatively, in one possible implementation, please refer again to... Figure 2 The column counter receives a row synchronization input signal hsy and a data valid input signal de at its input terminals. Furthermore, the column counter is used to count according to the clock input signal clk to output the column count signal hcnt when the data valid input signal de is valid, and to clear the column count signal hcnt when the row synchronization input signal hsy is valid.
[0081] Therefore, please refer to Figure 4 , Figure 4 The timing relationship between the column count signal hcnt and other signals is described. Since the data input signal din transmits one sub-pixel's data in each clock input signal clk pulse cycle during the valid data input signal de, the column counter is used to count the data input signal din based on the clock input signal clk when the valid data input signal de is valid. That is, the column count signal hcnt is a count of the sub-pixel data in each column of a row of signals, and the column count signal hcnt is cleared to zero at the start of a new row.
[0082] The odd / even line counter is used to count the input line synchronization input signal hsy, so as to output different odd / even line count signals vcnt for odd and even lines in the video signal.
[0083] Alternatively, in one possible implementation, please refer again to... Figure 2 The input terminals of the odd and even row counters receive the row synchronization input signal hsy and the field synchronization input signal vsy, respectively.
[0084] In one possible implementation, the parity row counter toggles its count to output the parity row count signal vcnt when the row synchronization input signal hsy is valid, and clears the parity row count signal vcnt to zero when the field synchronization input signal vsy is valid. Subsequent circuits can then use only the least significant bit of the parity row count signal vcnt output by the parity row counter.
[0085] Preferably, the odd-even row counter can be a 1-bit cyclic counter, that is, the odd-even row counter outputs only 1 bit of data in a cyclic toggling manner.
[0086] Therefore, please refer to Figure 5 , Figure 5 The timing relationship between the odd / even row count signal vcnt and other signals is defined. Specifically, based on the row synchronization input signal hsy, the odd / even row count signal vcnt can be 1 when the data input signal din transmits odd-numbered rows of data, 2 when the data input signal din transmits even-numbered rows of data, and reset to zero when a new frame of image transmission begins.
[0087] The odd-row controller is used to convert the single-channel serial signal of each odd-row in the data input signal din into a first intermediate sub-signal and a second intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The first intermediate sub-signal is the serial signal of each 2i+1 column sub-pixels in the odd-row, and the second intermediate sub-signal is the serial signal of each 2i+2 column sub-pixels in the odd-row, where n≥0.
[0088] Alternatively, in one possible implementation, please refer to Figure 6 The odd-row controller includes a first NOT gate INV1, a second NOT gate INV2, a first AND gate AND1, a second AND gate AND2, a row memory, a first data signal register group U1, and a second data signal register group U2.
[0089] The odd-row controller is used to save the current sub-pixel row when an odd-row input is received, and to read and output the odd-row data when an even-row input is received.
[0090] The two inputs of the first logic AND gate AND1 receive the data valid input signal de and the odd row count signal vcnt, respectively.
[0091] The input terminal of the first NOT gate INV1 receives the parity row count signal vcnt.
[0092] The two inputs of the second logic AND gate AND2 receive the data valid input signal de and the output signal of the first logic NOT gate INV1, respectively.
[0093] The clock input terminals of the first data signal register group U1 and the second data signal register group U2 of the row memory respectively receive the clock input signal clk.
[0094] The write signal input terminal of the row memory receives the signal output by the first logical AND gate AND1. That is, when the data valid input signal de is valid and the value of the odd row count signal vcnt is 1, it indicates that the current transmission is an odd row. At this time, the first logical AND gate AND1 outputs a valid signal, causing the row memory to perform a write signal operation.
[0095] The read signal input terminal of the row memory receives the signal output by the second logic AND gate AND2. That is, when the data valid input signal de is valid and the value of the odd / even row count signal vcnt is 0, it indicates that the current transmission is an even row. At this time, the second logic AND gate AND2 outputs a valid signal, causing the row memory to perform a read signal operation.
[0096] The address input terminal of the row memory receives the column count signal hcnt, and the data input terminal of the row memory receives the data input signal din, so that the row memory stores the data of the current row according to the count value of the column count signal hcnt.
[0097] In this way, the odd-row controller is configured to save the current sub-pixel row when an odd-row input is received, and to read and output odd-row data when an even-row input is received.
[0098] The data input terminals of the first data signal register group U1 and the second data signal register group U2 respectively receive the signals output by the row memory. The input terminal of the second logic NOT gate INV2 receives the least significant bit of the column count signal hcnt.
[0099] The enable terminal of the first data signal register group U1 receives the signal output by the second logic NOT gate INV2. The first data signal register group U1 is used to obtain the signal of the sub-pixel of the 2i+1th column in the current row, so as to output the first intermediate sub-signal.
[0100] The enable terminal of the second data signal register group U2 receives the least significant bit of the column count signal hcnt. The second data signal register group U2 is used to obtain the signal of the sub-pixel of the 2i+2th column in the current row, so as to output the second intermediate sub-signal.
[0101] That is, when the least significant bit of the column count signal hcnt is 0, it indicates that the currently transmitted data is an odd-numbered column. At this time, the second NOT gate INV2 outputs a valid signal, enabling the first data signal register group U1 to buffer and output the signal of the current column. When the least significant bit of the column count signal hcnt is 1, it indicates that the currently transmitted data is an odd-numbered column. This signal directly enables the second data signal register group U2 to buffer and output the signal of the current column.
[0102] Therefore, please refer to Figure 7 For the odd row din(odd) signal of the data input signal din, the odd row controller splits and reassembles the signals of each column of sub-pixels (O1 sub-pixels to ON sub-pixels) in the odd row din(odd) into a serial first intermediate sub-signal composed of the signals of each 2i+1 column of sub-pixels, and a serial second intermediate sub-signal composed of the signals of each 2i+2 column of sub-pixels.
[0103] The even-row controller is used to convert the serial signal of each even-row single channel in the data input signal din into a third intermediate sub-signal and a fourth intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The third intermediate sub-signal is the serial signal of each 2i+1 column sub-pixels in the even-row, and the fourth intermediate sub-signal is the serial signal of each 2i+2 column sub-pixels in the even-row, where i is a natural number.
[0104] Alternatively, in some possible implementations, please refer to Figure 8 The even-row controller includes a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a third NOT gate INV3, a fourth NOT gate INV4, a third data signal register group U3, and a fourth data signal register group U4.
[0105] The even-row controller is used to output even-row data when an even-row input occurs, wherein:
[0106] The clock input terminals of the third data signal register group U3 and the fourth data signal register group U4 respectively receive the clock input signal clk;
[0107] The data input terminals of the third data signal register group U3 and the fourth data signal register group U4 respectively receive the data input signal din;
[0108] The input terminal of the fourth NOT gate INV4 receives the parity row counting signal vcnt.
[0109] The two inputs of the third logic AND gate AND3 receive the data valid input signal de and the signal output by the fourth logic NOT gate INV4, respectively.
[0110] The input of the third NOT gate INV3 receives the least significant bit of the column counting signal hcnt;
[0111] The two inputs of the fourth logic AND gate AND4 receive the signal output by the third logic AND gate AND3 and the least significant bit of the column counting signal hcnt, respectively.
[0112] The two inputs of the fifth AND gate AND5 receive the signals output by the third AND gate AND3 and the third NOT gate INV3, respectively.
[0113] The enable terminal of the third data signal register group U3 receives the signal output by the fifth logic AND gate AND5. The third data signal register group U3 is used to obtain the signal of the sub-pixel of the 2i+1th column in the current row, so as to output the third intermediate sub-signal.
[0114] The enable terminal of the fourth data signal register group U4 receives the signal output by the fourth logic AND gate AND4. The fourth data signal register group U4 is used to obtain the signal of the sub-pixel of the 2i+2th column in the current row, so as to output the fourth intermediate sub-signal.
[0115] Specifically, when the valid data input signal *de* is valid and the odd / even row count signal *vcnt* is 0, it indicates that the currently transmitted row is an even number. In this case, the third logic AND gate AND3 can then display a valid signal, allowing the third and fourth data signal registers to potentially be enabled. That is, the third and fourth data signal registers can only be enabled on even-numbered rows.
[0116] When the least significant bit of the column count signal hcnt is 0, it indicates that the currently transmitted data is an odd-numbered column. At this time, the third NOT gate INV3 outputs a valid signal. This signal, together with the signal of the third AND gate AND3, enables the third data signal register group U3 to buffer and output the signal of the current column. When the least significant bit of the column count signal hcnt is 1, it indicates that the currently transmitted data is an odd-numbered column. This signal, together with the signal of the third AND gate AND3, enables the second data signal register group U2 to buffer and output the signal of the current column.
[0117] Therefore, please refer to Figure 9 For the even-numbered row din(even) signal of the data input signal din, the even-numbered row controller splits and reassembles the signals of each column of sub-pixels (E1 sub-pixels to EN sub-pixels) in the even-numbered row din(even) into a serial third intermediate sub-signal composed of the signals of each 2i+1 column of sub-pixels, and a serial fourth intermediate sub-signal composed of the signals of each 2i+2 column of sub-pixels.
[0118] The synchronization signal controller is used to synchronize the first intermediate sub-signal, the second intermediate sub-signal, the third intermediate sub-signal, and the fourth intermediate sub-signal to obtain the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal. The data of the sub-pixels in the 2j+1th row and the 2n+1st column of the data input signal din, the sub-pixels in the 2j+1st row and the 2n+2nd column of the data input signal din, and the sub-pixels in the 2j+2nd row and the 2n+2nd column of the data input signal din are synchronously output in the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal, respectively, where j is a natural number.
[0119] Optionally, in one possible implementation, the synchronization signal controller is further configured to perform synchronization processing on the line synchronization input signal hsy, the field synchronization input signal vsy, the data valid input signal de, and the clock input signal clk, and output a line synchronization valid signal HSYNC, a field synchronization valid signal VSYNC, a data valid signal VALID, and a pixel clock output signal PCLK that are synchronized with the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal.
[0120] Specifically, please refer to Figure 10 In one possible implementation, the synchronization signal controller includes a clock divider, a fifth data signal register group U5, a sixth data signal register group U6, a seventh data signal register group U7, an eighth data signal register group U8, a first field synchronization input signal register U9, a second field synchronization input signal register U10, a first row synchronization input signal register U11, a second row synchronization input signal register U12, a first data valid input signal register U13, and a second data valid input signal register U14.
[0121] The clock input terminals of the clock divider, the first field synchronization input signal register U9, the second field synchronization input signal register U10, the first row synchronization input signal register U11, the second row synchronization input signal register U12, the first data valid input signal register U13, and the second data valid input signal register U14 respectively receive the clock input signal clk;
[0122] The input terminal of the clock divider receives the signal output by the clock divider, and the clock divider also outputs a synchronized pixel clock output signal PCLK.
[0123] The clock input terminals of the fifth data signal register group U5, the sixth data signal register group U6, the seventh data signal register group U7, and the eighth data signal register group U8 respectively receive the signals output by the clock divider.
[0124] The data input terminals of the fifth data signal register group U5, the sixth data signal register group U6, the seventh data signal register group U7, and the eighth data signal register group U8 respectively receive the signals output by the first data signal register group U1, the second data signal register group U2, the third data signal register group U3, and the fourth data signal register group U4.
[0125] The data input terminal of the first field synchronization input signal register U9 receives the field synchronization input signal vsy;
[0126] The data input terminal of the second field synchronization input signal register U10 receives the signal output from the data output terminal of the first field synchronization input signal register U9, and the data output terminal of the second field synchronization input signal register U10 outputs the re-synchronized field synchronization valid signal VSYNC.
[0127] The data input terminal of the first line synchronization input signal register U11 receives the line synchronization input signal hsy;
[0128] The data input terminal of the second line synchronization input signal register U12 receives the signal output from the data output terminal of the first line synchronization input signal register U11, and the data output terminal of the second line synchronization input signal register U12 outputs the re-synchronized line synchronization valid signal HSYNC.
[0129] The data input terminal of the first data valid input signal register U13 receives the data valid input signal de;
[0130] The data input terminal of the second valid data input signal register U14 receives the signal output from the data output terminal of the first valid data input signal register U13, and the data output terminal of the second valid data input signal register U14 outputs the reconstituted and synchronized valid data signal VALID.
[0131] Please refer to Figure 11 , Figure 11This is a timing diagram of the signals output by the synchronization signal controller. Through the synchronization processing of the synchronization signal controller, the first intermediate sub-signal, the second intermediate sub-signal, the third intermediate sub-signal, and the fourth intermediate sub-signal, which have timing delays, can be adjusted so that the four sub-pixel signals output synchronously by the adjusted first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal each correspond to one pixel unit. For example, sub-pixel signal O1 in the first output sub-signal, sub-pixel signal O2 in the second output sub-signal, sub-pixel signal E1 in the third output sub-signal, and sub-pixel signal E2 in the fourth output sub-signal respectively correspond to... Figure 1 The sub-pixels shown are 1-1, 1-2, 2-1, and 2-2. This achieves the splitting and recombination of the single-channel data input signal din into four output signals, thereby significantly reducing the display driver's requirements for the number of external video input signal ports.
[0132] This embodiment also provides a display panel, which includes the video signal processing circuit provided in this embodiment.
[0133] In one possible implementation, the display panel includes a monochrome high-resolution display panel, wherein the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal are used to synchronously drive four sub-pixels in the same pixel.
[0134] This embodiment also provides an electronic device, which includes the display panel provided in this embodiment.
[0135] In summary, this application provides a video signal processing circuit, a display panel, and an electronic device. The video signal processing circuit can reassemble a single-channel data input signal din into synchronized first intermediate sub-signals, second intermediate sub-signals, third intermediate sub-signals, and fourth intermediate sub-signals corresponding to four sub-pixels of a pixel unit. Thus, only one data input signal din is needed in the input signal, significantly reducing the display driver's requirements for the number of external video input signal ports.
[0136] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0137] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0138] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0139] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A video signal processing circuit, characterized in that, The video signal processing circuit includes: The column counter is used to count and output the column count signal hcnt for each row of video signal based on the input row synchronization input signal hsy and the data valid input signal de. When the data valid input signal de is valid, the column count signal hcnt is based on the clock input signal clk. The odd / even line counter is used to count the input line synchronization signal hsy, so as to output different odd / even line counting signals vcnt for odd and even lines in the video signal; An odd-row controller is configured to convert the single-channel serial signal of each odd-row in the data input signal din into a first intermediate sub-signal and a second intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The first intermediate sub-signal is the serial signal of each 2i+1 column sub-pixels in the odd-row, and the second intermediate sub-signal is the serial signal of each 2i+2 column sub-pixels in the odd-row, where i is a natural number. An even-row controller is configured to convert the serial signal of each even-row single channel in the data input signal din into a third intermediate sub-signal and a fourth intermediate sub-signal in parallel output, based on the column counting signal hcnt, the odd-even row counting signal vcnt, and the input data input signal din. The third intermediate sub-signal is the serial signal of each 2i+1 column sub-pixel in the even-row, and the fourth intermediate sub-signal is the serial signal of each 2i+2 column sub-pixel in the even-row. A synchronization signal controller is used to synchronize the first intermediate sub-signal, the second intermediate sub-signal, the third intermediate sub-signal, and the fourth intermediate sub-signal to obtain a first output sub-signal, a second output sub-signal, a third output sub-signal, and a fourth output sub-signal. The data of the sub-pixels in the 2j+1th row and 2n+1th column of the data input signal din, the sub-pixels in the 2j+1th row and 2n+2th column of the data input signal din, and the sub-pixels in the 2j+2th row and 2n+2th column of the data input signal din are synchronously output in the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal, respectively, where j is a natural number.
2. The video signal processing circuit according to claim 1, characterized in that, The input terminals of the column counter receive the row synchronization input signal hsy and the data valid input signal de, respectively. The column counter is used to count according to the clock input signal clk when the data valid input signal de is valid, and to output the column count signal hcnt. When the row synchronization input signal hsy is valid, the column count signal hcnt is cleared.
3. The video signal processing circuit according to claim 1, characterized in that, The input terminals of the odd and even row counters receive the row synchronization input signal hsy and the field synchronization input signal vsy, respectively. The odd / even row counter flips and counts to output the odd / even row count signal vcnt when the row synchronization input signal hsy is valid, and clears the odd / even row count signal vcnt when the field synchronization input signal vsy is valid.
4. The video signal processing circuit according to claim 1, characterized in that, The odd-row controller includes a first NOT gate, a second NOT gate, a first AND gate, a second AND gate, a row memory, a first data signal register group, and a second data signal register group; The odd-row controller is used to save the current sub-pixel row when an odd-row input occurs, and to read and output odd-row data when an even-row input occurs, wherein: The two inputs of the first AND gate receive the data valid input signal de and the odd / even row count signal vcnt, respectively. The input of the first NOT gate receives the parity row counting signal vcnt; The two inputs of the second AND gate receive the data valid input signal de and the output signal of the first NOT gate, respectively. The clock input terminals of the first data signal register group and the second data signal register group of the row memory respectively receive the clock input signal clk. The write signal input terminal of the row memory receives the signal output by the first logic AND gate; The read signal input terminal of the row memory receives the signal output by the second logic AND gate; The address input terminal of the row memory receives the column counting signal hcnt; The data input terminal of the row memory receives the data input signal din; The data input terminals of the first data signal register group and the second data signal register group respectively receive the signals output by the row memory; The input of the second NOT gate receives the least significant bit of the column counting signal hcnt; The enable terminal of the first data signal register group receives the signal output by the second logic NOT gate. The first data signal register group is used to obtain the signal of the sub-pixel in the 2i+1th column of the current row, so as to output the first intermediate sub-signal. The enable terminal of the second data signal register group receives the least significant bit of the column count signal hcnt. The second data signal register group is used to obtain the signal of the sub-pixel of the 2i+2th column in the current row, so as to output the second intermediate sub-signal.
5. The video signal processing circuit according to claim 4, characterized in that, The even-row controller includes a third AND gate, a fourth AND gate, a fifth AND gate, a third NOT gate, a fourth NOT gate, a third data signal register group, and a fourth data signal register group; The even-row controller is used to output even-row data when an even-row input is received, wherein: The clock input terminals of the third data signal register group and the fourth data signal register group respectively receive the clock input signal clk; The data input terminals of the third data signal register group and the fourth data signal register group respectively receive the data input signal din; The input terminal of the fourth NOT gate receives the parity row counting signal vcnt; The two inputs of the third AND gate receive the data valid input signal de and the signal output by the fourth NOT gate, respectively. The input of the third NOT gate receives the least significant bit of the column count signal hcnt. The two inputs of the fourth AND gate receive the signal output by the third AND gate and the least significant bit of the column counting signal hcnt, respectively. The two inputs of the fifth AND gate receive the signals output by the third AND gate and the third NOT gate, respectively. The enable terminal of the third data signal register group receives the signal output by the fifth logic AND gate. The third data signal register group is used to obtain the signal of the sub-pixel in the 2i+1th column of the current row, so as to output the third intermediate sub-signal. The enable terminal of the fourth data signal register group receives the signal output by the fourth logic AND gate. The fourth data signal register group is used to obtain the signal of the sub-pixel in the 2i+2th column of the current row, so as to output the fourth intermediate sub-signal.
6. The video signal processing circuit according to claim 5, characterized in that, The synchronization signal controller is also used to perform synchronization processing on the line synchronization input signal hsy, the field synchronization input signal vsy, the data valid input signal de, and the clock input signal clk, and output the line synchronization valid signal HSYNC, the field synchronization valid signal VSYNC, the data valid signal VALID, and the pixel clock output signal PCLK that are synchronized with the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal.
7. The video signal processing circuit according to claim 6, characterized in that, The synchronization signal controller includes a clock divider, a fifth data signal register group, a sixth data signal register group, a seventh data signal register group, an eighth data signal register group, a first field synchronization input signal register, a second field synchronization input signal register, a first row synchronization input signal register, a second row synchronization input signal register, a first data valid input signal register, and a second data valid input signal register. The clock input terminals of the clock divider, the first field synchronization input signal register, the second field synchronization input signal register, the first row synchronization input signal register, the second row synchronization input signal register, the first data valid input signal register, and the second data valid input signal register respectively receive the clock input signal clk; The input terminal of the clock divider receives the signal output by the clock divider, and the clock divider also outputs a synchronized pixel clock output signal PCLK. The clock input terminals of the fifth, sixth, seventh, and eighth data signal register groups respectively receive the signals output by the clock divider. The data input terminals of the fifth data signal register group, the sixth data signal register group, the seventh data signal register group, and the eighth data signal register group respectively receive the signals output by the first data signal register group, the second data signal register group, the third data signal register group, and the fourth data signal register group; The data input terminal of the first field synchronization input signal register receives the field synchronization input signal vsy; The data input terminal of the second field synchronization input signal register receives the signal output from the data output terminal of the first field synchronization input signal register, and the data output terminal of the second field synchronization input signal register outputs the re-synchronized field synchronization valid signal VSYNC; The data input terminal of the first row synchronization input signal register receives the row synchronization input signal hsy; The data input terminal of the second row synchronization input signal register receives the signal output from the data output terminal of the first row synchronization input signal register, and the data output terminal of the second row synchronization input signal register outputs the re-synchronized row synchronization valid signal HSYNC. The data input terminal of the first valid data input signal register receives the valid data input signal de; The data input terminal of the second valid data input signal register receives the signal output from the data output terminal of the first valid data input signal register, and the data output terminal of the second valid data input signal register outputs the reassembled and synchronized valid data signal VALID.
8. A display panel, characterized in that, The display panel includes the video signal processing circuit according to any one of claims 1-7.
9. The display panel according to claim 8, characterized in that, The display panel includes a monochrome high-resolution display panel, and the first output sub-signal, the second output sub-signal, the third output sub-signal, and the fourth output sub-signal are used to synchronously drive four sub-pixels in the same pixel.
10. An electronic device, characterized in that, The electronic device includes the display panel as described in claim 9.