Display panel driving method, display device

Abstract

This application discloses a driving method and a display device for a display panel. The driving process of the display panel includes a first stage, a display stage, and a second stage, with the display stage located between the first and second stages. The driving method of the display panel includes: at a first moment within the first stage, starting to provide a first voltage to a metal pattern, the first voltage being greater than 0; at a second moment within the first stage, starting to provide a first black state voltage to a data line; at a third moment within the second stage, stopping the provision of a second voltage to the metal pattern, the second voltage being greater than 0; and at a fourth moment within the second stage, stopping the provision of a second black state voltage to the data line; wherein the first moment is before the second moment, and / or the third moment is after the fourth moment. According to the embodiments of this application, the flickering problem of the display panel during power-on and power-off processes can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving method for a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, users have increasingly higher requirements for the performance of display panels in all aspects.

[0003] Pixel circuits can be installed in the display panel to drive the light-emitting elements for display. Pixel circuits include multiple transistors, which can be used for data writing or driving current generation, etc.

[0004] However, transistors in pixel circuits are prone to leakage, which can cause screen flickering during power-on and power-off of the display panel, affecting the user experience. Summary of the Invention

[0005] This application provides a driving method and display device for a display panel, which can improve the screen flickering problem of the display panel during power-on and power-off processes.

[0006] In a first aspect, embodiments of this application provide a driving method for a display panel, wherein the display panel includes a substrate, a metal pattern, a pixel circuit, and a light-emitting element. In the thickness direction of the display panel, the metal pattern is located between the substrate and the pixel circuit, and the metal pattern overlaps with the orthographic projection of the channel of at least a portion of the transistors in the pixel circuit onto the substrate. The pixel circuit is electrically connected to a data line. The driving process of the display panel includes a first stage, a display stage, and a second stage, with the display stage located between the first stage and the second stage.

[0007] The driving methods include:

[0008] At the first moment within the first phase, a first voltage is applied to the metal pattern, and the first voltage is greater than 0; at the second moment within the first phase, a first black state voltage is applied to the data line; at the third moment within the second phase, the application of a second voltage to the metal pattern is stopped, and the second voltage is greater than 0; at the fourth moment within the second phase, the application of a second black state voltage to the data line is stopped; wherein, the first moment is before the second moment, and / or, the third moment is after the fourth moment.

[0009] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device, including:

[0010] The display panel includes a substrate, a metal pattern, a pixel circuit, and a light-emitting element. In the thickness direction of the display panel, the metal pattern is located between the substrate and the pixel circuit. The metal pattern overlaps with the orthographic projection of the channel of at least a portion of the transistors in the pixel circuit onto the substrate. The pixel circuit is electrically connected to a data line.

[0011] The driving process of the display panel includes a first stage, a display stage, and a second stage, with the display stage located between the first and second stages.

[0012] The power driver chip is used to start providing a first voltage to the metal pattern at a first moment in the first stage, and to stop providing a second voltage to the metal pattern at a third moment in the second stage, wherein the first voltage is greater than 0 and the second voltage is greater than 0.

[0013] The display driver chip is used to start providing a first black state voltage to the data line at a second moment in the first stage, and to stop providing a second black state voltage to the data line at a fourth moment in the second stage.

[0014] The display phase of the display panel is located between the first phase and the second phase, wherein the first moment is before the second moment, and / or the third moment is after the fourth moment.

[0015] According to the display panel driving method and display device provided in the embodiments of this application, for transistors overlapping with a metal pattern, the metal pattern can block bottom reflection and shield the bottom electrostatic field effect caused by static charge accumulation. In the first stage, the metal pattern is powered on before the data line, so that the threshold voltage of the transistor can be in a negative bias state before the data line is powered on, thereby offsetting at least part of the effect of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the screen flickering problem that occurs during the power-on process of the display panel. And / or, in the second stage, the metal pattern is powered off after the data line, so that the threshold voltage of the transistor can be in a negative bias state after the data line is powered off, thereby offsetting at least part of the effect of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the screen flickering problem that occurs during the power-off process of the display panel. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0017] Figure 1 This illustration shows a top view of a display device provided in an embodiment of this application.

[0018] Figure 2 This illustration shows a cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0019] Figure 3 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0020] Figure 4This diagram illustrates a timing schematic of a display panel provided in an embodiment of this application.

[0021] Figure 5 This illustration shows another timing diagram of the display panel provided in an embodiment of this application;

[0022] Figure 6 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0023] Figure 7 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0024] Figure 8 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0025] Figure 9 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0026] Figure 10 This illustration shows another circuit structure diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0027] Figure 11 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0028] Figure 12 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0029] Figure 13 This invention provides a different top view of the display device according to an embodiment of the present application.

[0030] Figure 14 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0031] Figure 15 This illustration shows another circuit structure diagram of the pixel circuit in the display panel provided in the embodiments of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100. Display panel; 200. Display driver chip; 300. Power driver chip;

[0034] 10. Substrate;

[0035] 20. Pixel circuit; 30. Light-emitting element;

[0036] 40. Transmit shift circuit; 41. First transmit shift circuit;

[0037] 50. First scan shift circuit; 51. First A scan shift circuit;

[0038] 60. Second scan shift circuit; 61. Second A scan shift circuit. Detailed Implementation

[0039] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0041] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0042] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] The term "connection" can refer to "electrical connection" or "electrical connection without intermediate transistors." The term "drive" can refer to "control" or "operation." The term "part" can refer to "section." The term "pattern" can refer to "component." The term "end" can refer to "end segment" or "end edge." A display panel can be a display device or a module / part of a display device.

[0044] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0045] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0046] Due to the presence of electrostatic fields such as triboelectric static electricity and electrostatic coupling, the threshold voltage of transistors in pixel circuits is forward biased. This causes the transistors to fail to completely shut off during power-on and power-off processes, resulting in leakage current and causing screen flickering issues on the display panel. For example, the high luminous efficiency of green light-emitting elements can cause a green flickering problem during power-on and power-off processes, affecting the user experience.

[0047] To address the aforementioned technical problems, this application provides a display panel and its driving method, as well as a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and its driving method, as well as the display device.

[0048] This application provides a driving method for a display panel, which can be applied to... Figure 1 In the display device shown.

[0049] Please refer to Figure 1 and Figure 2 The display device includes a display panel 100, a display driver chip 200, and a power driver chip 300. The display panel 100 includes a substrate 10, a metal pattern BSM, a pixel circuit 20, and a light-emitting element 30.

[0050] like Figure 1 As shown, multiple pixel circuits 20 can be arranged in an array along the first direction X and the second direction Y, and multiple light-emitting elements 30 can also be arranged in an array along the first direction X and the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X can be a row direction, and the second direction Y can be a column direction.

[0051] Pixel circuit 20 is electrically connected to light-emitting element 30, and pixel circuit 20 can be used to drive light-emitting element 30 to emit light. Light-emitting element 30 may include organic light-emitting diode (OLED). In addition, pixel circuit 20 is electrically connected to data line DATA.

[0052] like Figure 2 As shown, in the thickness direction Z of the display panel 100, the metal pattern BSM is located between the substrate 10 and the pixel circuit 20, and the metal pattern BSM overlaps with the orthographic projection of the communication of at least some transistors in the pixel circuit 20 onto the substrate 10.

[0053] As an example, such as Figure 3 As shown, the pixel circuit 20 may include a driving transistor M3 and at least one switching transistor. The driving transistor M3 can be used to generate a driving current to drive the light-emitting element 30 to emit light, and the magnitude of the driving current affects the brightness of the light-emitting element 30. The switching transistor can be used to perform on or off actions, and can be used to transmit signals when on. For example, the switching transistor includes light-emitting control transistors M1 and M6, a data writing transistor M2, a threshold compensation transistor M4, a reset transistor M5, and an initialization transistor M7. The first terminal of the data writing transistor M2 is electrically connected to the data line DATA, and the second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M3.

[0054] The metal pattern BSM may overlap with the channel of at least one of the following: driving transistor M3, light-emitting control transistors M1 and M6, data writing transistor M2, threshold compensation transistor M4, reset transistor M5, and initialization transistor M7.

[0055] like Figure 4 As shown, the driving process of the display panel 100 includes a first stage T1, a display stage T3, and a second stage T2, with the display stage T3 located between the first stage T1 and the second stage T2. The first stage T1 is the power-on stage before the display panel 100 enters normal display, such as the power-on stage / wake-up stage. The second stage T2 is the power-off stage after the display panel 100 ends normal display, such as the power-off stage / sleep stage.

[0056] The driving method for the display panel provided in this application embodiment may include: at a first time t1 within a first stage T1, starting to provide a first voltage V1 to the metal pattern BSM, where the first voltage V1 is greater than 0; at a second time t2 within the first stage T1, starting to provide a first black state voltage vgmp1 to the data line DATA; at a third time within the second stage T2, stopping the provision of a second voltage V2 to the metal pattern BSM, where the second voltage V2 is greater than 0; and at a fourth time t4 within the second stage T2, stopping the provision of a second black state voltage vgmp2 to the data line DATA. Wherein, the first time t1 is before the second time t2, and / or, the third time t3 is after the fourth time t4.

[0057] It should be noted that in the first stage T1 and the second stage T2, the display panel 100 is in a black state. The first black state voltage vgmp1 and the second black state voltage vgmp2 are voltages that can make the display panel 100 appear in a black state.

[0058] Furthermore, before voltage is supplied to the metal pattern BSM, the metal pattern BSM can be in a de-energized state; before voltage supply to the metal pattern BSM stops, the metal pattern BSM can be in a energized state; and after voltage supply to the metal pattern BSM stops, the metal pattern BSM can be in a de-energized state. Similarly, before voltage is supplied to the data line DATA, the data line DATA can be in a de-energized state; before voltage supply to the data line DATA stops, the data line DATA can be in a energized state; and after voltage supply to the data line DATA stops, the data line DATA can be in a de-energized state. Exemplarily, in the embodiments of this application and the embodiments mentioned below, the potential of the metal pattern or various signal lines in the de-energized or de-energized state can be equal to the ground potential (GND potential), for example, the GND potential can be 0V.

[0059] Due to the presence of electrostatic fields such as triboelectric static electricity and electrostatic coupling, the threshold voltage of the transistors in the pixel circuit is forward biased, preventing the transistors from completely turning off during power-on and power-off processes. If the data line DATA is powered on before the metal pattern BSM, or powered off after the metal pattern BSM, the higher black-state voltage on the data line DATA can easily flow into the light-emitting element 30, causing the light-emitting element 30 to emit light. This can lead to screen flickering issues on the display panel during power-on and power-off processes.

[0060] In this embodiment, for the transistor overlapping with the metal pattern BSM, the metal pattern BSM is disposed between the substrate and the transistor channel, and the metal pattern BSM can block bottom reflection; furthermore, the metal pattern BSM can shield the bottom electrostatic field effect caused by the accumulation of static charge in the substrate, thereby reducing the back channel phenomenon of the transistor caused by the static charge in the substrate. In the first stage T1, the metal pattern BSM is powered on before the data line DATA, so that the threshold voltage of the transistor is initially in a negative bias state before the data line DATA is powered on, thereby offsetting at least part of the effect of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the screen flickering problem that occurs during the power-on process of the display panel. And / or, in the second stage T2, the metal pattern BSM is powered off after the data line DATA, so that the threshold voltage of the transistor is in a negative bias state after the data line DATA is powered off, thereby offsetting at least part of the effect of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the screen flickering problem that occurs during the power-off process of the display panel.

[0061] For example, the metal pattern BSM may include a portion extending along a first direction X, and may also include a portion extending along a second direction Y. For instance, the metal pattern BSM may be in the form of a grid structure.

[0062] For example, the display panel 100 may also include multiple insulating layers, such as... Figure 2 As shown, the multiple insulating layers include a buffer layer, a gate insulating layer GI, a capacitor insulating layer IMD, an interlayer dielectric layer ILD, a planarization layer PLN, and a pixel definition layer PDL.

[0063] It should be noted that the structure of the display panel in this embodiment may include Figure 2 The structure shown is not limited to this.

[0064] like Figure 3 The pixel circuit 20 includes a driving transistor M3 and at least one switching transistor. Figure 3 The switching transistors include transistors M1, M2, M4, M5, M6, and M7. Additionally... Figure 3 The diagram shows that each transistor is a P-type transistor. It should be noted that the structure of the pixel circuit in this application may include... Figure 3 The structure shown is not limited to this.

[0065] In some embodiments, the metal pattern BSM may overlap at least with the orthogonal projection of the channel of the driving transistor M3 onto the substrate 10. During power-on and power-off processes, if leakage current exists in the driving transistor M3, it is more likely to cause the light-emitting element 30 to emit light. In this embodiment, the metal pattern BSM may overlap at least with the channel of the driving transistor M3. Thus, during power-on and / or power-off processes, the metal pattern BSM may at least be used to counteract the forward bias effect of the driving transistor M3, thereby improving the leakage current problem of the driving transistor M3 during power-on and / or power-off processes, and further improving the screen flicker problem of the display panel.

[0066] For example, the metal pattern BSM may overlap with the orthographic projection of the channel of each transistor in the pixel circuit 20 onto the substrate 10.

[0067] For example, each transistor in pixel circuit 20 may be a P-type transistor.

[0068] In some embodiments, the interval between the first time t1 and the second time t2 is t12, where t12 ≥ 1 / F; and / or, the interval between the third time t3 and the fourth time t4 is t34, where t34 ≥ 1 / F. Wherein, F is the frame refresh rate of the display panel.

[0069] The frame refresh rate is the frequency of change of the smallest unit of screen refresh, the subframe. During the driving process of the display panel, a field synchronization signal (VS) may be included, and the frame refresh rate can be equal to the refresh rate of the field synchronization signal VS. It can be understood that 1 / F represents the duration of one frame, and 2 / F represents the duration of two frames.

[0070] In this embodiment, powering on the data line DATA begins only after the metal pattern BSM has been powered on for at least one frame. This ensures that the power-on signal of the metal pattern BSM is basically stable before powering on the data line DATA. This further ensures the correction of transistor threshold voltage offset after the metal pattern BSM is powered on, thereby better improving the screen flickering problem during power-on. Similarly, powering off the metal pattern BSM begins only after the data line DATA has been powered off for at least one frame. This ensures that the power-off of the data line DATA is basically stable before powering off the metal pattern BSM. This further ensures the correction of transistor threshold voltage offset after the data line DATA is powered off, thereby better improving the screen flickering problem during power-off.

[0071] In some embodiments, the interval between the first time t1 and the second time t2 is t12, where t12 ≤ 2 / F; and / or, the interval between the third time t3 and the fourth time t4 is t34, where t34 ≤ 2 / F. Wherein, F is the frame refresh rate of the display panel.

[0072] The longer the power-on interval between the metal pattern BSM and the data line DATA, the longer the overall duration of the first stage T1 will be. This means a longer power-on time for the display panel, which exacerbates transistor leakage and negatively impacts user experience. In this embodiment, the power-on interval between the metal pattern BSM and the data line DATA is no greater than 2 / F, thus avoiding excessive power-on time for the display panel. Similarly, the longer the power-off interval between the metal pattern BSM and the data line DATA, the longer the overall duration of the second stage T2 will be. This means a longer power-off time for the display panel, which exacerbates transistor leakage and negatively impacts user experience. In this embodiment, the power-off interval between the metal pattern BSM and the data line DATA is no greater than 2 / F, thus avoiding excessive power-off time for the display panel. In addition, t12≤2 / F can maintain the continuity of the power-on timing of the metal pattern BSM and the data line DATA; similarly, t34≤2 / F can maintain the continuity of the power-off timing of the data line DATA and the metal pattern BSM.

[0073] For example, 1 / F≤t12≤2 / F means that the data line DATA is powered on within 1 to 2 frames after the metal pattern BSM is powered on.

[0074] 1 / F≤t34≤2 / F, within 1~2 frames after the data line DATA is de-energized (i.e., the data line DATA starts to de-energize), the metal pattern BSM is de-energized (i.e., the metal pattern BSM starts to de-energize).

[0075] In some embodiments, the interval between the first and second moments is t12, and the interval between the third and fourth moments is t34, where t12 = t34. That is, the power-on interval of the metal pattern BSM and the data line DATA is equal to the power-off interval of the metal pattern BSM and the data line DATA. In this way, the driving timing of the power-on and power-off phases can be symmetrical, and the offset adjustment of the threshold voltage of the transistor can achieve a basically consistent effect. This allows the display panel to present a basically consistent black state during the power-on and power-off processes, thereby improving the user experience.

[0076] In some embodiments, the first voltage V1 is equal to the second voltage V2, and / or, the first black state voltage vgmp1 is equal to the second black state voltage vgmp2. This ensures that the voltage supplied to the metal pattern BSM is the same during the first stage T1 and the second stage T2, guaranteeing the consistency of the voltage supplied to the metal pattern BSM of the display panel during power-on and power-off phases; and / or, the same black state voltage supplied to the data line DATA during the first stage T1 and the second stage T2, guaranteeing the consistency of the voltage supplied to the data line DATA of the display panel during power-on and power-off phases. This allows the driving voltages during power-on and power-off phases to be symmetrical, and the adjustment of the threshold voltage offset of the transistors can achieve a substantially consistent effect, thereby enabling the display panel to present a substantially consistent black state during power-on and power-off processes, thus improving the user experience.

[0077] For example, the display panel may have a uniform black state voltage vgmp, and the first black state voltage vgmp1 and the second black state voltage vgmp2 may be greater than or equal to the black state voltage vgmp. For instance, the first black state voltage vgmp1 and the second black state voltage vgmp2 may both be equal to the black state voltage vgmp. As another example, the first black state voltage vgmp1 and the second black state voltage vgmp2 may both be equal to the reference voltage AVDD of the display driver chip, where the reference voltage AVDD is greater than the black state voltage vgmp. In this case, the voltages of at least some signals on the display panel may be derived from the reference voltage AVDD.

[0078] In some embodiments, at a second moment within the first stage, the supply of a first black-state voltage to the data line begins, which may include: at a second moment t2 within the first stage T1, the supply of a first black-state voltage vgmp1 to the data line DATA begins and lasts for a duration t10, where 1 / F ≤ t10 ≤ 2 / F, and F is the frame refresh rate of the display panel. And / or, at a fourth moment within the second stage, the supply of a second black-state voltage to the data line ceases, which may include: at a fourth moment t4 within the second stage T2, the supply of a second black-state voltage vgmp2 to the data line DATA ceases, and the duration of the supply of the second black-state voltage vgmp2 to the data line DATA within the second stage T2 is t40, where 1 / F ≤ t40 ≤ 2 / F.

[0079] In this embodiment, the black state voltage can make the display panel black. During the power-on and power-off phase, the duration of providing the black state voltage to the data line DATA can be within 1 to 2 frames. This can ensure the stability of the power-on and power-off of the data line DATA and avoid the power-on time of the data line DATA being too long during the power-on and power-off phase, thereby avoiding the power-on and power-off time of the display panel being too long.

[0080] In some embodiments, such as Figure 3As shown, the pixel circuit 20 is also electrically connected to the first power line PVDD. For example, the first terminal of the light-emitting control transistor M1 is electrically connected to the first power line PVDD, and the second terminal of the light-emitting control transistor M1 is electrically connected to the first terminal of the driving transistor M3. The voltage on the first power line PVDD after being powered on can be a positive voltage. When the light-emitting control transistor M1 is turned on, the positive voltage on the first power line PVDD can be transmitted to the first terminal of the driving transistor M3.

[0081] The first power line PVDD and the metal pattern BSM can be electrically connected to different signal terminals for power supply. In this way, the power-on sequence, power-off sequence, and power-on voltage of the first power line PVDD and the metal pattern BSM can be independently controlled, which is beneficial for flexibly setting the drive sequence and power-on voltage according to requirements.

[0082] For example, such as Figure 4 As shown, voltage can be supplied to the first power line PVDD and the metal pattern BSM at the same time during the first stage T1, and the supply of voltage to the first power line PVDD and the metal pattern BSM can be stopped at the same time during the second stage T2.

[0083] Or, such as Figure 5 As shown, voltage can be supplied to the first power line PVDD and the metal pattern BSM at different times during the first stage T1, and voltage can be stopped at different times during the second stage T2.

[0084] For example, different voltages can be supplied to the first power line PVDD and the metal pattern BSM, or the same voltage can be supplied to the first power line PVDD and the metal pattern BSM.

[0085] For example, when the threshold voltage of the transistor is severely forward biased, a larger voltage can be supplied to the metal pattern BSM (e.g., the voltage supplied to the metal pattern BSM can be greater than the voltage supplied to the first power line PVDD) so that the threshold voltage of the transistor can be negatively biased to a greater extent, thereby offsetting the severe forward bias of the threshold voltage. Of course, this is just one example, and embodiments of this application may include, but are not limited to, this.

[0086] In other embodiments, the first power line PVDD can be electrically connected to the metal pattern BSM. This allows the power-on sequence, power-off sequence, and power-on voltage of the first power line PVDD and the metal pattern BSM to be identical, simplifying the drive timing. Furthermore, when the first power line PVDD and the metal pattern BSM are electrically connected, they can be electrically connected to the same power supply signal terminal, eliminating the need for multiple power supply signal terminals and simplifying the structure.

[0087] Understandably, since the first power line PVDD is electrically connected to the metal pattern BSM, therefore, as Figure 4 As shown, the driving method for the display panel provided in this application embodiment further includes: at a first time t1 within the first stage T1, starting to provide a first voltage V1 to the first power line PVDD; and at a third time t3 within the second stage T2, stopping the provision of a second voltage V2 to the first power line PVDD. The first voltage V1 and the second voltage V2 are the voltages provided to the metal pattern BSM.

[0088] For example, the first voltage V1 and the second voltage V2 can be approximately 4.6V.

[0089] In some embodiments, such as Figure 3 As shown, the anode of the light-emitting element 30 is electrically connected to the pixel circuit 20, and the cathode of the light-emitting element 30 is also electrically connected to the second power line PVEE.

[0090] like Figure 6 As shown, the driving method for the display panel provided in this application embodiment further includes: at a first time t1 within the first stage T1, starting to provide a first power supply voltage Vee1 to the second power line PVEE, the first power supply voltage Vee1 being less than 0; at a third time t3 within the second stage T2, stopping the supply of a second power supply voltage Vee2 to the second power line PVEE, the second power supply voltage Vee2 being less than 0.

[0091] As described above, the first power line PVDD starts to be powered on at the first time t1, and stops being powered on at the third time t3 (i.e., the first power line PVDD stops being powered off at the third time t3). In this embodiment, the second power line PVEE and the first power line PVDD are powered on and off at the same time, that is, the second power line PVEE and the first power line PVDD are powered on and off simultaneously, which simplifies the control timing.

[0092] It should be noted that before voltage is supplied to the second power line PVEE and the first power line PVDD, the second power line PVEE and the first power line PVDD can be in a non-powered state; before voltage is supplied to the second power line PVEE and the first power line PVDD is stopped, the second power line PVEE and the first power line PVDD can be in a powered-on state; and after voltage is supplied to the second power line PVEE and the first power line PVDD is stopped, the second power line PVEE and the first power line PVDD can be in a powered-off state.

[0093] In some embodiments, the first power supply voltage Vee1 can be equal to the second power supply voltage Vee2. This ensures that the voltage supplied to the second power line PVEE is the same during the first stage T1 and the second stage T2, guaranteeing the consistency of the voltage supplied to the second power line PVEE of the display panel during power-on and power-off phases. This allows the power supply voltage to be symmetrical during power-on and power-off phases, achieving a substantially consistent effect on the threshold voltage offset adjustment of the transistors. Consequently, the display panel can present a substantially consistent black state during power-on and power-off processes, improving the user experience.

[0094] For example, the first power supply voltage Vee1 and the second power supply voltage Vee2 can be approximately -2.7V.

[0095] In some embodiments, such as Figure 3 As shown, the anode of the light-emitting element 30 is electrically connected to the initialization signal line Vini. For example, the first electrode of the initialization transistor M7 is electrically connected to the initialization signal line Vini, and the second electrode of the initialization transistor M7 is electrically connected to the anode of the light-emitting element 30. The initialization voltage after the initialization signal line Vini is energized can be used to initialize the anode potential of the light-emitting element 30.

[0096] like Figure 7 As shown, the driving method for the display panel provided in this application embodiment may further include: at the fifth time t5 within the first stage T1, starting to provide a first initialization voltage Vin1 to the initialization signal line Vini, the first initialization voltage Vin1 being less than 0; at the sixth time t6 within the second stage T2, stopping the provision of a second initialization voltage Vin2 to the initialization signal line Vini, the second initialization voltage Vin2 being less than 0; wherein, the fifth time t5 is before the first time t1, and / or, the sixth time t6 is after the third time t3.

[0097] As described above, the second power line PVEE and the first power line PVDD can be powered on and off simultaneously, as can the first power line PVDD and the metal pattern BSM. If, during the first stage T1, the power-on time of the initialization signal line Vini is after the power-on time of the second power line PVEE and the first power line PVDD, or, during the second stage T2, the power-off time of the initialization signal line Vini is before the power-off time of the second power line PVEE and the first power line PVDD, the cathode potential of the light-emitting element 30 will be negative, and the anode potential of the light-emitting element 30 will be GND. This will result in residual charge flowing through the circuit where the light-emitting element 30 is located, which may cause the light-emitting element 30 to flicker.

[0098] In this embodiment, since the fifth time t5 is before the first time t1, and / or the sixth time t6 is after the third time t3, it is convenient to control the power-on time of the initialization signal line Vini before the power-on time of the second power line PVEE and the first power line PVDD in the first stage T1, and / or to control the power-off time of the initialization signal line Vini after the power-off time of the second power line PVEE and the first power line PVDD in the second stage T2. This helps to avoid residual charge flowing through the line where the light-emitting element 30 is located, thereby helping to avoid causing the light-emitting element 30 to flicker.

[0099] It should be noted that before voltage is supplied to the initialization signal line Vini, the initialization signal line Vini can be in a de-energized state; before voltage is supplied to the initialization signal line Vini, the initialization signal line Vini can be in a energized state; and after voltage is supplied to the initialization signal line Vini, the initialization signal line Vini can be in a de-energized state.

[0100] In some embodiments, the interval between the first time t1 and the fifth time t5 is t15, t15≥1 / F; and / or, the interval between the third time t3 and the sixth time t6 is t36, t36≥1 / F; F is the frame refresh rate of the display panel.

[0101] In this embodiment, the metal pattern BSM is powered on only after the initialization signal line Vini has been powered on for at least one frame. This ensures that the power-on signal of the initialization signal line Vini is basically stable before powering on the metal pattern BSM, thus further avoiding the problem of flickering of the light-emitting element during the power-on phase. Similarly, the initialization signal line Vini is powered off only after the metal pattern BSM has been powered off for at least one frame. This ensures that the power-off of the metal pattern BSM is basically stable before powering off the initialization signal line Vini, thus further avoiding the problem of flickering of the light-emitting element during the power-off phase.

[0102] In some embodiments, the interval between the first time t1 and the fifth time t5 is t15, where t15 ≤ 2 / F; and / or, the interval between the third time t3 and the sixth time t6 is t36, where t36 ≤ 2 / F. Where F is the frame refresh rate of the display panel.

[0103] A longer power-on interval between the initialization signal line Vini and the metal pattern BSM will result in a longer overall duration of the first stage T1, meaning a longer power-on time for the display panel. A longer power-on time exacerbates transistor leakage and negatively impacts user experience. In this embodiment, the power-on interval between the initialization signal line Vini and the metal pattern BSM is no greater than 2 / F, thus preventing excessive power-on time for the display panel. Similarly, a longer power-off interval between the initialization signal line Vini and the metal pattern BSM will result in a longer overall duration of the second stage T2, meaning a longer power-off time for the display panel. A longer power-off time exacerbates transistor leakage and negatively impacts user experience. In this embodiment, the power-off interval between the initialization signal line Vini and the metal pattern BSM is no greater than 2 / F, thus preventing excessive power-off time for the display panel. In addition, t15≤2 / F can maintain the continuity of the power-on timing of the initialization signal line Vini and the metal pattern BSM; similarly, t36≤2 / F can maintain the continuity of the power-off timing of the initialization signal line Vini and the metal pattern BSM.

[0104] For example, 1 / F≤t15≤2 / F means that the metal pattern BSM is powered on within 1 to 2 frames after the initialization signal line Vini is powered on.

[0105] 1 / F≤t36≤2 / F, within 1~2 frames after the metal pattern BSM stops powering on (i.e. the metal pattern BSM starts powering off), the initialization signal line Vini stops powering on (i.e. the initialization signal line Vini starts powering off).

[0106] In some embodiments, the time interval between the first time t1 and the fifth time t5 is t15, and the time interval between the third time t3 and the sixth time t6 is t36, where t15 = t36.

[0107] That is, the power-on interval of the metal pattern BSM and the initialization signal line Vini is equal to the power-off interval of the metal pattern BSM and the initialization signal line Vini. In this way, the driving timing of the power-on and power-off phases can be symmetrical, which can have a basically consistent effect on the flickering problem of the light-emitting element during the power-on and power-off phases. This allows the display panel to present a basically consistent black state during the power-on and power-off process, thereby improving the user experience.

[0108] In some embodiments, the first initialization voltage Vin1 is equal to the second initialization voltage Vin2. This ensures that the voltage supplied to the initialization signal line Vin1 is the same during the first stage T1 and the second stage T2, which guarantees the consistency of the voltage supplied to the initialization signal line Vin1 of the display panel during the power-on and power-off phases. This can achieve a basically consistent effect on the flickering problem of the light-emitting element during the power-on and power-off phases, thereby making the display panel present a basically consistent black state during the power-on and power-off process, thus improving the user experience.

[0109] In some embodiments, such as Figure 3 As shown, the driving transistor M3 of the pixel circuit 20 can also be electrically connected to the reset signal line Vref. For example, the first terminal of the reset transistor M5 is electrically connected to the reset signal line Vref, and the second terminal of the reset transistor M5 is electrically connected to the gate of the driving transistor M3.

[0110] In one example, such as Figure 8 As shown, the driving method for the display panel provided in this application embodiment may further include: at a fifth time t5, starting to provide a first reset voltage Vref1 to the reset signal line Vref, the first reset voltage Vref1 being less than 0; at a sixth time t6, stopping the provision of a second reset voltage Vref2 to the reset signal line Vref, the second reset voltage Vref2 being less than 0.

[0111] In this embodiment, the power-on time of the initialization signal line Vini and the power-on time of the reset signal line Vref are both at the fifth time t5, and the power-off time of the initialization signal line Vini and the power-off time of the reset signal line Vref are both at the sixth time t6, which simplifies the control timing.

[0112] In another example, such as Figure 9 As shown, at the seventh time t7 within the first stage T1, the first reset voltage Vref1 is supplied to the reset signal line Vref, and the first reset voltage Vref1 is less than 0; at the eighth time t8 within the second stage T2, the supply of the second reset voltage Vref2 to the reset signal line Vref stops, and the second reset voltage Vref2 is less than 0; the seventh time t7 is different from the fifth time t5, and / or the eighth time t8 is different from the sixth time t6.

[0113] In this embodiment, the power-on time of the initialization signal line Vini and the power-on time of the reset signal line Vref are different times, and / or the power-off time of the initialization signal line Vini and the power-off time of the reset signal line Vref are different times. In this way, the power-on and power-off timing of the reset signal line Vref and the initialization signal line Vini can be flexibly controlled according to the requirements.

[0114] It should be noted that before voltage is supplied to the reset signal line Vref, the reset signal line Vref can be in a de-energized state; before voltage is supplied to the reset signal line Vref is stopped, the reset signal line Vref can be in a energized state; and after voltage is supplied to the reset signal line Vref is stopped, the reset signal line Vref can be in a de-energized state.

[0115] In some embodiments, the first reset voltage Vref1 is equal to the second reset voltage Vref2. In this way, the voltage supplied to the reset signal line Vref is the same in the first stage T1 and the second stage T2, which can ensure the consistency of the voltage supplied to the reset signal line Vref of the display panel during the power-on and power-off phases. The gate reset of the driving transistor M3 during the power-on and power-off phases can achieve a basically consistent effect, thereby making the display panel present a basically consistent black state during the power-on and power-off process, so as to improve the user experience.

[0116] In some embodiments, the reset voltage provided to the reset signal line Vref may not be equal to the initialization voltage provided to the initialization signal line Vini. For example, the first reset voltage Vref1 is not equal to the first initialization voltage Vin1, and the second reset voltage Vref2 is not equal to the second initialization voltage Vin2.

[0117] In some embodiments, such as Figure 10 As shown, the driving transistor M3 of the pixel circuit 20 can also be electrically connected to the bias adjustment signal line DVH. For example, the pixel circuit 20 can also include a bias adjustment transistor M8, with the first terminal of the bias adjustment transistor M8 electrically connected to the bias adjustment signal line DVH, and the second terminal of the bias adjustment transistor M8 electrically connected to the first terminal of the driving transistor M3.

[0118] like Figure 11 As shown, the driving method provided in this application embodiment may further include: at a second time t2 within the first stage T1, starting to provide a first bias adjustment voltage DVH1 to the bias adjustment signal line DVH; and at a fourth time t4 within the second stage T2, stopping the provision of a second bias adjustment voltage DVH2 to the bias adjustment signal line DVH. In this way, the power-on and power-off timings of the bias adjustment signal line DVH and the data line DATA can be the same, which helps to simplify the driving timing.

[0119] It is understandable that if the bias adjustment signal line DVH is powered on before the metal pattern BSM, or powered off after the metal pattern BSM, the higher bias adjustment voltage on the bias adjustment signal line DVH can easily flow into the light-emitting element 30, causing the light-emitting element 30 to emit light, thus causing the display panel to flicker during power-on and power-off. In this embodiment, the metal pattern BSM is powered on before the bias adjustment signal line DVH in the first stage T1. This allows the threshold voltage of the transistor to be negatively biased before the bias adjustment signal line DVH is powered on, thereby offsetting at least part of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the flicker problem that occurs during power-on. And / or, the metal pattern BSM is powered off after the bias adjustment signal line DVH in the second stage T2. This allows the threshold voltage of the transistor to be negatively biased after the bias adjustment signal line DVH is powered off, thereby offsetting at least part of the positive bias of the transistor threshold voltage caused by static electricity, and thus improving the flicker problem that occurs during power-off. When the bias adjustment transistor M8 is turned on, the first bias adjustment voltage DVH1 or the second bias adjustment voltage DVH2 can be transmitted to the first terminal of the driving transistor M3. The first bias adjustment voltage DVH1 and the second bias adjustment voltage DVH2 can be used to adjust the bias state of the driving transistor M3.

[0120] For example, the first bias adjustment voltage DVH1 is greater than 0, and the second bias adjustment voltage DVH2 is greater than 0.

[0121] For example, the first bias adjustment voltage DVH1 is equal to the second bias adjustment voltage DVH2. In this way, the voltage supplied to the bias adjustment signal line DVH is the same in the first stage T1 and the second stage T2. This can help the bias state adjustment of the driving transistor M3 of the display panel to be more consistent during the power-on and power-off stages, so that the display panel can present a basically consistent black state during the power-on and power-off processes, thereby improving the user experience.

[0122] In some embodiments, such as Figure 3 or Figure 10 As shown, the pixel circuit 20 is also electrically connected to the light-emitting control signal line EMIT. For example, the gates of the light-emitting control transistors M1 and M6 of the pixel circuit 20 are electrically connected to the light-emitting control signal line EMIT, the first electrode of the light-emitting control transistor M1 is electrically connected to the first power supply line PVDD, the second electrode of the light-emitting control transistor M1 is electrically connected to the first electrode of the driving transistor M3, the first electrode of the light-emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M3, and the second electrode of the light-emitting control transistor M6 is electrically connected to the anode of the light-emitting element 30.

[0123] like Figure 4As shown, the driving method for the display panel provided in this application embodiment may further include: providing a light emission disabling voltage VGH to the light emission control signal line EMIT during the first stage T1 and the second stage T2; and providing alternating light emission disabling voltage VGH and light emission enabling voltage VGL to the light emission control signal line EMIT during the display stage T3.

[0124] The light-emitting de-enabling voltage VGH is the voltage that controls the light-emitting control transistors M1 and M6 to turn off, while the light-emitting enabling voltage VGL is the voltage that controls the light-emitting control transistors M1 and M6 to turn on. During the first stage T1 and the second stage T2, the light-emitting de-enabling voltage VGH on the light-emitting control signal line EMIT can control the light-emitting control transistors M1 and M6 to turn off. In this way, leakage current from data lines such as DATA can be prevented from flowing to the light-emitting element 30, thereby further improving the screen flickering problem during power-on and power-off phases.

[0125] During the display phase T3, the alternating light-emitting de-enabling voltage VGH and light-emitting enabling voltage VGL on the light-emitting control signal line EMIT can control the light-emitting control transistors M1 and M6 to alternately turn on and off. In this way, the light-emitting element 30 can be controlled to alternately perform the light-emitting phase and the non-light-emitting phase.

[0126] For example, such as Figure 1 As shown, the display panel 100 also includes multiple cascaded transmission shift circuits 40. The transmission shift circuits 40 are electrically connected to the light emission control signal line EMIT. The transmission shift circuit 40 includes a first transmission shift circuit 41, which is also electrically connected to the transmission frame start signal line STV_E.

[0127] For example, providing a light emission disabling voltage VGH to the light emission control signal line EMIT during the first stage T1 and the second stage T2 may include: providing a light emission disabling voltage VGH to the transmit frame start signal line STV_E during the first stage T1 and the second stage T2, so as to control the transmit shift circuit 40 to provide a light emission disabling voltage VGH to the light emission control signal line EMIT.

[0128] During the display phase T3, alternating light-disabling voltage VGH and light-enabling voltage VGL are provided to the light-emitting control signal line EMIT. This may include: during the display phase T3, alternating light-disabling voltage VGH and light-enabling voltage VGL are provided to the transmit frame start signal line STV_E to control the transmit shift circuit 40 to provide alternating light-disabling voltage VGH and light-enabling voltage VGL to the light-emitting control signal line EMIT.

[0129] For example, such as Figure 1 As shown, the transmit shift circuit 40 is also connected to the first transmit clock signal line CK1_E and the second transmit clock signal line CK2_E, respectively. Figure 12 As shown, the driving method for the display panel provided in this application embodiment may further include: providing normal pulse signals to the first transmit clock signal line CK1_E and the second transmit clock signal line CK2_E in the first stage T1, the second stage T2 and the display stage T3.

[0130] In some embodiments, such as Figure 1 As shown, pixel circuit 20 is also electrically connected to scan line SCAN. For example, as Figure 3 As shown, the gate of the reset transistor M5 of the pixel circuit 20 is electrically connected to the first scan line SCAN1, the gate of the data writing transistor M2 of the pixel circuit 20 is electrically connected to the second scan line SCAN2, the gate of the threshold compensation transistor M4 is electrically connected to the third scan line SCAN3, and the gate of the initialization transistor M7 is electrically connected to the fourth scan line SCAN4. For example, as... Figure 10 As shown, the gate of the bias adjustment transistor M8 is electrically connected to the fifth scan line SCAN5.

[0131] like Figure 4 As shown, the driving method for the display panel provided in this application embodiment may further include: providing an enable voltage to the scan line SCAN during at least a portion of the time periods of the first stage T1 and the second stage T2.

[0132] For example, the driving method for the display panel provided in the embodiments of this application may further include: providing normal pulse signals to the scan line SCAN during the first stage T1, the second stage T2 and the display stage.

[0133] In the first stage T1 and the second stage T2, the switching transistors controlled by the scan lines in the pixel circuit can conduct normally. This allows the reset voltage on the reset signal line to be written to the gate of the driving transistor, thus resetting the gate. The black-state voltage on the data line can also be written to the gate of the driving transistor, and the threshold compensation transistor can compensate for the threshold voltage of the driving transistor. The initialization voltage on the initialization signal line can be written to the anode of the light-emitting element, thus initializing the anode potential of the light-emitting element. Since the light-emitting control transistors M1 and M6 are cut off in the first stage T1 and the second stage T2, even if the scan lines drive the pixel circuit normally in the first stage T1 and the second stage T2, the flickering problem can be somewhat mitigated.

[0134] In some embodiments, please refer to Figure 1 The display panel also includes multiple cascaded first scan shift circuits 50, which are respectively connected to the first A scan clock signal line CK1_S1, the first B scan clock signal line CK2_S1, and the scan signal line SCAN (e.g., ...). Figure 3Each scan line is electrically connected. The first scan shift circuit 50 includes a first A scan shift circuit 51, which is also electrically connected to the first A scan frame start signal line STV_S1.

[0135] like Figure 12 As shown, the driving method for the display panel provided in this application embodiment may include: providing pulse signals to the first A scan clock signal line CK1_S1, the first B scan clock signal line CK2_S1, and the first A scan frame start signal line STV_S1 respectively in the first stage T1, the second stage T2, and the display stage T3. This ensures that the first scan shift circuit 50 operates normally in the first stage T1, the second stage T2, and the display stage T3, allowing the scan lines connected to the first scan shift circuit 50 to refresh the pixel circuit normally.

[0136] In other embodiments, such as Figure 10 As shown, the pixel circuit 20 may also include a bias adjustment transistor M8. Correspondingly, as... Figure 13 As shown, the display panel 100 also includes multiple cascaded second scan shift circuits 60, which are electrically connected to the second A scan clock signal line CK1_S2, the second B scan clock signal line CK2_S2, and the fifth scan signal line SCAN5, respectively. Among them, the second scan shift circuit 60 includes a second A scan shift circuit 61, which is also electrically connected to the second scan frame start signal line STV_S2.

[0137] like Figure 14 As shown, the driving method for the display panel provided in this application embodiment may further include: providing pulse signals to the second A scan clock signal line CK1_S2, the second B scan clock signal line CK2_S2, and the second scan frame start signal line STV_S2 respectively in the first stage T1, the second stage T2, and the display stage T3. In this way, the second scan shift circuit 60 operates normally in the first stage T1, the second stage T2, and the display stage T3, enabling the scan lines connected to the second scan shift circuit 60 to refresh the pixel circuit normally.

[0138] In some implementation paradigms, such as Figure 3 and Figure 10 As shown, the reset transistor M5 and the threshold compensation transistor M4 can both be P-type transistors.

[0139] In other embodiments, such as Figure 15 As shown, the reset transistor M5 and the threshold compensation transistor M4 can both be N-type transistors, such as indium gallium zinc oxide (IGZO) transistors.

[0140] For a P-type transistor, its on-level is low, and its off-level is high. For an N-type transistor, its on-level is high, and its off-level is low.

[0141] It should be noted that this application does not limit the operating timing of the pixel circuit 20. For example, the operating timing of the pixel circuit 20 in this embodiment includes, but is not limited to, a reset phase, a data writing phase, and a light-emitting phase. During the reset and data writing phases, the light-emitting control transistors M1 and M6 are turned off. During the reset phase, the reset transistor M5 is turned on, and the signal on the reset signal line Vref is transmitted to the gate of the driving transistor M3 to reset the gate of the driving transistor M3. During the data writing phase, the data writing transistor M2 and the threshold compensation transistor M4 are turned on, the signal on the data line DATA is written to the gate of the driving transistor M3, and the threshold compensation transistor M4 performs threshold compensation on the driving transistor M3. Additionally, the initialization transistor M7 can be turned on during the data writing phase, and the signal on the initialization signal line Vini is transmitted to the anode of the light-emitting element 30. During the light-emitting phase, the light-emitting control transistors M1 and M6 are turned on.

[0142] In the case where the pixel circuit 20 also includes a bias adjustment transistor M8, the operating timing of the pixel circuit 20 in this embodiment may also include a bias adjustment stage. In the bias adjustment stage, the light emission control transistors M1 and M6 are turned off, the bias adjustment transistor M8 is turned on, and the signal on the bias adjustment signal line DVH is transmitted to the driving transistor M3.

[0143] It should be noted that in the first stage T1 and the second stage T2, the operating timing of the pixel circuit 20 may not include the light emission stage; in the display stage T3, the operating timing of the pixel circuit 20 includes the light emission stage.

[0144] It should also be noted that, Figure 1 A transmission shift circuit 40 is provided on one side of the display panel, and a first scan shift circuit 50 is provided on the other side (illustrated). Figure 13 The diagram shows a second scan shift circuit 60 on one side of the display panel and a first scan shift circuit 50 on the other side. The arrangement of the shift circuits in the display panel provided in this application may include... Figure 1 or Figure 13 The example shown is not limited to this.

[0145] For example, in some examples, both sides of the display panel may be provided with a transmission shift circuit 40, both sides of the display panel may be provided with a first scan shift circuit 50, and both sides of the display panel may be provided with a second scan shift circuit 60.

[0146] Figure 13 Although the transmit shift circuit 40 is not shown in the diagram, Figure 13A corresponding embodiment may include a transmit shift circuit 40.

[0147] Based on the same inventive concept, embodiments of this application also provide a display device. For example... Figure 1 As shown Figure 4 As shown, the display device includes a display panel 100, a display driver chip 200, and a power driver chip 300. The display panel 100 includes a substrate 10, a metal pattern BSM, a pixel circuit 20, and a light-emitting element 30.

[0148] In the thickness direction Z of the display panel 100, the metal pattern BSM is located between the substrate 10 and the pixel circuit 20, and the metal pattern BSM overlaps with the orthographic projection of the communication of at least some transistors in the pixel circuit 20 on the substrate 10.

[0149] The driving process of the display panel 100 includes a first stage T1, a display stage T3, and a second stage T2, with the display stage T3 located between the first stage T1 and the second stage T2.

[0150] In the first stage T1, at the first moment t1, the power driver chip 300 starts to provide a first voltage V1 to the metal pattern BSM, and the first voltage V1 is greater than 0; in the third moment of the second stage T2, it stops to provide a second voltage V2 to the metal pattern BSM, and the second voltage V2 is greater than 0.

[0151] The display driver chip 200 is configured to start providing a first black-state voltage vgmp1 to the data line DATA at a second time t2 within the first stage T1; and to stop providing a second black-state voltage vgmp2 to the data line DATA at a fourth time t4 within the second stage T2. The first time t1 is before the second time t2, and / or the third time t3 is after the fourth time t4.

[0152] In this embodiment, for the transistor overlapping with the metal pattern BSM, the metal pattern BSM can block bottom reflections and shield the bottom electrostatic field caused by static charge accumulation. In the first stage T1, the metal pattern BSM is powered on before the data line DATA. This allows the transistor's threshold voltage to be negatively biased before the data line DATA is powered on, thus offsetting at least part of the positive bias of the transistor's threshold voltage caused by static electricity, thereby improving the screen flickering problem that occurs during power-on of the display panel. And / or, in the second stage T2, the metal pattern BSM is powered off after the data line DATA. This allows the transistor's threshold voltage to be negatively biased after the data line DATA is powered off, thereby offsetting at least part of the positive bias of the transistor's threshold voltage caused by static electricity, thereby improving the screen flickering problem that occurs during power-off of the display panel.

[0153] In some embodiments, the anode of the light-emitting element is electrically connected to the initialization signal line;

[0154] The power driver chip is also used to start providing a first initialization voltage to the initialization signal line at the fifth moment in the first stage, and to stop providing a second initialization voltage to the initialization signal line at the sixth moment in the second stage, wherein the first initialization voltage is less than 0 and the second initialization voltage is less than 0.

[0155] The fifth time point is before the first time point, and / or the sixth time point is after the third time point.

[0156] In some embodiments, the interval between the first time point and the second time point is t12, t12≥1 / F; and / or, the interval between the third time point and the fourth time point is t34, t34≥1 / F; where F is the frame refresh rate of the display panel.

[0157] In some embodiments, the interval between the first time point and the second time point is t12, t12≤2 / F; and / or, the interval between the third time point and the fourth time point is t34, t34≤2 / F; where F is the frame refresh rate of the display panel.

[0158] In some embodiments, the time interval between the first time point and the second time point is t12, and the time interval between the third time point and the fourth time point is t34, where t12 = t34.

[0159] In some embodiments, the interval between the first time point and the fifth time point is t15, where t15 ≥ 1 / F; and / or, the interval between the third time point and the sixth time point is t36, where t36 ≥ 1 / F; where F is the frame refresh rate of the display panel.

[0160] In some embodiments, the interval between the first time point and the fifth time point is t15, where t15 ≤ 2 / F; and / or, the interval between the third time point and the sixth time point is t36, where t36 ≤ 2 / F; where F is the frame refresh rate of the display panel.

[0161] In some embodiments, the interval between the first time point and the fifth time point is t15, and the interval between the third time point and the sixth time point is t36, where t15 = t36.

[0162] In some embodiments, the first voltage is equal to the second voltage, and / or the first black-state voltage is equal to the second black-state voltage.

[0163] In some embodiments, the display driver chip is used for:

[0164] At the second moment within the first phase, the first black-state voltage is supplied to the data line and lasts for a duration of t10, where 1 / F ≤ t10 ≤ 2 / F, and F is the frame refresh rate of the display panel.

[0165] And / or, at the fourth moment within the second phase, the supply of the second black-state voltage to the data line is stopped, and the duration of the supply of the second black-state voltage to the data line within the second phase is t40, 1 / F≤t40≤2 / F.

[0166] In some embodiments, the pixel circuit includes a driving transistor and at least one switching transistor, wherein the metal pattern overlaps at least with the orthographic projection of the channel of the driving transistor onto the substrate.

[0167] In some embodiments, the pixel circuit is also electrically connected to a first power line, which is electrically connected to a different signal terminal of the metal pattern.

[0168] In some embodiments, the pixel circuit is also electrically connected to a first power line, which is electrically connected to a metal pattern.

[0169] In some embodiments, the light-emitting element is also electrically connected to a second power line;

[0170] The power driver chip is also used to: at a first moment, start supplying a first power supply voltage to the second power line, where the first power supply voltage is less than 0; and at a third moment, stop supplying a second power supply voltage to the second power line, where the second power supply voltage is less than 0.

[0171] In some embodiments, the first power supply voltage is equal to the second power supply voltage.

[0172] In some embodiments, the driving transistor of the pixel circuit is electrically connected to the reset signal line;

[0173] The power driver chip is also used to: at the fifth moment, start providing a first reset voltage to the reset signal line, the first reset voltage being less than 0; at the sixth moment, stop providing a second reset voltage to the reset signal line, the second reset voltage being less than 0;

[0174] Alternatively, the power driver chip is also configured to: at the seventh moment in the first stage, start providing a first reset voltage to the reset signal line, the first reset voltage being less than 0; at the eighth moment in the second stage, stop providing a second reset voltage to the reset signal line, the second reset voltage being less than 0; the seventh moment and the fifth moment are different moments, and / or the eighth moment and the sixth moment are different moments.

[0175] In some embodiments, the driving transistor of the pixel circuit is electrically connected to the bias adjustment signal line;

[0176] The power driver chip is also used to: start providing a first bias adjustment voltage to the bias adjustment signal line at a second moment within the first stage; and stop providing a second bias adjustment voltage to the bias adjustment signal line at a fourth moment within the second stage.

[0177] In some embodiments, the pixel circuit is also electrically connected to the light emission control signal line; the display driver chip is also configured to: provide a light emission disabling voltage to the light emission control signal line during the first and second phases; and provide alternating light emission disabling voltage and light emission enabling voltage to the light emission control signal line during the display phase.

[0178] In some embodiments, the pixel circuit is also electrically connected to the scan line; the display driver chip is also used to: provide an enable voltage to the scan line during at least a portion of the time periods of the first and second phases.

[0179] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes a substrate, a metal pattern, a pixel circuit, and a light-emitting element. In the thickness direction of the display panel, the metal pattern is located between the substrate and the pixel circuit. The metal pattern overlaps with the orthographic projection of the channel of at least a portion of the transistors in the pixel circuit onto the substrate. The pixel circuit is electrically connected to a data line. The driving process of the display panel includes a first stage, a display stage, and a second stage, wherein the display stage is located between the first stage and the second stage; The driving method includes: At a first moment within the first stage, a first voltage is applied to the metal pattern, the first voltage being greater than 0. At the second moment within the first phase, a first black-state voltage is provided to the data line; At a third moment within the second phase, the supply of the second voltage to the metal pattern is stopped, and the second voltage is greater than 0. At the fourth moment within the second phase, the supply of the second black-state voltage to the data line is stopped; Wherein, the first time point is before the second time point, and / or the third time point is after the fourth time point.

2. The driving method for the display panel according to claim 1, characterized in that, The anode of the light-emitting element is electrically connected to the initialization signal line; The driving method further includes: At the fifth moment of the first phase, a first initialization voltage is provided to the initialization signal line, the first initialization voltage being less than 0. At the sixth moment of the second phase, the supply of the second initialization voltage to the initialization signal line is stopped, and the second initialization voltage is less than 0. Wherein, the fifth moment is before the first moment, and / or the sixth moment is after the third moment.

3. The driving method for the display panel according to claim 1, characterized in that, The time interval between the first time point and the second time point is t12, where t12 ≥ 1 / F; And / or, the time interval between the third time point and the fourth time point is t34, where t34 ≥ 1 / F; F represents the frame refresh rate of the display panel.

4. The driving method for a display panel according to claim 1, characterized in that, The time interval between the first time point and the second time point is t12, where t12 ≤ 2 / F; And / or, the time interval between the third time point and the fourth time point is t34, where t34 ≤ 2 / F; F represents the frame refresh rate of the display panel.

5. The driving method for a display panel according to claim 1, characterized in that, The time interval between the first time point and the second time point is t12, and the time interval between the third time point and the fourth time point is t34, where t12 = t34.

6. The driving method for a display panel according to claim 2, characterized in that, The time interval between the first time point and the fifth time point is t15, where t15 ≥ 1 / F; And / or, the time interval between the third time point and the sixth time point is t36, where t36 ≥ 1 / F; F represents the frame refresh rate of the display panel.

7. The driving method for a display panel according to claim 2, characterized in that, The time interval between the first time point and the fifth time point is t15, where t15 ≤ 2 / F; And / or, the time interval between the third time point and the sixth time point is t36, where t36 ≤ 2 / F; F represents the frame refresh rate of the display panel.

8. The driving method for a display panel according to claim 2, characterized in that, The interval between the first time point and the fifth time point is t15, and the interval between the third time point and the sixth time point is t36, where t15 = t36.

9. The driving method for a display panel according to claim 1, characterized in that, The first voltage is equal to the second voltage, and / or the first black-state voltage is equal to the second black-state voltage.

10. The driving method for a display panel according to claim 1, characterized in that, The provision of a first black-state voltage to the data line at the second moment within the first stage includes: At the second moment within the first stage, a first black state voltage is supplied to the data line and lasts for a duration of t10, where 1 / F ≤ t10 ≤ 2 / F, and F is the frame refresh rate of the display panel. And / or, stopping the supply of the second black-state voltage to the data line at the fourth moment within the second phase includes: At the fourth moment of the second phase, the supply of the second black state voltage to the data line is stopped, and the duration of supplying the second black state voltage to the data line during the second phase is t40, where 1 / F≤t40≤2 / F.

11. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit includes a driving transistor and at least one switching transistor, and the metal pattern at least overlaps with the orthographic projection of the channel of the driving transistor onto the substrate.

12. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit is also electrically connected to a first power line, which is electrically connected to a different signal terminal of the metal pattern.

13. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit is also electrically connected to a first power line, which is electrically connected to the metal pattern.

14. The driving method for a display panel according to claim 12 or 13, characterized in that, The light-emitting element is also electrically connected to the second power line; The driving method includes: At the first moment, a first power supply voltage is supplied to the second power line, and the first power supply voltage is less than 0. At the third moment, the supply of the second power supply voltage to the second power line is stopped, and the second power supply voltage is less than 0.

15. The driving method for a display panel according to claim 14, characterized in that, The first power supply voltage is equal to the second power supply voltage.

16. The driving method for a display panel according to claim 2, characterized in that, The driving transistor of the pixel circuit is electrically connected to the reset signal line; The driving method further includes: At the fifth moment, a first reset voltage is provided to the reset signal line, the first reset voltage being less than 0; At the sixth moment, the supply of the second reset voltage to the reset signal line is stopped, and the second reset voltage is less than 0. Alternatively, the driving method may further include: At the seventh moment within the first stage, a first reset voltage is provided to the reset signal line, the first reset voltage being less than 0. At the eighth moment of the second phase, the supply of the second reset voltage to the reset signal line is stopped, and the second reset voltage is less than 0. The seventh time point is different from the fifth time point, and / or the eighth time point is different from the sixth time point.

17. The driving method for a display panel according to claim 1, characterized in that, The driving transistor of the pixel circuit is electrically connected to the bias adjustment signal line; The driving method further includes: At a second moment within the first phase, a first bias adjustment voltage is started to be supplied to the bias adjustment signal line; At the fourth moment within the second phase, the supply of the second bias adjustment voltage to the bias adjustment signal line is stopped.

18. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit is also electrically connected to the light emission control signal line; The driving method further includes: During the first and second phases, a light emission disabling voltage is provided to the light emission control signal line; During the display phase, alternating light-disabling voltage and light-enabling voltage are provided to the light-emitting control signal line.

19. The driving method for a display panel according to claim 1, characterized in that, The pixel circuit is also electrically connected to the scan line; The driving method further includes: During at least a portion of the first and second phases, an enable voltage is provided to the scan line.

20. A display device, characterized in that, include: The display panel includes a substrate, a metal pattern, a pixel circuit, and a light-emitting element. In the thickness direction of the display panel, the metal pattern is located between the substrate and the pixel circuit. The metal pattern overlaps with the orthographic projection of the channel of at least a portion of the transistors in the pixel circuit onto the substrate. The pixel circuit is electrically connected to a data line. The driving process of the display panel includes a first stage, a display stage, and a second stage, wherein the display stage is located between the first stage and the second stage; A power driver chip is configured to start supplying a first voltage to the metal pattern at a first moment in the first stage, and to stop supplying a second voltage to the metal pattern at a third moment in the second stage, wherein the first voltage is greater than 0 and the second voltage is greater than 0. The display driver chip is configured to start providing a first black state voltage to the data line at a second moment within the first stage, and to stop providing a second black state voltage to the data line at a fourth moment within the second stage. The display phase of the display panel is located between the first phase and the second phase, wherein the first moment is before the second moment, and / or the third moment is after the fourth moment.

21. The display device according to claim 20, characterized in that, The anode of the light-emitting element is electrically connected to the initialization signal line; The power driver chip is further configured to start providing a first initialization voltage to the initialization signal line at a fifth moment in the first stage, and to stop providing a second initialization voltage to the initialization signal line at a sixth moment in the second stage, wherein the first initialization voltage is less than 0 and the second initialization voltage is less than 0. Wherein, the fifth moment is before the first moment, and / or the sixth moment is after the third moment.

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