Delay control circuit, semiconductor memory device, and delay control method

Abstract

The present application provides a delay control circuit, a semiconductor storage device and a delay control method, which can control the execution time of N-value detection sequence within a specified period. The delay control circuit includes a DLL control circuit, a delay line circuit and an N-value detection circuit. The DLL control circuit determines the delay amount according to the phase difference between the input clock signal and the output clock signal. The delay line circuit delays the input clock signal based on the delay amount to generate the output clock signal. The N-value detection circuit is configured to perform an N-value detection operation, which is used to detect the number of delay clock periods from the input clock signal to the output clock signal. When it is determined that the overflow state, the DLL control circuit outputs a signal indicating the overflow state to the N-value detection circuit. When the N-value detection circuit receives the signal indicating the overflow state, the N-value detection circuit does not perform the N-value detection operation, but sets a predetermined set value as the number of delay clock periods.

Description

Technical Field

[0001] This invention relates to a signal delay technology, and more particularly to a delay control circuit, a semiconductor memory device, and a delay control method suitable for a delay-locked loop. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor storage device. This volatile memory stores information by accumulating charge in capacitors; once the power supply is cut off, the stored information is lost. In existing DRAMs, such as those disclosed in Japanese Patent Application Publication No. 2015-35241, a Delay Locked Loop (DLL) circuit is provided as a phase synchronization circuit. The DRAM uses the DLL circuit to generate an internal clock signal, synchronizing the output data signal with the external clock signal.

[0003] In existing DRAM, in order to use the DLL circuit for clock delay adjustment, the following actions are performed: resetting the DLL circuit, locking the DLL circuit (e.g., activating each delay line while synchronizing the external clock signal with the internal clock signal), and detecting the N value to represent the number of delay clock cycles between the input clock signal and the internal clock signal.

[0004] Here, the lockout (also known as delay) time Tdll caused by the locking operation of the DLL circuit can be expressed by the following mathematical formula.

[0005] Tint+Tdll=N×tCK

[0006] In the above mathematical formula, Tint represents the existing delay time in the DLL circuit, and tCK represents the clock cycle. To avoid malfunctions, the clock delay adjustment procedure must be completed within a specified period tDLLK. However, when factors such as temperature within the semiconductor memory device cause the clock cycle tCK to be longer than the existing delay time Tint, especially when the number of activated delay lines exceeds a predetermined number, resulting in an overflow state, as shown in the above mathematical formula, the lock time Tdll of the DLL circuit will also be extended. If the lock time is extended in this way, the overall time required for the clock delay adjustment procedure will increase, potentially exceeding the specified period tDLLK. Summary of the Invention

[0007] In view of the above-mentioned problems, the present invention aims to provide a delay control circuit, a semiconductor memory device, and a delay control method that can complete the execution time of the N-value detection sequence within a specified period even if the lock time is lengthened due to the overflow state of the delay line.

[0008] The delay control circuit of the present invention includes: a DLL control circuit configured to determine a delay amount based on the phase difference between an input clock signal and an output clock signal; a delay line circuit configured to delay the input clock signal based on the delay amount to generate the output clock signal; and an N-value detection circuit configured to perform an N-value detection operation when the input clock signal and the output clock signal are synchronized, the N-value detection operation being used to detect the number of clock cycles of delay from the input clock signal to the output clock signal; wherein, the DLL control circuit is configured to determine whether an overflow state is present by determining whether the delay amount exceeds a predetermined delay amount in the delay line circuit, and when the overflow state is determined, outputting a signal indicating the overflow state to the N-value detection circuit; wherein, when the N-value detection circuit receives the signal indicating the overflow state, the N-value detection circuit does not perform the N-value detection operation, but instead sets a predetermined set value to the number of clock cycles of delay.

[0009] The semiconductor memory device of the present invention includes the aforementioned delay control circuit; a memory cell array; an input buffer configured to provide the input clock signal; and an output buffer coupled to the output of the delay line circuit. Because it includes the delay control circuit, the delay control circuit can shorten the execution time of the program and prevent the program execution time from exceeding a predetermined period; therefore, it can advance the scheduled recursion operation after the program and shorten the response time.

[0010] The delay control method of the present invention includes: determining a delay amount based on the phase difference between an input clock signal and an output clock signal; delaying the input clock signal based on the delay amount to generate the output clock signal; when the input clock signal and the output clock signal are synchronized, detecting the number of delay clock cycles from the input clock signal to the output clock signal through an N-value detection circuit; determining whether an overflow state is present by judging whether the delay amount exceeds a predetermined delay amount in the delay line circuit; when the overflow state is determined, outputting a signal indicating the overflow state to the N-value detection circuit; and when the N-value detection circuit receives the signal indicating the overflow state, the N-value detection circuit does not detect the number of delay clock cycles, but instead sets a predetermined set value as the number of delay clock cycles.

[0011] According to the present invention, when a signal indicating an overflow state is input, the N-value detection circuit sets a predetermined set value to the number of delay clock cycles. For example, when an overflow state occurs, that is, when the predetermined delay amount in the delay line is exceeded, the N-value detection circuit does not obtain the number of delay clock cycles by performing a count. This prevents the execution time of the N-value detection sequence from exceeding a predetermined period. Therefore, even if the lock time is prolonged due to the overflow state of the delay line, the execution time of the N-value detection sequence can be controlled to end within a predetermined period. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example of the configuration of a delay control circuit according to an embodiment of the present invention.

[0013] Figure 2A , Figure 2B This is a graph showing the changes in various signals and lockout time when tCK is greater than Tint, for both non-overflow and overflow states.

[0014] Figure 3 This is a schematic diagram illustrating an example of the configuration of an N-value detection circuit according to an embodiment of the present invention.

[0015] Figure 4 This is a timing diagram illustrating the voltage shift of each signal in the delay control circuit when it is not in an overflow state, according to an embodiment of the present invention.

[0016] Figure 5 This is a timing diagram illustrating the voltage shift of each signal in the overflow state within the delay control circuit according to an embodiment of the present invention.

[0017] Figure 6 This diagram illustrates the relationship between the execution time of the N-value detection sequence in the overflow state and the specified period, comparing the delay control circuit according to an embodiment of the present invention with that of the prior art.

[0018] Figure label:

[0019] 1: Semiconductor memory device; 10: DLL circuit

[0020] 11: Input buffer 12: Phase detection circuit

[0021] 13: DLL control circuit 14: Delay line circuit

[0022] 15: Replication circuit 16: Output buffer

[0023] 17: Multiplexer 20: N-value detection circuit

[0024] 21: n_clk signal generation circuit 22: N-value counting circuit

[0025] 30: Latent counter; 100: Delay control circuit

[0026] 211: First AND circuit 212: First latch

[0027] 213: Second AND circuit; 221, 222: Flip-flops

[0028] 223: 3rd AND circuit 224: 2nd latch

[0029] 225: 4th AND circuit 226: 4-bit counter

[0030] CK: External clock signal; clk: Input clock signal

[0031] count_clk, n_clk, n_detection, n_end, n_start: signal

[0032] dll_clk: Delay signal (output clock signal)

[0033] dll_code, dll_locked, dll_overflow, n_enable: Control signals

[0034] RST, dll_reset: reset signal; down, up: phase signal

[0035] fb_clk: Feedback signal; n_value: N-value signal

[0036] tCK: Clock cycle; Tdll: Lock (delay) time

[0037] tDLLK: Specified period Tint: Existing delay time Detailed Implementation

[0038] Hereinafter, with reference to the accompanying drawings, a delay control circuit, a semiconductor memory device, and a delay control method according to embodiments of the present invention will be described in detail. However, these embodiments are merely illustrative and the present invention is not limited thereto.

[0039] Furthermore, the terms "first," "second," and "third" used in this specification are intended to distinguish a component from other components and are not intended to limit the number, order, or priority of the components. For example, when "first component" and "second component" are mentioned, it does not mean that only two components, "first component" and "second component," are used, nor does it mean that "first component" must take precedence over "second component."

[0040] Figure 1The peripheral circuitry of a semiconductor memory device 1 according to an embodiment of the present invention is illustrated. In this embodiment, the peripheral circuitry includes an input buffer 11, a delay control circuit 100, and an output buffer 16. The delay control circuit 100 includes a DLL circuit 10, a multiplexer 17, an N-value detection circuit 20, and a latency counter 30. In this embodiment, the semiconductor memory device is, for example, DRAM, but the present invention is not limited thereto. When a reset signal RST (i.e., the start signal of the lock operation) is input from a predetermined circuit (not shown), the DLL circuit 10 begins the lock operation by delaying the input clock signal clk, so that the output clock signal dll_clk can be synchronized with the input clock signal clk, and ends the lock operation (or delay operation). When the DLL circuit 10 ends the lock operation, the N-value detection circuit 20 performs an N-value detection operation under predetermined conditions, wherein the N-value is equivalent to the number of delayed clock cycles, and outputs a signal n_value representing the N-value to the latency counter 30, which will be described in detail later. In this embodiment, the operations performed from the moment the DLL circuit 10 receives the reset signal RST until the output signal n_value of the N value are collectively referred to as the "N value detection sequence". Furthermore, in this embodiment, the "N value detection operation" refers to counting the number of clock cycles of delay from the input clock signal to the output clock signal.

[0041] In addition, for the sake of simplicity, in this embodiment, the existing configurations in semiconductor memory devices such as DRAM (e.g., command decoder, memory cell array, input / output interface circuit, etc.) are not shown except for input buffer 11 and output buffer 16.

[0042] The DLL circuit 10 in this embodiment includes a phase detection circuit 12, a DLL control circuit 13, a delay line circuit 14, and a replica circuit 15. In one embodiment, the replica circuit 15 is a replica structure of the output buffer 16 coupled to the output of the delay line circuit 14.

[0043] Input buffer 11 is configured to buffer an external clock signal CK input to it to generate an input clock signal clk. The input clock signal clk generated by input buffer 11 is transmitted to N-value detection circuit 20 and phase detection circuit 12, and selectively transmitted to delay line circuit 14 via multiplexer 17. Delay line circuit 14 is configured to generate a delayed signal of input clock signal clk (i.e., output clock signal dll_clk), and transmits it to output buffer 16 and replication circuit 15, which will be described in detail later. Replication circuit 15 outputs the output clock signal dll_clk generated by delay line circuit 14 as a feedback signal fb_clk to N-value detection circuit 20 and phase detection circuit 12.

[0044] The input clock signal clk, along with the feedback signal fb_clk, is input to the phase detection circuit 12. The phase detection circuit 12 detects the phase difference between the input clock signal clk and the feedback signal fb_clk. The phase detection circuit 12 generates a phase signal up / down and outputs the phase signal up / down to the DLL control circuit 13. The phase signal up / down indicates whether the phase of the feedback signal fb_clk leads or lags the phase of the input clock signal clk.

[0045] The DLL control circuit 13 determines the delay amount based on the phase difference detected by the phase detection circuit 12. Specifically, the DLL control circuit 13 determines the delay amount and controls the delay line circuit 14 according to the phase signal up / down from the phase detection circuit 12. The DLL control circuit 13 generates a control signal dll_code consisting of multiple bits and outputs it to the delay line circuit 14.

[0046] The delay line circuit 14 is, for example, a variable delay circuit, configured to activate its internal variable delay lines according to the control signal dll_code to change the delay time. When the enable control signal n_enable (described later) is input to the multiplexer 17 at a high level (i.e., during N-value detection), the multiplexer 17 outputs the clock control signal n_clk and provides it to the delay line circuit 14; when the enable control signal n_enable is input to the multiplexer 17 at a low level, the multiplexer 17 outputs the input clock signal clk and provides it to the delay line circuit 14. The more high-level bits in the control signal dll_code (i.e., the more delay lines are activated), the longer the delay time of the output delayed signal (i.e., the output clock signal dll_clk) is, as the delay line circuit 14 extends the input clock signal clk. Conversely, if the number of high-level bits in the control signal dll_code is smaller (i.e., fewer active delay lines), the delay line circuit 14 extends the input clock signal clk, resulting in a shorter delay time for the output delayed signal (i.e., the output clock signal dll_clk). In this way, the delay line circuit 14 generates the output clock signal dll_clk by delaying the input clock signal clk, and as described above, outputs the output clock signal dll_clk to the output buffer 16 and the copy circuit 15.

[0047] In this embodiment, the DLL control circuit 13 is configured to generate a control signal dll_locked and output the control signal dll_locked to the N-value detection circuit 20. The high-level control signal dll_locked indicates the end of the locking operation. Specifically, when the phase difference between the phase signals up / down converges to a predetermined range, the locking operation is considered complete. The DLL control circuit 13 sets the control signal dll_locked, indicating synchronization between the input clock signal clk and the feedback signal fb_clk (corresponding to the delay signal (output clock signal) dll_clk), to a high level and inputs it to the N-value detection circuit 20. Furthermore, when the DLL circuit 10 is in an overflow state (i.e., all bits constituting the control signal dll_code are high), that is, when all delay lines are activated, the DLL control circuit 13 sets the control signal dll_overflow, indicating the overflow state, to a high level and inputs it to the N-value detection circuit 20. In addition, in this embodiment, the overflow state refers to the state in which all delay lines are activated, but it is not limited to this; it can also refer to the state in which a predetermined number or more delay lines are activated (i.e., a predetermined number or more bits constituting the control signal dll_code are at a high level). In addition, when the DLL circuit 10 is in the overflow state, the DLL control circuit 13 can also input the control signal dll_locked at a high level to the N value detection circuit 20.

[0048] Additionally, when the DLL circuit 10 is determined to be in an overflow state, the DLL control circuit 13 can also set the control signal dll_locked to a high level and input it to the N-value detection circuit 20. Therefore, even if the input clock signal clk and the output clock signal dll_clk are not synchronized when an overflow occurs, the DLL control circuit 13 can directly notify the N-value detection circuit 20 that the input clock signal clk and the delay signal (output clock signal) dll_clk have been synchronized (in other words, the locking operation has ended).

[0049] After the locking operation is completed, in other words, when the input clock signal clk and the delay signal dll_clk are synchronized (here, the control signal dll_locked is high), the N-value detection circuit 20 detects the N-value and outputs it to the latent counter 30. Here, the so-called N-value is the N-value shown as Tint (the existing delay time in the DLL circuit 10) + Tdll (the locking (delay) time caused by the locking operation of the DLL circuit 10) = N × tCK, which is used to represent the number of clock cycles of delay from the input clock signal to the output clock signal during the locking operation of the DLL (therefore, it is an integer).

[0050] When the locking operation of DLL circuit 10 ends, N-value detection circuit 20 detects the N-value by counting. However, when DLL circuit 10 is in an overflow state (i.e., when the control signal dll_overflow is high (also known as Assert)), N-value detection circuit 20 does not perform N-value detection, but instead uses a predetermined set value as the N-value. Therefore, when DLL circuit 10 is in an overflow state, the N-value detection sequence can end earlier without requiring N-value detection. Previously, when tCK was much larger than Tint, especially when DLL circuit 10 was in an overflow state and Tdll was lengthened, the overall time of the N-value detection sequence exceeded a predetermined period (tDLLK, for example, 512 clock cycles). However, in this embodiment, when in an overflow state, since counting is not performed and the predetermined set value is directly used as the N-value, the N-value detection sequence can end within a predetermined period (tDLLK).

[0051] Specifically, in this embodiment, when the DLL circuit 10 ends the locking operation and is not in an overflow state, that is, when the N-value detection circuit 20 receives a low-level control signal dll_overflow and a high-level control signal dll_locked, the N-value detection circuit 20 performs an N-value detection operation, uses the detected N-value as the N-value signal n_value, and generates an N-value signal n_value indicating the N-value, which is output to the latent counter 30. Then, when the DLL circuit 10 becomes an overflow state, that is, when the N-value detection circuit 20 receives a high-level control signal dll_overflow, the N-value detection circuit 20 does not perform an N-value detection operation, but instead uses a predetermined set value as (also known as set as) the N-value signal n_value, and generates an N-value signal n_value indicating the N-value, which is output to the latent counter 30. In this embodiment, the predetermined set value is 1, but it is not limited to this and can be set appropriately as needed.

[0052] In the existing technology, such as Figure 2A As shown, when tCK is greater than Tint and is not in an overflow state, in response to the high-level control signal dll_locked, the N value detected by the N value detection circuit 20 is 1, so that the rising edge of the external clock signal CLK is synchronized with the rising edge of the output clock signal dll_clk after the locking operation is completed. Figure 2B As shown, when tCK is greater than Tint and is in an overflow state (lock time Tdll is the maximum value Tdll), even if N is 1, the rising edge of the external clock signal CLK and the rising edge of the output clock signal dll_clk are still out of sync after the locking operation is completed (for example, after the locking operation is completed, the rising edge of the external clock signal CLK is later than the rising edge of the output clock signal dll_clk by time tDQSCK).

[0053] Figure 3 This is a schematic diagram illustrating the configuration of an N-value detection circuit 20 according to an embodiment of the present invention.

[0054] The N-value detection circuit 20 includes an n_clk signal generation circuit 21 and an N-value counting circuit 22. The n_clk signal generation circuit 21 includes a first AND circuit 211, a first latch 212, and a second AND circuit 213. The N-value counting circuit 22 includes two D-type flip-flops (FF) 221 and 222, a third AND circuit 223, a second latch 224, a fourth AND circuit 225, and a 4-bit counter 226.

[0055] During the N-value detection operation, the n_clk signal generation circuit 21 generates a clock control signal n_clk corresponding to the input clock signal clk. The first AND circuit 211 of the n_clk signal generation circuit 21 receives the control signal dll_locked, the end signal n_end (described later), and the control signal dll_overflow, and generates an enable control signal n_enable. When the enable control signal n_enable is high, the N-value detection operation is enabled. The first latch 212 receives the enable control signal n_enable and the input clock signal clk as the clock signal. Additionally, the second AND circuit 213 receives the signal output from the first latch 212 and the input clock signal clk, and outputs the clock control signal n_clk.

[0056] During the N-value detection operation, the N-value counting circuit 22 detects the N-value by counting the number of clock cycles of the input clock signal clk from the input of the input clock signal clk until the input of the feedback signal fb_clk. The flip-flop 221 of the N-value counting circuit 22 receives the clock control signal n_clk and the control signal dll_locked, and generates a start signal n_start. The flip-flop 222 receives the feedback signal fb_clk corresponding to the output clock signal dll_clk and the control signal dll_locked, and generates an end signal n_end. Then, the third AND circuit 223 receives the start signal n_start and the end signal n_end, and generates a detection signal n_detection. The second latch 224 receives the detection signal n_detection and the clock control signal n_clk as the clock signal, and couples its output to the fourth AND circuit 225. The fourth AND circuit 225 receives the output of the second latch 224 and the clock control signal n_clk, and outputs the signal count_clk, which is the counting signal for the value of N. The signal count_clk is input to the 4-bit counter 226.

[0057] The 4-bit counter 226 detects the N value through pulses of the counting signal count_clk and outputs an N value signal n_value to indicate the detected N value. When the 4-bit counter 226 receives a reset signal dll_reset to reset the count value, the count value will be reset to 0.

[0058] In this way, when the control signal dll_locked is high, the N-value counting circuit 22 performs the N-value detection operation by counting the number of clock cycles (pulses) of the signal count_clk during the period from the input clock control signal n_clk corresponding to the input clock signal clk to the input feedback signal fb_clk corresponding to the delayed signal (output clock signal) dll_clk.

[0059] Back Figure 1 The latent counter 30 is configured to receive the N-value signal n_value, which indicates the N-value detected by the N-value detection circuit 20.

[0060] In addition, when the control signal dll_overflow is input to the N-value detection circuit 20 at a high level, the 4-bit counter 226 of the N-value counting circuit 22 will take the predetermined set value (1 here) as the N-value signal n_value and output it to the latent counter 30.

[0061] The latent counter 30 is synchronized with the internal clock generated by the DLL circuit 10 to count the latent time. Furthermore, after a predetermined period tDLLK has elapsed, the latent counter 30 performs latent time counting via the N-value signal n_value. For example, in the case of Column Address Strobe (CAS) latent time, the set latent time is the number of clock cycles from when a signal (e.g., a read command) is input to the semiconductor memory device (here, DRAM) until data (e.g., read data) is output from the semiconductor memory device. In this case, when the reset signal RST is input to the DLL circuit 10, the latent counter 30 counts, for example, based on the value obtained by subtracting the N-value from the CAS latent time value set in the mode register (not shown). For example, when the CAS latent time value is 10 and the N-value is 5, the latent counter 30 performs the subtraction operation, and the resulting 5 clock cycles are used as the latent time count result.

[0062] The following combinations Figure 4 The timing diagram shown illustrates the control method of the delay control circuit in this embodiment. First, the control method when the DLL circuit 10 is in a non-overflow state will be explained.

[0063] At time t1, when the reset signal RST (start signal for locking operation) is input to DLL circuit 10 from a predetermined circuit (not shown in the diagram), causing DLL circuit 10 to enter the DLL reset state, at time t2, DLL circuit 10 begins the locking operation. Additionally, when DLL circuit 10 enters the DLL reset state, the reset signal dll_reset is input to the 4-bit counter 226 of the N-value counting circuit 22, and the N-value is set to 0 in the 4-bit counter 226.

[0064] Next, at time t2, the DLL locking operation begins, and the DLL circuit 10 is transferred to the DLL locked state. First, the phase detection circuit 12 performs phase detection based on the received input clock signal clk and feedback signal fb_clk, and transmits the phase signal up / down to the DLL control circuit 13. The DLL control circuit 13 determines the delay amount based on the phase signal up / down, and transmits the control signal dll_code, set to a high level, to the delay line circuit 14 according to the delay amount. In the delay line circuit 14, an output clock signal dll_clk is generated by delaying the input clock signal clk by a predetermined time. The output clock signal dll_clk is output as a feedback signal fb_clk through the replication circuit 15 and input to the phase detection circuit 12 for feedback.

[0065] At time t3, the phase difference between the up and down phase signals converges to a predetermined range, and the delay is eliminated (at... Figure 4 In the example shown, the control signal dll_code is "10" at this time, which means it is in the stage of activating 10 delay lines. Therefore, at time point t3, the DLL control circuit 13 sets the control signal dll_locked to a high level and the control signal dll_overflow to a low level, and inputs it to the N-value detection circuit 20. Thus, the N-value detection state starts from time point t3.

[0066] At time t3, when the control signal dll_locked is input high to the first AND circuit 211 of the n_clk signal generation circuit 21, and the end signal n_end and the control signal dll_overflow are input low to the first AND circuit 211, a high-level enable control signal n_enable is generated. The first latch 212 receives the enable control signal n_enable and the input clock signal clk. The signal generated by the first latch 212, together with the input clock signal clk, is input to the second AND circuit 213 to generate the clock control signal n_clk.

[0067] In the N-value counting circuit 22, when the control signal dll_locked is input high to the first flip-flop 221, a high-level start signal n_start is generated based on the clock control signal n_clk. Conversely, when the feedback signal fb_clk is input low to the second flip-flop 222, a low-level end signal n_end is generated. Then, the high-level start signal n_start and the low-level end signal n_end are input to the third AND circuit 223, generating a high-level detection signal n_detection. The detection signal n_detection and the clock control signal n_clk are input to the second latch 224. The fourth AND circuit 225 receives the output of the second latch 224 and the clock control signal n_clk to generate and output the signal count_clk, which is the N-value counting signal. The signal count_clk is input to the 4-bit counter 226.

[0068] In the 4-bit counter 226, the N value is set to 0 at the start of the N value detection state. Each time a pulse of the count_clk signal corresponding to the clock control signal n_clk is received, the 4-bit counter 226 increments the N value signal n_value by 1 and outputs it. Thus, the value of the N value signal n_value is counted upwards according to the clock control signal n_clk, and the N value signal n_value is output to the latent counter 30. In the N value counting circuit 22, the value of the N value signal n_value is counted upwards according to the clock control signal n_clk after time point t3, until time point t4. Furthermore, in Figure 4 In the example shown, the case where the value of N is counted up to the value "a" (where a is an integer greater than 3) is taken as an example.

[0069] At time t4, in the N-value counting circuit 22, when the feedback signal fb_clk is input to the second flip-flop 222 at a high level, a high-level end signal n_end is generated. Furthermore, in response to the end signal n_end becoming high, the n_clk signal generation circuit 21 generates a low-level enable control signal n_enable and a low-level clock control signal n_clk, and ends the N-value detection operation. Additionally, in the N-value counting circuit 22, in response to the end signal n_end becoming high, the detection signal n_detection and the signal count_clk become low. On the other hand, in response to the low-level enable control signal n_enable, the multiplexer 17 selects the input clock signal clk as its output, causing the delay line circuit 14 to output dll_clk synchronized with the input clock signal clk.

[0070] In this way, the N-value detection circuit 20 outputs the detected value "a" as the N-value to the latent counter 30.

[0071] Alternatively, the 4-bit counter 226 can also constantly output the N-value signal n_value to the latent counter 30 between time points t3 and t4; or it can output the N-value signal n_value to the latent counter 30 at time point t4, when the N-value detection state ends. After the specified period tDLLK, since the latent counter 30 uses the N-value signal n_value to perform latent counting, as long as the correct N-value is input from the N-value detection circuit 20, the latent counting can be performed appropriately during the period before the specified period tDLLK.

[0072] Next, with Figure 5 Explain the operation method of DLL circuit 10 in the overflow state.

[0073] At time t11, when the reset signal RST is input from a predetermined circuit (not shown) to the DLL circuit 10, causing the DLL circuit 10 to enter the DLL reset state, the reset signal dll_reset is input to the 4-bit counter 226, setting the N value to 0.

[0074] After entering the DLL reset state, DLL circuit 10, as described above, also performs a locking operation at time point t12; however, when the delay is not resolved and becomes an overflow state where all delay lines are active ( Figure 5 In the example shown, during the stage of activating all 32 delay lines, at time t13, the DLL control circuit 13 inputs the control signal dll_overflow high to the N-value detection circuit 20. Alternatively, the DLL control circuit 13 can also input the control signal dll_locked high to the N-value detection circuit 20.

[0075] At time t13, a low-level enable control signal n_enable is generated in the n_clk signal generation circuit 21. Additionally, when the enable control signal n_enable is low, a low-level clock control signal n_clk is generated.

[0076] In response to a low-level clock control signal n_clk, the count_clk signal generated in the N-value detection circuit 20 for counting N-values ​​is input to the 4-bit counter 226 at a low level. Additionally, at time t13, when the N-value detection circuit 20 receives a high-level control signal dll_overflow, the 4-bit counter 226 outputs a predetermined set value (here, 1) as the N-value signal n_value to the latent counter 30.

[0077] Accordingly, when an overflow occurs in the DLL circuit 10, the N-value detection circuit 20 does not perform the N-value detection operation, but uses a predetermined set value (here, 1) as the N-value and outputs it to the latency counter 30.

[0078] In this way, when the DLL circuit 10 is not in an overflow state at the end of the lock operation (i.e., tCK<Tint), the N-value detection circuit 20 performs the N-value detection operation and outputs the detected N-value to the latency counter 30. Therefore, as shown in Figure 6 Part (A) of the figure, the N-value detection sequence ends after going through the reset state, the lock state, and the N-value detection state. Here, when tCK<Tint, the detected N-value is generally considered to be an integer of 2 or more. Figure 6 Part (A) of the figure schematically illustrates a case where the detected N-value is the aforementioned value "a" as an example. According to the embodiment of the present invention, when the DLL circuit 10 is in an overflow state at the end of the lock operation, the N-value detection circuit 20 does not perform the operation of counting clock cycles to detect the N-value. Therefore, when an overflow occurs, as shown in Figure 6 Part (B) of the figure, since the N-value detection state can be omitted, compared with Figure 6 the prior art case shown in Part (C) of the figure, even if the time required for the lock state is longer than that in the non-overflow state, the time taken for the N-value detection sequence can be shortened. Accordingly, the execution time of the N-value detection sequence can be made shorter than the specified period tDLLK, and the DLL circuit 10 can immediately return to the next DLL control right after the N-value detection sequence.

[0079] In addition, in the present embodiment, a DRAM is taken as an example of the semiconductor memory device including the control circuit for description, but the present invention is not limited thereto. For example, the semiconductor memory device may also be a Static Random Access Memory (SRAM), a flash memory, or other semiconductor memory devices.

[0080] The respective embodiments and modified examples described above are described to facilitate understanding of the present invention, not to limit the present invention. Therefore, each element shown in the above respective embodiments and modified examples is intended to cover all design changes or equivalents belonging to the technical field of the present invention.

[0081] The configuration of the DLL circuit 10 in the above-described embodiment is merely an example, which may be appropriately modified or adopt various other configurations. In addition, although it is illustrated Figure 3 as the configuration of the N-value detection circuit 20, the described configuration is also merely an example, which may be appropriately modified or adopt various other configurations.

Claims

1. A delay control circuit, characterized in that, Include: The DLL control circuit is configured to determine the delay amount based on the phase difference between the input clock signal and the output clock signal. A delay line circuit is configured to delay the input clock signal based on the delay amount to generate the output clock signal; as well as The N-value detection circuit is configured to perform an N-value detection operation when the input clock signal and the output clock signal are synchronized. The N-value detection operation is used to detect the number of clock cycles of delay from the input clock signal to the output clock signal. The DLL control circuit is configured to determine whether it is an overflow state by determining whether the delay amount exceeds the predetermined delay amount in the delay line circuit. When the overflow state is determined, a signal indicating the overflow state is output to the N value detection circuit. When the N-value detection circuit receives a signal indicating the overflow state, the N-value detection circuit does not perform the N-value detection operation, but instead sets the predetermined set value to the number of delay clock cycles.

2. The delay control circuit as described in claim 1, characterized in that, When the overflow state is not determined and the input clock signal and the output clock signal are synchronized, the N-value detection circuit performs the N-value detection operation by counting the number of delayed clock cycles from the input clock signal to the output clock signal.

3. The delay control circuit as described in claim 2, characterized in that, It also includes: The replication circuit is configured to output the output clock signal generated by the delay line circuit as a feedback signal. The N-value detection circuit detects the number of delayed clock cycles based on the input clock signal and the feedback signal output from the replication circuit.

4. The delay control circuit as described in claim 2, characterized in that, It also includes: The replication circuit is configured to output the output clock signal generated by the delay line circuit as a feedback signal. as well as A phase detection circuit is configured to receive the input clock signal and the feedback signal to detect the phase difference; The DLL control circuit determines the delay amount based on the phase difference output by the phase detection circuit.

5. The delay control circuit as described in claim 1, characterized in that, When the signal indicating the overflow state is output at a high level to the N-value detection circuit, the N-value detection circuit sets the set value to the number of delay clock cycles.

6. The delay control circuit as described in claim 1, characterized in that, When the input clock signal and the output clock signal are synchronized, the DLL control circuit will output a signal indicating that the input clock signal and the output clock signal are synchronized to the N value detection circuit. Specifically, when the N-value detection circuit receives a signal indicating that the input clock signal and the output clock signal are synchronized, the N-value detection circuit performs the N-value detection operation.

7. The delay control circuit as described in claim 3, characterized in that, When the overflow state is determined, the DLL control circuit outputs a signal indicating the end of the locking operation to the N value detection circuit.

8. The delay control circuit as described in claim 1, characterized in that, The set value is 1.

9. The delay control circuit as described in claim 7, characterized in that, The N-value detection circuit includes: An N-value counting circuit is configured to generate an end signal based on the signal indicating the end of the locking operation and the feedback signal; and The signal generation circuit is configured to generate an enable control signal based on the signal indicating the end of the locking operation, the signal indicating the overflow state, and the end signal.

10. The delay control circuit as described in claim 1, characterized in that, The overflow state is the state in which all delay lines in the delay line circuit are activated.

11. The delay control circuit as described in claim 9, characterized in that, The signal generation circuit of the N-value detection circuit is configured to generate a clock control signal based on the enable control signal and the input clock signal, and the N-value counting circuit generates a start signal based on the clock control signal and the signal indicating the end of the locking operation.

12. The delay control circuit as described in claim 11, characterized in that, The N-value counting circuit of the N-value detection circuit includes: A first AND circuit receives the start signal and the end signal to generate a detection signal; A latch receives the detection signal and the clock control signal; A second AND circuit is coupled to the output of the latch and the clock control signal to generate a counting signal for the N value; and A 4-bit counter receives the counting signal and reset signal of the N value, and outputs an N value signal to indicate the detected N value.

13. The delay control circuit as described in claim 11, characterized in that, Including: The multiplexer receives the input clock signal and the clock control signal generated by the N-value detection circuit, selects either the input clock signal or the clock control signal as the output according to the enable control signal generated by the signal generation circuit, and provides the output to the delay line circuit; and A latent counter is coupled to the N-value detection circuit to receive the number of delayed clock cycles.

14. A semiconductor memory device, characterized in that, Include: The delay control circuit as described in any one of claims 1 to 13; Storage cell array; An input buffer is configured to provide the input clock signal; and An output buffer is coupled to the output of the delay line circuit.

15. The semiconductor memory device as claimed in claim 14, characterized in that, The semiconductor memory device is a dynamic random access memory.

16. A delay control method, characterized in that, Include: The delay amount is determined based on the phase difference between the input clock signal and the output clock signal; The input clock signal is delayed based on the delay amount to generate the output clock signal; When the input clock signal and the output clock signal are synchronized, the number of clock cycles of delay from the input clock signal to the output clock signal is detected by the N-value detection circuit. The overflow state is determined by whether the delay exceeds the predetermined delay in the delay line circuit. When the overflow state is determined, a signal indicating the overflow state is output to the N value detection circuit. as well as When the N-value detection circuit receives a signal indicating the overflow state, the N-value detection circuit does not detect the number of delay clock cycles, but instead sets a predetermined value as the number of delay clock cycles.

17. The delay control method as described in claim 16, characterized in that, When the overflow state is not determined and the input clock signal and the output clock signal are synchronized, the N-value detection circuit performs the N-value detection operation by counting the number of delayed clock cycles from the input clock signal to the output clock signal.

18. The delay control method as described in claim 16, characterized in that, When the overflow state is determined, the DLL control circuit outputs a signal indicating the end of the locking operation to the N value detection circuit.

19. The delay control method as described in claim 18, characterized in that, Including: The output clock signal generated by the delay line circuit is used as a feedback signal and output through the replication circuit. An end signal is generated by an N-value counting circuit based on the signal indicating the end of the locking operation and the feedback signal; and The signal generation circuit generates an enable control signal based on the signal indicating the end of the locking operation, the signal indicating the overflow state, and the end signal.

20. The delay control method as described in claim 19, characterized in that, The overflow state is the state in which all the delay lines in the delay line circuit are activated.

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