Memory device and operating method of the memory device

Abstract

A memory device and an operating method of the memory device are provided. The memory device includes a memory block including a plurality of pages, each page from the plurality of pages including memory cells configured to be programmed to different program states according to a plurality of target voltages, and a peripheral circuit to perform a program operation of a selected page among the plurality of pages. The peripheral circuit is configured to, in the program operation of the selected page, lower at least one target voltage among the plurality of target voltages to a sub-target voltage, and after a program operation of a page adjacent to the selected page is performed, program the memory cells in the selected page programmed according to the sub-target voltage according to a final target voltage corresponding to the sub-target voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0083292, filed on July 6, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a memory device and a method of operating the memory device, and more specifically, to a memory device configured to program memory cells and a method of operating the memory device. Background Technology

[0004] A memory system may include a storage device configured to store data and a controller configured to control the storage device.

[0005] A storage device may include one or more memory devices, and a controller may output commands for controlling the memory devices. For example, the controller may generate programming, reading, or erasing commands in response to a request from the host and send those commands to the memory devices. The memory devices may perform programming, reading, or erasing operations in response to the commands. Programming operations will be described as an example. The memory devices may program memory cells included in a selected memory block on a page-by-page basis.

[0006] As the integration density of memory devices increases, the distance between memory cells included in a memory block also decreases. When the distance between memory cells narrows, the threshold voltage of a memory cell may change due to interference between memory cells during programming operations. Summary of the Invention

[0007] According to one embodiment, a memory device may be provided, comprising: a memory block including a plurality of pages, each page including a memory cell configured to be programmed into different programming states according to a plurality of target voltages; and peripheral circuitry configured to perform a programming operation on a selected page among the plurality of pages, wherein the peripheral circuitry is configured to: reduce at least one of the plurality of target voltages to a sub-target voltage during the programming operation on the selected page; and, after the programming operation on a page adjacent to the selected page is performed, program the memory cells in the selected page programmed according to the sub-target voltage according to a final target voltage corresponding to the sub-target voltage.

[0008] According to one embodiment, a method for operating a memory device can be provided, the method comprising: setting a target voltage corresponding to a programming state of a memory cell; reducing a target voltage below a reference voltage to a sub-target voltage; performing a programming operation on a selected page based on other target voltages and sub-target voltages besides the target voltage corresponding to the sub-target voltage; performing a programming operation on a page adjacent to the selected page when the programming operation on the selected page is completed; and performing an additional programming operation on a memory cell in the selected page programmed according to the sub-target voltage when the programming operation on the adjacent page is completed.

[0009] According to one embodiment, a method of operating a memory device may be provided, the method comprising: setting a first target voltage to a Kth target voltage; reducing the first target voltage to a first sub-target voltage; programming memory cells to be programmed according to the first target voltage in memory cells included in a page included in a memory block, which are included in a page m, according to the first sub-target voltage, and programming other memory cells according to a second target voltage to a Kth target voltage; programming memory cells included in a (m+1)th page adjacent to the mth page in the same manner as the programming operation performed on the mth page, where 'm' is a positive integer; and when the programming operation on the (m+1)th page is completed, additionally programming memory cells included in the mth page that are programmed according to the first sub-target voltage according to the first target voltage. Attached Figure Description

[0010] Examples of embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein.

[0011] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Throughout the drawings, the same reference numerals refer to the same elements.

[0012] Figure 1 This is a diagram illustrating an example of a memory system.

[0013] Figure 2 This is a diagram illustrating an example of a memory device.

[0014] Figure 3 This is a diagram illustrating an example of the arrangement of a memory cell array and peripheral circuitry.

[0015] Figure 4This is a circuit diagram illustrating an example of the connection configuration of a memory block.

[0016] Figure 5 This is a diagram illustrating an example of the structure of a string.

[0017] Figure 6A , Figure 6B , Figure 7A and Figure 7B This is a diagram illustrating an example of how the threshold voltage of a memory cell can be altered due to interference during programming operations.

[0018] Figure 8 This is a diagram illustrating an example of programming operations according to an embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating an example of the page selection order in a programming operation according to an embodiment of the present disclosure.

[0020] Figure 10A , Figure 10B and Figure 10C This is a diagram illustrating an example of programming operations according to a first embodiment of the present disclosure.

[0021] Figure 11A , Figure 11B and Figure 11C This is a diagram illustrating an example of programming operations according to a second embodiment of the present disclosure.

[0022] Figure 12 This is an illustration of an example of a memory card system that utilizes a memory device according to an embodiment of the present disclosure.

[0023] Figure 13 This is an illustration of an example of a solid-state drive (SSD) system that utilizes a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0024] The specific structural and functional descriptions disclosed herein are shown for the purpose of illustrating embodiments based on the concepts of this disclosure. Additional embodiments based on the concepts of this disclosure may be implemented in various forms. Therefore, this disclosure should not be construed as limited to the embodiments set forth herein.

[0025] In the following text, it will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0026] Various embodiments provide a memory device and a method of operating the memory device that can improve the reliability of programming operations.

[0027] Figure 1 It is a diagram illustrating a memory system.

[0028] refer to Figure 1 The memory system 1000 may include a memory module 1100 and a host 1200.

[0029] The memory module 1100 may include a memory bank 1110 and a controller 1120. The memory module 1100 may be configured to store or output data under the control of a host 1200, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment system.

[0030] The memory module 1100 can be manufactured as any of various types of memory modules, depending on the host interface serving as the communication scheme with the host 1200. For example, the memory module 1100 can be configured with any of a variety of memory modules, such as solid-state drives (SSDs), multimedia cards in the form of MMC, eMMC, RS-MMC and micro-MMC, secure digital cards in the form of SD, mini-SD and micro-SD, universal serial bus (USB) memory modules, universal flash storage (UFS) devices, PCMCIA card-type memory modules, peripheral component interconnect (PCI) card-type memory modules, PCI Express (PCI-E) card-type memory modules, compact flash (CF) cards, smart media cards (SMCs), and memory sticks.

[0031] The memory module 1100 can be manufactured in any of a variety of package types. For example, the memory module 1100 can be manufactured in any of a variety of package types, such as a stacked package (POP), a system-in-package (SIP), a system-on-a-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabrication package (WFP), and a wafer-level stacked package (WSP).

[0032] Memory module 1100 may include at least one memory device 100. Memory device 100 may store data. Memory device 100 may operate under the control of controller 1120. Memory device 100 may include a memory cell array comprising memory blocks in which data can be stored. Memory blocks may be units for erasing data.

[0033] Each memory block may include multiple memory cells. Each memory cell may be configured as a single-level cell storing one bit of data, a multi-level cell storing two bits of data, a three-level cell storing three bits of data, or a four-level cell storing four bits of data. Furthermore, each memory cell may store five or more bits of data.

[0034] Each memory block may include multiple pages configured with memory cells. A page may be a group of memory cells connected to a word line. Memory device 100 can program or read memory cells included in a selected memory block on a page-by-page basis.

[0035] The memory device 100 can be configured as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc.

[0036] Memory device 100 can be configured to receive commands and addresses from controller 1120 and access memory blocks selected according to addresses. That is, memory device 100 can perform operations instructed by commands within the memory blocks selected by addresses. Memory device 100 can perform programming, reading, or erasing operations in response to commands. Commands can be programming commands, reading commands, or erasing commands. For example, memory device 100 can program data in the memory block selected by addresses in response to a programming command. Memory device 100 can read and output data from the memory block selected by addresses in response to a read command. Memory device 100 can erase data in the memory block selected by addresses in response to an erase command. Furthermore, memory device 100 can suspend the currently executing operation in response to a pause command and resume the suspended operation in response to a resume command.

[0037] Controller 1120 can control the overall operation of memory module 1100. For example, when power is applied to memory module 1100, controller 1120 can execute firmware (FW). When memory device 100 is a flash memory device, controller 1120 can execute firmware such as a flash translation layer (FTL) for controlling communication between host 1200 and memory device 100. For example, controller 1120 can receive data and logical addresses from host 1200 and receive requests for various operations. Controller 1120 can translate logical addresses into physical addresses, which represent the location of memory cells in memory device 100 where data will be stored.

[0038] The controller 1120 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., according to the request of the host 1200, or control the memory device 100 to suspend the operation being performed in the memory device 100. During a programming operation, the controller 1120 can provide the memory device 100 with programming commands, physical block addresses, and data. During a read operation, the controller 1120 can provide the memory device 100 with read commands and physical block addresses. During an erase operation, the controller 1120 can provide the memory device 100 with erase commands and physical block addresses.

[0039] Controller 1120 can perform background operations to autonomously manage memory devices regardless of any requests from host 1200. For example, in background operations, controller 1120 can generate commands, addresses, and data and send them to memory device 100 without any requests from host 1200. For instance, controller 1120 can provide commands, addresses, and data to memory device 100 to perform background operations such as wear leveling, garbage collection, automatic refresh, and read reclamation. Controller 1120 can control at least two memory devices 100.

[0040] The host 1200 can communicate with the memory module 1100 using at least one of a variety of communication schemes, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Interconnect Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Compute Fast Link (CXL), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0041] Figure 2 It is a diagram illustrating a memory device.

[0042] refer to Figure 2 The memory device 100 may include a memory cell array 110 and peripheral circuitry 190.

[0043] The memory cell array 110 may include memory cells therein for storing data. In one embodiment, the memory cell array 110 may include a three-dimensional memory cell array. Memory cells may store one bit of data or two or more bits of data, depending on a programming configuration. Memory cells may form a memory cell string. For example, each in a memory cell string may be connected between a bit line BL and a source line.

[0044] The peripheral circuitry 190 can be configured to perform programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations for erasing data stored in the memory cell array 110. The peripheral circuitry 190 may include a row decoder 120, a voltage generation circuit 130, a source line driver 140, a control circuit 150, a page buffer set 160, a column decoder 170, and an input / output circuit 180.

[0045] The row decoder 120 can be connected to the memory cell array 110 via the drain select line DSL, the word line WL, and the source select line SSL. The row decoder 120 can transmit the operating voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL in response to the row address RADD. When a dummy line is connected to the memory cell array 110, the row decoder 120 can transmit the operating voltage Vop to the dummy line in response to the row address RADD.

[0046] The voltage generation circuit 130 can generate various operating voltages Vop for programming, reading, or erasing operations in response to the operation signal OP_S. For example, the voltage generation circuit 130 can generate operating voltages Vop with various levels in response to the operation signal OP_S, and output operating voltage Vop in response to the operation signal OP_S. The operating voltage Vop can include programming voltage, through voltage, turn-on voltage, turn-off voltage, ground voltage, read voltage, etc. The programming voltage is the voltage applied to the selected word line during a programming operation and can be used to increase the threshold voltage of the memory cell. The through voltage is the voltage applied to an unselected word line during a programming or reading operation and can be used to turn on the unselected memory cell. The turn-on voltage is the voltage used to turn on the drain or source select transistor connected to the drain or source select line DSL or SSL, and can be a positive voltage. The turn-off voltage is the voltage used to turn off the drain or source select transistor and can be a ground voltage or 0V. The read voltage is the voltage applied to the selected word line during a read operation and can be set to various levels depending on the logical page data stored in the memory cell.

[0047] In response to the source line control signal SL_S, the source line driver 140 can send a source voltage Vsl supplied therefrom to the source line connected to the source line of the memory cell array 110 or float the source line. The source voltage Vsl can be ground voltage or 0V, a positive voltage above 0V, or a negative voltage below 0V. During an erase operation, the source line driver 140 can send an erase voltage to the source line. The erase voltage is a voltage used to lower the threshold voltage of the memory cell and can be set to a positive voltage.

[0048] Control circuit 150 can output operation signals OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S, and column address CADD in response to command CMD and address ADD. For example, when a programming command is input to control circuit 150, control circuit 150 can control peripheral circuit 190 to perform programming operations on selected pages included in the selected memory block. When the memory cell included in the selected page is programmed to store two or more bits of data, control circuit 150 can change the target voltage that is lower than the reference voltage to a sub-target voltage by taking into account possible interference between adjacent pages, and output operation signals OP_S for generating various voltages including the sub-target voltage.

[0049] When the control circuit 150 outputs the operation signal OP_S, the voltage generation circuit 130 can respond to the operation signal OP_S to set the level of the programming voltage, pass voltage, or verification voltage, and output the set voltage according to the setting time. For example, the voltage generation circuit 130 can respond to the operation signal OP_S to send the programming voltage to the selected global line connected to the selected word line, and send the pass voltage to the unselected global line connected to the unselected word line. When the selected word line is changed, the voltage generation circuit 130 can send the programming voltage to the global line connected to the changed word line, and send the pass voltage to other unselected global lines.

[0050] The control circuit 150 can output an operation signal OP_S to reduce the target voltage of the memory cell included in the selected page, which is lower than the reference voltage, to the sub-voltage. Due to interference occurring during programming operations of adjacent memory cells, the voltage difference between the target voltage and the sub-voltage can be set to a level higher than the threshold voltage.

[0051] Page buffer group 160 may include multiple page buffers connected to memory cell array 110 via bit lines BL. The page buffers may store data DATA received via multiple bit lines BL in response to a page buffer control signal PB_S. During programming operations, the page buffers may apply a programming enable voltage to the selected bit line and a programming disable voltage to the disabled bit line. The programming enable voltage may be 0V or a negative voltage, and the programming disable voltage may be a power supply voltage.

[0052] Column decoder 170 can send data DATA input from input / output circuit 180 to page buffer group 160, or send data DATA stored in page buffer group 160 to input / output circuit 180, in response to column address CADD. Column decoder 170 can exchange data DATA with input / output circuit 180 via column line CLL. Column decoder 170 can exchange data DATA with page buffer group 160 via data line DTL.

[0053] Input / output circuit 180 can transmit commands CMD and addresses ADD to control circuit 150, which are transmitted from external devices (e.g., controllers) of memory device 100. Input / output circuit 180 can receive data transmitted from external devices during programming operations and output data DATA read from selected memory cells to external devices during read operations.

[0054] Figure 3 It is a diagram illustrating the arrangement of the memory cell array and peripheral circuitry.

[0055] refer to Figure 3 Memory devices ( Figure 2 The 100 shown may include peripheral circuitry 190 and memory cell array 110. Peripheral circuitry 190 may be disposed above a substrate, and memory cell array 110 may be disposed above peripheral circuitry 190. Memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Multiple bit lines BL may be disposed above the first to j-th memory blocks BLK1 to BLKj.

[0056] Multiple bit lines BL can be arranged to be spaced apart from each other in the X direction and extend along the Y direction. First to j-th memory blocks BLK1 to BLKj can be arranged to be spaced apart from each other in the Y direction. First to j-th memory blocks BLK1 to BLKj can be configured identically to each other, and therefore, the first memory block BLK1 will be described below as an example.

[0057] Figure 4 This is a circuit diagram illustrating the connection configuration of the memory blocks.

[0058] refer to Figure 4The first memory block BLK1 includes a string ST connected between the first to nth bit lines BL1 to BLn and the source line SL. The first to nth bit lines BL1 to BLn extend along the Y direction and are arranged to be spaced apart from each other along the X direction. Therefore, the string ST can also be arranged to be spaced apart from each other along both the X and Y directions. For example, the string ST can be arranged between the first bit line BL1 and the source line SL, and the string ST can be arranged between the second bit line BL2 and the source line SL. In this way, the string ST can be arranged between the nth bit line BLn and the source line SL. The string ST can extend along the Z direction.

[0059] The string ST connected to the nth bit line BLn is described as an example. The string ST may include the source selection transistor SST, the first to the i-th memory cells MC1 to MCi, and the drain selection transistor DST. Figure 4 The first memory block BLK1 shown is a schematic diagram illustrating the structure of the memory block, and therefore, the number of source selection transistors SST, first to i memory cells MC1 to MCi, and drain selection transistors DST included in the string ST can vary depending on the memory device.

[0060] The gate of the source selection transistor SST included in different strings can be connected to the first or second source selection line SSL1 or SSL2, the gate of the first to i memory cells MC1 to MCi included in different strings can be connected to the first to i word lines WL1 to WLi, and the gate of the drain selection transistor DST included in different strings can be connected to any one of the first to fourth drain selection lines DSL1 to DSL4.

[0061] The lines connected to the first memory block BLK1 will now be described. Source select transistors (SSTs) arranged along the X-direction can be connected to the same source select line, and source select transistors (SSTs) arranged along the Y-direction can be connected to isolated source select lines. For example, some of the source select transistors (SSTs) arranged in the Y-direction can be connected to the first source select line SSL1, and others can be connected to the second source select line SSL2. The second source select line SSL2 is isolated from the first source select line SSL1. Therefore, the voltage applied to the first source select line SSL1 can be equal to or different from the voltage applied to the second source select line SSL2.

[0062] Memory cells formed in the same layer among the first to the i-th memory cells MC1 to MCi can be connected to the same word line. For example, the first memory cell MC1, which is included in different strings ST, can be connected to the first word line WL1, and the i-th memory cell MCi, which is included in different strings ST, can be connected to the i-th word line WLi. Memory cells included in different strings ST and connected to the same word line constitute a page PG. Programming and reading operations can be performed on a page PG basis.

[0063] Drain select transistors (DSTs) arranged in the Y direction can be connected to the first to fourth drain select lines DSL1 to DSL4, which are isolated from each other. Specifically, drain select transistors (DSTs) arranged in the X direction can be connected to the same drain select line, and drain select transistors (DSTs) arranged in the Y direction can be connected to the first to fourth drain select lines DSL1 to DSL4, which are isolated from each other. Since the first to fourth drain select lines DSL1 to DSL4 are isolated from each other, different voltages can be applied to the first to fourth drain select lines DSL1 to DSL4.

[0064] Figure 5 It is a diagram illustrating the structure of a string.

[0065] refer to Figure 5 The source line SL can be formed on the lower structure UDS, and the stacked structure STK can be formed on the source line SL. The lower structure UDS can be a substrate or peripheral circuitry. The source line SL can be formed of a conductive material. For example, the source line SL can be formed of polysilicon. The stacked structure STK can include an insulating layer ISL formed between the gate lines. The gate lines can include a source select line SSL, first to i-th word lines WL1 to WLi, and a drain select line DSL. The gate lines can be formed of a conductive material. For example, the gate lines can be formed of conductive materials such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (polycrystalline silicon). Furthermore, the gate lines can be formed of various metal materials. The insulating layer ISL can be formed of an oxide layer or a silicon oxide layer. For example, the gate line adjacent to the source line SL can become the source select line SSL, some of the gate lines stacked above the source select line SSL can become the first to the i-th word lines WL1 to WLi, and the gate line formed above the i-th word line WLi can become the drain select line DSL.

[0066] The string ST can be configured with a cell plug CPL that penetrates the stacked structure STK. The cell plug CPL can include a barrier layer BX, a charge trapping layer CT, a tunnel insulating layer TX, a channel layer CH, a core pillar CP, and a capping layer CAP. The barrier layer BX can be formed as a cylinder penetrating the stacked structure STK and is formed of an oxide layer or a silicon oxide layer. The charge trapping layer CT can be formed as a cylinder along the inner wall of the barrier layer BX and is formed of a nitride layer. The tunnel insulating layer TX can be formed as a cylinder along the inner wall of the charge trapping layer CT and is formed of an oxide layer or a silicon oxide layer. The channel layer CH can be formed as a cylinder along the inner wall of the tunnel insulating layer TX and is formed of polysilicon. The core pillar CP can be formed as a cylinder filling the interior of the channel layer CH and is formed of an insulating material such as an oxide layer or a silicon oxide layer. The capping layer CAP can be formed as a cylinder on top of the core pillar CP and is formed of a conductive material. When the capping layer CAP is formed on top of the core pillar CP, the height of the top surface of the core pillar CP can be formed to be lower than the height of the top surface of the channel layer CH, and the capping layer CAP can be formed in the upper region of the core pillar CP surrounded by the channel layer CH.

[0067] Bit line contacts BC and bit lines BL can be formed on top of the unit plug CPL. For example, bit line contacts BC can be formed of a conductive material and contact the channel layer CH included in the unit plug CPL. Bit lines BL can be formed on top of bit line contacts BC and are also formed of a conductive material.

[0068] Figure 6A , Figure 6B , Figure 7A and Figure 7B This diagram illustrates the phenomenon where the threshold voltage of a memory cell is altered due to interference during programming operations.

[0069] Figure 6A and Figure 6B It is a diagram illustrating the programming operations of PGM on page m, and Figure 7A and Figure 7B This is a diagram illustrating the threshold voltage of the memory cell included in the memory cell ...

[0070] refer to Figure 6A and Figure 6BAssume a programming operation is performed in the direction from the source select line SSL to the drain select line DSL. When the m-th page PGm connected to the m-th word line WLm is the selected page in the programming operation, the memory cells included in the m-th page PGm can be programmed into different states depending on the target voltage. For example, when performing a programming operation in three-level cell mode, the memory cells included in the m-th page PGm can be programmed into the erase state ER or any of the first to seventh programming states.

[0071] Programming operations can be performed using Incremental Step Pulse Programming (ISPP), which gradually increases the programming voltage applied to the m-th word line WLm. Multiple programming cycles can be executed in an ISPP programming operation. Within a programming cycle, a phase can be executed where a threshold voltage of the memory cell is increased using a programming voltage and a phase can be executed where a threshold voltage of the memory cell is verified using a verification voltage. In the phase where the threshold voltage of the memory cell is verified, if it is determined that the threshold voltage of the selected memory cell has not been increased to the target voltage, a programming voltage higher than that used in the previous programming cycle can be used to increase the threshold voltage of the memory cell in the next programming cycle. For example, the programming voltage can be gradually increased by a predetermined step voltage as the number of programming cycles is increased. As used herein with respect to parameters such as a predetermined step voltage, the term "predetermined" means that the value of the parameter is determined before the parameter is used in the process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0072] Memory cells with a target voltage set to a first target voltage can be programmed into a first programming state P1, and memory cells with a target voltage set to a second target voltage higher than the first target voltage can be programmed into a second programming state P2 higher than the first programming state P1. In this way, memory cells included in page m, PGm, can be programmed into first to seventh programming states P1 to P7 according to the first to seventh target voltages.

[0073] refer to Figure 7A and Figure 7B When the programming operation of page m PGm is completed, the selected page is changed to page (m+1) PG(m+1). When the selected page is changed to page (m+1) PG(m+1), the programming operation of page (m+1) PG(m+1) can be performed by applying a gradually increasing programming voltage.

[0074] Since the programming voltage is a positive voltage used to move electrons to the channel layer of memory cells included in the selected page, it may affect not only memory cells included in the selected page but also unselected memory cells included in unselected pages. For example, when performing a programming operation on memory cells included in page (m+1) PG(m+1), some memory cells in page m PGm that are already fully programmed may be affected by the programming voltage applied to page (m+1) PG(m+1). Memory cells with relatively low threshold voltages among those included in page m PGm may be further affected by programming operations on adjacent pages. For example, among the memory cells programmed into programming states P1 to P7 in page m of PGm, the memory cell programmed into programming state P1 may be most affected by the programming operation of PG(m+1) in page (m+1), and among the memory cells programmed into programming states P1 to P7 in page m of PGm, the memory cell programmed into programming state P7 may be least affected by the programming operation of PG(m+1) in page (m+1).

[0075] In page m, PGm, the threshold voltage change level of the memory cell programmed to the first programming state P1 is the highest, and therefore the threshold voltage of some memory cells programmed to the first programming state P1 may become higher than the second target voltage V2 of the second programming state P2. In one embodiment, when the threshold voltage distributions of memory cells programmed to different programming states partially overlap, the number of error bits detected in read operations increases, and therefore, the reliability of the memory device may deteriorate.

[0076] Therefore, in one embodiment described below, considering the programming operations of adjacent pages, the programming operation can be performed by lowering the target voltage of some memory cells. Subsequently, when the programming operations of adjacent pages are completed, additional programming operations can be performed to increase the threshold voltage of the memory cells to be programmed to the lowered target voltage to the target voltage.

[0077] Figure 8 This is a diagram illustrating programming operations according to an embodiment of the present disclosure. Figure 9 This is a diagram illustrating the page selection sequence in a programming operation according to an embodiment of the present disclosure.

[0078] refer to Figure 8 and Figure 9When programming operations on the selected memory block begin, step S81 can be executed to set a target voltage corresponding to the programming state of the memory cell. For example, when performing a programming operation in a three-level cell mode where three bits of data are stored in one memory cell, the first to seventh target voltages corresponding to the first to seventh programming states can be set. For example, when performing a programming operation in a four-level cell mode where four bits of data are stored in one memory cell, the first to fifteenth target voltages corresponding to the first to fifteenth programming states can be set. The programming operation mode can vary depending on the memory device, and therefore, the target voltage can be set according to the mode of the programming operation performed in the memory device.

[0079] Step S82 can be performed to change at least one target voltage lower than a reference voltage to a sub-target voltage with a level lower than a default level. The default level can be a basic level set at startup in the memory device. The reference voltage can be any of the target voltages. For example, the reference voltage can be any target voltage other than the lowest target voltage. For example, when the second target voltage among the first to seventh target voltages is set as the reference voltage, a target voltage lower than the reference voltage becomes the first target voltage. Therefore, the first target voltage can be changed to a first sub-target voltage. The first sub-target voltage can be set to a voltage higher than the highest threshold voltage among the memory cells in the erase state and lower than a positive voltage of the first target voltage. For example, when the fourth target voltage among the first to seventh target voltages is set as the reference voltage, a target voltage lower than the reference voltage becomes the first to third target voltages. The first to third target voltages can be changed to first to third sub-target voltages. The first sub-target voltage can be set to a voltage higher than the highest threshold voltage among the memory cells in the erase state and lower than a positive voltage of the first target voltage. The second sub-target voltage can be set to a voltage higher than the highest threshold voltage among the memory cells in the first programming state and lower than the first target voltage. The third sub-target voltage can be set to be higher than the highest of the threshold voltages of the memory cell in the second programming state and lower than the third target voltage.

[0080] When a sub-target voltage is set, the programming operation on page m can be performed. The programming operation on page m can be performed by other target voltages and sub-target voltages that have not been changed to the sub-target voltage. For example, when the first target voltage is changed to the first sub-target voltage in step S82, and the second to seventh target voltages are maintained at their default levels, the memory cells can be programmed according to the first sub-target voltage and the second to seventh target voltages in the programming operation on page m. When a memory cell to be programmed to the first target voltage is programmed to a second sub-target voltage lower than the first target voltage, and memory cells to be programmed to the second to seventh target voltages are programmed to the second to seventh target voltages, the programming operation on the next page can be performed.

[0081] When a memory cell is programmed according to a sub-target voltage and a target voltage in the programming operation of page m (S83), the programming operation of page (m+1), which is the next page, can be performed (S84). Similar to the programming operation of page m, the programming operation of page (m+1) can also be performed using a sub-target voltage and other target voltages. When the programming operation of page (m+1) is performed, the threshold voltage of some memory cells included in page m may increase due to the programming voltage applied to the word line (m+1) connected to page (m+1). However, since the memory cells included in page m that are greatly affected by the programming operations of adjacent pages have been programmed with sub-target voltages lower than the target voltage, even when the threshold voltage of a memory cell increases, the threshold voltage of the corresponding memory cell will not increase to the target voltage.

[0082] When a memory cell is programmed according to a sub-target voltage and a target voltage during the programming operation of page (m+1) (S84), an additional programming operation for page m, which is the previous page, can be performed (S85). The additional programming operation can be selectively performed on memory cells in the selected page that are programmed according to the sub-target voltage. For example, memory cells in page m that are programmed according to the sub-target voltage can be selected, and the additional programming operation can be performed only on the selected memory cells. The additional programming operation can be performed by using a target voltage higher than the sub-target voltage. That is, the additional programming operation can be performed to increase the threshold voltage of the memory cell in the previous page, which will be programmed to a level lower than the default level, to the target voltage. The additional programming operation can be performed by using the lowest voltage among the programming voltages as the starting programming voltage. The additional programming operation can be performed in ISPP mode. When the additional programming operation for page m ends, the programming operation for page m is completed.

[0083] When the additional programming operation of page m executed in step S85 is completed, the programming operation of page (m+2) can be executed (S86). Similar to the programming operation of page (m+1), the programming operation of page (m+2) can be executed using sub-target voltages and other target voltages. When the programming operation of page (m+2) is executed, the threshold voltage of some memory cells included in page (m+1) may increase due to the programming voltage applied to the word line (m+2) connected to page (m+2). However, since the memory cells included in page (m+1) that are greatly affected by the programming operations of adjacent pages have been programmed to sub-target voltages lower than the target voltage, even when the threshold voltage of a memory cell increases, the threshold voltage of the corresponding memory cell will not increase to the target voltage.

[0084] When the memory cell is programmed according to the sub-target voltage and the target voltage in the programming operation of page (m+2) (S86), the additional programming of page (m+1) can be performed (S87). The additional programming of page (m+1) is performed in the same manner as the additional programming operation performed in step S85, and therefore a repeated description of the additional programming will be omitted.

[0085] As described in steps S81 to S87, programming operations and additional programming operations can be performed on other pages included in the selected memory block. In the programming operation of the last page among the pages included in the selected memory block, the sub-target voltage set in step S82 is not used, and only the target voltage set in step S81 can be used. When the programming operation of the last page is completed, additional programming operations on the page preceding the last page can be performed. When the additional programming operations on the page preceding the last page are completed, the programming operation of the selected memory block can be terminated. Figures 10A to 10C This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0086] Figure 10A The diagram illustrates the threshold voltage distribution of memory cells included in page m during the programming operation on page m. Figure 10B The diagram illustrates the threshold voltage distribution of memory cells included in page m during the programming operation on page (m+1). Figure 10C The diagram illustrates the threshold voltage distribution of memory cells included in page m during the additional programming operation on page m.

[0087] refer to Figures 10A to 10C The first embodiment describes the programming operation when the second target voltage V2 is set to the reference voltage Vref.

[0088] refer to Figure 10AWhen the reference voltage Vref is set to the second target voltage V2, a target voltage lower than the reference voltage Vref becomes the first target voltage V1. Therefore, in the programming operation of page m PGm, the first target voltage V1 can be changed to a first sub-target voltage sV1 lower than the first target voltage V1. For example, the first sub-target voltage sV1 can be set to a positive voltage higher than the highest threshold voltage among the memory cells in the erase state and lower than the first target voltage V1. The voltage difference between the first target voltage V1 and the first sub-target voltage sV1 can be set to be greater than the change in threshold voltage added during the programming operation of adjacent pages. The change in threshold voltage added during the programming operation of adjacent pages can be calculated through a test programming operation of the memory device, and the first sub-target voltage sV1 can be determined based on the voltage difference greater than the calculated change. Test programming operations can be performed on some pages during the manufacture of the memory device. For example, in a test programming operation, dummy data is programmed onto the selected page. After performing a test programming operation on the selected page, the change in threshold voltage of the programmed pages among the pages adjacent to the selected page can be measured. After the test programming operation, the selected memory block is erased. Other target voltages besides the first target voltage V1 can have default levels set in the memory device.

[0089] When the first target voltage V1 is changed to the first sub-target voltage sV1, the verification voltage corresponding to the first target voltage V1 is reduced to the voltage corresponding to the first sub-target voltage sV1. Therefore, when performing the programming operation on page m PGm, the memory cell corresponding to the first target voltage V1 can be programmed according to the first sub-target voltage sV1, and other memory cells can be programmed according to the target voltage with a default level.

[0090] refer to Figure 10BAfter the programming operation of page m, PGm, is completed, the programming operation of page (m+1), PGm+1, can be performed. Page (m+1), PGm+1, can be a page selected from the pages adjacent to page m, according to the order of the programming operations. The programming operation performed on page (m+1), PGm+1, can be performed in the same manner as the programming operation performed on page m, PGm. When performing the programming operation on page (m+1), the threshold voltage of the memory cells included in page m, programmed according to the first sub-target voltage sV1, may increase. For example, the threshold voltage of some memory cells included in page m, PGm, may increase due to the programming voltage applied to the (m+1)th word line connected to page (m+1), PGm+1. Since the voltage difference between the first target voltage V1 and the first sub-target voltage sV1 is greater than the change in threshold voltage calculated by the test programming operation of adjacent pages, the threshold voltage of the memory cell programmed according to the first sub-target voltage sV1 in page m PGm will not increase to the first target voltage V1 or higher.

[0091] refer to Figure 10C When the programming operation for page (m+1)PGm+1 is completed, the selected page can be changed back to page mPGm, and an additional programming operation for page mPGm can be performed. In the additional programming operation, the memory cell programmed according to the first sub-target voltage sV1 becomes the selected memory cell Sel_Cell, and the other memory cells become the unselected memory cells Unsel_Cell. The first target voltage V1 can be used as the target voltage in the additional programming operation. In the additional programming operation, a programming enable voltage can be applied to the bit line of the selected memory cell Sel_Cell, and a programming disable voltage can be applied to the bit line of the unselected memory cell Unsel_Cell. The programming enable voltage can be 0V or a negative voltage, while the programming disable voltage can be a positive voltage or the power supply voltage.

[0092] Additional programming operations can be performed in ISPP mode. In ISPP programming, the programming voltage can be applied starting from the lowest possible programming voltage and continuing to the m-th word line connected to the m-th page PGm. For example, when additional programming begins, the initial programming voltage can be applied to the m-th word line, and the programming voltage can be gradually increased as the number of programming cycles is executed. In ISPP programming, a verification operation can be performed on the first target voltage V1.

[0093] The programming operations on page m of PGM can be completed when the additional programming operations on page m of PGM are finished.

[0094] Figures 11A to 11CThis is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0095] Figure 11A The diagram illustrates the threshold voltage distribution of memory cells included in page m during the programming operation on page m. Figure 11B The diagram illustrates the threshold voltage distribution of memory cells included in page m during the programming operation on page (m+1). Figure 11C The diagram illustrates the threshold voltage distribution of memory cells included in page m during the additional programming operation on page m.

[0096] refer to Figures 11A to 11C The second embodiment describes the programming operation when multiple target voltages are lower than a reference voltage Vref. The reference voltage Vref can be set to any one of the third to seventh target voltages V3 to V7. The second embodiment described below illustrates the programming operation in which a fourth target voltage V4 is set as the reference voltage.

[0097] refer to Figure 11A When the reference voltage Vref is set to the fourth target voltage V4, the target voltages lower than the reference voltage Vref become the first to third target voltages V1 to V3. Therefore, in the programming operation of page m, PGm, the first target voltage V1 can be changed to a first sub-target voltage sV1 lower than the first target voltage V1, the second target voltage V2 can be changed to a second sub-target voltage sV2 lower than the second target voltage V2, and the third target voltage V3 can be changed to a third sub-target voltage sV3 lower than the third target voltage V3. For example, the first sub-target voltage sV1 can be set to a voltage higher than the highest threshold voltage of the memory cell in the erase state and lower than the positive voltage of the first target voltage V1. The second sub-target voltage sV2 can be set to a voltage higher than the highest threshold voltage HV1 of the first programming state P1. The third sub-target voltage sV3 can be set to a voltage higher than the highest threshold voltage HV2 of the second programming state P2.

[0098] The voltage differences between the first target voltage V1 and the first sub-target voltage sV1, the second target voltage V2 and the second sub-target voltage sV2, and the third target voltage V3 and the third sub-target voltage sV3 can be set to be greater than the change in the threshold voltage corresponding to each programming state in the programming operation of adjacent pages. The change in the threshold voltage during the programming operation of adjacent pages can be calculated by test programming operations of the memory device, and the first to third sub-target voltages sV1 to sV3 can be determined based on the voltage differences greater than the calculated changes. The other target voltages besides the first to third sub-target voltages sV1 to sV3 can have a default level basically set in the memory device.

[0099] When the first target voltage V1 is changed to the first sub-target voltage sV1, the verification voltage corresponding to the first target voltage V1 is reduced to the voltage corresponding to the first sub-target voltage sV1. When the second target voltage V2 is changed to the second sub-target voltage sV2, the verification voltage corresponding to the second target voltage V2 is reduced to the voltage corresponding to the second sub-target voltage sV2. When the third target voltage V3 is changed to the third sub-target voltage sV3, the verification voltage corresponding to the third target voltage V3 is reduced to the voltage corresponding to the third sub-target voltage sV3. Therefore, when performing the programming operation on page m, the memory cell corresponding to the first target voltage V1 can be programmed according to the first sub-target voltage sV1, the memory cell corresponding to the second target voltage V2 can be programmed according to the second sub-target voltage sV2, and the memory cell corresponding to the third target voltage V3 can be programmed according to the third sub-target voltage sV3. Other memory cells can be programmed according to target voltages with default levels.

[0100] refer to Figure 11B After the programming operation of page m, PGm, is completed, the programming operation of page (m+1), PGm+1, can be performed. Page (m+1), PGm+1, can be a page selected from the pages adjacent to page m, according to the programming order. The programming operation performed on page (m+1), PGm+1, can be performed in the same manner as the programming operation performed on page m, PGm. When programming page (m+1), PGm+1 may increase the threshold voltage of memory cells included in page m, programmed according to the first to third sub-target voltages sV1 to sV3. As the threshold voltage becomes lower, the change in the increased threshold voltage becomes larger. For example, the change in the threshold voltage of memory cells programmed according to the first sub-target voltage sV1 may be the largest, while the change in the threshold voltage of memory cells programmed according to the third sub-target voltage sV3 may be the smallest.

[0101] refer to Figure 11CWhen the programming operation for page (m+1)PGm+1 is completed, the selected page can be changed back to page mPGm, and an additional programming operation for page mPGm can be performed. In the additional programming operation, the memory cell programmed according to the first to third sub-target voltages sV1 to sV3 becomes the selected memory cell Sel_Cell, and the other memory cells become the unselected memory cells Unsel_Cell. The first to third target voltages V1 to V3 can be used as target voltages in the additional programming operation. In the additional programming operation, a programming enable voltage can be applied to the bit line of the selected memory cell Sel_Cell, and a programming disable voltage can be applied to the bit line of the unselected memory cell Unsel_Cell. The programming enable voltage can be 0V or a negative voltage, while the programming disable voltage can be a positive voltage or the power supply voltage.

[0102] Additional programming operations can be performed in ISPP mode. In ISPP programming, the programming voltage can be applied starting from the lowest programming voltage and continuing up to the m-th word line connected to the m-th page PGm. For example, when additional programming begins, the initial programming voltage can be applied to the m-th word line, and the programming voltage can be gradually increased as the number of programming cycles is executed. In ISPP programming, verification operations can be performed on the first to third target voltages V1 to V3.

[0103] The programming operations on page m of PGM can be completed when the additional programming operations on page m of PGM are finished.

[0104] Figure 12 This is a diagram illustrating a memory card system that utilizes a memory device according to an embodiment of the present disclosure.

[0105] refer to Figure 12 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0106] Controller 3100 can be connected to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming, reading, or erasing operations, or control background operations of memory device 3200. Controller 3100 can provide an interface between memory device 3200 and a host. Controller 3100 can drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0107] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0108] The memory device 3200 may include memory cells and is configured to... Figure 2 The memory device 100 shown is the same.

[0109] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can form a memory card such as: a personal computer (PC) card (PCMCIA International Association)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (SD, miniSD, microSD and SDHC), and a universal flash storage device (UFS).

[0110] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system that utilizes a memory device according to an embodiment of the present disclosure.

[0111] refer to Figure 13 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0112] Controller 4210 can control multiple storage devices 4221 to 422n in response to signals received from host 4100. For example, the signals can be signals based on the interface between host 4100 and SSD 4200. For example, the signals can be signals defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0113] The plurality of memory devices 4221 to 422n may include units capable of storing data. Each of the plurality of memory devices 4221 to 422n can be connected to... Figure 2 The memory device 100 shown is configured similarly.

[0114] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power input PWR from host 4100 and charge the power PWR. When the power supply from host 4100 is unreliable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 can be located inside SSD 4200 or externally to SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0115] Buffer memory 4240 may operate as a buffer memory for SSD 4200. For example, buffer memory 4240 may temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0116] According to this disclosure, in one embodiment, the reliability of the memory device can be improved.

[0117] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0118] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0119] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is merely for the purpose of explaining the embodiments of this disclosure. Therefore, this disclosure is not limited to the above embodiments, and many variations can be made within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

Claims

1. A memory device, comprising: A memory block comprising multiple pages, each page comprising a memory cell configured to be programmed into different programming states according to multiple target voltages; as well as The peripheral circuitry is configured to perform programming operations on a selected page among the plurality of pages. The peripheral circuit is configured as follows: In the programming operation of the selected page, at least one of the plurality of target voltages is reduced to a corresponding sub-target voltage; The programming operation of the selected page is performed based on the target voltages other than the at least one target voltage corresponding to the corresponding sub-target voltage and the corresponding sub-target voltage. When the programming operation of the selected page is completed, the programming operation of the page adjacent to the selected page is executed; as well as When the programming operation of the adjacent page is completed, an additional programming operation is performed on the memory cell in the selected page that was programmed according to the corresponding sub-target voltage, based on the at least one target voltage corresponding to the corresponding sub-target voltage.

2. The memory device of claim 1, wherein the peripheral circuitry is configured to perform the programming operation in such a manner as to store at least two bits of data in a memory cell included in the selected page.

3. The memory device of claim 1, wherein the plurality of target voltages are voltages for dividing the memory cells included in the selected page into memory cells with different programming states.

4. The memory device of claim 1, wherein the peripheral circuitry is configured as follows: The selected voltage from the plurality of target voltages, excluding the lowest voltage, is set as the reference voltage; and The at least one target voltage that is lower than the reference voltage is reduced to the corresponding sub-target voltage.

5. The memory device of claim 1, wherein the voltage difference between the corresponding sub-target voltage and the at least one target voltage is set to be equal to or greater than the change in the threshold voltage of the memory cell included in the selected page, which is altered during the programming operation of the page adjacent to the selected page.

6. The memory device of claim 5, wherein the change in the threshold voltage of the memory cell is calculated through test programming operations of the plurality of pages.

7. The memory device of claim 1, wherein the peripheral circuitry is configured to perform the programming operation of the page adjacent to the selected page in the same manner as the programming operation of the selected page.

8. The memory device of claim 1, wherein the peripheral circuitry is configured to perform the programming operation in an incremental step pulse programming (ISPP) manner.

9. The memory device of claim 1, wherein the peripheral circuitry comprises: The control circuit is configured to output operation signals, page buffer control signals, and row addresses in response to programming commands and addresses; A voltage generation circuit is configured to generate a programming voltage or a verification voltage in response to the operation signal; Page buffer groups are configured to supply programming disable voltage or programming enable voltage to bit lines connected to the memory block in response to page buffer control signals. as well as A row decoder is configured to transmit the programming voltage or the verification voltage to a word line connected to the memory block in response to the row address.

10. The memory device of claim 9, wherein the control circuitry is configured to determine the levels of the plurality of target voltages and the corresponding sub-target voltages to be applied to the plurality of pages, and to generate and output the operating signal such that the verification voltage is generated based on the plurality of target voltages and the corresponding sub-target voltages.

11. A method of operating a memory device, the method comprising: Set the target voltage corresponding to the programming state of the memory cell; Reduce the target voltage that is lower than the reference voltage to a sub-target voltage; Based on the target voltages other than the target voltage corresponding to the sub-target voltage, and the sub-target voltage, perform the programming operation of the selected page; When the programming operation of the selected page is completed, the programming operation of the page adjacent to the selected page is executed; as well as When the programming operation of the adjacent page is completed, an additional programming operation is performed on the memory cell in the selected page that was programmed according to the sub-target voltage.

12. The method of claim 11, wherein the target voltage is the lowest of the threshold voltages corresponding to the corresponding programming state.

13. The method of claim 11, wherein the reference voltage is selected from among the target voltages other than the lowest voltage.

14. The method of claim 11, wherein the voltage difference between the target voltage and the sub-target voltage, which is below the reference voltage, is set to be equal to or greater than the change in the threshold voltage of the memory cell included in the selected page, which is altered during the programming operation of the adjacent page.

15. The method of claim 14, wherein the change in the threshold voltage of the memory cell is calculated through a test programming operation of the page.

16. The method of claim 11, wherein the programming operation and the additional programming operation are performed in an incremental step pulse programming (ISPP) manner.

17. The method according to claim 11, wherein, In the additional programming operation, the memory cell in the selected page that is programmed according to the sub-target voltage becomes the selected memory cell, and the other memory cells become the unselected memory cells.

18. The method according to claim 17, wherein, In the additional programming operation, programming allows voltage to be applied to the bit lines connected to the selected memory cell, and programming prevents voltage from being applied to the bit lines connected to the unselected memory cell.

19. The method of claim 18, wherein the programming enable voltage is set to ground voltage and the programming disable voltage is set to power supply voltage.

20. The method of claim 11, wherein the target voltage has a default level predetermined in the memory device.

21. A method of operating a memory device, the method comprising: Set the first target voltage to the Kth target voltage, where 'K' is an integer greater than 1; Reduce the first target voltage to the first sub-target voltage; Programming operations are performed on memory cells to be programmed according to the first target voltage in the pages included in the memory block, which are included in the m-th page, and programming operations are performed on other memory cells in the m-th page according to the second target voltage to the K-th target voltage. When the programming operation on the m-th page is completed, the memory cell included in the (m+1)-th page adjacent to the m-th page is programmed in the same manner as the programming operation performed on the m-th page; as well as When the programming operation on page (m+1) is completed, additional programming operations are performed on the memory cells included in page m that have been programmed according to the first sub-target voltage, based on the first target voltage. Where 'm' is an integer greater than zero.

22. The method of claim 21, wherein the first sub-target voltage is set to be higher than the highest of the threshold voltages of the memory cell in the erase state and lower than the first target voltage.

23. The method of claim 21, wherein the voltage difference between the first sub-target voltage and the first target voltage is set to be greater than the change in the threshold voltage of the memory cell in the m-th page that is altered during the programming operation in the (m+1)-th page.

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