Ultra-wideband high-frequency interconnection structure and preparation method

Abstract

The application provides an ultra-wideband high-frequency interconnection structure and a preparation method. The structure comprises, from bottom to top, a bottom conductive layer, a deformation metal layer and a bonding interconnection metal layer which are sequentially stacked, and the two ends of the bottom conductive layer are respectively connected to the two ends of the bonding interconnection metal layer. The deformation metal layer comprises at least one first sub-metal layer and at least one second sub-metal layer which are stacked, and the thermal stress of the first sub-metal layer and the second sub-metal layer is different. The two ends of the bonding interconnection metal layer, the two ends of the deformation metal layer and the two ends of the bottom conductive layer are all curved towards the middle position close to the upper surface of the bonding interconnection metal layer, and the curvature is a natural deformation formed based on the different thermal stress of the first sub-metal layer and the second sub-metal layer. The interconnection structure provided by the application has high strength and good consistency.

Description

Technical Field

[0001] This invention relates to the field of radio frequency microwave technology, and in particular to an ultra-wideband high-frequency interconnect structure and its fabrication method. Background Technology

[0002] In the field of radio frequency and microwave, radio frequency and microwave circuits are generally distributed parameter circuits. Distributed parameter circuits refer to circuits in which the distributed parameter effect of the transmission line cannot be ignored under high frequency operation. Their electrical characteristics are described by the distributed inductance, distributed capacitance, distributed resistance and distributed conductance per unit length of the line. At this time, the transmission line is integrated with series inductance and resistance, parallel capacitance and conductance. The circuit composed of the distributed parameter characteristics of the transmission line is called a distributed parameter circuit.

[0003] Radio frequency (RF) chip ports are typically interconnected using bonding, which is equivalent to introducing an inductance to ground in the RF circuit, thus degrading the impedance skew characteristics of the entire circuit. With the continuous development of high-frequency chips, a method using spot-welded gold strip interconnects has emerged, but this introduces additional capacitance to ground.

[0004] However, existing interconnect structures have poor frequency bandwidth coverage, and the gold strip is prone to deformation and inconsistency during use, resulting in variations in impedance characteristics and significant insertion losses at ports in the millimeter-wave and even terahertz high-frequency bands. Therefore, a new gold strip interconnect structure is urgently needed. Summary of the Invention

[0005] This invention provides an ultra-wideband high-frequency interconnect structure and its fabrication method to solve the problem of easy deformation and poor consistency in current gold strip interconnect structures.

[0006] In a first aspect, embodiments of the present invention provide an ultra-wideband high-frequency interconnect structure, comprising a bottom conductive layer, a deformable metal layer and a bonding interconnect metal layer stacked sequentially from bottom to top, wherein the two ends of the bottom conductive layer are respectively connected to the two ends of the bonding interconnect metal layer.

[0007] The deformable metal layer includes at least one first sub-metal layer and at least one second sub-metal layer stacked together, wherein the thermal stresses of the first sub-metal layer and the second sub-metal layer are different;

[0008] Both ends of the bonding interconnect metal layer, both ends of the deformable metal layer, and both ends of the bottom conductive layer are bent toward the middle position near the upper surface of the bonding interconnect metal layer, and this bending is a natural deformation based on the difference in thermal stress between the first sub-metal layer and the second sub-metal layer.

[0009] In one possible implementation, a matching structure matching the broadband is also provided at a preset location of the deformable metal layer.

[0010] In one possible implementation, the two ends of the ultra-wideband high-frequency interconnect structure have different dimensions, with one end being larger than the other.

[0011] In one possible implementation, both the bonding interconnect metal layer and the underlying conductive layer are gold layers; the first sub-metal layer is a nickel layer, and the second sub-metal layer is a copper layer.

[0012] In one possible implementation, the two ends of the deformable metal layer are serrated, and the serrated ends of the deformable metal layer are bent toward the middle position near the upper surface of the bonding interconnect metal layer during heat treatment.

[0013] Secondly, embodiments of the present invention provide a method for fabricating an ultra-wideband high-frequency interconnect structure, comprising:

[0014] A sacrificial layer and a seed layer are prepared on the surface of a substrate, respectively.

[0015] A first photoresist layer is coated on a seed layer and a first photoresist definition layer is prepared by photolithography on the first photoresist layer. Undeveloped first photoresist layers are provided at both ends of the first photoresist definition layer.

[0016] A first metal layer is obtained by growing a first metal on a first photoresist defining layer and performing pretreatment.

[0017] A second positive photoresist layer is prepared on a first metal layer and an undeveloped first photoresist layer, and a second photoresist defining layer is prepared on the second positive photoresist layer. Undeveloped second positive photoresist layers are provided at both ends of the second photoresist defining layer, wherein the length of the undeveloped second positive photoresist layer is greater than the length of the undeveloped first photoresist layer.

[0018] A second metal layer is obtained by growing a second metal on the second photoresist defining layer and performing pretreatment.

[0019] A third positive photoresist layer is prepared on the second metal layer and the undeveloped second positive photoresist layer, and a third photoresist definition layer is prepared on the third positive photoresist layer. Undeveloped third positive photoresist layers are provided at both ends of the third photoresist definition layer.

[0020] A third metal layer is prepared on the third photoresist defining layer and pretreated to obtain the third metal layer. The thermal stress of the second metal layer is different from that of the third metal layer.

[0021] Remove the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer, and prepare the fourth metal layer by photolithography and perform pretreatment to obtain the fourth metal layer. The two ends of the first metal layer are connected to the two ends of the fourth metal layer.

[0022] Remove the undeveloped first photoresist layer, the seed layer not covered by the fourth metal layer, and the sacrificial layer, and peel off to obtain the interconnect structure;

[0023] The interconnect structure is subjected to heat treatment to obtain an ultra-wideband high-frequency interconnect structure.

[0024] In one possible implementation, the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer are removed, and a fourth metal layer is prepared by photolithography and pretreated to obtain the fourth metal layer, including:

[0025] Organic solvents were used to remove the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer;

[0026] A fourth metal layer is prepared on the surface where the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer have been removed, using the same photomask and first photoresist as the first photoresist defining layer, and then pretreated to obtain the fourth metal layer.

[0027] In one possible implementation, the undeveloped first photoresist layer, the seed layer not covered by the fourth metal layer, and the sacrificial layer are removed, and the interconnect structure is obtained by stripping, including:

[0028] All undeveloped first photoresist layers were removed using a photoresist remover.

[0029] The seed layer and sacrificial layer not covered by the fourth metal layer are removed sequentially using an etching solution, so that the interconnect structure is peeled off from the sacrificial layer.

[0030] In one possible implementation, the interconnect structure is heat-treated to obtain an ultra-wideband high-frequency interconnect structure, including:

[0031] The interconnect structure is subjected to vacuum heat treatment at 150-350℃ for 10-30 minutes to cause the ends of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer to naturally deform and bend under thermal stress.

[0032] In one possible implementation, the two ends of the third metal layer are serrated; the two ends of the ultra-wideband high-frequency interconnect structure have different dimensions, with one end being larger than the other.

[0033] This invention provides an ultra-wideband high-frequency interconnect structure and its fabrication method. The interconnect structure includes a bottom conductive layer, a deformable metal layer, and a bonding interconnect metal layer. Both ends of the bonding interconnect metal layer, both ends of the deformable metal layer, and both ends of the bottom conductive layer are bent towards the center of the upper surface of the bonding interconnect metal layer. This bending is a natural deformation caused by the difference in thermal stress between the first and second sub-metal layers. This interconnect structure is self-curling, exhibiting high strength and consistency as a semi-rigid interconnect. The two ends of the interconnect structure can be fixed to the desired interconnection location by spot welding. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1A This is a schematic diagram of the cross-sectional structure of the substrate provided in an embodiment of the present invention;

[0036] Figure 1B This is a top view of the substrate provided in an embodiment of the present invention;

[0037] Figure 2A This is a schematic cross-sectional view of the growth of a sacrificial layer and a seed layer on a substrate provided in an embodiment of the present invention;

[0038] Figure 2B This is a top view schematic diagram of the structure of a sacrificial layer and a seed layer grown on a substrate according to an embodiment of the present invention;

[0039] Figure 3A This is a schematic diagram of the cross-sectional structure of the first photoresist defining layer provided in an embodiment of the present invention;

[0040] Figure 3B This is a top view schematic diagram of the structure for forming the first photoresist defining layer provided in an embodiment of the present invention;

[0041] Figure 4A This is a schematic diagram of the cross-sectional structure of the first metal layer provided in an embodiment of the present invention;

[0042] Figure 4B This is a top view schematic diagram of the structure for growing the first metal layer provided in an embodiment of the present invention;

[0043] Figure 5A This is a schematic diagram of the cross-sectional structure of the first metal layer being thickened and pretreated according to an embodiment of the present invention;

[0044] Figure 5B This is a top view schematic diagram of the structure for thickening and pre-processing the first metal layer provided in an embodiment of the present invention;

[0045] Figure 6A This is a schematic diagram of the cross-sectional structure for preparing the second photoresist defining layer provided in an embodiment of the present invention;

[0046] Figure 6B This is a top view schematic diagram of the fabrication of the second photoresist defining layer provided in an embodiment of the present invention;

[0047] Figure 7A This is a schematic diagram of the cross-sectional structure for preparing the second metal layer provided in an embodiment of the present invention;

[0048] Figure 7B This is a top view schematic diagram of the fabrication structure of the second metal layer provided in an embodiment of the present invention;

[0049] Figure 8A This is a schematic diagram of the cross-sectional structure of the second metal layer being thickened and pretreated according to an embodiment of the present invention;

[0050] Figure 8B This is a top view schematic diagram of the structure for thickening and pre-processing the second metal layer provided in an embodiment of the present invention;

[0051] Figure 9A This is a schematic diagram of the cross-sectional structure for preparing the third photoresist defining layer provided in an embodiment of the present invention;

[0052] Figure 9B This is a top view schematic diagram of the fabrication of the third photoresist defining layer provided in an embodiment of the present invention;

[0053] Figure 10A This is a schematic diagram of the cross-sectional structure for preparing the third metal layer provided in an embodiment of the present invention;

[0054] Figure 10B This is a top view schematic diagram of the fabrication of the third metal layer provided in an embodiment of the present invention;

[0055] Figure 11A This is a schematic diagram of the cross-sectional structure of the positive photoresist removal provided in an embodiment of the present invention;

[0056] Figure 11B This is a top view schematic diagram of the structure for removing positive photoresist provided in an embodiment of the present invention;

[0057] Figure 12A This is a schematic diagram of the cross-sectional structure of the re-fabrication of the first photoresist provided in an embodiment of the present invention;

[0058] Figure 12B This is a top view schematic diagram of the re-fabrication of the first photoresist provided in an embodiment of the present invention;

[0059] Figure 13A This is a schematic diagram of the cross-sectional structure for preparing the fourth metal layer provided in an embodiment of the present invention;

[0060] Figure 13B This is a top view schematic diagram of the fabrication of the fourth metal layer provided in an embodiment of the present invention;

[0061] Figure 14A This is a schematic diagram of the cross-sectional structure after all photoresist has been removed, provided in an embodiment of the present invention.

[0062] Figure 14B This is a top view of the structure after all photoresist has been removed, as provided in an embodiment of the present invention.

[0063] Figure 15A This is a schematic cross-sectional view of the interconnect structure after stripping provided in an embodiment of the present invention;

[0064] Figure 15B This is a top view of the stripped interconnect structure provided in an embodiment of the present invention;

[0065] Figure 16A This is a schematic diagram of the cross-sectional structure of the ultra-wideband high-frequency interconnect structure finally formed after heat treatment according to an embodiment of the present invention;

[0066] Figure 16B This is a schematic diagram of the heat treatment self-curling structure of the ultra-wideband high-frequency interconnect structure provided in the embodiment of the present invention. Detailed Implementation

[0067] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0068] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0069] As described in the background section, port interconnects of RF chips introduce parasitic effects into the circuit. When using bonding interconnects, it's equivalent to introducing an inductance to ground, causing impedance bias and degrading characteristics. With the continuous development of high-frequency chips, spot-welded gold strip interconnects have emerged. This interconnect scheme can optimize port transmission characteristics by introducing additional capacitance to ground to adjust port impedance. Currently, for higher frequency applications such as the W-band, interconnect structures made of special gold strips stamped with one end smaller and the other larger, featuring a matching structure, have appeared. However, due to limitations in the fabrication method, this matching structure is only optimized for a few commonly used frequency bands such as 76-77GHz and 92-95GHz, resulting in poor band coverage. Furthermore, this gold strip is prone to deformation during use, leading to inconsistent port losses.

[0070] As the frequency of radio frequency (RF) circuits increases and the wavelength becomes shorter, the skin effect becomes more pronounced. The problems of inconsistent spatial distribution of bonded interconnects and increased chip transmission loss due to parasitic effects also become more prominent. While the effects of parasitic inductance can be mitigated in conventional K-band circuits by optimizing the number and shape distribution of bonding wires, higher frequency bands require additional capacitors for matching. Common methods include increasing port capacitance and using gold-band interconnects. However, matching in the 75-110GHz ultra-wideband range suffers significant damage; therefore, a new interconnect structure is urgently needed.

[0071] To address the problems of existing technologies, embodiments of the present invention provide an ultra-wideband high-frequency interconnect structure and its fabrication method. The fabrication method of the ultra-wideband high-frequency interconnect structure provided by the embodiments of the present invention will be described first below.

[0072] Step S110: Prepare a sacrificial layer and a seed layer on the surface of a substrate.

[0073] In some embodiments, such as Figure 1A and 1B As shown, substrate 10 can be a soluble substrate used as a temporary carrier. The thickness of substrate 10 can be selected according to pre-designed values, and it is necessary to ensure that substrate 10 will not warp during subsequent processing. In actual production, the production of large-size substrates using multiple unit arrays can improve production efficiency. This application only uses a single unit as an example for illustration. It should be noted that... Figure 1B The black line in the middle is the dividing line.

[0074] In some embodiments, the substrate 10 may be selected from substrates such as silicon wafers or sapphire.

[0075] like Figure 2A and 2B As shown, to facilitate the subsequent peeling of the substrate and the fabricated interconnect structure, a sacrificial layer 20 can be grown on the substrate 10. The sacrificial layer 20 can be removed using a stripping solution, thereby allowing the interconnect structure to be peeled off from the substrate 10.

[0076] In some embodiments, the sacrificial layer 20 may be an A1 layer.

[0077] In addition, to facilitate subsequent electroplating, a seed layer 30 needs to be prepared on the sacrificial layer. The typical structure of the seed layer 30 is TiW / Al / TiW / Au, with a total thickness of 50nm-5000nm. The deposition method of the seed layer 30 can be either physical vapor deposition (PVD) or chemical vapor deposition (CVD), which is not limited here.

[0078] Step S120: Coat a first photoresist layer on the seed layer and photolithographically prepare a first photoresist definition layer on the first photoresist layer.

[0079] like Figure 3A and 3B As shown, the first photoresist is coated onto the upper surface of the seed layer 30 by spin coating or hot pressing to form the first photoresist layer 40. Then, the developed pattern first photoresist definition layer 41 is obtained by photolithography processes such as exposure and development. Figure 3B The diagram shows a top view of the structure of the first photoresist defining layer 41, the pattern of which is used for subsequent fabrication of interconnect structures. Undeveloped first photoresist layers 40 are provided at both ends of the first photoresist defining layer 41.

[0080] In some embodiments, the first photoresist is a non-positive photoresist. The first photoresist can be a high-viscosity photoresist, such as the THB series negative photoresist from JSR Corporation. It can also be a high-resolution photosensitive dry film, such as the ST series dry film from DuPont Corporation. The thickness of the first photoresist layer is greater than 25 μm, the line resolution is less than 10 μm, and the sidewalls are steep after exposure.

[0081] In some embodiments, a matching structure can also be provided in the middle of the first photoresist definition layer to match the width to be connected. Figure 3B The window 43 in the middle is the broadband matching structure. 43 is an empty window, and the bottom layer inside this empty window is the seed layer 30.

[0082] Furthermore, to further achieve a match with the width, the two ends of the interconnect structure can be fabricated to different sizes, with one end smaller and the other larger.

[0083] Step S130: Grow the first metal on the first photoresist defining layer and perform pretreatment to obtain the first metal layer.

[0084] like Figure 4A-5B As shown, a first metal layer 42 can be formed by growing a first metal on the patterned surface of the first photoresist defining layer 41 using electrochemical deposition. The first metal layer 42 is then thickened to 10-20 μm. Finally, the coating surface can be thinned and surface-treated using two steps: grinding and chemical mechanical polishing, thereby obtaining a more precise metal layer thickness and a lower surface roughness, thus obtaining the first metal layer 42.

[0085] In some embodiments, the first metal can be gold, which can be electroplated using an electrochemical deposition method. During electroplating, a combination of pulse plating and DC plating is used to improve growth efficiency.

[0086] Step S140: Prepare a second positive photoresist layer on the first metal layer and the undeveloped first photoresist layer, and prepare a second photoresist definition layer on the second positive photoresist layer.

[0087] At both ends of the second photoresist defining layer, there are undeveloped second positive photoresist layers 50, wherein the length of the undeveloped second positive photoresist layer 50 is greater than the length of the undeveloped first photoresist layer 40.

[0088] like Figure 6A and 6B As shown, a second positive photoresist is applied to the first metal layer 42 and the undeveloped first photoresist layer 40 using a positive photoresist coating or hot-press coating method to form a second positive photoresist layer 50. Then, a second photoresist defining layer 51 is formed through standard photolithography processes such as exposure and development. The structure of the second photoresist defining layer 51 is the same as the pattern of the first photoresist defining layer 41. The second photoresist defining layer 51 is used to prepare one of the metal layers in the deformable metal layer.

[0089] Step S150: Grow a second metal on the second photoresist defining layer and perform pretreatment to obtain the second metal layer.

[0090] like Figures 7A-8B As shown, a second metal layer 52 can be formed by growing a second metal on the patterned surface of the second photoresist defining layer using electrochemical deposition. Then, the second metal layer 52 is thickened to 10-20 μm using electrochemical deposition again, serving as the first metal layer of the deformable metal layer, i.e., the gold strip support layer of the interconnect structure. Finally, the coating surface can be thinned and surface-treated using two steps: grinding and chemical mechanical polishing, thereby obtaining a higher precision metal layer thickness and a lower surface roughness, thus obtaining the second metal layer 52.

[0091] In some embodiments, the second metal can be nickel, and gold can be electroplated using an electrochemical deposition method. During electroplating, a combination of pulse plating and DC plating is used to improve growth efficiency.

[0092] Step S160: Prepare a third positive photoresist layer on the second metal layer and the undeveloped second positive photoresist layer, and prepare a third photoresist definition layer on the third positive photoresist layer.

[0093] Undeveloped third positive photoresist layers are provided at both ends of the third photoresist defining layer.

[0094] like Figure 9A and 9B As shown, a third positive photoresist layer is prepared by coating the second metal layer 52 and the undeveloped second positive photoresist layer 50 with a third positive photoresist by spin coating or hot pressing. Then, a third photoresist defining layer 60 is prepared by standard photolithography processes such as exposure and development. The third photoresist defining layer 60 is used to prepare another metal layer on the second metal layer 52. Figure 9B The middle one is the window 43, and the two sides are the serrated structures at both ends of the third metal layer that need to be prepared later, defined by the third photoresist defining layer 60.

[0095] It should be noted that the third positive photoresist, like the second positive photoresist, is a positive photoresist.

[0096] Step S170: Prepare a third metal layer on the third photoresist defining layer and perform pretreatment to obtain the third metal layer.

[0097] The thermal stress of the second metal layer 51 is different from that of the third metal layer 61.

[0098] like Figures 10A-10B As shown, a third metal layer 61 can be formed by growing a third metal on the patterned surface of the third photoresist defining layer 60 using electrochemical deposition. Then, the third metal layer 61 is thickened to 10-20 μm using another electrochemical deposition method, serving as the second metal layer in the deformation metal layer. Finally, the coating surface can be thinned and surface-treated using two steps: grinding and chemical mechanical polishing, achieving a tolerance of ±2 μm, thereby obtaining a more precise metal layer thickness and lower surface roughness, resulting in the third metal layer 61.

[0099] In some embodiments, the two ends of the third metal layer 61 can be fabricated in a serrated shape, which is related to the deformation of the final interconnect structure. The specific structure of the serrated shape at the two ends of the third metal layer 61 can be designed according to the final required curvature deformation.

[0100] In some embodiments, the third metal may be copper, and correspondingly, the third metal layer 61 is a copper layer. The second metal layer 52 and the third metal layer 61 constitute the deformable metal layer of the interconnect structure. During heat treatment, the copper layer and the nickel layer naturally deform and curl into the desired shape due to the stress difference between them.

[0101] In some embodiments, the final heat-treated curled pattern can be adjusted by adjusting the pattern width and thickness of the second metal layer 52 and the third metal layer 61, as well as the shape of the serrations at both ends of the third metal layer 61.

[0102] In some embodiments, more metal layers can be prepared based on the existing second metal layer 52 and third metal layer 61, and the number of deformable metal layers is not limited here. As long as the thermal stress between the multiple metal layers is different, natural deformation and curling will occur due to the stress during heat treatment.

[0103] Step S180: Remove the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer, and prepare the fourth metal layer by photolithography and perform pretreatment to obtain the fourth metal layer.

[0104] The two ends of the first metal layer are connected to the two ends of the fourth metal layer.

[0105] A fourth metal layer is fabricated on the third metal layer 61 as a bonding interconnect metal layer for the interconnect structure. The specific fabrication process is as follows:

[0106] Step S1801: Remove the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer using an organic solvent.

[0107] like Figure 11A-11B As shown, the undeveloped third positive photoresist layer 60 and the undeveloped second positive photoresist layer 50 are both positive photoresists, which can be selectively removed by ultrasonic means using organic solvents such as ethanol. However, the undeveloped first photoresist layer 40 cannot be peeled off.

[0108] Step S1802: Using the same photomask and first photoresist as the first photoresist defining layer, a fourth metal is prepared on the surface where the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer have been removed, and pretreatment is performed to obtain the fourth metal layer.

[0109] like Figure 12A-12B As shown, in order to cover the third metal layer 61 with a bonding interconnect metal layer, it is necessary to prepare another photoresist definition layer using the same photolithography method as in step S120 to define the electroplated gold pattern of the bonding interconnect metal layer. The first photoresist is also used in this process, and the same photomask is employed. An undeveloped photoresist layer 70 remains above the undeveloped first photoresist layer 40.

[0110] like Figures 13A-13B As shown, then, using the same method as in step S130, a fourth metal layer is formed on the pattern on the surface of the first photoresist defining layer. The fourth metal layer is then thickened to 10-20 μm. Finally, the coating surface is thinned and surface-treated using two steps: grinding and chemical mechanical polishing, to obtain a more precise metal layer thickness and lower surface roughness, resulting in the fourth metal layer 71. The fourth metal layer 71 is a bonded interconnect metal layer with an interconnect structure. The two ends of the fourth metal layer 71 are connected to the two ends of the first metal layer 42.

[0111] In some embodiments, both the fourth metal layer 71 and the first metal layer 42 are metal layers made of gold.

[0112] Step S190: Remove the sacrificial layer, the undeveloped first photoresist layer, and the seed layer not covered by the fourth metal layer, and peel off to obtain the interconnect structure.

[0113] like Figures 14A-14B As shown, after the fourth metal layer 71 is fabricated, a resist remover is used to remove all undeveloped first photoresist layers 40 and the undeveloped photoresist layer 70 from the last photolithography process. Figures 15A-15BAs shown, the seed layer 30 not covered by the fourth metal layer 71 and all of the sacrificial layers 20 are then removed sequentially using an etching solution, so that the interconnect structure is peeled off from the sacrificial layer.

[0114] Step S200: Perform heat treatment on the interconnect structure to obtain an ultra-wideband high-frequency interconnect structure.

[0115] Will Figure 15B The interconnect structure in the middle undergoes vacuum heat treatment at 150-350℃ for 10-30 minutes, such as... Figure 16A As shown, this allows the ends of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer to naturally deform and bend under thermal stress. Furthermore, the bonding strength between the first metal layer 42, the second metal layer 52, the third metal layer 61, and the fourth metal layer 71 can be increased during heat treatment. For example... Figure 16B As shown, the second metal layer 52 and the third metal layer 61 will deform according to a preset arc under structural stress. Finally, the interconnect structure, i.e., the composite gold strip, can be interconnected with the corresponding pads by spot welding. During the heat treatment process, the seed layer will fuse with the first metal layer 42, therefore, Figure 16A , Figure 16B The seed layer is not shown. The second metal layer 52 and the second metal layer 61 will also be fused together, therefore Figure 16A , Figure 16B No clear dividing line was observed in the middle.

[0116] The interconnect structure, namely the composite gold strip, fabricated using the method provided in this invention is a semi-rigid interconnect with high strength and simple assembly. The XY plane of this interconnect structure, i.e., the composite gold strip, is fabricated using semiconductor photolithography, allowing for the fabrication of matching patterns based on simulations to meet the requirements of low insertion loss interconnects in ultra-wideband applications. This invention is also suitable for millimeter-wave multi-chip module packaging, and can solve the low insertion loss interconnect problem for 75-110GHz ultra-wideband matching.

[0117] The interconnect structure prepared by this invention is self-curling, transforming the original flexible interconnect into a semi-rigid interconnect, resulting in higher strength and better consistency. The interconnect structure is prepared by a layered electroplating method, with the first metal layer and the fourth metal layer serving as conductive layers. The first metal layer is the bottom conductive layer, and the fourth metal layer is the bonding interconnect metal layer. The inner second and third metal layers form a deformable metal layer.

[0118] Furthermore, to achieve ultra-wideband matching and reduce parasitic effects, the width of the interconnect structure can be customized to facilitate matching of the chip interconnect ends with the chip pads. The width of the interconnect structure can be 50-150 μm, and the width of the interconnect end with the motherboard can be widened by 10-1000 μm. Matching is set according to simulation to achieve broadband matching in the DC-W band. The interconnect structure prepared by this invention, with one end smaller and the other larger, can achieve broadband matching and reduce parasitic inductance.

[0119] Secondly, the present invention also provides an ultra-wideband high-frequency interconnect structure, comprising a bottom conductive layer, a deformable metal layer, and a bonding interconnect metal layer stacked sequentially from bottom to top, wherein both ends of the bottom conductive layer are respectively connected to both ends of the bonding interconnect metal layer. The deformable metal layer includes at least one first sub-metal layer and at least one second sub-metal layer stacked together, wherein the thermal stresses of the first sub-metal layer and the second sub-metal layer are different. The two ends of the bonding interconnect metal layer, the two ends of the deformable metal layer, and the two ends of the bottom conductive layer all bend towards the middle position near the upper surface of the bonding interconnect metal layer, and this bending is a natural deformation formed based on the difference in thermal stress between the first sub-metal layer and the second sub-metal layer.

[0120] In some embodiments, to achieve broadband matching, a broadband-matching structure can also be fabricated on the interconnect structure, such as in... Figure 16B The window structure shown is a window prepared for broadband matching.

[0121] In some embodiments, in order to achieve broadband matching and reduce parasitic inductance, the two ends of the interconnect structure can be designed with different broadband, with one end having a larger size and the other end having a smaller size.

[0122] In some embodiments, in order to achieve a preset bending deformation, the two ends of the deformable metal layer can be set as serrated, and the serrated ends of the deformable metal layer are bent towards the middle position near the upper surface of the bonding interconnect metal layer during heat treatment.

[0123] In some embodiments, both the bonding interconnect metal layer and the underlying conductive layer are gold layers, the first sub-metal layer is a nickel layer, and the second sub-metal layer is a copper layer. Of course, depending on the actual application requirements, the deformable metal layer can be multi-layered and can be made of nickel, copper, or silver.

[0124] The following is still in the format of Figure 16ATaking an example, the ultra-wideband high-frequency interconnect structure includes a bottom conductive layer 42, a deformable metal layer, and a bonding interconnect metal layer 71. The deformable metal layer includes a first sub-metal layer 52 and a second sub-metal layer 61, and the thermal stresses of the first sub-metal layer 52 and the second sub-metal layer 61 are different. The two ends of the bonding interconnect metal layer 71, the two ends of the deformable metal layer, and the two ends of the bottom conductive layer 42 all bend towards the middle position near the upper surface of the bonding interconnect metal layer 71, and this bending is a natural deformation based on the difference in thermal stress between the first sub-metal layer 52 and the second sub-metal layer 61. The curvature of this deformation can be determined by the specific structure of the first sub-metal layer 52 and the second sub-metal layer 61 within the deformable metal layer, such as the width and thickness of the two sub-metal layers, and the serrations at both ends of the second sub-metal layer 61.

[0125] Ultra-wideband high-frequency interconnect structures can achieve broadband matching and reduce parasitic inductance through a structure with one small end and one large end. A windowed structure can also be incorporated in the middle of the interconnect structure to meet the interconnect requirements of ultra-wideband low insertion loss.

[0126] The interconnect structure prepared by this invention is self-curling, transforming the original flexible interconnect into a semi-rigid interconnect, resulting in higher strength and better consistency. The interconnect structure is prepared by a layered electroplating method, with the first metal layer and the fourth metal layer serving as conductive layers. The first metal layer is the bottom conductive layer, and the fourth metal layer is the bonding interconnect metal layer. The inner second and third metal layers form a deformable metal layer.

[0127] Furthermore, to achieve ultra-wideband matching and reduce parasitic effects, the width of the interconnect structure can be customized to facilitate matching of the chip interconnect ends with the chip pads. The width of the interconnect structure can be 50-150 μm, and the width of the interconnect end with the motherboard can be widened by 10-1000 μm. Matching is set according to simulation to achieve broadband matching in the DC-W band. The interconnect structure prepared by this invention, with one end smaller and the other larger, can achieve broadband matching and reduce parasitic inductance.

[0128] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0129] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating an ultra-wideband high-frequency interconnect structure, characterized in that, include: A sacrificial layer and a seed layer are prepared on the surface of a substrate, respectively. A first photoresist layer is coated on the seed layer and a first photoresist definition layer is formed on the first photoresist layer by photolithography. Undeveloped first photoresist layers are provided at both ends of the first photoresist definition layer. A first metal layer is obtained by growing a first metal on the first photoresist defining layer and performing pretreatment. A second positive photoresist layer is prepared on the first metal layer and the undeveloped first photoresist layer, and a second photoresist definition layer is prepared on the second positive photoresist layer. Undeveloped second positive photoresist layers are provided at both ends of the second photoresist definition layer, wherein the length of the undeveloped second positive photoresist layer is greater than the length of the undeveloped first photoresist layer. A second metal layer is obtained by growing a second metal on the second photoresist defining layer and performing pretreatment. A third positive photoresist layer is prepared on the second metal layer and the undeveloped second positive photoresist layer, and a third photoresist definition layer is prepared on the third positive photoresist layer. Undeveloped third positive photoresist layers are provided at both ends of the third photoresist definition layer. A third metal is prepared on the third photoresist defining layer and pretreated to obtain a third metal layer. The thermal stress of the second metal layer is different from that of the third metal layer. Remove the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer, and prepare the fourth metal layer by photolithography and perform pretreatment to obtain the fourth metal layer. The two ends of the first metal layer are connected to the two ends of the fourth metal layer. The sacrificial layer, the undeveloped first photoresist layer, and the seed layer not covered by the fourth metal layer are removed, and the interconnect structure is obtained by stripping. The interconnect structure is subjected to heat treatment to obtain the ultra-wideband high-frequency interconnect structure.

2. The preparation method according to claim 1, characterized in that, The process of removing the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer, and then photolithographically preparing the fourth metal layer and performing pretreatment to obtain the fourth metal layer includes: The undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer are removed using an organic solvent; A fourth metal layer is prepared on the surface after removing the undeveloped third positive photoresist layer and the undeveloped second positive photoresist layer using the same photomask and first photoresist as the first photoresist defining layer, and then pretreated to obtain the fourth metal layer.

3. The preparation method according to claim 1, characterized in that, The process of removing the sacrificial layer, the undeveloped first photoresist layer, and the seed layer not covered by the fourth metal layer, and then peeling off the interconnect structure, includes: All undeveloped first photoresist layers were removed using a photoresist remover. The seed layer and the sacrificial layer, which are not covered by the fourth metal layer, are removed sequentially using an etching solution, so that the interconnect structure is peeled off from the sacrificial layer.

4. The preparation method according to claim 1, characterized in that, The process of heat-treating the interconnect structure to obtain the ultra-wideband high-frequency interconnect structure includes: The interconnect structure is subjected to vacuum heat treatment at 150-350°C for 10-30 minutes to cause the ends of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer to naturally deform and bend under thermal stress.

5. The preparation method according to any one of claims 1 to 4, characterized in that, The two ends of the third metal layer are serrated; the two ends of the ultra-wideband high-frequency interconnect structure are different in size, with one end being larger than the other.

6. An ultra-wideband high-frequency interconnect structure, characterized in that, The method according to any one of claims 1-5 is used to prepare the material, which includes a bottom conductive layer, a deformable metal layer and a bonding interconnect metal layer stacked sequentially from bottom to top, wherein the two ends of the bottom conductive layer are respectively connected to the two ends of the bonding interconnect metal layer; wherein the bottom conductive layer is a first metal layer, the deformable metal layer includes a second metal layer and a third metal layer, and the bonding interconnect metal layer includes a fourth metal layer. The deformable metal layer includes at least one first sub-metal layer and at least one second sub-metal layer stacked together, and the thermal stresses of the first sub-metal layer and the second sub-metal layer are different; wherein, the at least one first sub-metal layer is the second metal layer, and the at least one second sub-metal layer is the third metal layer; Both ends of the bonding interconnect metal layer, both ends of the deformable metal layer, and both ends of the bottom conductive layer are bent toward the middle position near the upper surface of the bonding interconnect metal layer, and this bending is a natural deformation based on the difference in thermal stress between the first sub-metal layer and the second sub-metal layer.

7. The ultra-wideband high-frequency interconnect structure as described in claim 6, characterized in that, The deformable metal layer is also provided with a matching structure that matches the broadband at a preset position.

8. The ultra-wideband high-frequency interconnect structure as described in claim 6 or 7, characterized in that, Both the bonding interconnect metal layer and the bottom conductive layer are gold layers; the first sub-metal layer is a nickel layer, and the second sub-metal layer is a copper layer.

9. The ultra-wideband high-frequency interconnect structure as described in claim 6 or 7, characterized in that, The two ends of the third metal layer are serrated, and the serrated ends of the third metal layer are bent towards the middle position near the upper surface of the bonding interconnect metal layer during heat treatment.

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