A gallium oxide field effect transistor and a method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a gallium oxide field effect transistor and a preparation method thereof. The preparation method comprises the following steps: preparing photoresist on the surface of an n-type gallium oxide channel layer, a source electrode and a metal mask, then performing baking and reflow treatment on the photoresist to form a photoresist inclined surface; vertically injecting elements on the photoresist inclined surface to form an ion injection area which is longitudinally distributed in a trapezoidal shape in the n-type gallium oxide channel layer; preparing a gate dielectric on the n-type gallium oxide channel layer between the source electrode and the drain electrode; and preparing a gate electrode on the gate dielectric corresponding to the ion injection area, thereby obtaining the gallium oxide field effect transistor. The application has the advantages of simple process, good controllability, a larger range of the included angle of the prepared photoresist inclined surface, deeper ion injection depth and lower on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a gallium oxide field-effect transistor and its fabrication method. Background Technology

[0002] Ultra-wide bandgap power electronic devices, represented by gallium oxide (GaN), have gradually become an important development area in power semiconductor devices in recent years, and are expected to replace traditional Si-based power devices in certain specific fields. As a novel semiconductor material, ultra-wide bandgap gallium oxide (GaN) has significant advantages in breakdown field strength, Baliga figure of merit, and cost. Internationally, the Baliga figure of merit (~Eb3) is commonly used to characterize the suitability of a material for power devices. For example, the Baliga figure of merit of β-Ga2O3 is 4 times that of GaN, 10 times that of SiC, and 3444 times that of Si. Under the same breakdown voltage conditions, β-Ga2O3 power devices exhibit lower on-resistance and lower power consumption than GaN and SiC devices, significantly reducing power loss during device operation.

[0003] Since the National Institute of Information and Communications Technology (NICT) of Japan developed the first gallium oxide metal-oxide-semiconductor field-effect transistor (Ga2O3 MOSFET) device in 2013, researchers have continuously improved the performance of Ga2O3 MOSFET devices by enhancing the quality of Ga2O3 crystal materials and optimizing device fabrication processes, including optimizing channel layer doping, ohmic and Schottky contact processes, and gate field plate structures. In 2016, NICT used Al2O3 as the under-gate dielectric and combined it with a gate field plate structure to fabricate a Ga2O3 MOSFET device with a breakdown voltage of 750V.

[0004] However, the breakdown voltage and conduction characteristics of existing Ga2O3 field-effect transistor (FET) devices still need improvement. Furthermore, the fabrication process of existing Ga2O3 FETs is cumbersome, has poor controllability, requires highly sophisticated ion implanters, and suffers from shallow ion implantation depths, high on-resistance, and significant power loss. Summary of the Invention

[0005] To address the above technical problems, this invention provides a gallium oxide field-effect transistor and its fabrication method. This method can effectively improve the average breakdown field strength of the gallium oxide transistor. The fabrication method of this invention has the advantages of simple process, good controllability, a wider range of photoresist bevel angles, deeper ion implantation depth, lower on-resistance, lower power consumption, and can greatly reduce the power loss during device operation.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for fabricating a gallium oxide field-effect transistor, comprising:

[0008] An n-type gallium oxide channel layer is grown on the substrate;

[0009] Source and drain electrodes are fabricated on the n-type gallium oxide channel layer;

[0010] A metal mask is prepared on the surface of the n-type gallium oxide channel layer and the drain electrode;

[0011] Photoresist is prepared on the surfaces of the n-type gallium oxide channel layer, the source electrode, and the metal mask. The photoresist is then baked and reflowed to form a photoresist bevel.

[0012] Elements are vertically implanted onto the beveled surface of the photoresist to form ion implantation regions that are longitudinally trapezoidally distributed within the n-type gallium oxide channel layer;

[0013] A gate dielectric is fabricated on the n-type gallium oxide channel layer between the source electrode and the drain electrode;

[0014] A gate electrode is fabricated on the gate dielectric corresponding to the ion implantation region to obtain a gallium oxide field-effect transistor.

[0015] In conjunction with the first aspect, in some possible implementations, the baking and reflow treatment of the photoresist includes: baking the photoresist on the n-type gallium oxide channel layer, source electrode and metal mask surface at 80-90°C for the first time, evaporating, exposing and developing, and removing the photoresist on the metal mask; then baking the remaining photoresist a second time at a rate of 10-15°C / min to raise the temperature to 130-150°C, so that the edges of the remaining photoresist reflow and form a photoresist slope.

[0016] In conjunction with the first aspect, in some possible implementations, the first baking time is 1-10 minutes; the second baking time is 1-15 minutes.

[0017] Only by selecting the above-mentioned baking and reflow process parameters can the photoresist bevel be prepared according to the present invention.

[0018] In conjunction with the first aspect, in some possible implementations, the angle between the bevel of the photoresist and the horizontal plane is 10-80 degrees.

[0019] The photoresist prepared by this invention has a larger bevel angle range and a deeper ion implantation depth, which can achieve a lower on-resistance.

[0020] In conjunction with the first aspect, in some possible implementations, the implanted element in the ion implantation region is any one or more of B, Mg, N, He, and H. This implanted element acts as an acceptor in gallium oxide, thereby depleting the carriers within the n-type gallium oxide channel. The dose of the implanted element is 1E12-1E20; the implantation energy is 1-200 keV. This dose and energy allow the element to distribute deeper within the n-type gallium oxide channel layer, fully depleting the carriers and resulting in lower on-resistance in this region, thus improving the device's breakdown characteristics.

[0021] Secondly, the present invention also provides a gallium oxide field-effect transistor obtained by the above-described fabrication method, comprising a substrate, an n-type gallium oxide channel layer disposed on the substrate, a source electrode and a drain electrode disposed on the n-type gallium oxide channel layer, a gate dielectric disposed between the source electrode and the drain electrode, a gate electrode disposed on the gate dielectric, and an ion implantation region disposed in the n-type gallium oxide channel layer below the gate electrode; the depth of the ion implantation region gradually increases from the end near the source electrode to the end near the drain electrode; wherein the ion implantation region is longitudinally trapezoidally distributed within the n-type gallium oxide channel layer.

[0022] In conjunction with the second aspect, in some possible implementations, the longitudinal section of the ion implantation region is a right-angled triangle, wherein the angle between the hypotenuse of the right-angled triangle and the horizontal plane is 10-80 degrees, indicating that the implanted ions are implanted at a deeper depth, which can achieve lower on-resistance, greatly reduce power loss during device operation, eliminate peak electric fields, and improve breakdown resistance.

[0023] In conjunction with the second aspect, in some possible implementations, the right-angled triangle has its right-angled sides perpendicular to the surface of the n-type gallium oxide channel layer.

[0024] In conjunction with the second aspect, in some possible implementations, the maximum depth of the ion implantation region is less than that of the n-type gallium oxide channel layer, the thickness of which is 10 nm-1000 nm.

[0025] In conjunction with the second aspect, in some possible implementations, the length of the gate electrode is ≥50nm and ≤10μm.

[0026] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0027] The preparation method of the present invention has the advantages of simple process, good controllability, larger range of photoresist bevel angle, deeper ion implantation depth, and the ion implantation depth gradually increases from the end near the source electrode to the end near the drain electrode, which can achieve lower on-resistance, lower power consumption, and greatly reduce the power loss of the device during operation.

[0028] This fabrication method precisely controls the baking and reflow processes of the photoresist to form a photoresist bevel as the photolithographic pattern. The area protected by the metal mask is not implanted with elements; the photoresist bevel acts as a mask during the element implantation process. The photoresist bevel is gradually removed, and the implanted elements continue to enter the n-type gallium oxide channel layer beneath the photoresist bevel mask. In the n-type gallium oxide channel layer, ion implantation regions are formed that are symmetrical to the photoresist bevel and have a longitudinally trapezoidal distribution. The depth of the ion implantation regions gradually increases from the end closer to the source electrode to the end closer to the drain electrode to significantly reduce on-resistance, thereby greatly reducing power loss during device operation, eliminating peak electric fields, and improving breakdown performance. The gallium oxide field-effect transistors fabricated using this method have low power loss and good breakdown performance, making them suitable for high-voltage applications.

[0029] In existing transistors, a high peak field strength exists at the gate-to-drain region (gate-to-drain region), leading to reduced device breakdown characteristics. The gallium oxide field-effect transistor of this invention utilizes a vertically trapezoidal ion implantation technique to reduce the carrier concentration in the n-type gallium oxide channel layer beneath the gate electrode, thereby lowering the peak field strength in the gate-to-drain region and improving breakdown characteristics. The vertically trapezoidal ion region ensures that the implanted elements penetrate deeper into the gate electrode towards the drain end, achieving lower high-pass resistance and reducing power loss compared to non-stepped ion implantation.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the fabrication process of the gallium oxide field-effect transistor of the present invention.

[0032] Figure 2 This is a schematic diagram of the preparation of an n-type gallium oxide channel layer on a substrate according to the present invention.

[0033] Figure 3 This is a schematic diagram of the fabrication of source and drain electrodes on an n-type gallium oxide channel layer according to the present invention.

[0034] Figure 4 This is a schematic diagram of the process for preparing the metal mask according to the present invention.

[0035] Figure 5 This is a schematic diagram of the process for preparing the photoresist bevel in this invention.

[0036] Figure 6 This is a schematic diagram of the ion implantation region located in the n-type gallium oxide channel layer of the present invention.

[0037] Figure 7 This is a schematic diagram of the structure for preparing the gate dielectric according to the present invention.

[0038] Figure 8 This is a schematic cross-sectional view of the gallium oxide field-effect transistor of the present invention.

[0039] In the above figures, 1 is the substrate, 2 is the n-type gallium oxide channel layer, 3 is the source electrode, 4 is the drain electrode, 5 is the ion implantation region, 6 is the gate dielectric, and 7 is the gate electrode. Detailed Implementation

[0040] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0041] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0042] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0043] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0045] Figure 1 This is a flowchart illustrating the fabrication of a gallium oxide field-effect transistor according to the present invention.

[0046] The specific preparation method is as follows:

[0047] Step 101: An n-type gallium oxide channel layer 2 is epitaxially grown on substrate 1.

[0048] For example, Figure 2 This is a schematic diagram of the preparation of an n-type gallium oxide channel layer on a substrate according to the present invention.

[0049] In some embodiments, substrate 1 may be a high-resistivity gallium oxide substrate, a semi-insulating SiC substrate, magnesium oxide, sapphire substrate, etc.

[0050] For example, the doping element in the n-type gallium oxide channel layer 2 is achieved by doping with elements such as Si or Sn, with a doping concentration of 1.0 × 10⁻⁶. 15 cm -3 -1.0×10 20 cm -3 The thickness of the n-type gallium oxide channel layer ranges from 10 nm to 1000 nm.

[0051] In some possible embodiments, before epitaxially growing the n-type gallium oxide channel layer 2 on the substrate 1, an undoped gallium oxide layer may be grown on the substrate as a buffer layer to prevent impurity ions in the semi-insulating substrate from entering the channel layer, and then the n-type gallium oxide channel layer 2 is epitaxially grown on the undoped gallium oxide layer.

[0052] Step 102: The source electrode 3 and the drain electrode 4 are fabricated on the above-mentioned n-type gallium oxide channel layer by electron beam evaporation.

[0053] For example, Figure 3 This is a schematic diagram of the fabrication of source and drain electrodes on an n-type gallium oxide channel layer according to the present invention.

[0054] In some embodiments, before depositing the source electrode 3 and the drain electrode 4, in order to achieve good ohmic contact between the source electrode 3 and the drain electrode 4, n-type ion implantation can be performed at a predetermined position in the channel layer below the source electrode 3 and the drain electrode 4 in the n-type gallium oxide channel layer 2 to form n+ regions in the predetermined regions of the source electrode 3 and the drain electrode 4, respectively. Then, the source electrode 3 and the drain electrode 4 are deposited in the n+ regions (i.e., heavily doped regions, which are regions where the number of doped elements is greater than that of the epitaxial n-type gallium oxide channel layer. The more doped elements, the lower the resistance and the easier it is to form ohmic contact) at both ends of the channel layer, thereby achieving ohmic contact.

[0055] For example, the deposition of source electrode 3 and drain electrode 4 is achieved by electron beam evaporation, and the deposited metal is Ti / Au or Ti / Al / Ni / Au.

[0056] Step 103: Prepare a metal mask on the surface of the n-type gallium oxide channel layer and the drain electrode.

[0057] For example, Figure 4This is a schematic diagram of the process for preparing the metal mask according to the present invention.

[0058] from Figure 4 As can be seen, firstly, a layer of photoresist is coated on the surface of the n-type gallium oxide channel layer 2, the source electrode 3 and the drain electrode 4, and photolithography and development are performed to prepare the required photolithographic pattern; then, an electron beam evaporation method is used to deposit a Ti / Ni layer (thickness should be greater than 10nm and less than 5000nm) as a metal mask on the drain electrode 4 and part of the n-type gallium oxide channel layer 2, and then the photoresist and the metal mask on its surface are stripped away.

[0059] Step 104: Apply a layer of photoresist to the surface of the n-type gallium oxide channel layer 2, the source electrode 3 and the metal mask, and perform photolithography and development to prepare the required photolithographic pattern; then bake and reflow the photoresist to form a slope on one side of the metal mask.

[0060] For example, Figure 5 This is a schematic diagram of the process for preparing the right-angled triangular photoresist according to the present invention;

[0061] like Figure 5 As shown, specifically: the photoresist on the n-type gallium oxide channel layer 2, source electrode 3, and metal mask surface is first baked at 80-100℃ for 1-10 minutes, followed by evaporation, exposure, and development to remove the photoresist from the metal mask; then, the temperature is increased to no more than 150℃ at a rate of 10-15℃ / min, and the remaining photoresist is baked a second time for 1-15 minutes, causing the edges of the remaining photoresist to reflow and form a slope, preventing deformation of the metal mask. The angle between the photoresist slope and the horizontal plane is 10-80 degrees.

[0062] Step 105: Vertically implant elements onto the inclined surface of the photoresist to obtain ion implantation regions 5 with a longitudinal trapezoidal distribution within the n-type gallium oxide channel layer 2.

[0063] In some embodiments, the implanted element can be B, Mg, N, He, H, etc., which acts as acceptor in gallium oxide, thereby depleting the carriers in the channel. The dose of the implanted element is 1E12-1E20; the implantation energy is 1-200 keV. The area protected by the metal mask will not be implanted with elements. The beveled photoresist serves as a mask during the ion implantation process. Due to the strong physical particle bombardment effect of the implanted element, the photoresist molecules will continuously undergo chemical reactions or be removed by physical bombardment during the element implantation process, so that the beveled portion of the photoresist is gradually removed, and ions continue to enter the channel layer under the photoresist mask, thereby forming a right-angled triangular ion implantation region 5 in the n-type gallium oxide channel layer.

[0064] For example, Figure 6 This is a schematic diagram of the ion implantation region located in the n-type gallium oxide channel layer of the present invention.

[0065] from Figure 6 It can be seen that the depth of the ion implantation region gradually increases from the end closer to the source electrode to the end closer to the drain electrode. The longitudinal section of the ion implantation region is a right-angled triangle (basically symmetrical to the shape of the original photoresist on its surface), wherein the angle between the hypotenuse of the right-angled triangle and the horizontal plane is 10-80 degrees, and the right-angled side of the right-angled triangle is perpendicular to the surface of the n-type gallium oxide channel layer. The maximum depth of the ion implantation region is less than that of the n-type gallium oxide channel layer.

[0066] Step 106: A gate dielectric 6 with a thickness of 10-100 nm is grown on the surface of the n-type gallium oxide channel layer 2 between the source electrode 3 and the drain electrode 4 using atomic layer deposition.

[0067] In some embodiments, the atomic layer deposition temperature is 300-500°C; the gate dielectric is alumina or hafnium oxide, and the thickness of the gate dielectric is 10-100 nm.

[0068] Figure 7 This is a schematic diagram of the structure for preparing the gate dielectric according to the present invention.

[0069] Step 107: The gate electrode 7 is fabricated on the gate dielectric 6 corresponding to the ion implantation region 5 using electron beam evaporation, thus obtaining the gallium oxide field-effect transistor.

[0070] In some embodiments, the gate length is ≥50nm and ≤10μm, and the deposited metal is Ni / Au or Pt / Au.

[0071] For example, Figure 8 This is a schematic cross-sectional view of the gallium oxide field-effect transistor of the present invention.

[0072] from Figure 8 As can be seen, a gallium oxide field-effect transistor includes a substrate 1, an n-type gallium oxide channel layer 2 disposed on the substrate 1, a source electrode 3 and a drain electrode 4 disposed on the n-type gallium oxide channel layer 2, a gate dielectric 6 disposed between the source electrode and the drain electrode, a gate electrode 7 disposed on the gate dielectric 6, and an ion implantation region 5 disposed in the n-type gallium oxide channel layer below the gate electrode; wherein, the depth of the ion implantation region 5 gradually increases from the end near the source electrode 3 to the end near the drain electrode 4; the ion implantation region 5 is longitudinally trapezoidally distributed in the n-type gallium oxide channel layer.

[0073] The fabrication method of this invention features simple process, good controllability, lower requirements for ion implanters, a wider range of angles in the beveled right-angled triangles that can be fabricated, deeper ion implantation depth, lower on-resistance, and lower power consumption, significantly reducing power loss during device operation. This fabrication method forms a photoresist bevel as a photolithographic pattern by precisely controlling the baking and reflow processes of the photoresist. The area protected by the metal mask is not implanted with elements; the photoresist bevel acts as a mask during the element implantation process. The photoresist bevel is gradually removed, and the implanted elements continue to enter the n-type gallium oxide channel layer under the photoresist bevel mask, forming an ion implantation region in the n-type gallium oxide channel layer that is symmetrical to the photoresist bevel and has a longitudinally trapezoidal distribution. The depth of the ion implantation region gradually increases from the end near the source electrode to the end near the drain electrode to significantly reduce on-resistance, greatly reducing power loss during device operation, eliminating peak electric fields, and improving breakdown performance. The gallium oxide field-effect transistors prepared by this method have low power loss and good breakdown resistance, making them suitable for high-voltage applications.

[0074] Corresponding to the gallium oxide field-effect transistor fabrication method of the above embodiments, the present invention also provides a gallium oxide field-effect transistor, which is fabricated using the gallium oxide field-effect transistor fabrication method of any of the above embodiments, and has the beneficial effects of operating the gallium oxide field-effect transistor fabrication method of any of the above embodiments.

[0075] In some embodiments, the gallium oxide field-effect transistor provided by this invention uses a vertically trapezoidal ion implantation technique to reduce the carrier concentration in the n-type gallium oxide channel layer under the gate electrode, thereby reducing the peak field strength in the gate bias drain region and improving breakdown characteristics. The vertically trapezoidal ion region ensures that the implanted elements are deeper towards the drain end of the gate electrode, achieving a lower high-pass resistance and reducing energy loss compared to non-stepped ion implantation.

[0076] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a gallium oxide field-effect transistor, characterized in that, include: An n-type gallium oxide channel layer is grown on the substrate; Source and drain electrodes are fabricated on the n-type gallium oxide channel layer; A metal mask is prepared on the surface of the n-type gallium oxide channel layer and the drain electrode; Photoresist is prepared on the surfaces of the n-type gallium oxide channel layer, the source electrode, and the metal mask. The photoresist is then baked and reflowed to form a photoresist bevel. Elements are vertically implanted into the photoresist bevel to form ion implantation regions that are longitudinally trapezoidally distributed within the n-type gallium oxide channel layer; A gate dielectric is fabricated on the n-type gallium oxide channel layer between the source electrode and the drain electrode; A gate electrode is fabricated on the gate dielectric corresponding to the ion implantation region to obtain a gallium oxide field-effect transistor. The photoresist baking and reflow process includes: baking the photoresist on the n-type gallium oxide channel layer, source electrode and metal mask surface at 80-100°C for the first time, evaporating, exposing and developing, and removing the photoresist on the metal mask; then baking the remaining photoresist a second time at a rate of 10-15°C / min to a temperature not exceeding 150°C, so that the edges of the remaining photoresist reflow to form a photoresist bevel; The gallium oxide field-effect transistor includes: a substrate, an n-type gallium oxide channel layer disposed on the substrate, a source electrode and a drain electrode disposed on the n-type gallium oxide channel layer, a gate dielectric disposed between the source electrode and the drain electrode, a gate electrode disposed on the gate dielectric, and an ion implantation region disposed in the n-type gallium oxide channel layer below the gate electrode. The depth of the ion implantation region gradually increases from the end near the source electrode to the end near the drain electrode; wherein the ion implantation region is longitudinally trapezoidally distributed within the n-type gallium oxide channel layer.

2. The preparation method according to claim 1, characterized in that, The first baking time is 1-10 minutes; and / or The second baking time is 1-15 minutes.

3. The preparation method according to claim 1, characterized in that, The angle between the inclined plane of the photoresist and the horizontal plane is 10-80 degrees.

4. The preparation method according to claim 1, characterized in that, The implanted element in the ion implantation region is any one or more of B, Mg, N, He and H, and the dose of the implanted element is 1E12-1E20; the implantation energy is 1-200keV.

5. The gallium oxide field-effect transistor obtained by the preparation method according to any one of claims 1-4, characterized in that, include: A substrate, an n-type gallium oxide channel layer disposed on the substrate, a source electrode and a drain electrode disposed on the n-type gallium oxide channel layer, a gate dielectric disposed between the source electrode and the drain electrode, a gate electrode disposed on the gate dielectric, and an ion implantation region disposed in the n-type gallium oxide channel layer below the gate electrode; characterized in that: The depth of the ion implantation region gradually increases from the end near the source electrode to the end near the drain electrode; wherein the ion implantation region is longitudinally trapezoidally distributed within the n-type gallium oxide channel layer.

6. The gallium oxide field-effect transistor according to claim 5, characterized in that, The longitudinal section of the ion implantation region is a right triangle, wherein the angle between the hypotenuse of the right triangle and the horizontal plane is 10-80 degrees, and the right-angled side of the right triangle is perpendicular to the surface of the n-type gallium oxide channel layer.

7. The gallium oxide field-effect transistor according to any one of claims 5-6, characterized in that, The maximum depth of the ion implantation region is less than that of the n-type gallium oxide channel layer, and the thickness of the n-type gallium oxide channel layer is 10 nm-1000 nm.

8. The gallium oxide field-effect transistor according to claim 6, characterized in that, The length of the gate electrode is ≥50nm and ≤10μm.

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