Through-silicon via structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor devices, and discloses a through-silicon via structure and a preparation method thereof. The through-silicon via structure comprises a semiconductor substrate, a first cavity arranged on the semiconductor substrate along a preset direction, a second cavity arranged outside the first cavity along the preset direction and spaced from the first cavity, a conductive layer filled in the first cavity, and a first insulating medium layer filled in the second cavity. In the embodiment, the first cavity and the second cavity are spaced, and when the temperature rises, the influence caused by the deformation and internal stress change of the semiconductor layer will be concentrated in the semiconductor substrate between the first cavity and the second cavity, so that the deformation and cracks of the semiconductor substrate outside the second cavity caused by the large thermal expansion coefficient adaptation are reduced or avoided, the thermal mechanical reliability is improved, and the electrical performance of the through-silicon via structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to through-silicon via (TSV) structures and their fabrication methods. Background Technology

[0002] Through Silicon Via (TSV) technology is a feasible method for achieving 3D wafer-level packaging (WLP) and 3D integration. In 3D chip stacking technology, TSV technology has attracted much attention, as it provides a method for achieving high-performance interconnect integration. Currently, the mainstream filling method for TSVs or blind vias is copper (Cu) electroplating. However, during reliability verification, due to the significant mismatch in the coefficients of thermal expansion (CTE) between the Cu material and the silicon substrate, the deformation degrees of the two materials differ greatly when the temperature rises. This leads to a large difference in internal stress, which can easily cause deformation or cracking of the silicon substrate, thus affecting the reliability and electrical performance of the TSV structure. Summary of the Invention

[0003] In view of this, the present invention provides a through-silicon via (TSV) structure and its fabrication method to solve the problem that the reliability and electrical performance of TSV structures are affected by the large mismatch in the coefficients of thermal expansion between copper materials and dielectric substrates.

[0004] In a first aspect, the present invention provides a through-silicon via (TSV) structure, the TSV structure comprising:

[0005] A semiconductor substrate; a first cavity disposed on the semiconductor substrate along a preset direction; a conductive layer filling the first cavity; a second cavity disposed around the outside of the first cavity and disposed on the semiconductor substrate along a preset direction, the first cavity and the second cavity being spaced apart; and a first insulating dielectric layer filling the second cavity.

[0006] The through-silicon via (TSV) structure provided in this embodiment includes a semiconductor substrate, a first cavity disposed on the semiconductor substrate along a predetermined direction, a second cavity disposed around the outside of the first cavity along a predetermined direction and spaced apart from the first cavity, a conductive layer filled in the first cavity, and a first insulating dielectric layer filled in the second cavity. By spaced the first and second cavities, this embodiment concentrates the effects of deformation and internal stress changes in the semiconductor layer when the temperature rises into the semiconductor substrate between the first and second cavities. This reduces or avoids deformation and cracks in the semiconductor substrate outside the second cavity caused by a large thermal expansion coefficient mismatch, improves thermomechanical reliability, and enhances the electrical performance of the TSV structure.

[0007] In one alternative embodiment, the through-silicon via structure further includes:

[0008] The third cavity is located between the first cavity and the second cavity, and the first cavity, the second cavity and the third cavity are spaced apart; the second insulating dielectric layer is filled in the third cavity.

[0009] This embodiment adds a third cavity between the first cavity and the second cavity, and fills the third cavity with a second insulating dielectric layer. This not only improves the insulation of the through-silicon via structure, but also buffers the compression of the surrounding semiconductor substrate caused by the large thermal expansion coefficient between the materials through the two semiconductor substrates between the three cavities, thereby further improving the reliability and electrical performance of the through-silicon via structure.

[0010] In one alternative implementation, the structure further includes:

[0011] A third insulating dielectric layer is laid between the first cavity and the conductive layer. The first surface of the third insulating dielectric layer is in close contact with the surface of the first cavity, and the second surface of the third insulating dielectric layer is in close contact with the first surface of the conductive layer.

[0012] In one alternative implementation, the conductive layer is made of copper.

[0013] In one alternative embodiment, the material of the first insulating dielectric layer is one or more of silicon oxide, silicon nitride, and polymer.

[0014] In one alternative implementation, the first cavity is a cylindrical cavity, and the second and third cavities are both annular cavities.

[0015] Secondly, the present invention provides a method for preparing a through-silicon via structure, the method comprising:

[0016] A semiconductor substrate is provided; a second cavity is formed on the semiconductor substrate along a preset direction; an insulating material is filled into the second cavity until the second cavity is completely filled and the insulating material covers the first surface of the semiconductor substrate, at which point the filling operation ends, forming a first insulating dielectric layer; a first cavity is formed on the semiconductor substrate along a preset direction, and a second cavity is disposed around the outside of the first cavity, with the first cavity and the second cavity spaced apart; a conductive material is filled into the first cavity until the conductive material completely fills the first cavity, at which point the filling operation ends, forming a conductive layer; the conductive layer is subjected to chemical mechanical planarization treatment so that the surface of the conductive layer is flush with the surface of the first insulating dielectric layer away from the semiconductor substrate, resulting in a through-silicon via (TSV) structure.

[0017] The method for fabricating a through-silicon via (TSV) structure provided in this embodiment involves spaced first and second cavities on a semiconductor substrate. A semiconductor layer is formed by filling the first cavity with semiconductor material, and a first insulating dielectric layer is formed by filling the second cavity with insulating material. This concentrates the effects of deformation and internal stress changes in the semiconductor layer on temperature rise within the semiconductor substrate between the first and second cavities. This reduces deformation and cracking of the semiconductor substrate outside the second cavity, improves thermomechanical reliability, and enhances the electrical performance of the TSV structure.

[0018] In an alternative embodiment, before filling the first cavity with conductive material, the method further includes:

[0019] A seed layer of a predetermined thickness is sputtered in the first cavity.

[0020] In one optional embodiment, a first cavity is formed on a semiconductor substrate along a predetermined direction, including:

[0021] A windowing process is performed in a first target area on the surface of the first insulating dielectric layer to obtain a first windowed area. The first target area is the area corresponding to the cross section of the second cavity and the semiconductor substrate, and the first windowed area is a sub-region of the first target area.

[0022] In the first window area, the first cavity is etched out along a preset direction.

[0023] In one optional embodiment, after performing a windowing process in a first target area on the surface of the first insulating dielectric layer to obtain the first windowed area, the method further includes:

[0024] In the first window area, a third cavity is formed on the semiconductor substrate along a preset direction, and the third cavity is spaced apart from the second cavity;

[0025] The third cavity is filled with insulating material until the surface of the insulating material is flush with the surface of the first insulating dielectric layer away from the semiconductor substrate. The filling operation is then stopped to form the second insulating dielectric layer.

[0026] A windowing process is performed on the second target region on the surface of the second insulating dielectric layer to obtain a second windowed region. The second target region is the region corresponding to the cross section of the third cavity and the semiconductor substrate, and the second windowed region is a sub-region of the second target region.

[0027] In the second window area, the first cavity is etched out along a preset direction. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a cross-sectional schematic diagram of a traditional through-silicon via (TSV) structure;

[0030] Figure 2 This is a top view of a traditional through-silicon via (TSV) structure;

[0031] Figure 3 This is a schematic cross-sectional view of a semiconductor substrate according to an embodiment of the present invention;

[0032] Figure 4 This is a schematic cross-sectional view of a semiconductor substrate having a second cavity according to an embodiment of the present invention;

[0033] Figure 5 This is a schematic cross-sectional view of a semiconductor substrate after the first insulating dielectric layer has been filled, according to an embodiment of the present invention.

[0034] Figure 6 This is a cross-sectional schematic diagram of the semiconductor substrate after the windowing operation according to an embodiment of the present invention;

[0035] Figure 7 This is a schematic cross-sectional view of a semiconductor substrate having a first cavity according to an embodiment of the present invention;

[0036] Figure 8 This is a schematic cross-sectional view of a semiconductor substrate after the semiconductor layer has been filled, according to an embodiment of the present invention.

[0037] Figure 9 This is a cross-sectional schematic diagram of a through-silicon via structure according to an embodiment of the present invention;

[0038] Figure 10 This is a top view schematic diagram of a through-silicon via structure according to an embodiment of the present invention;

[0039] Figure 11 This is a schematic cross-sectional view of a semiconductor substrate after sputtering a seed layer according to another embodiment of the present invention;

[0040] Figure 12 This is a cross-sectional schematic diagram of a through-silicon via structure according to another embodiment of the present invention;

[0041] Figure 13 This is a cross-sectional view of a semiconductor substrate having a third cavity according to another embodiment of the present invention;

[0042] Figure 14 This is a cross-sectional view of a semiconductor substrate after filling with a second insulating dielectric layer according to another embodiment of the present invention;

[0043] Figure 15 This is a cross-sectional view of a semiconductor substrate after the first cavity has been etched following filling with a second insulating dielectric layer, according to yet another embodiment of the present invention.

[0044] Figure 16 This is a cross-sectional schematic diagram of a through-silicon via structure according to another embodiment of the present invention;

[0045] Figure 17 This is a top view schematic diagram of a through-silicon via structure according to another embodiment of the present invention;

[0046] Figure 18 This is a cross-sectional schematic diagram of a through-silicon via structure according to another embodiment of the present invention;

[0047] Figure 19 This is a top view schematic diagram of a through-silicon via structure according to another embodiment of the present invention. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the drawings, not all structures. In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if one layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component can be "below" that other layer / component.

[0049] The coefficient of thermal expansion affects the degree of deformation and internal thermal stress of a material. Therefore, in traditional through-silicon via (TSV) structures, when the temperature rises, the large mismatch in the coefficients of thermal expansion (CTE) between the copper material and the dielectric substrate silicon material causes different degrees of deformation in both materials. This results in a large difference in internal thermal stress, which in turn leads to deformation or cracking of the substrate silicon material, thus degrading the reliability and electrical performance of the TSV structure.

[0050] Figure 1 This is a cross-sectional view of the current through-silicon via (TSV) structure. Figure 2 This is a top view of the current through-silicon via (TSV) structure. (Summary) Figure 1 and Figure 2 As can be seen, in the current through-silicon via (TSV) structure, the conductive material copper 30 and the insulating material silicon oxide 20 are in direct contact. Due to the large mismatch in the coefficients of thermal expansion between the conductive material copper 30 and the insulating material silicon oxide 20, and also between the conductive material copper 30 and the substrate silicon material 10, when the temperature rises, the difference between the degree of deformation and the internal stress generated by the inner conductive material copper 30 and the degree of deformation and the internal stress generated by the outer insulating material silicon oxide 20 is significant. Therefore, the difference in the degree of deformation and the difference in internal stress can easily lead to compression of the substrate silicon material 10, causing deformation or cracks in the substrate silicon material 10, thereby affecting the reliability and electrical performance of the TSV structure.

[0051] To avoid the above-mentioned defects, embodiments of the present invention provide a through-silicon via (TSV) structure and its fabrication method. By alternating the conductive and insulating materials, the influence caused by the large mismatch in the coefficients of thermal expansion between the two materials is concentrated on the substrate silicon material between the conductive and insulating materials. This reduces or avoids the compression of the peripheral substrate silicon material, thereby reducing or avoiding the deformation and cracks caused to the semiconductor substrate outside the second cavity due to the large mismatch in the coefficients of thermal expansion, thus improving the reliability and electrical performance of the TSV structure.

[0052] This embodiment provides a method for fabricating a through-silicon via (TSV) structure, the specific fabrication process of which is as follows:

[0053] Provide sectional views such as Figure 3 The semiconductor substrate 100 shown can be a silicon substrate, but is not limited to it. For example, the semiconductor substrate 100 can also be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG), etc.

[0054] like Figure 4As shown, a second cavity 200 is etched on the semiconductor substrate 100 along a predetermined direction. The predetermined direction is perpendicular to the upper surface of the semiconductor substrate 100 and points towards the lower surface of the semiconductor substrate 100; for example, the predetermined direction can be vertical. The second cavity 200 can be, for example, an annular cavity. This annular cavity can be a circular ring-shaped cavity or a square ring-shaped cavity. The specific spatial shape of the second cavity 200 is not limited here; those skilled in the art can choose according to the actual situation. Figure 4 The image shows a cross-sectional view of the semiconductor substrate 100 after etching the annular second cavity 200. When the second cavity is annular, in this embodiment, the diameter of the outer ring of the annular cavity is set in the range of 5-30 μm in the specific through-silicon via (TSV) structure, the distance between the inner and outer rings of the annular cavity is set to 0.5 μm, and the depth of the second cavity is set to 50-200 μm. It should be noted that the depth of the annular cavity must be less than the depth of the semiconductor substrate.

[0055] like Figure 5 As shown, insulating material is injected into the second cavity 200. When the insulating material completely fills the second cavity 200, the injection of insulating material continues until it overflows from the second cavity 200 and extends outwards, until the insulating material completely covers the upper surface of the semiconductor substrate 100. The filling operation of the insulating material is then completed to form the first insulating dielectric layer 300. Therefore, the first insulating dielectric layer 300 comprises two parts: the portion filled within the second cavity 200 and the portion covering the upper surface of the semiconductor substrate 100. After forming the first insulating dielectric layer 300, the following can be obtained: Figure 5 The diagram shows a cross-sectional view of the semiconductor substrate 100. The insulating material can be one or more of silicon dioxide, silicon nitride, or a polymer.

[0056] A windowing process is performed on a first target region on the upper surface of the first insulating dielectric layer 300 (i.e., the surface facing away from the semiconductor substrate 100) to obtain a first windowed region. The first target region is the cross-sectional area formed by the second cavity 200 and the semiconductor substrate 100, and the first windowed region is a sub-region of the first target region. Figure 6 As shown, if the second cavity 200 is annular, then the first target region is the area covered by a circle with diameter L1 on the upper surface of the first insulating dielectric layer 300. The first window region can be any region with the same center as the first target region. For example, if the first target region is a circle, then the first window region can be an area covered by any polygon whose center coincides with the center of the circle, or it can be an area covered by a circle with the same center as the first target region within the first target region, or it can be any annular region whose center coincides with the center of the circle, such as a circle, a square ring, etc.

[0057] When the first window area is a polygonal or circular region whose center coincides with the center of the first target area, after determining the first window area, the first cavity 400 is etched along a preset direction, using the first window area as the aperture of the first cavity 400. The first cavity 400 can be a cylinder surrounded by a second cavity 200. Clearly, the cross-sectional shape of the first cavity 400 corresponds to the shape of the first window area. For example... Figure 7 The diagram shows a cross-sectional view of the semiconductor substrate 100 after etching the first cavity 400. The preset direction used for etching the first cavity 400 is consistent with the preset direction used for etching the second cavity 200, and the first cavity 400 and the second cavity 200 are spaced apart, with the second cavity 200 surrounding the outside of the first cavity 400. It should also be emphasized that the depth of the first cavity 400 and the depth of the second cavity 200 are consistent and both are less than the depth of the semiconductor substrate 100.

[0058] Conductive material is filled into the first cavity 400 until the cavity is completely filled, at which point the filling operation ends, forming a conductive layer 500. Figure 8 The diagram shows a cross-sectional view of the semiconductor substrate 100 after the first cavity 400 is filled with conductive material. The conductive material can be any highly conductive metal, such as copper, which is highly conductive but inexpensive, to improve conductivity and reduce costs.

[0059] The conductive layer 500 is subjected to chemical mechanical planarization to make its upper surface flush with the upper surface of the first insulating dielectric layer 300 (i.e., the surface facing away from the semiconductor substrate 100), thereby obtaining a cross-sectional view as shown below. Figure 9 As shown, the top view is as follows Figure 10 The silicon through-hole structure is shown. The chemical mechanical planarization process can be polishing; however, the specific planarization method is not limited here, and those skilled in the art can choose any feasible approach.

[0060] The through-silicon via (TSV) structure obtained by the fabrication method provided in this embodiment includes a semiconductor substrate, a first cavity disposed on the semiconductor substrate along a predetermined direction, a second cavity disposed around the outside of the first cavity along a predetermined direction and spaced apart from the first cavity, a conductive layer filling the first cavity, and a first insulating dielectric layer filling the second cavity. By spaced the first cavity and the second cavity, when the temperature rises, the effects of deformation and internal stress changes in the semiconductor layer are concentrated in the semiconductor substrate between the first and second cavities. This reduces or avoids deformation and cracks in the semiconductor substrate outside the second cavity caused by a large thermal expansion coefficient mismatch, improves thermomechanical reliability, and enhances the electrical performance of the TSV structure. In another optional embodiment, the fabrication method of the TSV structure further includes the following steps:

[0061] After etching of the first cavity 400 is completed, a seed layer 600 of a predetermined thickness is sputtered into the inner wall of the first cavity 400. The seed layer 600 can be made of titanium (0.3-0.5 μm) or copper (0.8-2.6 μm). The choice of the predetermined thickness depends on the material used for the seed layer 600. Figure 11 The image shown is a cross-sectional view of the semiconductor substrate 100 obtained after sputtering the seed layer 600 in the first cavity 400.

[0062] Then, conductive material is filled into the cavity formed by the seed layer until the cavity is completely filled, forming a conductive layer 500. The upper surface of the conductive layer 500 is then chemically and mechanically planarized to make it flush with the upper surface of the first insulating dielectric layer 300, thus obtaining a cross-sectional view as shown below. Figure 12 The through-silicon via (TSV) structure is shown.

[0063] This embodiment improves the adhesion and conductivity between the conductive layer and the first insulating dielectric layer by sputtering a seed layer.

[0064] In yet another alternative embodiment, after the step described in the previous embodiment, "when a windowing process is performed in a first target region on the upper surface of the first insulating dielectric layer 300 (i.e., the surface facing away from the semiconductor substrate 100 to obtain a first windowed region)," the method for fabricating a through-silicon via structure further includes the following steps:

[0065] First, when the first windowed area is an annular region whose center coincides with the center of the first target area, the third cavity 700, spaced apart from the second cavity 200, is etched along a preset direction, using the first windowed area as the aperture of the third cavity 700. The third cavity 700 is an annular cavity surrounded by the second cavity. The resulting cross-sectional view is shown below. Figure 13 The semiconductor substrate 100 is shown, and an insulating material is filled into the third cavity 700 until the second insulating dielectric layer 800 completely fills the third cavity 700 and the upper surface of the second insulating dielectric layer 800 is flush with the upper surface of the first insulating dielectric layer 300, resulting in a cross-sectional view as shown. Figure 14 The semiconductor substrate 100 is shown. The insulating material used in the second insulating dielectric layer 800 may be the same as or different from the insulating material used in the first insulating dielectric layer 300. Furthermore, it should be noted that the upper surface of the second insulating dielectric layer 800 is flush with the upper surface of the first insulating dielectric layer 300.

[0066] Then, as Figure 15As shown, a windowing process is performed in the second target region on the upper surface of the second insulating dielectric layer 800 to obtain the second windowed region. The second target region is the cross-sectional area formed by the third cavity 700 and the semiconductor substrate 100 (i.e., the first windowed region), and the second windowed region is a sub-region of the second target region. It should be noted that the second windowed region and the second target region have the same center.

[0067] Finally, using the second window area as the etching area, the first cavity is etched along a predetermined direction, and conductive material is filled into the first cavity to form a conductive layer. The surface of the conductive layer is then subjected to chemical mechanical planarization treatment to obtain a through-silicon via (TSV) structure. When the second target area is directly used as the second window area, a cross-sectional view can be obtained as shown below. Figure 16 As shown, the top view is as follows Figure 17 The through-silicon via (TSV) structure is shown.

[0068] This embodiment adds a third cavity between the first cavity and the second cavity, and fills the third cavity with a second insulating dielectric layer. This not only improves the insulation of the through-silicon via structure, but also buffers the compression of the surrounding semiconductor substrate caused by the large thermal expansion coefficient between the materials through the two semiconductor substrates between the three cavities, thereby further improving the reliability and electrical performance of the through-silicon via structure.

[0069] In yet another alternative embodiment, after etching the first cavity on the semiconductor substrate, the method further includes:

[0070] An insulating material is laid in the first cavity to form a third insulating dielectric layer 900 of a specified thickness on the inner wall of the first cavity. Then, a conductive material is filled into the cavity formed by the third insulating dielectric layer 900 to form a conductive layer 500. This results in a cross-sectional view as shown below. Figure 18 As shown, the top view is as follows Figure 19 The through-silicon via (TSV) structure is shown.

[0071] This embodiment does not specifically limit the thickness of the third insulating dielectric layer; those skilled in the art can determine it based on the degree of mismatch in the coefficients of thermal expansion between the conductive and insulating materials. In the description of this specification, the terms "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0072] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0073] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0074] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0075] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A through-silicon via (TSV) structure, characterized in that, The through-silicon via structure includes: Semiconductor substrate; A first cavity is disposed on the semiconductor substrate along a preset direction, wherein the preset direction is perpendicular to the upper surface of the semiconductor substrate and points to the lower surface of the semiconductor substrate; A conductive layer is filled into the first cavity; The second cavity is disposed around the outside of the first cavity and is disposed on the semiconductor substrate along the preset direction; the first cavity and the second cavity are disposed at intervals. A first insulating dielectric layer is filled into the second cavity; A third cavity is located between the first cavity and the second cavity, and the first cavity, the second cavity and the third cavity are spaced apart; A second insulating dielectric layer is filled into the third cavity.

2. The structure according to claim 1, characterized in that, The structure also includes: A third insulating dielectric layer is laid between the first cavity and the conductive layer, with the first surface of the third insulating dielectric layer in close contact with the surface of the first cavity and the second surface of the third insulating dielectric layer in close contact with the first surface of the conductive layer.

3. The structure according to claim 1 or 2, characterized in that, The conductive layer is made of copper.

4. The structure according to claim 3, characterized in that, The material of the first insulating dielectric layer is one or more of silicon oxide, silicon nitride, and polymer.

5. The structure according to claim 1, characterized in that, The first cavity is a cylindrical cavity, and the second and third cavities are both annular cavities.

6. A method for preparing a through-silicon via (TSV) structure, characterized in that, The method includes: Provide semiconductor substrates; A second cavity is formed on the semiconductor substrate along a preset direction, wherein the preset direction is perpendicular to the upper surface of the semiconductor substrate and points to the lower surface of the semiconductor substrate; The second cavity is filled with insulating material until the second cavity is completely filled and the insulating material covers the first surface of the semiconductor substrate, at which point the filling operation ends and a first insulating dielectric layer is formed. A first cavity is formed on the semiconductor substrate along the preset direction, and a second cavity is disposed around the outside of the first cavity, with the first cavity and the second cavity being spaced apart. A third cavity is formed on the semiconductor substrate along the preset direction, and the third cavity is spaced apart from the second cavity; The third cavity is filled with insulating material until the surface of the insulating material is flush with the surface of the first insulating dielectric layer away from the semiconductor substrate. The filling operation is then stopped to form the second insulating dielectric layer. The first cavity is filled with conductive material until the conductive material completely fills the first cavity, thus forming a conductive layer. The conductive layer is subjected to chemical mechanical planarization to make the surface of the conductive layer flush with the surface of the first insulating dielectric layer away from the semiconductor substrate, thereby obtaining a through-silicon via structure.

7. The method according to claim 6, characterized in that, Before filling the first cavity with conductive material, the method further includes: A seed layer of a predetermined thickness is sputtered in the first cavity.

8. The method according to claim 6, characterized in that, The process of forming a first cavity on the semiconductor substrate along the preset direction includes: A windowing process is performed in a first target area on the surface of the first insulating dielectric layer to obtain a first windowed area. The first target area is the area corresponding to the cross section of the second cavity and the semiconductor substrate. The first windowed area is a sub-region of the first target area. In the first window area, the first cavity is etched out along the preset direction.

9. The method according to claim 8, characterized in that, After performing a windowing process in a first target area on the surface of the first insulating dielectric layer to obtain the first windowed area, the method further includes: In the first windowed area, a third cavity is formed on the semiconductor substrate along the preset direction; A windowing process is performed on the second target area on the surface of the second insulating dielectric layer to obtain a second windowed area. The second target area is the area corresponding to the cross section of the third cavity and the semiconductor substrate, and the second windowed area is a sub-region of the second target area. In the second window area, the first cavity is etched out along the preset direction.

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