Test structures and methods of forming and testing the same

Abstract

A test structure and a method for forming and testing the same, the test structure comprising: a first pad array located on one side of the plurality of devices under test, the first pad array comprising a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group being arranged along a second direction, the second direction being perpendicular to the first direction, the first pad group comprising a plurality of first signal pads arranged along the first direction, the second pad group comprising a plurality of second signal pads and ground pads arranged along the first direction, each of the second signal pads being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged obliquely with respect to the first direction, and adjacent first signal pads and ground pads being arranged obliquely with respect to the first direction, one ground pad being shared by two or three devices under test, thereby reducing the area of the test structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to test structures, their formation methods, and testing methods. Background Technology

[0002] In recent years, CMOS technology has been applied in radio frequency microwave circuits within integrated circuits. To ensure product effectiveness, it is necessary to measure the performance of the device under test (DUT). Therefore, a test structure needs to be designed on the wafer to measure the DUT. The test structure includes pads, the DUT, and metal interconnects. Probes are connected to the DUT via pads, and the pads are connected to the DUT via metal interconnects.

[0003] The layout of test pads must be determined based on the probe type and the spacing between probes, such as GS, GSG, and GSGSG pad tests, where G stands for Ground and S stands for Signal. The GSG structure is a planar waveguide and is the most commonly used structure. However, in devices such as inductors, MOS devices, MOM capacitors, resistors, diodes, and varactor diodes, the existing GSG structure pads occupy a large area, which is detrimental to device circuit integration.

[0004] Therefore, the existing GSG testing structure needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a test structure and its formation method, as well as a test method, to improve the integration of device circuits.

[0006] To address the aforementioned technical problems, the present invention provides a test structure comprising: a plurality of devices under test (DUTs) arranged along a first direction; a first pad array located on one side of the plurality of DUTs, the first pad array comprising a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group being arranged along a second direction perpendicular to the first direction, the first pad group comprising a plurality of first signal pads arranged along the first direction, the second pad group comprising a plurality of second signal pads and ground pads arranged along the first direction, each second signal pad being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads being arranged at an angle relative to the first direction; and a second pad array located on the other side of the plurality of DUTs, the first pad array and the second pad array being centrally symmetrically distributed.

[0007] Optionally, the plurality of devices under test may include at least five devices under test.

[0008] Optionally, the angle between adjacent first signal pads and second signal pads relative to the first direction is 60 degrees; the angle between adjacent first signal pads and the ground pad relative to the first direction is 60 degrees.

[0009] Optionally, along the first direction, the distance between adjacent first signal pads, and between the second signal pad and the adjacent ground pad, ranges from 50µm to 1000µm.

[0010] Optionally, the width of the first signal pad, the second signal pad, and the ground pad ranges from 20µm to 200µm.

[0011] Accordingly, the technical solution of the present invention provides a method for forming a test structure, comprising: providing a plurality of devices under test (DUTs) arranged along a first direction; forming a first pad array located on one side of the plurality of DUTs, the first pad array including a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group being arranged along a second direction, the second direction being perpendicular to the first direction, the first pad group including a plurality of first signal pads arranged along the first direction, the second pad group including a plurality of second signal pads and ground pads arranged along the first direction, each second signal pad being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads being arranged at an angle relative to the first direction; forming a second pad array located on the other side of the plurality of DUTs, the first pad array and the second pad array being centrally symmetrically distributed.

[0012] Optionally, the plurality of devices under test may include at least five devices under test.

[0013] Optionally, the angle between adjacent first signal pads and second signal pads relative to the first direction is 60 degrees; the angle between adjacent first signal pads and the ground pad relative to the first direction is 60 degrees.

[0014] Optionally, along the first direction, the distance between adjacent first signal pads, and between the second signal pad and the adjacent ground pad, ranges from 50µm to 1000µm.

[0015] Optionally, the width of the first signal pad, the second signal pad, and the ground pad ranges from 20µm to 200µm.

[0016] Accordingly, the technical solution of the present invention provides a testing method, comprising: providing a test structure, the test structure comprising: a plurality of devices under test (DUTs) arranged along a first direction; a first pad array located on one side of the plurality of DUTs, the first pad array comprising a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group being arranged along a second direction, the second direction being perpendicular to the first direction, the first pad group comprising a plurality of first signal pads arranged along the first direction, the second pad group comprising a plurality of second signal pads and ground pads arranged along the first direction, each second signal pad being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads being arranged at an angle relative to the first direction; a second pad array located on the other side of the plurality of DUTs, the first pad array and the second pad array being centrally symmetrically distributed; placing a first probe on the first pad array and a second probe on the second pad array, such that the first probe and the second probe are respectively connected to each DUT, and testing the connected DUTs.

[0017] Optionally, the test structure further includes: the plurality of devices under test includes at least five devices under test.

[0018] Optionally, the test structure includes: the adjacent first signal pad and the second signal pad are tilted at an angle of 60 degrees relative to the first direction; the adjacent first signal pad and the ground pad are tilted at an angle of 60 degrees relative to the first direction.

[0019] Optionally, the test structure includes a distance ranging from 50µm to 1000µm between adjacent first signal pads and between the second signal pad and adjacent ground pad along the first direction.

[0020] Optionally, the width of the first signal pad, the second signal pad, and the ground pad ranges from 20µm to 200µm.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] In a test structure provided by the present invention, a first pad array is located on one side of a plurality of devices under test (DUTs). The first pad array includes a first pad group and a second pad group located on both sides of the first pad group. The first pad group and the second pad group are arranged along a second direction, which is perpendicular to the first direction. The first pad group includes a plurality of first signal pads arranged along the first direction, and the second pad group includes a plurality of second signal pads and ground pads arranged along the first direction. Each second signal pad is located between adjacent ground pads. Adjacent first signal pads and second signal pads are arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads are arranged at an angle relative to the first direction. In use, one ground pad is shared by two or three DUTs, reducing the number of pads and significantly reducing the area of ​​the test structure, which is beneficial for improving the integration of the circuit. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a test structure;

[0024] Figure 2 This is a schematic diagram of another test structure;

[0025] Figure 3 and Figure 4 This is a schematic diagram of each step in the test structure formation method in the embodiments of the present invention. Detailed Implementation

[0026] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0027] As described in the background section, existing GSG testing structures need further improvement. A detailed explanation of one such testing structure is provided below.

[0028] Figure 1 This is a schematic diagram of a test structure.

[0029] Please refer to Figure 1 The test structure includes six pads, comprising a first array and a second array arranged along a first direction X. The first array includes a first ground pad 101, a second ground pad 102, and a first signal pad 103 arranged along a second direction Y. The first signal pad 103 is located between the first ground pad 101 and the second ground pad 102. The second array includes a third ground pad 104, a fourth ground pad 105, and a second signal pad 106 arranged along the second direction Y. The second signal pad 106 is located between the third ground pad 104 and the fourth ground pad 105.

[0030] In use, the above test structure places the device under test (DUT) 107 between the first signal pad 103 and the second signal pad 106. The first ground pad 101, the second ground pad 102, and the first signal pad 103 are connected to one port via a first set of probes 11, and the first ground pad 101, the second ground pad 102, and the first signal pad 103 are connected to another port via a second set of probes 12. Along the first direction X, the size of the DUT 107 typically ranges from 4µm to 20µm, while the size of a single pad is 50µm × 50µm. The spacing between adjacent pads along the second direction Y is 100µm. This test structure occupies a large area, which is detrimental to the integration of device circuits.

[0031] In another embodiment, two adjacent devices under test share a single grounding pad; please refer to [reference needed]. Figure 2 .

[0032] Figure 2 This is a schematic diagram of another test structure.

[0033] Please refer to Figure 2 The test structure includes several test units arranged along a first direction X. Each test unit includes a first array and a second array arranged along a second direction. The first array includes a first ground pad 201, a second ground pad 202, and a first signal pad 203 arranged along the second direction Y. The first signal pad 203 is located between the first ground pad 201 and the second ground pad 202. The second array includes a third ground pad 204, a fourth ground pad 205, and a second signal pad 206 arranged along the second direction Y. The second signal pad 206 is located between the third ground pad 204 and the fourth ground pad 205. Adjacent test units share the first ground pad 201 and the second ground pad 202 or the third ground pad 204 and the fourth ground pad 205.

[0034] In the above structure, two adjacent devices under test share a grounding pad. If there are N devices under test in a column, 4*N+2 pads are needed, and the area of ​​the test structure is still very large.

[0035] To address the aforementioned technical problem, embodiments of the present invention provide a test structure and its formation method. In the test method, a first pad array is located on one side of the plurality of devices under test (DUTs). The first pad array includes a first pad group and second pad groups located on both sides of the first pad group. The first pad group and the second pad group are arranged along a second direction, which is perpendicular to the first direction. The first pad group includes a plurality of first signal pads arranged along the first direction, and the second pad group includes a plurality of second signal pads and ground pads arranged along the first direction. Each second signal pad is located between adjacent ground pads. Adjacent first signal pads and second signal pads are arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads are arranged at an angle relative to the first direction. In use, one ground pad is shared by two or three DUTs, reducing the number of solder pads and significantly reducing the area of ​​the test structure, which is beneficial for improving circuit integration.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 3 to 4 This is a schematic diagram of each step in the test structure formation method in the embodiments of the present invention.

[0038] Please refer to Figure 3 A plurality of devices under test 301 are provided, and the plurality of devices under test 301 are arranged along a first direction X.

[0039] The plurality of devices under test 301 includes at least five devices under test. In this embodiment, the plurality of devices under test 301 includes device under test DUT1, device under test DUT2, device under test DUT3, device under test DUT4, and device under test DUT5.

[0040] The plurality of devices under test 301 can be inductors, MOS devices, MOM capacitors, resistors, diodes, and varactor diodes, etc. In this embodiment, the plurality of devices under test 301 are inductors.

[0041] Please refer to Figure 4A first pad array is formed on one side of the plurality of devices under test 301. The first pad array includes a first pad group 302 and a second pad group 303 located on both sides of the first pad group 302. The first pad group 302 and the second pad group 303 are arranged along a second direction Y, which is perpendicular to the first direction X. The first pad group 302 includes a plurality of first signal pads S1 arranged along the first direction X. The second pad group 303 includes a plurality of second signal pads S2 and ground pads G arranged along the first direction X. Each second signal pad S2 is located between adjacent ground pads G. Adjacent first signal pads S1 and second signal pads S2 are arranged at an angle relative to the first direction X. Adjacent first signal pads S1 and ground pads G are arranged at an angle relative to the first direction X. A second pad array is formed on the other side of the plurality of devices under test 301. The first pad array and the second pad array are centrally symmetrically distributed.

[0042] In use, the grounding pad G of the formed test structure is shared by two or three devices under test, which reduces the number of pads and greatly reduces the area of ​​the test structure, thus improving the integration of the circuit.

[0043] In this embodiment, the tilt angle between adjacent first signal pad S1 and second signal pad S2 and the first direction is 60 degrees; the tilt angle between adjacent first signal pad S1 and ground pad G and the first direction X is 60 degrees.

[0044] Along the first direction X, the distance Pp between adjacent first signal pads S1, the distance Pp between the second signal pad S2 and the adjacent ground pad G all range from 50µm to 1000µm. In this embodiment, the value of Pp is 100µm.

[0045] The width Lp of the first signal pad S1, the second signal pad S2, and the ground pad G ranges from 20µm to 200µm. In this embodiment, the Lp value is 80µm.

[0046] The distance Dp between the edge of the first pad array and the edge of the second pad array ranges from 100µm to 1000µm. In this embodiment, the Dp value is 400µm.

[0047] Accordingly, this invention also provides a test structure formed by the above-described method. Please refer to [the documentation for further details]. Figure 4The device includes: a plurality of devices under test (DUTs) 301 arranged along a first direction X; a first pad array located on one side of the plurality of DUTs 301, the first pad array including a first pad group 302 and a second pad group 303 located on both sides of the first pad group 302, the first pad group 302 and the second pad group 303 being arranged along a second direction Y, the second direction Y being perpendicular to the first direction X, the first pad group 302 including a plurality of first signal pads S1 arranged along the first direction X, the second pad group 303 including a plurality of second signal pads S2 and ground pads G arranged along the first direction X, each second signal pad S2 being located between adjacent ground pads G, adjacent first signal pads S1 and second signal pads S2 being arranged at an angle relative to the first direction X, and adjacent first signal pads S1 and ground pads G being arranged at an angle relative to the first direction X; and a second pad array located on the other side of the plurality of DUTs 301, the first pad array and the second pad array being centrally symmetrically distributed.

[0048] In use, one grounding pad G of the test structure is shared by two or three devices under test, which reduces the number of pads and greatly reduces the area of ​​the test structure, thus improving the integration of the circuit.

[0049] The plurality of devices under test (DUTs) includes at least five DUTs. In this embodiment, the plurality of DUTs 301 includes DUT1, DUT2, DUT3, DUT4, and DUT5.

[0050] The plurality of devices under test 301 can be inductors, MOS devices, MOM capacitors, resistors, diodes, and varactor diodes, etc. In this embodiment, the plurality of devices under test 301 are inductors.

[0051] When the test structure is in use, the first probe is placed on the first pad array and the second probe is placed on the second pad array, so that the first probe and the second probe are respectively connected to each device under test, and the connected devices under test are tested.

[0052] In this embodiment, specifically, the first probe is placed on each pad in region I and the second probe is placed on each pad in region I' to test the device under test (DUT1); the first probe is placed on each pad in region II and the second probe is placed on each pad in region II' to test the device under test (DUT2); the first probe is placed on each pad in region III and the second probe is placed on each pad in region III' to test the device under test (DUT3); the first probe is placed on each pad in region IV and the second probe is placed on each pad in region IV' to test the device under test (DUT4); and the first probe is placed on each pad in region V and the second probe is placed on each pad in region V' to test the device under test (DUT5). It should be noted that when testing Device Under Test (DUT3) and DUT4, the wafer needs to be rotated 60 degrees clockwise relative to the wafer position when testing DUT1 (DUT2) to facilitate testing of DUT3 and DUT4; when testing DUT5, the wafer needs to be rotated 60 degrees counterclockwise relative to the wafer position when testing DUT1 (DUT2) to facilitate testing of DUT5.

[0053] The adjacent first signal pad S1 and the second signal pad S2 are tilted at an angle of 60 degrees relative to the first direction; the adjacent first signal pad S1 and the ground pad G are tilted at an angle of 60 degrees relative to the first direction X.

[0054] Along the first direction X, the distance Pp between adjacent first signal pads S1, the distance Pp between the second signal pad S2 and the adjacent ground pad G all range from 50µm to 1000µm. In this embodiment, the value of Pp is 100µm.

[0055] The width Lp of the first signal pad S1, the second signal pad S2, and the ground pad G ranges from 20µm to 200µm. In this embodiment, the Lp value is 80µm.

[0056] Accordingly, another embodiment of the present invention also provides a test method using the above-described test structure; please refer to [the relevant documentation]. Figure 4The test structure includes: a plurality of devices under test (DUTs) 301 arranged along a first direction X; a first pad array located on one side of the plurality of DUTs 301, the first pad array including a first pad group 302 and a second pad group 303 located on both sides of the first pad group 302, the first pad group 302 and the second pad group 303 being arranged along a second direction Y, the second direction Y being perpendicular to the first direction X, the first pad group 302 including a plurality of first signal pads S1 arranged along the first direction X, and the second pad group 303 including a plurality of second signal pads S2 and a ground pad G arranged along the first direction X. Each of the second signal pads S2 is located between adjacent ground pads G. Adjacent first signal pads S1 and second signal pads S2 are arranged at an angle relative to the first direction X. Adjacent first signal pads S1 and ground pads G are arranged at an angle relative to the first direction X. A second pad array is located on the other side of the plurality of devices under test 301. The first pad array and the second pad array are centrally symmetrically distributed. A first probe is placed on the first pad array, and a second probe is placed on the second pad array, so that the first probe and the second probe are respectively connected to each device under test, and the connected devices under test are tested.

[0057] In this embodiment, specifically, the first probe is placed on each pad in region I and the second probe is placed on each pad in region I' to test the device under test (DUT1); the first probe is placed on each pad in region II and the second probe is placed on each pad in region II' to test the device under test (DUT2); the first probe is placed on each pad in region III and the second probe is placed on each pad in region III' to test the device under test (DUT3); the first probe is placed on each pad in region IV and the second probe is placed on each pad in region IV' to test the device under test (DUT4); and the first probe is placed on each pad in region V and the second probe is placed on each pad in region V' to test the device under test (DUT5). It should be noted that when testing Device Under Test (DUT3) and DUT4, the wafer needs to be rotated 60 degrees clockwise relative to the wafer position when testing DUT1 (DUT2) to facilitate testing of DUT3 and DUT4; when testing DUT5, the wafer needs to be rotated 60 degrees counterclockwise relative to the wafer position when testing DUT1 (DUT2) to facilitate testing of DUT5.

[0058] The plurality of devices under test (DUTs) includes at least five DUTs. In this embodiment, the plurality of DUTs 301 includes DUT1, DUT2, DUT3, DUT4, and DUT5.

[0059] The test structure includes: the adjacent first signal pad S1 and the second signal pad S2 are tilted at an angle of 60 degrees relative to the first direction; the adjacent first signal pad S1 and the ground pad G are tilted at an angle of 60 degrees relative to the first direction X.

[0060] The test structure includes a distance Pp ranging from 50µm to 1000µm between adjacent first signal pads S1 and between the second signal pad S2 and adjacent ground pad G along the first direction X. In this embodiment, the value of Pp is 100µm.

[0061] In the test structure, the widths of the first signal pad S1, the second signal pad S2, and the ground pad G range from 20µm to 200µm. In this embodiment, the Lp value is 80µm.

[0062] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Several devices under test arranged along the first direction; A first pad array located on one side of the plurality of devices under test, the first pad array including a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group are arranged along a second direction, the second direction being perpendicular to the first direction, the first pad group including a plurality of first signal pads arranged along the first direction, the second pad group including a plurality of second signal pads and ground pads arranged along the first direction, each second signal pad being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads being arranged at an angle relative to the first direction; A second pad array is located on the other side of the plurality of devices under test, and the first pad array and the second pad array are centrally symmetrically distributed.

2. The test structure as described in claim 1, characterized in that, The plurality of devices under test includes at least five devices under test.

3. The test structure as described in claim 1, characterized in that, The angle between adjacent first signal pads and second signal pads relative to the first direction is 60 degrees; the angle between adjacent first signal pads and the ground pad relative to the first direction is 60 degrees.

4. The test structure as described in claim 1, characterized in that, Along the first direction, the distance between adjacent first signal pads, and between the second signal pad and the adjacent ground pad, ranges from 50µm to 1000µm.

5. The test structure as described in claim 1, characterized in that, The widths of the first signal pad, the second signal pad, and the ground pad range from 20µm to 200µm.

6. A method for forming a test structure, characterized in that, include: A plurality of devices under test are provided, the plurality of devices under test being arranged along a first direction; A first pad array is formed on one side of the plurality of devices under test. The first pad array includes a first pad group and a second pad group located on both sides of the first pad group. The first pad group and the second pad group are arranged along a second direction, which is perpendicular to the first direction. The first pad group includes a plurality of first signal pads arranged along the first direction. The second pad group includes a plurality of second signal pads and ground pads arranged along the first direction. Each second signal pad is located between adjacent ground pads. Adjacent first signal pads and second signal pads are arranged at an angle relative to the first direction. Adjacent first signal pads and ground pads are arranged at an angle relative to the first direction. A second pad array is formed on the other side of the plurality of devices under test, and the first pad array and the second pad array are centrally symmetrically distributed.

7. The method for forming the test structure as described in claim 6, characterized in that, The plurality of devices under test includes at least five devices under test.

8. The method for forming the test structure as described in claim 6, characterized in that, The angle between adjacent first signal pads and second signal pads relative to the first direction is 60 degrees; the angle between adjacent first signal pads and the ground pad relative to the first direction is 60 degrees.

9. The method for forming the test structure as described in claim 6, characterized in that, Along the first direction, the distance between adjacent first signal pads, and between the second signal pad and the adjacent ground pad, ranges from 50µm to 1000µm.

10. The method for forming the test structure as described in claim 6, characterized in that, The widths of the first signal pad, the second signal pad, and the ground pad range from 20µm to 200µm.

11. A testing method, characterized in that, include: A test structure is provided, comprising: a plurality of devices under test (DUTs) arranged along a first direction; a first pad array located on one side of the plurality of DUTs, the first pad array comprising a first pad group and a second pad group located on both sides of the first pad group, the first pad group and the second pad group being arranged along a second direction, the second direction being perpendicular to the first direction, the first pad group comprising a plurality of first signal pads arranged along the first direction, the second pad group comprising a plurality of second signal pads and ground pads arranged along the first direction, each second signal pad being located between adjacent ground pads, adjacent first signal pads and second signal pads being arranged at an angle relative to the first direction, and adjacent first signal pads and ground pads being arranged at an angle relative to the first direction; and a second pad array located on the other side of the plurality of DUTs, the first pad array and the second pad array being centrally symmetrically distributed. The first probe is placed on the first pad array, and the second probe is placed on the second pad array, so that the first probe and the second probe are respectively connected to each device under test, and the connected devices under test are tested.

12. The test method as described in claim 11, characterized in that, The test structure also includes: the plurality of devices under test includes at least five devices under test.

13. The test method as described in claim 11, characterized in that, The test structure includes: the adjacent first signal pad and the second signal pad are tilted at an angle of 60 degrees relative to the first direction; the adjacent first signal pad and the ground pad are tilted at an angle of 60 degrees relative to the first direction.

14. The test method as described in claim 11, characterized in that, The test structure includes a distance ranging from 50µm to 1000µm between adjacent first signal pads and between the second signal pad and the adjacent ground pad along the first direction.

15. The test method as described in claim 11, characterized in that, In the test structure, the widths of the first signal pad, the second signal pad, and the ground pad range from 20µm to 200µm.

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