Test structure and test method

Abstract

The application provides a test structure and a test method. The test structure comprises a first metal layer, a second metal layer and an intermediate dielectric layer. The second metal layer comprises a metal edge portion and a dielectric portion. The first metal layer is connected to one end of a via, and the other end of the via penetrates the intermediate dielectric layer and is connected to the dielectric portion of the second metal layer; a copper covering layer is arranged in the via. The vias are arranged in the dielectric portion of the second metal layer according to a preset rule; the metal edge portion of the second metal layer surrounds the dielectric portion, and the distance between the metal edge portion and the via is different at different positions of the second metal layer. In the embodiments of the present application, the first metal layer and the second metal layer containing the via are arranged to form a test unit, so as to form a test loop by loading a device working voltage on the test unit, and the current value in the test loop is compared with a standard current value. If a preset condition is met, the copper diffusion barrier capability of the copper covering layer in the via can be directly monitored.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a test structure and test method. Background Technology

[0002] Damascus double-nested copper interconnect technology is used to combat electromigration issues. Metallic copper readily diffuses into silicon and silicides, leading to metal contamination that affects device performance. Therefore, tantalum and tantalum nitride are used as diffusion barrier layers for vias and metal interconnects before the copper plating process. Figure 1 As shown, due to the process characteristics of the damascus structure, a copper diffusion capping layer must be used at the contact surface between the copper interconnect layer and the via to prevent copper from diffusing in the dielectric layer above the interconnect layer, thereby avoiding short circuits between adjacent layers and within the same layer of the copper wiring.

[0003] While existing technologies can check the copper interconnect wiring design rules in damascus structures, they cannot accurately distinguish between copper barrier layer failure and copper cover layer failure if the copper capping film deposition quality is poor, causing copper to diffuse horizontally and short-circuit the interconnects in the same layer.

[0004] Therefore, a new testing scheme is needed to detect copper interconnect wiring rules. Summary of the Invention

[0005] In view of this, the embodiments of this specification provide a test structure and test method, which are applied to the process of copper interconnects in a damascus structure.

[0006] The embodiments in this specification provide the following technical solutions:

[0007] This specification provides a test structure, which includes: a first metal layer, a second metal layer, and an intermediate dielectric layer;

[0008] The second metal layer includes a metal edge portion and a dielectric portion;

[0009] The first metal layer is connected to one end of the via, and the other end of the via penetrates the intermediate dielectric layer and is connected to the dielectric portion of the second metal layer; a copper cover layer is disposed in the via.

[0010] The vias are arranged according to a preset rule in the dielectric portion of the second metal layer;

[0011] The metal edge portion of the second metal layer surrounds the dielectric portion, and the distance between the metal edge portion and the via is different at different locations of the second metal layer;

[0012] The first metal layer and the second metal layer form a test unit. The test unit is used to form a test circuit by loading the working voltage of the device between the test units, so as to compare the current value in the test circuit with the standard current value. If the preset conditions are met, it is determined that the copper diffusion blocking capability of the copper cover layer in the test unit is effective.

[0013] Another test method provided in the embodiments of this specification includes:

[0014] A test unit consisting of a first metal layer and a second metal layer is obtained, and a test circuit is formed by the operating voltage of the load device in the test unit;

[0015] Compare the current value in the test circuit with the standard current value;

[0016] If the preset conditions are met, the copper diffusion blocking ability of the copper overlay layer in the test unit is determined to be effective.

[0017] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0018] By setting up test units corresponding to the vias between metal layers, applying the operating voltage of the device to the test units, and judging the test current, the copper diffusion barrier capability of the copper capping layer can be directly monitored if preset conditions are met. Furthermore, the copper diffusion barrier capability of the copper capping layer is used to verify whether the copper capping layer process settings meet the design rules. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the copper interconnect structure of the Damascus process in the prior art;

[0021] Figure 2 This is a schematic diagram of the test structure for the copper interconnect wiring rules in this application. Figure 1 ;

[0022] Figure 3 This is a top view of the test structure for the copper interconnect wiring rules in this application;

[0023] Figure 4 This is a cross-sectional view of the test structure for the copper interconnect wiring rules in this application;

[0024] Figure 5This is a schematic diagram of the test structure for the copper interconnect wiring rules in this application. Figure 2 . Detailed Implementation

[0025] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0026] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0028] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0030] Existing damascus structure copper interconnect wiring design rules can be checked. For example... Figure 1As shown, due to the process characteristics of the damascus structure, a copper diffusion capping layer must be used at the contact surface between the copper interconnect layer and the via to prevent copper from diffusing into the dielectric layer above the interconnect layer, thereby avoiding short circuits between adjacent layers and within the same layer of copper wiring. However, if the copper capping layer film deposition quality is poor, causing copper to diffuse horizontally and resulting in short circuits in the interconnects within the same layer, it becomes impossible to distinguish between copper barrier layer failure and copper capping layer failure.

[0031] Based on this, the inventors discovered that by designing a test structure for detecting the rules of copper interconnect wiring, the test structure arranges the vias between metal layers in a specific rule, forms a test circuit for the working voltage of the load device in the test unit containing the copper cover layer, and then compares the current value obtained in the test circuit with the standard current value. If the preset conditions are met, it is determined that the copper diffusion blocking ability of the copper cover layer in the test unit is effective.

[0032] The embodiments in this specification, through the design of via layout in the test structure for detecting copper interconnect routing rules, can directly monitor the copper diffusion blocking capability of the copper overlay. Furthermore, the test structure for detecting the copper overlay's blocking capability can be used as a reference test structure for checking routing rules, thereby accurately determining the failure mechanism of copper interconnect routing rules.

[0033] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0034] like Figure 2 or Figure 5 As shown in the embodiment of this specification, a test structure for detecting the rules of copper interconnect wiring is provided. The test structure includes: a first metal layer, a second metal layer, and an intermediate dielectric layer; the second metal layer includes a metal edge portion and a dielectric portion; the first metal layer is connected to one end of a via, and the other end of the via penetrates the intermediate dielectric layer and is connected to the dielectric portion of the second metal layer; a copper overlay is disposed in the via; the vias are arranged according to a preset rule in the dielectric portion of the second metal layer; the metal edge portion of the second metal layer surrounds the dielectric portion, and the distance between the metal edge portion and the via is different at different positions in the second metal layer. The first metal layer and the second metal layer form a test unit, and a test circuit is formed by applying the operating voltage of the load device to the test unit. By comparing the current value in this test circuit with a standard current value, if a preset condition is met, the copper diffusion blocking capability of the copper overlay in the test unit is determined to be effective.

[0035] The test structure for the matrix vias designed in the embodiments of this specification is as follows: Figure 2A test structure for detecting copper interconnect routing rules is configured in a horizontal series. Specifically, the test structure for detecting copper interconnect routing rules includes a first metal layer 11, a second metal layer 13, and an intermediate dielectric layer 12. The second metal layer 13 includes a metal edge portion 131 and a dielectric portion 132. The terms "first" and "second" are used only in conjunction with the accompanying drawings and do not imply any order, quantity, or other limitations on the embodiments described in this specification.

[0036] Specifically, this is illustrated using the example of an adjacent first metal layer and a second metal layer. The first metal layer is the upper metal layer, and the second metal layer is the lower metal layer. A via 14 is provided between the upper and lower metal layers. The upper metal layer is directly connected to one end of the via, while the lower metal layer is not directly connected to the via. For example, the metal edge portion 131 of the lower metal layer surrounds the via matrix, and the via is located in the dielectric portion 132 of the lower metal layer. The other end of the via passes through an intermediate dielectric layer and connects to the dielectric portion of the lower metal layer. A copper overlay is provided in the via. The vias are arranged in the dielectric portion of the lower metal layer according to a preset rule, forming a via matrix (e.g., ...). Figure 3 (As shown at the through-hole 14). The metal edge portion 131 in the lower metal layer surrounds the dielectric portion 132. And as... Figure 2 As shown, the spacing between the metal edge and the via varies in different locations of the second metal layer, such as Space1, ... Space x. For example... Figure 2 As shown and Figure 5 The test structure shown was obtained using the damascus process.

[0037] In this system, each upper metal layer and lower metal layer form a test unit. This test unit is used to form a test circuit at the operating voltage of the load device in the test unit. By comparing the current value obtained in this test circuit with a standard current value, if a preset condition is met, the copper diffusion blocking capability of the copper overlay layer in the test unit is determined to be effective. In some embodiments, the preset condition includes obtaining the maximum current corresponding to a certain test unit in the test structure as a standard current value, and then comparing the current values ​​of other test units with the standard current value. If the current value exceeds three orders of magnitude, the copper diffusion blocking capability of the copper overlay layer in the test unit is determined to be effective.

[0038] In some embodiments, the vias are arranged in a matrix structure in the dielectric portion of the second metal layer.

[0039] Specifically, the through-hole 14 is located in the dielectric portion of the second metal layer, as shown in the figure. Figure 3As shown, the vias are arranged in a matrix structure. In the embodiments of this specification, the vias are arranged regularly between the upper and lower metal layers to form test units. The spacing between the vias and the metal edge of the lower metal layer is different in different test units. In this way, a test circuit is formed by loading the working voltage of the device in the test unit. The current value in the test circuit is compared with the standard current value. If the preset conditions are met, the copper diffusion blocking capability of the copper cover layer can be directly monitored, solving the problem in the prior art that it is impossible to distinguish between copper barrier layer failure and copper cover layer failure.

[0040] In some embodiments, the spacing between the metal edge portion and the via in different locations of the second metal layer is set in a preset order.

[0041] Specifically, with the setting of different second metal layers, the distance between the metal edge portion and the via in different positions of the second metal layer gradually increases from the minimum distance to the maximum distance.

[0042] In conjunction with the above embodiments, the vias between the upper and lower metal layers not only exhibit a matrix arrangement within the dielectric portion of the lower metal layer, but the spacing between the vias and their corresponding metal edges between different upper and lower metal layers is also set according to specific rules. For example... Figure 2 As shown, from left to right, the spacing between the metal edge and the via in each lower metal layer position is set in ascending order, such as Space 1, ... Space x. Another example is... Figure 5 As shown, from top to bottom, the spacing between the metal edge and the via in each lower metal layer is arranged in ascending order. This ensures that the test units consisting of the first metal layer, the second metal layer, and the vias are arranged in a regular pattern, and that the different test units are also arranged in a specific pattern, thus forming the overall test structure. Test circuits are formed by applying the operating voltage of the load device to the corresponding test unit, and the current value in the test circuit is compared with a standard current value. If the preset conditions are met, the copper diffusion capability of the copper overlay layer is monitored.

[0043] In some embodiments, the number of vias corresponding to different test units is the same. As the distance between the metal edge portion and the via in the second metal layer changes from small to large, the specific distance setting is made according to the actual situation.

[0044] In some embodiments, through holes arranged identically in different second metal layers are misaligned in a preset direction to form a through hole.

[0045] In conjunction with the above embodiments, through-holes at the same location in different second metal layers of different test units are staggered in a preset direction to form a through-hole. For example... Figure 2As shown, vias arranged identically in different second metal layers are horizontally offset to form a single via, such as the vias corresponding to Space 1, ... Space x being offset to form a single via. Another example is... Figure 5 As shown, through holes arranged identically in different second metal layers are staggered in the vertical direction to form a through hole.

[0046] In some embodiments, through-holes of different sizes are provided between the first metal layer and the second metal layer.

[0047] In conjunction with the above embodiments, by setting the first metal layer, the second metal layer, and the vias according to specific rules, the test units formed by different metal layers and vias are also set according to specific rules, thereby achieving direct monitoring of the copper diffusion blocking capability of the copper overlay. In some embodiments, vias of different sizes are set between the first metal layer and the second metal layer according to the different via sizes in the damascus structure, so that the current value of the largest via can be obtained as a standard current value to compare and judge the current values ​​of each test unit in the circuit, thereby achieving monitoring of the copper diffusion blocking capability of the copper overlay in the test unit. The specific comparison and judgment process is detailed below.

[0048] In some embodiments, the intermediate dielectric layer comprises ULK and SiCN, or the intermediate dielectric layer comprises USG and SiCN.

[0049] In conjunction with the above embodiments, such as Figure 4 As shown, the intermediate dielectric layer between the first metal layer and the second metal layer includes ULK (ultra-low k, abbreviated as ULK, ultra-low dielectric layer) and SiCN (silicon carbon nitride). For example... Figure 5 As shown, the intermediate dielectric layer between the first metal layer and the second metal layer includes USG (Undoped Silicate Glass) and SiCN (Silicon Carbon Nitrogen).

[0050] In some embodiments, through-holes of different sizes are provided between the upper and lower metal layers of each test unit.

[0051] This specification provides a test method for detecting copper interconnect wiring rules. The test method for detecting copper interconnect wiring rules includes step 1: obtaining a test unit composed of a first metal layer and a second metal layer, and forming a test circuit with the operating voltage of the load device in the test unit; step 2: comparing the current value in the test circuit with a standard current value; step 3: if the preset conditions are met, it is determined that the copper diffusion blocking ability of the copper cover layer in the test unit is effective.

[0052] In conjunction with the above embodiments, such as Figure 2As shown, specifically, a test unit consisting of an upper metal layer and a lower metal layer is obtained, and a test circuit is formed with the operating voltage of the load device in the test unit. The current value of each test unit in the test structure is obtained sequentially, and the current value obtained from each test circuit is compared with the standard current value to determine the blocking ability of the SiCN copper capping layer for copper diffusion. For example... Figure 2 As shown, by connecting the pads in each test unit, such as pad1, ... padx, the working voltage of the load device is used to form a test circuit, and the test current value of the corresponding test circuit is obtained, which is then compared with the standard current value for judgment.

[0053] In some embodiments, the test method for detecting copper interconnect rules further includes: obtaining the current value of each test unit and using the maximum current value as the standard current value; if the ratio of the measured current value to the standard current value is greater than a preset order of magnitude, then the copper diffusion blocking capability of the copper overlay in the test unit is determined to be effective.

[0054] In conjunction with the above embodiments, the following can be obtained: Figure 2 The current value of each test unit is measured. Specifically, the working voltage of the load device between the upper and lower metal layers of the test unit forms a test circuit. The maximum current value I(max space) in the corresponding test circuit of all test units is measured as the standard current value. The current value of each test unit is measured sequentially. If the ratio of the measured current value I(x space) to I(max space) exceeds three orders of magnitude, the via at this time is the maximum copper diffusion blocking capability that the copper diffusion capping layer can achieve under the current process conditions. That is, the copper diffusion blocking capability of the copper capping layer in the test unit is determined to be effective.

[0055] In some embodiments, the test method for detecting copper interconnect wiring rules further includes: determining the spacing between vias and metal edges that effectively correspond to the copper diffusion blocking capability between metal layers; if the spacing between vias and metal edges is less than a preset spacing threshold, then the current copper coverage process is determined to meet the design requirements.

[0056] Based on the above embodiments, the spacing between the via and the metal edge portion that effectively corresponds to the copper diffusion blocking capability between metal layers is determined. If the spacing between the via and the metal edge portion is less than a preset spacing threshold, then the current copper overlay process is determined to meet the design requirements. The preset spacing threshold is the minimum spacing required for the copper overlay process conditions to meet the design specifications.

[0057] In some embodiments, regardless of the method used... Figure 2 The test structure shown is composed of multiple test units, and it still adopts the following method: Figure 5 As shown, stacking and connecting different metal interconnect layers in series can directly monitor whether the copper blocking diffusion capability of the copper overlay layer in different metal layers is effective.

[0058] In the embodiments of this specification, not only can the copper blocking diffusion capability of the copper capping layer in the test unit formed by adjacent first metal layers and second metal layers be directly monitored, but in some embodiments, the copper blocking diffusion capability of the copper capping layer can also be monitored in several test units corresponding to non-adjacent first metal layers and second metal layers using the above detection method, which will not be elaborated here.

[0059] In this specification, similar or identical parts among the various embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the product embodiments described later are relatively simple in description since they correspond to the methods, and relevant parts can be referred to the descriptions in the system embodiments.

[0060] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A test structure, characterized in that, include: First metal layer, second metal layer and intermediate dielectric layer; The second metal layer includes a metal edge portion and a dielectric portion; The first metal layer is connected to one end of the via, and the other end of the via penetrates the intermediate dielectric layer and is connected to the dielectric portion of the second metal layer; a copper cover layer is disposed in the via. The vias are arranged according to a preset rule in the dielectric portion of the second metal layer; The metal edge portion of the second metal layer surrounds the dielectric portion, and the distance between the metal edge portion and the via is different in different locations of the second metal layer; The first metal layer and the second metal layer form a test unit. The test unit is used to apply the operating voltage of the device to the test unit to form a test circuit. The current value in the test circuit is compared with the standard current value. If the preset conditions are met, the copper diffusion blocking capability of the copper cover layer in the test unit is determined to be effective.

2. The test structure according to claim 1, characterized in that, The vias are arranged in a matrix structure in the dielectric portion of the second metal layer.

3. The test structure according to claim 1, characterized in that, The spacing between the metal edge portion and the through hole in the second metal layer at different locations is set according to a preset order.

4. The test structure according to claim 3, characterized in that, As the second metal layers at different locations are arranged sequentially, the distance between the metal edge and the through hole gradually increases from the minimum distance to the maximum distance.

5. The test structure according to claim 1, characterized in that, Through holes arranged in the same way in different second metal layers are staggered in sequence according to a preset direction to form multiple through holes arranged in a straight line.

6. The test structure according to claim 1, characterized in that, Through-holes of different sizes are set between the first metal layer and the second metal layer.

7. The test structure according to claim 1, characterized in that, The intermediate dielectric layer comprises an ultra-low dielectric layer and silicon carbon nitride, or the intermediate dielectric layer comprises undoped silicon glass and silicon carbon nitride.

8. A testing method, characterized in that, The test method, using the test structure as described in any one of claims 1-7, comprises: A test unit consisting of a first metal layer and a second metal layer is obtained, and the operating voltage of the device is applied to the test unit to form a test circuit; Compare the current value in the test circuit with the standard current value; If the preset conditions are met, the copper diffusion blocking ability of the copper overlay layer in the test unit is determined to be effective.

9. The test method according to claim 8, characterized in that, The testing method also includes: Obtain the current value of each test unit and use the maximum current value as the standard current value; If preset conditions are met, the ability of the copper overlay layer in the test unit to block diffusion is determined to be effective, including: If the ratio of the measured current value to the standard current value is greater than a preset order of magnitude, then the copper diffusion blocking capability of the copper coating in the test unit is confirmed to be effective.

10. The test method according to claim 9, characterized in that, The testing method also includes: Determine the spacing between the via and the metal edge that effectively corresponds to the copper diffusion blocking capability between metal layers; If the distance from the via to the metal edge is less than the preset distance threshold, then the current copper coverage process meets the design requirements.

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