3DS FET and its manufacturing method

Abstract

A three-dimensional stacked field effect transistor (3DS FET) and a method of manufacturing the same are disclosed. According to embodiments, the 3DS FET can include a lower active region disposed on a substrate, an upper active region above the lower active region, and a gate stack. The lower active region includes a fin extending along a first direction on the substrate and lower source / drain portions at opposite ends of the fin in the first direction, respectively. The upper active region includes one or more nanosheets, with a lowermost nanosheet spaced apart from the fin in a vertical direction with respect to the substrate, and upper source / drain portions at opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting the first direction to intersect the fin and the one or more nanosheets.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a three-dimensional stacked field-effect transistor (3DS FET) and a method for manufacturing the same. Background Technology

[0002] To address the trend of continuous miniaturization in integrated circuits (ICs), various device structures have been proposed to achieve higher integration density and overall performance. For example, nanosheet (NS) gate-all-around field-effect transistors (GAAFETs) are expected to replace FinFET technology at 3nm and below. Furthermore, three-dimensional stacked field-effect transistors (3DSFETs) or vertical field-effect transistors (VFETs) are expected to become the main technology route after the 1nm node.

[0003] Currently, there are two main types of process methods for realizing 3DS FETs: sequential integration (Sequential 3D) and self-aligned monolithic 3D. Sequential integration is simpler but requires two processes, resulting in higher costs, and upper-layer devices face integration thermal budget constraints. Self-aligned monolithic 3D offers high integration density and superior performance, but its process is more complex, not fully compatible with existing GAAFET processes, requires significantly more process steps, and suffers from poor controllability. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a novel three-dimensional stacked field-effect transistor (3DS FET) and a method for manufacturing the same.

[0005] According to one aspect of this disclosure, a 3DS FET is provided, including a lower active region disposed on a substrate, an upper active region above the lower active region, and a gate stack. The lower active region includes a fin extending on the substrate along a first direction and lower source / drain portions at opposite ends of the fin in the first direction. The upper active region includes: one or more nanosheets, wherein the lowermost nanosheet is spaced apart from the fin in a vertical direction relative to the substrate; and upper source / drain portions at opposite ends of the one or more nanosheets in the first direction. The gate stack extends in a second direction intersecting the first direction to intersect the fin and the one or more nanosheets.

[0006] According to another aspect of this disclosure, a method for manufacturing a 3DS FET is provided, comprising: forming a stack of sacrificial layers and nanosheet layers alternating with each other on a substrate; patterning the upper portion of the stack and the substrate into a strip extending along a first direction, wherein fins are formed on the upper portion of the patterned substrate; thinning the fins to reduce their width in a second direction intersecting the first direction; forming an isolation layer on the substrate, the isolation layer covering the fins; etching the isolation layer downward to expose the upper portion of the fins; forming a dummy gate on the isolation layer; etching the stack and the fins based on the dummy gate; forming lower source / drain portions at opposite ends of the fins in the first direction; forming an inter-source / drain isolation layer on the lower source / drain portions; forming upper source / drain portions at opposite ends of the nanosheets in the first direction; and replacing the dummy gate with a gate stack.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned 3DS FET.

[0008] According to embodiments of this disclosure, a novel 3DS FET and its manufacturing method are proposed. According to embodiments of this disclosure, in the manufacturing process of a gate-all-around field-effect transistor (GAAFET), by modifying some processes, a lower-layer fin field-effect transistor (FinFET) device is formed in situ in the sub-fin region, and then integrated with the upper-layer GAAFET device to form a highly integrated 3DS FET. This significantly reduces the complexity of the manufacturing process and greatly increases controllability. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1(a) to 1(d) A partial exploded perspective view of a 3DS FET according to an embodiment of the present disclosure is shown schematically;

[0011] Figures 2(a) to 20(c) The illustration schematically shows some stages in the process of manufacturing a 3DS FET according to an embodiment of the present disclosure.

[0012] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0015] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0016] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0017] Figures 1(a) to 1(d) A partial exploded perspective view of a 3DS FET according to an embodiment of the present disclosure is shown schematically.

[0018] Figure 1(a) schematically illustrates the channel portion of a 3DS FET according to an embodiment. The 3DS FET may be disposed on a substrate SUB and includes a lower device (e.g., a FinFET) and an upper device (e.g., a GAAFET) vertically stacked on the substrate SUB. Figure 1(a) shows the lower channel portion FIN for the lower device and the upper channel portions (NS1, NS2, NS3) for the upper device.

[0019] The lower channel portion (FIN) may have a fin shape extending along a first direction (e.g., the x-direction). At opposite ends of the lower channel portion (FIN) in the first direction (e.g., the x-direction), lower source / drain portions (see S / D shown in Figure 1(b)) may be formed. L -1, S / D L -2).

[0020] The upper channel portion may include nanosheets NS1, NS2, and NS3, each extending substantially parallel to the upper surface of the substrate SUB, having a length in a first direction (e.g., the x-direction) and a width in a second direction (e.g., the y-direction) intersecting (e.g., perpendicular to) the first direction. Depending on the width in the second direction, the nanosheets NS1, NS2, and NS3 may also be formed as nanowires. At opposite ends of the upper channel portion in the first direction (e.g., the x-direction), upper source / drain portions (see the S / D shown in FIG. 1(b)) may be formed. U -1, S / D U -2).

[0021] This illustration shows an upper channel portion comprising three semiconductor nanosheets NS1, NS2, and NS3, but the disclosure is not limited thereto. For example, the upper channel portion may include more or fewer nanosheets.

[0022] The upper and lower channel portions can be spaced apart in the vertical direction (e.g., the z-direction) and can be self-aligned with each other, particularly substantially center-aligned in the vertical direction (e.g., the z-direction). The nanosheets NS1, NS2, and NS3 in the upper channel portion can be spaced apart in the vertical direction (e.g., the z-direction) and can be self-aligned with each other. This will be described in further detail below.

[0023] The length of the lower channel portion in the first direction (e.g., the x-direction) may be greater than the length of the upper channel portion in the first direction (e.g., the x-direction). As shown by the dashed line in FIG1(a), the lower channel portion may include an elongated portion extending relative to the upper channel portion in the first direction (e.g., the x-direction). For example, this elongated portion may correspond to the second sidewall described below. Furthermore, the width of the upper channel portion in the second direction (e.g., the y-direction) may be greater than the width of the lower channel portion in the second direction (e.g., the y-direction). As shown by the dashed line in FIG1(a), the upper channel portion may include an elongated portion extending relative to the lower channel portion in the second direction (e.g., the y-direction). For example, this elongated portion is due to a process of thinning the lower channel portion to form thin fins.

[0024] Figure 1(b) schematically illustrates the source / drain portion of a 3DS FET according to an embodiment. More specifically, the underlying device may include lower source / drain portions S / D formed at opposite ends of the lower channel portion. L -1, S / D L -2 (together with the lower channel portion, it constitutes the active region of the lower-layer device, also known as the lower active region), the upper-layer device may include the upper source / drain S / D portions formed at opposite ends of the upper channel portion. U -1, S / D U-2 (Together with the upper channel, it constitutes the active region of the upper device, also known as the upper active region). In the case where the upper channel includes discrete nanosheets NS1, NS2, and NS3, the upper source / drain S / D... U -1 can connect one end of each of these nanosheets to each other in the first direction, upper source / drain S / D U -2 can connect the other ends of these nanosheets to each other in the first direction.

[0025] To facilitate the formation of the lower source / drain S / D in the underlying device. L -1, S / D L -2 contact plug, lower source / drain S / D L -1, S / D L -2 can be relative to the source / drain S / D respectively. U -1, S / D U -2 extends relative to each other in at least one of the first direction (e.g., the x-direction) and the second direction (e.g., the y-direction), and then the contact plug can be attached to the extended portion.

[0026] Figure 1(c) schematically illustrates the sidewall structure of the 3DS FET according to an embodiment. In Figure 1(c), for clarity, each nanosheet in the upper channel is cut in the middle along a first direction (e.g., the x-direction), and the sidewall structure is cut accordingly (the cross-section of the cut portion is indicated by a diagonal line).

[0027] As shown in Figure 1(c), the sidewall structure may include an outer sidewall SPACER_1 and an inner sidewall SPACER_2. The sidewall structure may extend in a second direction (e.g., the y-direction) and define space for gate stacking. The ends of the upper channel portion (each nanosheet in the channel) and the lower channel portion in the first direction (e.g., the x-direction) may be exposed from the sidewall structure (connected to the corresponding source / drain portions).

[0028] The sidewalls of the upper channel portion (each nanosheet in it) extending along a second direction (e.g., the y direction) can be self-aligned with the sidewalls of the outer wall SPACER_1, for example, substantially coplanar; while the sidewalls of the lower channel portion extending along the second direction (e.g., the y direction) can extend relative to the sidewalls of the outer wall SPACER_1 in a first direction.

[0029] When viewed in the first direction (e.g., the x direction), the outer wall SPACER_1 may have an opening having: a first side extending along the upper surface of the uppermost nanosheet (in this case, NS3) of the upper channel portion; a second side and a third side extending along the sides of each nanosheet on opposite sides in the second direction (e.g., the y direction) respectively (only one of them is visible in FIG. 1(c) due to the cutting), wherein the second side and the third side extend vertically downward (e.g., along the z direction) from the first side on opposite sides in the second direction (e.g., the y direction) to near the top surface of the lower channel portion FIN; and a fourth side and a fifth side extending from the second side and the third side toward the lower channel portion FIN respectively (only one of them is visible in FIG. 1(c) due to the cutting).

[0030] Inner sidewalls SPACER_2 are formed between the nanosheets in the upper channel portion and between the lowermost nanosheet (in this case, NS1) and the lower channel portion. Inner sidewalls SPACER_2 can be self-aligned with outer sidewalls SPACER_1, for example, substantially coplanar. The sidewalls of inner sidewalls SPACER_2 extending along a second direction (e.g., the y-direction) can be substantially coplanar with the sidewalls of outer sidewalls SPACER_1 (and the sidewalls of the nanosheets in the upper channel portion).

[0031] When viewed in the first direction (e.g., the x-direction), the inner wall SPACER_2 can extend vertically between adjacent nanosheets and in the second direction between the second and third sides of the outer wall SPACER_1. The inner wall SPACER_2 can also extend on the lower surface of the bottommost nanosheet (here, NS1) between the second and third sides of the outer wall SPACER_1.

[0032] As can be seen, the inner sidewall SPACER_2 closes the openings of the outer sidewall SPACER_1 between the nanosheets. In Figure 1(c), a portion of the opening in the outer sidewall SPACER_1, more specifically, the portion between the lowermost nanosheet (here, NS1) and the lower channel FIN, remains open, allowing the source / drain isolation layer between the upper and lower source / drain portions to fill this portion. Thus, the gate stack formed inside the sidewall structure and the source / drain formed outside the sidewall structure can be reliably electrically isolated from each other. This will be described in further detail below.

[0033] Here, the outer wall SPACER_1 and the inner wall SPACER_2 are shown in different shades of gray because they can be formed in different process steps. As described below, the outer wall SPACER_1 and the inner wall SPACER_2 can comprise substantially the same material.

[0034] Figure 1(d) schematically illustrates the gate stack of the 3DS FET according to an embodiment. Similar to Figure 1(c), in Figure 1(d), for clarity, each nanosheet in the upper channel is cut in the middle along a first direction (e.g., the x-direction), and the sidewall structure and gate stack are cut accordingly (the cross-section of the cut portion is indicated by a diagonal line).

[0035] As shown in Figure 1(d), the gate stack GS can be formed within the space defined by the sidewall structure. The gate stack GS can include a gate dielectric layer and a gate conductor layer (in Figure 1(d), the stacked structure of the gate stack is not shown for convenience). The gate stack GS can extend on the upper and lower surfaces of the nanosheets in the upper channel portion, and can also extend on the opposite sides of the nanosheets in the second direction (e.g., the y-direction), thereby forming a fully encircling gate structure, and together with the upper channel portion and the upper source / drain portion, constitutes a GAAFET. In addition, the gate stack GS can extend on the top surface of the lower channel portion FIN and on the opposite sides in the second direction (e.g., the y-direction), thereby together with the lower channel portion FIN and the lower source / drain portion, constitutes a FinFET. The FinFET and GAAFET are stacked in the vertical direction (e.g., the z-direction), they can have their own source / drain portions, and can have a common gate stack.

[0036] exist Figures 1(a) to 1(d) The perspective view shows only the main components of the 3DS FET, omitting other components such as the isolation layer and gap fill layer. Those skilled in the art will understand the other components of the 3DS FET based on this disclosure.

[0037] Figures 2(a) to 20(c) The illustration schematically shows some stages in the process of manufacturing a 3DS FET according to an embodiment of the present disclosure.

[0038] like Figures 2(a) to 2(c) As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate will be used as an example. Here, a silicon wafer is provided as the substrate 1001.

[0039] Well regions can be formed in substrate 1001. The doping type of the well region can be determined based on the conductivity type of the device to be formed on substrate 1001, particularly the underlying device. For example, if a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well. Well regions can be formed, for example, by implanting a dopant of the appropriate conductivity type (p-type dopant such as B or In, or n-type dopant such as As or P) into substrate 1001 and subsequently performing thermal annealing. Various methods exist in the art for setting such well regions, which will not be elaborated here.

[0040] like Figures 3(a) to 3(c) As shown, on substrate 1001, a first sacrificial layer 1003, a first nanosheet layer 1005, a second sacrificial layer 1007, a second nanosheet layer 1009, a third sacrificial layer 1011, and a third nanosheet layer 1013 can be sequentially formed, for example, by epitaxial growth. The sacrificial layers and nanosheet layers can be alternately stacked on substrate 1001 and can be etch-selective relative to each other. For example, the sacrificial layers may include SiGe (e.g., a Ge atomic percentage of about 10%-50%, preferably about 30%-35%), and the nanosheet layers may include Si. The nanosheet layers can be relatively thin, for example, with a thickness of about 1 nm-40 nm, preferably about 6 nm-12 nm. The bottommost first sacrificial layer 1003 can be relatively thick, for example, with a thickness of about 2 nm-100 nm, preferably about 30 nm-50 nm, to define the spacing between the lower and upper devices. Other sacrificial layer thicknesses are, for example, about 1 nm to 50 nm, preferably about 8 nm to 15 nm, to define the spacing between adjacent nanosheets in the upper device.

[0041] Here, the formation of three nanosheets is described as an example, thus forming three nanosheet layers accordingly. However, this disclosure is not limited to this. For example, fewer or more nanosheet layers (and correspondingly more or fewer sacrificial layers stacked therewith) can be formed.

[0042] Next, the fins can be patterned. To better control the thickness of the fins during patterning, the sidewall pattern transfer (SIT) process can be used.

[0043] For example, such as Figures 4(a) to 4(c) As shown, a sidewall 1015 can be formed on the third nanosheet 1013 using a sidewall formation process. In this process, a mandrel can be formed, followed by the deposition of a sidewall material layer in a generally conformal manner. The sidewall material layer is then anisotropically etched, such as by reactive ion etching (RIE) in the vertical direction, leaving the sidewall material layer on the sidewall of the mandrel to form the sidewall. The mandrel can then be removed. The sidewall 1015 thus formed can be positioned along, for example, a first direction (e.g., ...). Figure 4(a) and 4(b)The sidewall 1015 extends horizontally within the paper plane (perpendicular to the paper plane in Figure 4(c)). Considering etching selectivity in subsequent processes, the sidewall 1015 may include nitrides, oxides, carbides, organic materials, or combinations thereof, such as SiCO. x aC, SOG (spin-coated glass).

[0044] like Figures 5(a) to 5(c) As shown, the sidewall 1015 can be used as an etching mask to perform anisotropic etching, such as vertical RIE, on the underlying nanosheet layer and sacrificial layer, to transfer the pattern of the sidewall 1015 into the underlying layer. Here, etching can be performed into the substrate 1001. Thus, the upper part of the substrate 1001 and the nanosheet layer and sacrificial layer thereon can form stripes that protrude relative to the substrate 1001 and extend along a first direction, as shown in FIG. 5(c). The dashed lines in FIG. 5(c) show the outline after etching using the sidewall 1015 as a mask.

[0045] In the following description, for convenience, the protruding portion of substrate 1001 will be referred to as a "fin" (based on which the underlying FinFET is subsequently formed).

[0046] To improve the performance of the underlying devices, the fins can be thinned. For example, selective lateral etching of the substrate 1001 (here, Si) can reduce the thickness of the fins in a second direction (e.g., the horizontal direction within the plane of the paper in FIG. 5(c), the vertical direction within the plane of the paper in FIG. 5(a), and the direction perpendicular to the plane of the paper in FIG. 5(b)). For example, the thickness of the thinned fins in the second direction can be from about 1 nm to 50 nm.

[0047] Here, the etchant etches the fins from opposite sides in the second direction. The etching conditions on both sides are essentially the same, so the etching amount can also be essentially the same. Therefore, the fins can still maintain self-alignment with the upper nanosheet layer, or in other words, can maintain essentially center alignment with the upper nanosheet layer.

[0048] In this example, the nanosheet layer comprises the same material as the fins (here, Si). In this case, to protect the nanosheet layer during the fin thinning process, the process can be performed as follows: For example, anisotropic etching using sidewall 1015 as a mask can first stop at the top surface of substrate 1001, and the etched sacrificial layer and nanosheet layer can be subjected to surface plasma thin-film oxidation or nitriding to form thin oxide or nitride layers on their sidewalls, followed by continued etching and thinning of the substrate 1001 below. Alternatively, anisotropic etching using sidewall 1015 as a mask can first stop at the top surface of substrate 1001, forming temporary protective sidewalls on the top surface of substrate 1001, before etching and thinning of the substrate 1001 below. Such thin oxide or nitride layers or temporary protective sidewalls can protect the nanosheet layer during the thinning process and can be removed by selective etching after the thinning process.

[0049] After that, side wall 1005 can be removed.

[0050] Grooves are formed in the substrate 1001 on both sides of the fin. Isolation, such as shallow trench isolation (STI), can be formed in these grooves. For example, as... Figures 6(a) to 6(c) As shown, an isolation layer 1017 can be formed by depositing oxide, planarizing the deposited oxide (e.g., chemical mechanical polishing (CMP), and etching back the planarized oxide (e.g., RIE). Here, the top surface of the isolation layer 1017 can be near the top surface of the substrate 1001.

[0051] As shown in Figure 6(c), the fins can be surrounded by an isolation layer 1017. In conventional GAAFET processes, GAAFETs are primarily fabricated based on the upper nanosheet layer; therefore, the fins surrounded by the isolation layer 1017 can be considered as a sub-fin region. According to embodiments of this disclosure, FinFETs can be fabricated based on this sub-fin region.

[0052] like Figure 7 As shown, photoresist can be formed, for example, to pattern the photoresist into openings extending along a first direction, and the patterned photoresist can be used as an etching mask to selectively etch the isolation layer 1017 to form openings in the isolation layer 1017 extending along the first direction. Figure 7 A groove extending in a direction perpendicular to the paper surface can expose the upper part of the fins. For example, the groove can have a width of about 3 nm to 20 μm in the second direction and a depth (relative to the top surface of the insulating layer 1017) of about 3 nm to 500 nm.

[0053] A dummy barrier can be formed on isolation layer 1017. For example, as... Figures 8(a) to 8(c)As shown, a dummy gate dielectric layer 1019 and a dummy gate conductor layer 1021 can be sequentially formed, for example, by deposition. The dummy gate dielectric layer 1019 can be formed in a generally conformal manner, for example, it can include oxides, with a thickness of about 0.5 nm to 20 nm, preferably about 0.7 nm to 1.2 nm. The dummy gate conductor layer 1029 can, for example, include polysilicon. The dummy gate conductor layer 1029 can be planarized, such as by CMP, to have a substantially flat top surface. A hard mask layer 1023 can be formed on the dummy gate conductor layer 1021 by deposition. The hard mask layer 1023 can include nitrides, carbides, oxides, organic materials, amorphous silicon, polysilicon, or combinations thereof, such as dielectric antireflective coating (DARC) / a-Si / SiN. x The SiuO2 stacked structure has a thickness of approximately 3nm-1000nm, preferably approximately 30nm-100nm. The hard mask layer 1023, along with the underlying dummy gate conductor layer 1021 and dummy gate dielectric layer 1019, can be patterned by photolithography into a stripe extending along a second direction (e.g., the vertical direction within the paper in FIG. 8(a), the direction perpendicular to the paper in FIG. 8(b), and the horizontal direction within the paper in FIG. 8(c)). This stripe is then placed in the first direction (e.g., Figure 8(a) and 8(b) First sidewalls 1025 may be formed on opposite sidewalls in the horizontal direction (within the plane of the paper). For example, the first sidewalls 1025 may include nitrides, carbides, oxides, organic materials, or combinations thereof, such as SiN. x or SiCO x The thickness is approximately 1 nm to 70 nm, preferably approximately 5 nm to 15 nm. This first sidewall 1025 can correspond to the aforementioned outer sidewall.

[0054] Although not shown in the figure, the first sidewall 1025 may also be formed on the sidewall of the fin.

[0055] The location of the channel section can be defined based on a dummy gate.

[0056] For example, such as Figures 9(a) to 9(c) As shown, the hard mask layer 1023 and the first sidewall 1025 can be used as etching masks. The nanosheet layer and the sacrificial layer are selectively etched sequentially through anisotropic etching, such as vertical RIE. The etching can stop at the top surface of the fin. Thus, the sacrificial layer and the nanosheet layer are formed as a stack below the dummy gate. The nanosheet layer in this stack is in the form of nanosheets and can constitute the upper channel portion of the upper device.

[0057] like Figure 10(a) and 10(b)As shown, a second sidewall 1027 can be formed on the sidewall of the first sidewall 1025. For example, the second sidewall 1027 may include nitrides, carbides, oxides, organic compounds, or combinations thereof, such as SiN. x or SiCO x The thickness is approximately 1 nm to 70 nm, preferably approximately 5 nm to 15 nm. The second sidewall 1027 can cover the sidewalls of the sacrificial layer and the nanosheet layer to prevent the formation of lower source / drain portions on these sidewalls. Similarly, the second sidewall 1027 may also be present on the sidewalls of the fins.

[0058] like Figure 11 As shown, the hard mask layer 1023, the first sidewall 1025, and the second sidewall 1027 can be used as etching masks to selectively etch the fins through anisotropic etching, such as vertical RIE. The etching may not reach the bottom of the fin (the area where the fin meets the substrate). Thus, a self-aligned dummy gate and a nanosheet portion are formed in the fin, which can constitute the lower channel portion of the underlying device.

[0059] Next, a lower source / drain section and an upper source / drain section can be formed at the ends of the lower channel section and the upper channel section, respectively.

[0060] For example, such as Figure 12(a) and 12(b) As shown, selective epitaxial growth processes can be used, for example, to grow the lower channel portion in the first direction (e.g., Figure 12(a) and 12(b) Lower source / drain portions 1029 are formed at opposite ends on the horizontal plane within the paper. For example, the lower source / drain portions 1029 may include the same material as the lower channel portion (here, Si), or may include a different material, such as SiGe or Si:C, to apply appropriate stress to the lower channel portion to improve device performance. During epitaxial growth, the lower source / drain portions 1029 may be in-situ doped to an appropriate conductivity type. For example, if the underlying device is to be formed as a p-type device, the lower source / drain portions 1029 may be doped to p-type; if the underlying device is to be formed as an n-type device, the lower source / drain portions 1029 may be doped to n-type. Alternatively, the lower source / drain portions 1029 may be doped after epitaxial growth using other processes such as ion implantation.

[0061] Note that the lower source / drain 1029 does not necessarily have a flat outer surface as shown in the figure, but may have a surface orientation determined by its crystal plane.

[0062] As described above, due to the presence of the second sidewall 1027, the lower source / drain 1029 can be avoided being formed on the sidewall of the stack of nanosheets and sacrificial layers. Subsequently, as... Figure 13As shown, the second sidewall 1027 can be removed by selective etching to expose the sidewalls of the nanosheet, so that the source / drain can be formed on these sidewalls.

[0063] For electrical isolation between the lower source / drain and the upper source / drain, such as Figure 14(a) and 14(b) As shown, an inter-source / outlet isolation layer 1031 can be formed on the lower source / outlet portion 1029. The inter-source / outlet isolation layer 1031 can be formed, for example, by depositing oxide, planarizing the deposited oxide (e.g., CMP), and etching back the planarized oxide. The top surface of the inter-source / outlet isolation layer 1031 can be between the top and bottom surfaces of the bottommost sacrificial layer (here, sacrificial layer 1003), thereby exposing all the sidewalls of the nanosheets while reliably covering the lower source / outlet portion 1029.

[0064] For upper-layer devices, inner walls can be formed to provide electrical isolation between the sacrificial layer and the source / drain regions to be formed. For example, as... Figure 15 As shown, selective etching can be used to laterally recess the exposed sidewalls of each sacrificial layer to a certain depth, the recess depth of which can be substantially the same as the thickness of the previously formed first sidewall 1025. To better control the recess depth, atomic layer etching (ALD) can be used. In the recess thus formed, the inner sidewall 1033 can be formed by depositing and then etching back a dielectric material. The inner sidewall 1033 can include the same material as the first sidewall 1025 and can be self-aligned to the first sidewall 1025.

[0065] Similarly, such as Figure 16(a) and 16(b) As shown, selective epitaxial growth processes can be used to grow nanosheets in a first direction (e.g., Figure 16(a) and 16(b) The upper source / drain portion 1035 is formed at opposite ends on the upper channel portion (in the horizontal direction within the plane of the paper). For example, the upper source / drain portion 1035 may include the same material as the upper channel portion (here, Si), or it may include a different material, such as SiGe or Si:C, to apply appropriate stress to the upper channel portion to improve device performance. During epitaxial growth, the upper source / drain portion 1035 may be in-situ doped to an appropriate conductivity type. Alternatively, the upper source / drain portion 1035 may be doped after epitaxial growth by other processes such as ion implantation. Similarly, the upper source / drain portion 1035 may have a surface orientation determined by its crystal plane.

[0066] According to embodiments of this disclosure, upper-layer devices and lower-layer devices may have the same conductivity type, such as n-type or p-type; or they may have different conductivity types, such as one being n-type and the other being p-type.

[0067] It should be noted that although the upper source / drain portion is shown as wider than the lower source / drain portion in the second direction in Figure 16(a), this is merely an example. As described above, in order to achieve contact plugs to the upper source / drain portion and the lower source / drain portion respectively, the lower source / drain portion may extend relative to the upper source / drain portion in at least one of the first and second directions.

[0068] Next, an alternative gate process can be implemented.

[0069] For example, such as Figure 17 As shown, an interlayer dielectric layer 1037 can be formed by depositing a dielectric such as an oxide and then planarizing the deposited dielectric such as by CMP. CMP can stop at the dummy gate conductor layer 1021 to expose the dummy gate conductor layer 1021.

[0070] like Figure 18(a) and 18(b) As shown, the dummy gate conductor layer 1021 can be removed by selective etching, thereby removing the dummy gate dielectric layer 1019 exposed by the removal of the dummy gate conductor layer 1021. Then, as... Figure 19(a) and 19(b) As shown, the sacrificial layer can be further removed by selective etching, thus separating the nanosheets from each other and from the fins below.

[0071] like Figures 20(a) to 20(c) As shown, a gate stack can be formed within the space defined by the first sidewall 1025 and the inner sidewall 1033 (and the source / drain isolation layer 1031). For example, a gate dielectric layer 1039 and a gate conductor layer 1041 can be formed sequentially. The gate dielectric layer 1039 can be formed in a generally conformal manner and may include a high-k gate dielectric such as HfO. x The thickness is approximately 0.3 nm to 20 nm, preferably approximately 0.7 nm to 2.8 nm. The gate conductor layer 1041 may include a metal gate conductor such as metals such as Ti, Al, W, etc. and / or a conductive metal nitride such as TiN, TaN, etc., with a thickness of approximately 3 nm to 100 nm, preferably approximately 10 nm to 30 nm.

[0072] Gate stacks can surround the individual nanosheets, thus forming the upper GAAFET. Alternatively, gate stacks can extend on the top and sides of the fins, thus forming the lower FinFET.

[0073] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Therefore, this disclosure also provides an electronic device including the above-described semiconductor devices. The electronic device may also include components such as a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablet computers (PCs), artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

[0074] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0075] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0076] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A three-dimensional stacked field-effect transistor, comprising: A lower active region disposed on a substrate, wherein the lower active region includes: The fins extending along the first direction on the substrate, and The lower source / drain portions at opposite ends of the fin in the first direction; and An upper active region is located above the lower active region, wherein the upper active region includes: One or more nanosheets, wherein the lowermost nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and Source / drain portions are located at opposite ends of one or more nanosheets in the first direction, respectively; A gate stack extending in a second direction intersecting the first direction to intersect the fin and the one or more nanosheets; The isolation layer between the lower source / drain and the upper source / drain; and The gate is stacked on the sidewall structure on opposite sides of the first direction. The sidewall structure includes: an outer sidewall extending along the second direction; and an inner sidewall extending along the second direction between adjacent nanosheets and on the lower surface of the lowermost nanosheet. The outer sidewall, the inner sidewall, and the isolation layer are located between the grid stack and the lower source / drain section and the upper source / drain section. Wherein, the length of the fin in the first direction is greater than the length of the nanosheet in the first direction. The portion of the gate stack below the bottommost nanosheet includes an upper portion adjacent to the bottommost nanosheet and a lower portion adjacent to the fin. The inner sidewall on the lower surface of the bottommost nanosheet is on the opposite sidewall of the upper portion in the first direction and defines a first width of the upper portion in the first direction. The isolation layer is on the opposite sidewall of the lower portion in the first direction and defines a second width of the lower portion in the first direction, the second width being greater than the first width.

2. The three-dimensional stacked field-effect transistor according to claim 1, wherein, The fin is self-aligned with the one or more nanosheets.

3. The three-dimensional stacked field-effect transistor according to claim 1, wherein, The active region comprises a plurality of nanosheets, wherein each nanosheet is spaced apart from the others in the vertical direction and is self-aligned with the others.

4. The three-dimensional stacked field-effect transistor according to claim 1, wherein, The gate stack surrounds the outer periphery of each of the one or more nanosheets and extends on the top and side surfaces of the fin.

5. The three-dimensional stacked field-effect transistor according to claim 1, wherein, The width of the fin in the second direction is smaller than the width of the nanosheet in the second direction.

6. The three-dimensional stacked field-effect transistor according to claim 5, wherein, The width of the fin in the second direction is 1 nm to 50 nm.

7. The three-dimensional stacked field-effect transistor according to claim 1, wherein, The lower source / drain portion may have the same doping type as the upper source / drain portion, or a different doping type.

8. A method for manufacturing a three-dimensional stacked field-effect transistor, comprising: A sacrificial layer and nanosheet layers are stacked alternately on a substrate; The stack and the upper part of the substrate are patterned into strips extending along a first direction, wherein the upper part of the patterned substrate forms fins; The fins are thinned to reduce their width in the second direction intersecting the first direction; An isolation layer is formed on the substrate, the isolation layer covering the fin; The isolation layer is etched downwards to expose the upper part of the fin; A dummy barrier is formed on the isolation layer; Based on the dummy gate, the stack and the fins are etched; Lower source / drain portions are formed at opposite ends of the fin in the first direction; An inter-source / drain isolation layer is formed on the lower source / drain portion; At opposite ends of the nanosheet in the first direction, upper source / drain portions are formed; and Replace the dummy gate with a gate stack. Specifically, based on the dummy gate, etching the stack and the fins includes: A first sidewall is formed on the sidewall of the dummy gate in the first direction; Using the dummy gate and the first sidewall as a mask, the stack is etched; A second sidewall is formed on the sidewalls stacked in the first direction; and Using the dummy gate, the first sidewall, and the second sidewall as a mask, the fins are etched. In the presence of the second sidewall, the lower source / drain portion is formed by selective epitaxial growth, and the method further includes removing the second sidewall after forming the lower source / drain portion.

9. The method according to claim 8, wherein, Forming the source / drain includes: The sacrificial layer in the stack is selectively etched to make it laterally recessed at its end in the first direction, and to form an inner wall in the resulting recess. The source / drain portions are formed at opposite ends of the nanosheet in the first direction by selective epitaxial growth.

10. The method according to claim 9, wherein, Replacing the dummy gate with the gate stack includes: Remove the dummy grid and the sacrificial layer, and form a grid stack in the space resulting inside the first sidewall and the inner sidewall.

11. The method according to claim 8, wherein, The width of the thinned fin in the second direction is 1 nm to 50 nm.

12. The method according to claim 8, wherein, The downward etching depth of the isolation layer is 3 nm to 500 nm, and the width in the second direction is 3 nm to 20 μm.

Images