Data processing method of control chip of inverter and inverter

Abstract

The application relates to a data processing method of a control chip of an inverter and the inverter. The first control chip and the second control chip of the inverter share one storage device, and the two communicate with each other. In the case that the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, target data of the first control chip is received by the second control chip and stored into the storage device. In the case that the second control chip detects that the first control chip is in the power-on state, a data reading instruction is sent to the first control chip, and the first control chip is instructed to obtain the target data from the storage device. The first control chip receives and responds to the data reading instruction, and obtains the target data from the storage device. The problem that, in the related art, the control chip of the inverter is provided with a special storage device, and in some working conditions, part of the control chip is powered on, so that it is difficult to save the data of the control chip which is not powered on, is solved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing method for an inverter control chip and an inverter. Background Technology

[0002] Inverters have complex functions and a large number of user-configurable parameters. To prevent the loss of these parameters after a power outage, they need to be saved to an EEPROM (a type of electrically erasable programmable non-volatile memory chip that does not lose data after a power outage). The data can then be recovered from the EEPROM after power is restored.

[0003] Inverter control chips (MCUs) generally come in two types: one primarily implements the inverter's control algorithm, and the other primarily implements the inverter's communication functions. Different control chips have different power supply methods; some can be powered by DC input, some by AC input, and some by both DC and AC input.

[0004] This leads to a situation where, under certain operating conditions, it is not possible to power on all control chips, but some control chips can be powered on. If, at this time, some parameters that need to be stored by the unpowered control chips are input through the powered-on control chips, they cannot be stored effectively, resulting in parameter loss. Alternatively, the parameters of the unpowered control chips may be inconsistent with those of the powered-on control chips after powering on.

[0005] In related technologies, the control chips of inverters are equipped with dedicated storage devices. However, under certain operating conditions, some control chips are powered on, making it difficult to save the data of the control chips that are not powered on. This is a technical problem that needs to be solved in this field. Summary of the Invention

[0006] The present invention provides a data processing method for the control chip of an inverter and an inverter, which at least solves the problem in the related art that the control chip of the inverter is equipped with a dedicated storage device, and under some operating conditions, it is difficult to save the data of the control chip that is not powered on when some control chips are powered on.

[0007] This invention provides a data processing method for an inverter control chip, comprising: when a first control chip of the inverter is in a power-off state and a second control chip is in a power-on state, the second control chip receives target data from the first control chip and stores it in a storage device, wherein the power supply methods of the first control chip are fewer than those of the second control chip, and the storage device is accessed by both the first and second control chips; when the second control chip detects that the first control chip is in a power-on state, it sends a data read instruction to the first control chip, wherein the data read instruction instructs the first control chip to retrieve the target data from the storage device; the first control chip receives and responds to the data read instruction, retrieves the target data from the storage device, and after the target data is retrieved, sends a data read completion instruction to the second control chip.

[0008] The beneficial effects of this invention are as follows: A second control chip with multiple power supply options stores the target data in a storage device. When the first control chip with fewer power supply options is powered off, the second control chip receives the target data from the first control chip and stores it in the storage device. When the first control chip is detected to be powered on, a data read command is sent to the first control chip, instructing it to retrieve the target data from the storage device. This ensures that the storage of the target data is performed by the second control chip, guaranteeing data storage even if the first control chip loses power. After the first control chip powers on, the target data can be successfully read from the storage device. This addresses the problem in related technologies where inverter control chips have dedicated, independent storage devices. In some operating conditions, when some control chips are powered on, it is difficult to save data from the unpowered control chips.

[0009] As an optional embodiment, when the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, before the second control chip receives the target data from the first control chip and stores it in the storage device, the method further includes: the second control chip periodically sending a power-on command to the first control chip, wherein the power-on command is used to detect whether the first control chip is in a power-on state; when the first control chip is in a power-on state, receiving and responding to the power-on command sent by the second control chip, and sending a feedback message to the second control chip; when the second control chip receives the feedback message, determining that the first control chip is in a power-on state; when the second control chip does not receive the feedback message within a preset time period, determining that the first control chip is in a power-off state, and continuing to periodically send a power-on command to the first control chip.

[0010] The second control chip periodically sends a power-on command to the first control chip. The first control chip determines whether the second control chip is powered on based on whether it receives the power-on command from the second control chip. When the first control chip is powered on, it receives and responds to the power-on command sent by the second control chip and sends a feedback message to the second control chip. The second control chip can detect whether the first control chip is powered on based on whether it receives the feedback message.

[0011] As an optional embodiment, the first control chip receives and responds to the data read instruction, obtains the target data from the storage device, and sends a data read completion instruction to the second control chip after the target data is read. This includes: the first control chip receives and responds to the data read instruction, obtains the target data from the storage device; the first control chip performs corresponding data operations based on the read target data; and after the data operations of the first control chip are completed, it sends a data read completion instruction to the second control chip.

[0012] After the first control chip responds to the data read instruction and completes the data operation on the target data, it sends a data read completion instruction to the second control chip. Only after receiving the data read completion instruction can the second control chip perform subsequent write and read operations on the storage device.

[0013] As an optional embodiment, the method further includes: when the first control chip is power-on initialized, it directly reads historical target data that the first control chip did not read before the last power failure from the inverter's storage device; the first control chip enters the power-on state after power-on initialization is completed.

[0014] During power-on initialization, the first control chip can directly read historical target data from the storage device to successfully obtain the historical target data that was not read during the power-down period and perform initialization. This ensures that the target data that should have been obtained during the power-down period can be obtained after power-on, thus guaranteeing data consistency between the first and second control chips.

[0015] As an optional embodiment, the method further includes: when both the first control chip and the second control chip of the inverter are powered on, controlling the first control chip to perform power-on initialization first; after the first control chip completes power-on initialization, sending a read completion command to the second control chip; after receiving the read completion command, the second control chip starts power-on initialization and reads the historical target data stored before the last power failure from the storage device.

[0016] Both the first and second control chips are powered on. The second chip needs to first read historical target data for initialization, and then the first control chip, based on the data read completion instruction, reads historical target data for initialization. This is to avoid the first control chip initializing first, which could affect the data reading for the second control chip's initialization.

[0017] As an optional embodiment, when the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, receiving target data from the first control chip through the second control chip and storing it in a storage device includes: the second control chip sending a read-prohibit instruction to the first control chip, wherein the read-prohibit instruction is used to instruct the first control chip to prohibit reading from the storage device; the second control chip writing the target data into the storage device; and after the target data is successfully written, the second control chip sending a read-enabled instruction to the first control chip, wherein the read-enabled instruction is used to instruct the first control chip to release the read-prohibit instruction on the storage device.

[0018] When the second control chip stores the target data, it first sends a read-prohibit command to the first control chip, and then sends a read-allow command to the first control chip after successful writing. This avoids errors caused by interference from the first control chip during the writing of target data to the second control chip.

[0019] As an optional embodiment, before the second control chip writes the target data into the storage device, the method further includes: receiving the target data through an interaction device of the second control chip; the second control chip performing anomaly detection on the target data; and, if the target data is detected as normal, executing the step of the second control chip writing the target data into the storage device.

[0020] Anomaly detection is performed on the target data. If the target data is found to be normal, the target data is stored on a storage device to improve the storage security of the target data.

[0021] As an optional embodiment, the first control chip is powered by DC power, and the second control chip is powered by both DC and AC power.

[0022] The second control chip is compatible with both DC and AC power supplies, allowing it to operate normally under various inverter operating conditions and ensuring the reception of target data. The first control chip is DC powered and may experience power loss in some situations, but it can still receive target data through the second control chip.

[0023] As an optional embodiment, the first control chip is a digital signal processing chip (DSP), and the second control chip is an ARM chip.

[0024] This invention provides an inverter, including: a storage device, a first control chip, and a second control chip. The first control chip and the second control chip are connected via communication pins for data communication according to a set communication method. Both the first control chip and the second control chip are connected to the storage device. The first control chip is used to receive and respond to a data read command when powered on, to obtain the target data from the storage device, and to send a data read completion command to the second control chip after the target data is read. The first control chip has fewer power supply options than the second control chip. The storage device is accessed by both the first and second control chips. The second control chip is used to receive the target data from the first control chip and store it in the storage device when the first control chip is powered off. When the first control chip is detected to be powered on, the second control chip sends a data read command to the first control chip, wherein the data read command instructs the first control chip to obtain the target data from the storage device.

[0025] This invention provides an electronic device, including: a processor, and a memory storing a program, the program including instructions that, when executed by the processor, cause the processor to perform the method according to any one of the preceding descriptions.

[0026] This invention provides a non-transitory machine-readable medium storing computer instructions for causing the computer to perform the method according to any one of the preceding descriptions.

[0027] Details of one or more embodiments of the present invention are set forth in the following drawings and description, so that other features, objects and advantages of the invention will be more readily understood. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the control chip and storage device of the inverter based on related technologies.

[0030] Figure 2This is a schematic diagram of the control chip and storage device of the inverter according to an embodiment of the present invention.

[0031] Figure 3 This is a flowchart of a data processing method for the control chip of an inverter according to an embodiment of the present invention.

[0032] Figure 4 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the data processing flow of the DSP control chip of the inverter in an embodiment of the present invention.

[0034] Figure 6 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention.

[0035] Figure 7 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention.

[0036] Figure 8 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of the data processing flow of the ARM control chip of the inverter in an embodiment of the present invention.

[0038] Figure 10 This is a schematic diagram of the circuit structure of the DSP and ARM of the inverter in an embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram of an inverter according to an embodiment of the present invention.

[0040] Figure 12 This is a schematic diagram of the structure of the electronic device in this embodiment. Detailed Implementation

[0041] Embodiments of this embodiment will now be described in more detail with reference to the accompanying drawings. While some embodiments of this embodiment are shown in the drawings, it should be understood that this embodiment can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this embodiment. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of this embodiment.

[0042] An inverter's controller MCU typically has two data chips: a DSP chip and an ARM chip. The DSP chip primarily implements the inverter's control algorithm, while the ARM chip mainly handles the inverter's communication functions. The DSP chip is powered by the DC input, while the ARM chip is powered by both DC and AC inputs. Key parameters of the DSP chip are stored in its EEPROM memory, and key parameters of the ARM chip are stored in their respective EEPROM memory. When the inverter is only connected to AC power (due to insufficient PV in the grid-connected unit or the energy storage unit's battery being in sleep mode), the ARM chip can function normally, but the DSP chip cannot. If the user sets parameters for the inverter in this situation, ARM-related parameters can be set and saved correctly, but DSP-related parameters cannot.

[0043] If the inverter parameters set by the user cannot be saved to their respective EEPROM storage chips in real time, the inverter will not be able to read the user-set parameters when powered on, resulting in a discrepancy between the system's operating mode and the user's settings, and thus failing to meet the user's requirements.

[0044] Figure 1 These are schematic diagrams of the control chip and storage device of the inverter, such as... Figure 1 As shown, when the inverter has no DC input and is only connected to AC power, the DSP chip will lose power, causing the data that the user sets and needs to be stored in the EEPROM on the DSP side to be lost.

[0045] To address the problem in related technologies where inverter control chips have dedicated storage devices, and under certain operating conditions, some control chips are powered on, making it difficult to retain data from the unpowered control chips, this embodiment provides a data processing method for inverter control chips. The structure of the inverter's control chip and storage device is improved, enabling communication between the control chips and allowing them to share a single storage device. When some control chips are powered on, the powered-on control chips store the data, which is then retrieved when the unpowered control chips are powered on.

[0046] Figure 2 This is a schematic diagram of the control chip and storage device of the inverter according to an embodiment of the present invention, as shown below. Figure 2 As shown, the DSP chip and ARM chip still use electrical isolation. The difference from the old technical solution is that the EEPROM storage chip on the DSP side is removed, and a communication circuit module is added (those already present on the DSP and ARM do not need to be added separately). For example, an SCI communication circuit or an SPI communication circuit, etc.

[0047] When the inverter is powered on for the first time on both the DC and AC sides, both the DSP and ARM chips are powered. The DSP reads data from the EEPROM and initializes the variables. After reading is complete, it sends a read completion status to the ARM, which then reads data from the EEPROM. The machine then starts up and runs normally.

[0048] The inverter's DC side is powered, and both the DSP chip and the ARM chip are powered. At this time, the user sets the inverter parameters. After receiving the user's settings, the ARM first sends an EEPROM write command to prevent the DSP from reading the EEPROM. Then, the ARM writes the parameters to the EEPROM and saves them. After saving, it sends a read-enabled command to the DSP, which reads the data of the corresponding page and updates it.

[0049] After the ARM processor powers on, it sends a power-on command to the DSP via the communication circuit. If the DSP powers on, the ARM processor receives a feedback message from the DSP, and thus knows that the DSP has powered on. Similarly, if the DSP receives a power-on command from the ARM processor after powering on, it knows that the ARM processor has powered on; otherwise, it does not.

[0050] The ARM processor acts as the master because it's primarily responsible for processing user settings. By acting as the master, the ARM can detect when the user has completed the setup process. When the ARM writes data to the EEPROM, it needs to send a read-disable instruction to the DSP. Upon receiving this instruction, the DSP will not attempt to read from the EEPROM.

[0051] When the inverter's DC side is de-energized but the AC side is energized, only the ARM chip is operational, and communication between the ARM and DSP is lost. If the user sets inverter parameters at this time, the ARM chip receives the settings and saves them in the EEPROM.

[0052] When the DC side is powered on again, the DSP reads data from the EEPROM and initializes the variables. After reading is complete, it sends a read completion status to the ARM, which then reads data from the EEPROM. The machine then powers on and runs normally.

[0053] When the inverter's DC side is de-energized but the AC side is energized, and the user sets the inverter parameters, the ARM processor receives the user's settings and saves them in the EEPROM. If the AC side then loses power, the user's settings, already saved in the EEPROM, will not affect the machine's ability to read correct data from the previous power-on.

[0054] This allows the user-set parameters to be saved in the EEPROM when the inverter is being edited, regardless of whether there is power on the DSP side, thus solving related technical problems and product defects.

[0055] Figure 3 This is a flowchart of a data processing method for the control chip of an inverter according to an embodiment of the present invention, such as... Figure 3 As shown, this embodiment of the invention provides a data processing method for an inverter control chip, applied to a first control chip with fewer power supply options, including the following steps:

[0056] In step S301, when the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, the second control chip receives the target data of the first control chip and stores it in the storage device. The first control chip has fewer power supply methods than the second control chip, and the storage device is used for access by the first control chip and the second control chip.

[0057] In step S302, when the second control chip detects that the first control chip is powered on, it sends a data read instruction to the first control chip, wherein the data read instruction is used to instruct the first control chip to obtain target data from the storage device.

[0058] In step S303, the first control chip receives and responds to the data read instruction, retrieves the target data from the storage device, and sends a data read completion instruction to the second control chip after the target data is read.

[0059] The beneficial effects of this invention are as follows: A second control chip with multiple power supply options stores the target data in a storage device. When the first control chip with fewer power supply options is powered off, the second control chip receives the target data from the first control chip and stores it in the storage device. When the first control chip is detected to be powered on, a data read command is sent to the first control chip, instructing it to retrieve the target data from the storage device. This ensures that the storage of the target data is performed by the second control chip, guaranteeing data storage even if the first control chip loses power. After the first control chip powers on, the target data can be successfully read from the storage device. This addresses the problem in related technologies where inverter control chips have dedicated, independent storage devices. In some operating conditions, when some control chips are powered on, it is difficult to save data from the unpowered control chips.

[0060] The first control chip, which offers fewer power supply options, could be a DSP chip in an inverter, and DSPs only support DC power. The second control chip offers more power supply options than the first; for example, it could be an ARM chip in an inverter. It provides both DC and AC power.

[0061] The first and second control chips mentioned above can be powered on together under compatible power supply methods. Under some power supply methods unique to the first control chip, the second control chip will be powered off, and under some power supply methods unique to the second control chip, the first control chip will be powered off.

[0062] This embodiment addresses the problem in related technologies where inverter control chips all use dedicated, independent storage devices. It connects the first and second control chips communicatively, allowing them to share the same storage device. This ensures the reception and storage of target data in various scenarios, including when both the first and second control chips are powered on, or when the first control chip is powered on and the second control chip is powered off, or vice versa. Furthermore, it allows for timely and effective data updates after the powered-off control chip is powered on.

[0063] The power supply method described above can be DC power supply or AC power supply. In this embodiment, the first control chip only supports DC power supply or AC power supply, while the second control chip can support both DC power supply and AC power supply. Therefore, when the second control chip is powered on, the first control chip may be powered on or powered off.

[0064] When the second control chip is powered off, the first control chip is also powered off. This facilitates control, with the second control chip primarily handling the reception and storage of target data. The first control chip acquires target data using different methods depending on the power-on conditions.

[0065] When the inverter's second control chip is powered on, the inverter's interactive device generates target data through user operation and sends it to the second control chip for reception. After receiving the target data, the second control chip stores the target data in the inverter's storage device.

[0066] Regardless of whether the first control chip is powered on, the second control chip can receive and store the target data once it is powered on. If the first control chip is powered on, the second control chip generates a data read command based on the target data and sends it to the first control chip, instructing it to read the new target data. If the first control chip is not powered on, the target data is stored in a storage device, waiting to be read by the first control chip after it is powered on.

[0067] That is, when it is confirmed that the first control chip is powered on, a data read command is sent to the first control chip. The data read command is used to instruct the first control chip to read the target data from the inverter.

[0068] The power-on state includes power-on initialization, which means that after power-on, both the first and second control chips need to be initialized to synchronize the target data generated during their power-off period and ensure data consistency. Specific initialization operations include data synchronization, program startup, parameter settings, etc. In this embodiment, the power-on initialization is mainly for data synchronization.

[0069] During the initialization of the first control chip, regardless of whether the second control chip is powered on, historical target data is directly retrieved from the storage device for initialization. However, if the second control chip is powered on, the first control chip can receive and store target data, and can also instruct the first control chip to read target data. If the second control chip is powered on but not on, the first control chip cannot receive new target data, and therefore cannot read new target data; it can wait for the second control chip to power on.

[0070] In other embodiments, the first control chip may be configured to receive and store target data in place of the second control chip when the second control chip is not powered on.

[0071] In this embodiment, since the first control chip only supports DC or AC power supply, while the second control chip supports both DC and AC power supply, the second control chip will also power on when the first control chip is powered on. The difference lies in whether the second control chip is in a power-on initialization state or a state after power-on initialization is complete. Therefore, the first control chip does not need to receive and store target data in place of the second control chip when the second control chip is not powered on.

[0072] After the first control chip completes its power-on initialization, and assuming the second control chip of the inverter is powered on, it receives a data read command from the second control chip. That is, while the second control chip is powered on, it receives and stores the target data. After storing the target data, it sends a data read command to the first control chip, instructing the first control chip to read the newly stored target data.

[0073] At this point, the first control chip will respond to the data read command and read the target data corresponding to the data read command from the inverter's storage device. This target data can be user-set data, updated data, etc. After reading the target data, the first control chip can perform data synchronization, data update, and other operations to improve data consistency.

[0074] After the first control chip finishes reading the target data, it sends a data reading completion command to the second control chip, instructing the second control chip to continue receiving and storing the target data.

[0075] It should be noted that the aforementioned storage devices can be non-volatile storage media. Before a power outage, the stored data will be saved, and upon power-on, the data will be restored to its previous state, ensuring that no data is lost. For example, the EEPROM storage chip in an inverter.

[0076] The aforementioned storage device exchanges data with the first control chip and the second control chip through a serial communication channel. Only one device is allowed to perform read and write operations on the storage device at a time. Therefore, after the first control chip completes the read operation, it needs to send a read completion command to notify the second control chip so that the second control chip can perform subsequent operations.

[0077] Figure 4 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention, such as... Figure 4 As shown, in an optional embodiment, when the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, before receiving the target data from the first control chip through the second control chip and storing it in the storage device, the method further includes:

[0078] Step S401: The second control chip periodically sends a power-on command to the first control chip, wherein the power-on command is used to detect whether the first control chip is in a power-on state.

[0079] Step S402: When the first control chip is powered on, receive and respond to the power-on command sent by the second control chip, and send a feedback message to the second control chip.

[0080] Step S403: When the second control chip receives the feedback message, it determines that the first control chip is in the power-on state.

[0081] In step S404, if the second control chip does not receive a feedback message within a preset time period, it determines that the first control chip is in a power-off state and continues to send power-on commands to the first control chip periodically.

[0082] The second control chip periodically sends a power-on command to the first control chip. The first control chip determines whether the second control chip is powered on based on whether it receives the power-on command from the second control chip. When the first control chip is powered on, it receives and responds to the power-on command sent by the second control chip and sends a feedback message to the second control chip. The second control chip can detect whether the first control chip is powered on based on whether it receives the feedback message.

[0083] When the second control chip determines whether the first control chip is in a powered-on state, it can send a power-on command to the first control chip; if it receives a feedback message from the first control chip responding to the power-on command, it determines that the first control chip is in a powered-on state; if it does not receive a feedback message from the first control chip responding to the power-on command, it sends a power-on command to the first control chip at a preset frequency.

[0084] The second control chip sends a power-on command to the first control chip. Whether the first control chip is powered on is determined by whether a feedback message responding to the power-on command is received from the second control chip. Only when the second control chip is powered on can it send data read commands to the first control chip.

[0085] The second control chip determines whether the first control chip is powered on by sending a power-on command to the first control chip and whether it receives a feedback message for the power-on command. If the second control chip receives a feedback message for the power-on command sent by the first control chip, it determines that the first control chip is powered on; if it does not receive a feedback message for the power-on command sent by the first control chip, it determines that the first control chip is not powered on.

[0086] It should be noted that the power-on time of the first control chip cannot be determined. The second control chip, as the host, will continuously send power-on commands to the first control chip at a preset frequency after power-on, and determine whether the first control chip is powered on based on whether the first control chip replies with feedback information.

[0087] For the first control chip, whether the second control chip is powered on can be determined by whether a power-on command has been received. If a power-on command is received for the second control chip, it is determined that the second control chip is powered on; if no power-on command is received for the second control chip, it is determined that the second control chip is not powered on.

[0088] The second control chip acts as the host. After power-on, it continuously sends power-on commands to the first control chip and determines whether the first control chip is powered on based on whether the first control chip replies with feedback information.

[0089] Upon receiving a power-on command from the second control chip, the first control chip determines that the second control chip is powered on and sends a feedback message to the second control chip. The feedback message is used to inform the second control chip that the first control chip has been powered on.

[0090] After receiving the power-on command, the first control chip sends a feedback message to the second control chip to inform the second control chip that the first control chip has been powered on. This allows the second control chip to send a corresponding data read command after storing the target data in the storage device, instructing the first control chip to read the target data.

[0091] As an optional embodiment, the first control chip receives and responds to a data read instruction, retrieves target data from the storage device, and sends a data read completion instruction to the second control chip after the target data is read. Alternatively, the first control chip can receive and respond to the data read instruction and retrieve the target data from the storage device. The first control chip performs corresponding data operations based on the read target data. After the data operations of the first control chip are completed, it sends a data read completion instruction to the second control chip.

[0092] After the first control chip responds to the data read command and completes the data operation on the target data, it sends a data read complete command to the second control chip. Only after receiving the data read complete command can the second control chip perform subsequent write and read operations on the storage device.

[0093] When the first control chip finishes reading the target data and sends a data reading completion command to the second control chip, it can perform corresponding data operations based on the read target data; after the data operations are completed, it sends a data reading completion command to the second control chip.

[0094] After completing the data operation on the target data, a data read completion command is sent to the second control chip. Only after receiving the data read completion command can the second control chip perform subsequent write and read operations on the storage device.

[0095] The target data mentioned above can be updated data, and the data operation mentioned above can be a data update operation. After the update operation is completed, a data read completion command is sent to the second control chip.

[0096] Figure 5 This is a schematic diagram of the data processing flow of the DSP control chip of the inverter according to an embodiment of the present invention, as shown below. Figure 4 As shown, in the inverter, the DSP control chip determines whether it is the first time powering on after the user sets the data.

[0097] If it is the first time powering on, the historical target data in the EEPROM is read directly, and the parameters that need to be updated are read based on the historical target data to perform initialization. After the reading is completed, a read completion command is sent to the ARM control chip.

[0098] If it is not the first time powering on, it receives the data read instruction sent by the ARM, and reads the target data from the corresponding page number in the EEPROM according to the data read instruction. After the reading is completed, it sends a read completion instruction to the ARM control chip.

[0099] Figure 6 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention, such as... Figure 6 As shown, as an optional embodiment, the method further includes:

[0100] In step S601, when the first control chip is initialized upon power-on, it directly reads the historical target data that the first control chip did not read before the last power failure from the inverter's storage device.

[0101] Step S602: After the first control chip completes the power-on initialization, it enters the power-on state.

[0102] During power-on initialization, the first control chip can directly read historical target data from the storage device to successfully obtain the historical target data that was not read during the power-down period and perform initialization. This ensures that the target data that should have been obtained during the power-down period can be obtained after power-on, thus guaranteeing data consistency between the first and second control chips.

[0103] When the first control chip is powered on and initialized, the historical target data that the first control chip did not read before the last power failure is directly read from the inverter's storage device.

[0104] During power-on initialization, the first control chip can directly read historical target data from the storage device to successfully obtain the historical target data that was not read during the power-down period and perform initialization. This ensures that the target data that should have been obtained during the power-down period can be obtained after power-on, thus guaranteeing data consistency between the first and second control chips.

[0105] Since the second control chip provides the function of receiving and storing target data, even if the first and second control chips are powered on simultaneously, the first control chip must read the historical target data first. This is because if the second control chip powers on first and writes new target data, it may affect the historical target data stored in the storage device. Therefore, during power-on initialization, the first control chip directly reads the historical target data from the storage device.

[0106] When the second control chip is powered on and initialized, it can be determined whether the first control chip is powered on. If the first control chip is determined to be powered on, a read completion instruction is received from the first control chip, and the historical target data stored before the last power failure is read from the storage device.

[0107] When the second control chip is powered on and initialized, if the first control chip is powered on, after the first control chip completes reading the historical target data in the storage device, it receives the read completion instruction, then reads the historical target data from the storage device and performs initialization.

[0108] Since the second control chip provides the function of receiving and storing target data, even if the first and second control chips are powered on simultaneously, the first control chip must read the historical target data first. This is because if the second control chip powers on first and writes new target data, it may affect the historical target data stored in the storage device. Therefore, during power-on initialization, the first control chip directly reads the historical target data from the storage device.

[0109] Therefore, when the second control chip is powered on and initialized, the second control chip will determine whether the first control chip is powered on. If it is determined that the first control chip is powered on, it will receive the read completion instruction sent by the first control chip and read the historical target data stored before the last power failure from the storage device.

[0110] If it is determined that the first control chip is not powered on, the historical target data stored before the last power failure is read directly from the storage device for initialization.

[0111] Figure 7 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention, such as... Figure 7 As shown, as an optional embodiment, the method further includes:

[0112] Step S701: When both the first control chip and the second control chip of the inverter are powered on, control the first control chip to perform power-on initialization first.

[0113] Step S702: After the first control chip is powered on and initialized, a read completion command is sent to the second control chip.

[0114] In step S703, after receiving the read completion instruction, the second control chip begins power-on initialization and reads the historical target data stored before the last power failure from the storage device.

[0115] Both the first and second control chips are powered on. The second chip needs to first read historical target data for initialization, and then the first control chip, based on the data read completion instruction, reads historical target data for initialization. This is to avoid the first control chip initializing first, which could affect the data reading for the second control chip's initialization.

[0116] When the first control chip and the second control chip are powered on simultaneously, after receiving the read completion instruction sent by the first control chip, the second control chip reads the historical target data from the storage device and performs initialization.

[0117] When the second control chip is in power-on initialization, the first control chip powers on, indicating that both the first and second control chips are being powered on for the first time. The second control chip needs to read the historical target data for initialization first, and then the first control chip reads the historical target data for initialization based on the data read completion instruction.

[0118] If the first control chip is not being powered on for the first time, then the second control chip is in a powered-on state, and the first control chip can directly read the historical target data stored before the last power failure for initialization.

[0119] It should be noted that in this embodiment, the power supply method of the first control chip is less than that of the second control chip. During the power-on period of the second control chip, the first control chip may power on and off multiple times. In the case that the first control chip is the first power-on during the current power-on period of the second control chip, after receiving the data read completion instruction, the second control chip reads the historical target data from the storage device and initializes the second control chip.

[0120] If the first control chip is not the first power-on during the current power-on period of the second control chip, the historical target data stored before the last power-off is directly read from the storage device to initialize the second control chip. Then, after the second control chip is initialized, it waits for the input of target data before storing the target data.

[0121] Figure 8 This is a flowchart of a data processing method for the control chip of an inverter according to another embodiment of the present invention, such as... Figure 8 As shown, in an optional embodiment, when the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, the second control chip receives the target data from the first control chip and stores it in a storage device, including:

[0122] Step S801: The second control chip sends a read-prohibit instruction to the first control chip, wherein the read-prohibit instruction is used to instruct the first control chip to prohibit reading from the storage device;

[0123] In step S802, the second control chip writes the target data into the storage device;

[0124] In step S803, after the target data is successfully written, the second control chip sends a readable instruction to the first control chip, wherein the readable instruction is used to instruct the first control chip to release the prohibition on reading the storage device.

[0125] When the second control chip stores the target data, it first sends a read-prohibit command to the first control chip, and then sends a read-allow command to the first control chip after successful writing. This avoids errors caused by interference from the first control chip during the writing of target data to the second control chip.

[0126] When the second control chip stores the target data into the inverter's storage device, it sends a read-prohibit command to the first control chip. The read-prohibit command instructs the first control chip to prohibit reading from the storage device. After successfully writing the target data into the storage device, the second control chip sends a read-allow command to the first control chip. The read-allow command instructs the first control chip to lift the read-prohibit command on the storage device.

[0127] When storing target data, the second control chip first sends a read-prohibit command to the first control chip, and then sends a read-allow command after successful writing. This avoids errors caused by interference from the first control chip during the target data writing process.

[0128] The aforementioned storage device exchanges data with the first control chip and the second control chip through a serial communication channel. Only one device is allowed to perform read and write operations on the storage device at a time during serial communication.

[0129] Therefore, when writing target data, the system first sends a read-prohibit command to the first control chip, instructing it to prohibit reading from the storage device. Then, after successfully writing the target data into the storage device, it sends a read-allow command to the first control chip, instructing it to release the read-prohibit command. This completes the operation of writing the target data into the storage device.

[0130] As an optional embodiment, before the second control chip writes the target data into the storage device, the method further includes: receiving the target data through an interaction device of the second control chip; the second control chip performing anomaly detection on the target data; and if the target data is detected as normal, executing the step of the second control chip writing the target data into the storage device.

[0131] Anomaly detection is performed on the target data. If the target data is found to be normal, the target data is stored on a storage device to improve the storage security of the target data.

[0132] Figure 9 This is a schematic diagram of the data processing flow of the ARM control chip in the inverter according to an embodiment of the present invention, as shown below. Figure 7 As shown, in the inverter, after receiving the target data set by the user, the ARM control chip determines whether the parameter range of the target data is normal. If it is not normal, it may not store the data or update the corresponding parameters in the storage device.

[0133] If everything is normal, the target data is written to the corresponding page number, which is the corresponding storage location in the storage device. Then, the updated parameters are read, and a data read instruction is generated to instruct the DSP control chip to read the updated parameters, which means reading the target data from the EEPROM.

[0134] Before the second control chip stores the target data in the inverter's storage device, it can perform anomaly detection on the target data; if the target data is found to be normal, then the target data is stored in the inverter's storage device.

[0135] Anomaly detection is performed on the target data. If the target data is found to be normal, the target data is stored on a storage device to improve the storage security of the target data.

[0136] The aforementioned anomaly detection can include permission checks, security authentication, parameter range checks, etc.

[0137] As an optional embodiment, the first control chip is powered by DC power, and the second control chip is powered by both DC and AC power.

[0138] The second control chip is compatible with both DC and AC power supplies, allowing it to operate normally under various inverter operating conditions and ensuring the reception of target data. The first control chip is DC powered and may experience power loss in some situations, but it can still receive target data through the second control chip.

[0139] Figure 10 This is a schematic diagram of the circuit structure of the DSP and ARM of the inverter in an embodiment of the present invention, as shown below. Figure 10 As shown, in one optional embodiment, the first control chip is a digital signal processing chip (DSP), and the second control chip is an ARM chip.

[0140] exist Figure 10 In this diagram, U1 is the ARM chip, U2 is the DSP chip, U3 is the chip select chip, U4 is the isolation chip, and U5 is the EEPROM memory chip. VCC is the power supply, R1 to R6 are current-limiting resistors for the circuits between the ARM and DSP chips and the memory chip, R7 to R10 are pull-up resistors, and R11 to R14 are current-limiting resistors for the communication circuits between the ARM and DSP chips.

[0141] Since the ARM chip and DSP chip communicate serially with the memory chip, meaning that only the ARM chip or the DSP chip can access the memory chip at a time, the U3 chip is set as a chip select chip between the ARM chip and the memory chip to select whether the ARM chip or the DSP chip is accessing the memory chip.

[0142] The ARM chip and DSP chip can communicate via the receive pin RXD and the transmit pin TXD, combined with relevant communication protocols such as SCI and SPI. The intermediate isolation chip, part of the inverter's own circuit structure, is used to isolate the ARM chip and the DSP chip.

[0143] Figure 11 This is a schematic diagram of an inverter according to an embodiment of the present invention, such as... Figure 11 As shown, an embodiment of the present invention provides an inverter, including: a storage device 111, a first control chip 112, and a second control chip 113.

[0144] The communication pins of the first control chip 112 and the second control chip 113 are connected for data communication according to a set communication mode. Both the first control chip 112 and the second control chip 113 are connected to the storage device 111. The first control chip 112 is used to receive and respond to data read commands when powered on, and to obtain target data from the storage device 111. After the target data is read, it sends a data read completion command to the second control chip 113. The power supply of the first control chip 112 is less than that of the second control chip 113. The storage device 111 is used for access by both the first control chip 112 and the second control chip 113. The second control chip 113 is used to receive the target data from the first control chip 112 when the first control chip 112 is powered off, and to store it in the storage device 111. When the first control chip 112 is detected to be powered on, the second control chip 113 sends a data read command to the first control chip 112, which instructs the first control chip 112 to obtain the target data from the storage device 111.

[0145] The beneficial effects of this invention are as follows: A second control chip with multiple power supply options stores the target data in a storage device. When the first control chip with fewer power supply options is powered off, the second control chip receives the target data from the first control chip and stores it in the storage device. When the first control chip is detected to be powered on, a data read command is sent to the first control chip, instructing it to retrieve the target data from the storage device. This ensures that the storage of the target data is performed by the second control chip, guaranteeing data storage even if the first control chip loses power. After the first control chip powers on, the target data can be successfully read from the storage device. This addresses the problem in related technologies where inverter control chips have dedicated, independent storage devices. In some operating conditions, when some control chips are powered on, it is difficult to save data from the unpowered control chips.

[0146] As an optional embodiment, the first control chip 112 and the second control chip 113 are connected via an SCI communication circuit or an SPI communication circuit.

[0147] As an optional embodiment, the SCL pins of the first control chip 112 and the second control chip 113 are connected, and the SDA pins are also connected, with the storage device connected in parallel between the SCL and SDA pins to form a serial communication mode. A chip select chip is provided between the first control chip 112, the second control chip 113, and the storage device to perform serial communication and avoid communication confusion and interference.

[0148] As an optional embodiment, an electrical isolation circuit is provided between the first control chip 112 and the second control chip 113. For example, an isolation chip.

[0149] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the method of this invention.

[0150] The present invention also provides a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the method of the present invention.

[0151] This invention also provides a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the method of this invention.

[0152] refer to Figure 12The present invention will now describe a structural block diagram of an electronic device that can serve as a server or client in embodiments of the present invention, which is an example of a hardware device that can be applied to various aspects of the present invention. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0153] like Figure 12 As shown, the electronic device includes a computing unit 1201, which can make decisions based on data stored in a read-only memory (ROM).

[0154] The computer program in 1202 or the computer program loaded from storage unit 1208 into random access memory (RAM) 1203 performs various appropriate actions and processes. RAM 1203 may also store various programs and data required for the operation of the electronic device. The computing unit 1201, ROM 1202, and RAM 1203 are interconnected via bus 1204. Input / output (I / O) interface 1205 is also connected to bus 1204.

[0155] Multiple components in the electronic device are connected to the I / O interface 1205, including: an input unit 1206, an output unit 1207, a storage unit 1208, and a communication unit 1209. The input unit 1206 can be any type of device capable of inputting information into the electronic device. The input unit 1206 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device. The output unit 1207 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. The storage unit 1208 may include, but is not limited to, a hard disk and an optical disk. The communication unit 1209 allows the electronic device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, a modem, network card, infrared communication device, wireless communication transceiver, and / or chipset, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0156] The computing unit 1201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, CPUs, graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. The computing unit 1201 performs the various methods and processes described above. For example, in some embodiments, the method embodiments of the present invention may be implemented as a computer program tangibly contained in a machine-readable medium, such as storage unit 1208. In some embodiments, part or all of the computer program may be loaded and / or installed on an electronic device via ROM 1202 and / or communication unit 1209. In some embodiments, the computing unit 1201 may be configured to perform the methods described above by any other suitable means (e.g., by means of firmware).

[0157] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0158] In the context of embodiments of the present invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0159] It should be noted that the term "comprising" and its variations used in the embodiments of the present invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "multiple" mentioned in the embodiments of the present invention are illustrative and not restrictive. Those skilled in the art should understand that, unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0160] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0161] The steps described in the method embodiments provided by this invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of this invention is not limited in this respect.

[0162] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0163] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A data processing method for a control chip of an inverter, characterized in that, include: When the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, the second control chip receives the target data from the first control chip and stores it in a storage device. The first control chip has fewer power supply methods than the second control chip. The storage device is used for access by both the first and second control chips. When the second control chip detects that the first control chip is powered on, it sends a data read instruction to the first control chip, wherein the data read instruction is used to instruct the first control chip to obtain the target data from the storage device; The first control chip receives and responds to the data read instruction, retrieves the target data from the storage device, and sends a data read completion instruction to the second control chip after the target data is read.

2. The method according to claim 1, characterized in that, Before the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, and before the second control chip receives the target data from the first control chip and stores it in the storage device, the method further includes: The second control chip periodically sends a power-on command to the first control chip, wherein the power-on command is used to detect whether the first control chip is in a power-on state; When the first control chip is powered on, it receives and responds to the power-on command sent by the second control chip, and sends a feedback message to the second control chip. Upon receiving the feedback message, the second control chip determines that the first control chip is in a powered-on state. If the second control chip does not receive the feedback message within a preset time period, it determines that the first control chip is in a power-off state and continues to send power-on commands to the first control chip at regular intervals.

3. The method according to claim 1, characterized in that, The first control chip receives and responds to the data read instruction, retrieves the target data from the storage device, and sends a data read completion instruction to the second control chip after the target data is read, including: The first control chip receives and responds to the data read instruction to obtain the target data from the storage device; The first control chip performs corresponding data operations based on the read target data; After the data operation of the first control chip is completed, a data read completion command is sent to the second control chip.

4. The method according to claim 1, characterized in that, The method further includes: When the first control chip is initialized upon power-on, it directly reads the historical target data that it had not read before the last power failure from the inverter's storage device. The first control chip enters the power-on state after power-on initialization is completed.

5. The method according to claim 4, characterized in that, The method further includes: When both the first control chip and the second control chip of the inverter are powered on, the first control chip is controlled to perform power-on initialization first. After the first control chip completes its power-on initialization, it sends a read completion command to the second control chip. After receiving the read completion instruction, the second control chip begins power-on initialization and reads the historical target data stored before the last power failure from the storage device.

6. The method according to claim 1, characterized in that, When the first control chip of the inverter is in a power-off state and the second control chip is in a power-on state, the second control chip receives the target data from the first control chip and stores it in the storage device, including: The second control chip sends a read-prohibit instruction to the first control chip, wherein the read-prohibit instruction is used to instruct the first control chip to prohibit reading from the storage device; The second control chip writes the target data into the storage device; After the target data is successfully written, the second control chip sends a readable instruction to the first control chip, wherein the readable instruction is used to instruct the first control chip to release the read restriction on the storage device.

7. The method according to claim 6, characterized in that, Before the second control chip writes the target data into the storage device, the method further includes: The target data is received through the interaction device of the second control chip; The second control chip performs anomaly detection on the target data; If the target data detection is normal, the second control chip will write the target data into the storage device.

8. The method according to any one of claims 1 to 7, characterized in that, The first control chip is powered by DC power, and the second control chip is powered by both DC and AC power.

9. The method according to claim 8, characterized in that, The first control chip is a digital signal processing chip (DSP), and the second control chip is an ARM chip.

10. An inverter, characterized in that, include: Storage device, first control chip and second control chip, The first control chip and the second control chip are connected to each other via communication pins for data communication according to a set communication method. Both the first control chip and the second control chip are connected to the storage device. The first control chip is used to receive and respond to a data read command when powered on, obtain target data from the storage device, and send a data read completion command to the second control chip after the target data is read. The first control chip has fewer power supply methods than the second control chip. The storage device is used for access by both the first control chip and the second control chip. The second control chip is used to receive target data from the first control chip when the first control chip is in a power-off state and store it in a storage device; when the first control chip is detected to be in a power-on state, the second control chip sends a data read instruction to the first control chip, wherein the data read instruction is used to instruct the first control chip to retrieve the target data from the storage device.

11. An electronic device, comprising: A processor and a memory storing a program, characterized in that the program includes instructions that, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 9.

12. A non-transitory machine-readable medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 9.

Images