LDO circuit and chip with pre-charge function

Abstract

The application discloses an LDO circuit and chip with a pre-charge function, which comprises a pre-charge module, a power tube module and a voltage stabilizing module; wherein: the pre-charge module receives an enable signal and a reference voltage establishing judgment signal, and outputs a pre-charge voltage in response to the enable signal indicating that the pre-charge module is enabled and the reference voltage establishing judgment signal indicating that the reference voltage is not established, otherwise, the pre-charge module does not output the pre-charge voltage; the voltage stabilizing module receives the reference voltage establishing judgment signal, and outputs a stabilized voltage in response to the reference voltage establishing judgment signal indicating that the reference voltage is established, otherwise, the voltage stabilizing module does not output the stabilized voltage; the power tube module outputs a supply voltage based on the pre-charge voltage and the stabilized voltage; wherein, the reference voltage establishing judgment signal is generated by a biasing module, and the biasing module is powered by the supply voltage. The application accelerates the charging speed of the pre-charge module and saves the chip area by making the pre-charge module and the voltage stabilizing module share the power tube module.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more specifically to a circuit and chip for starting a DC-DC converter. Background Technology

[0002] DC / DC converters are typically used in switching power supply chips. They utilize the energy storage characteristics of capacitors and inductors, and through high-frequency switching via controllable switches (such as MOSFETs), they store the input electrical energy in the capacitors (inductors). When the switch is opened, the electrical energy is released to the load, providing power. DC / DC converters usually require a startup circuit to power on during startup.

[0003] Currently, the startup circuit of existing DC-DC converters typically includes: a pre-power-on module PREVDD, a bias module BIAS, and a low dropout regulator (LDO). The PREVDD module provides power to the LDO and the DC-DC converter's bias module BIAS; once the LDO is established, the PREVDD module is turned off. The BIAS module generates the reference voltage and reference current required by the DC-DC converter. The LDO module supplies power to relevant modules within the DC-DC converter during operation.

[0004] In existing startup circuits, the output terminals of the PREVDD module and the LDO module are typically shorted together and connected to a 4.7uF capacitor. Furthermore, the power transistors in the PREVDD module are significantly smaller than those in the LDO module. This means the charging current of the PREVDD module is much lower than that of the LDO module, resulting in a very slow charging slope for the PREVDD module and a slower build-up speed. Consequently, this leads to a longer build-up time for the LDO module. This is the fundamental reason for the longer time from receiving the enable signal to the first switching action in a DC-DC converter. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an LDO circuit and chip with pre-charge function to accelerate the charging speed of the pre-charge module, shorten the setup time of the pre-charge module, and thus save the time from the start of receiving the enable signal to the first switching action of the DC-DC converter.

[0006] The present invention adopts the following technical solution.

[0007] According to a first aspect of the present invention, an LDO circuit with a pre-charge function is provided. The circuit includes a pre-charge module, a power transistor module, and a voltage regulator module; wherein:

[0008] The pre-charge module receives an enable signal and a reference voltage establishment determination signal, and outputs a pre-charge voltage in response to the enable signal indicating that the module is enabled and the reference voltage establishment determination signal indicating that the reference voltage is not established; otherwise, it does not output a pre-charge voltage.

[0009] The voltage regulator module receives a reference voltage establishment determination signal and outputs a regulated voltage in response to the reference voltage establishment determination signal indicating that the reference voltage has been established; otherwise, it does not output a regulated voltage.

[0010] The power transistor module outputs a supply voltage based on the pre-charge voltage and the regulated voltage;

[0011] The reference voltage establishment determination signal is generated by the bias module, which is powered by the supply voltage.

[0012] Preferably, the pre-charge module includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor;

[0013] R1 and R2 are connected in series between the power supply voltage and the ground voltage;

[0014] The source of the first NMOS transistor is connected to the ground voltage via a fourth resistor, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor.

[0015] The drain of the second NMOS transistor is connected to the pre-charge voltage, and the gate of the second NMOS transistor is connected to the junction of R1 and R2.

[0016] One end of R3 is connected to the enable signal, and the other end of R3 is connected to the gate of the first NMOS transistor and the collector of the transistor.

[0017] The emitter of the transistor is connected to ground, and the base of the transistor is connected to the source of the first NMOS transistor.

[0018] The gate of the third NMOS transistor is connected to the reference voltage to establish a determination signal, and the drain and source of the third NMOS transistor are respectively connected to the gate of the first NMOS transistor and the ground voltage.

[0019] Preferably, when the enable signal indicates activation, the enable signal is at a high potential and greater than the threshold voltage of the first NMOS transistor.

[0020] Preferably, when the reference voltage establishment determination signal indicates that the reference voltage has been established, the reference voltage establishment determination signal is at a high potential and is greater than the threshold voltage of the third NMOS transistor.

[0021] Preferably, the voltage regulator module includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an amplifier;

[0022] R5 and R6 are connected in series between the supply voltage and the ground voltage;

[0023] The non-inverting input of the amplifier is connected to the junction of R5 and R6, the inverting input of the amplifier is connected to the reference voltage, the output of the amplifier is connected in series with R7 and outputs the regulated voltage, and the amplifier also has a control terminal for receiving the reference voltage establishment determination signal.

[0024] Preferably, the amplifier is enabled in response to the reference voltage establishment determination signal indicating that the reference voltage has been established, otherwise it is not enabled.

[0025] Preferably, the power transistor module includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor:

[0026] The sources of the first and second PMOS transistors are connected to the power supply voltage.

[0027] The drain of the second PMOS transistor is connected to the source of the third PMOS transistor;

[0028] The drain of the third PMOS transistor is connected to the pre-charge voltage and the regulated voltage;

[0029] The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together.

[0030] The drain of the first PMOS transistor is led out and the supply voltage is output.

[0031] Preferably, the power supply voltage is connected to the ground voltage via a capacitor.

[0032] Preferably, the LDO circuit with pre-charge function further includes an eighth resistor R8 disposed between the power supply voltage and the input terminal of the power transistor module.

[0033] According to a second aspect of the present invention, a chip is provided. The chip includes an LDO circuit with a pre-charge function as described in the first aspect of the present invention.

[0034] The beneficial effects of this invention are that, compared with the prior art, by controlling the pre-charge module and the voltage regulator module to conduct with the power transistor module before and after the reference voltage is established by the enable signal and the reference voltage establishment determination signal, respectively, the pre-charge module and the voltage regulator module can share the same large power transistor module, which greatly speeds up the charging speed of the pre-charge module; at the same time, compared with the scheme of using different power transistors for the pre-charge module and the voltage regulator module, chip area is saved. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the circuit used to start a DC-DC converter in the prior art;

[0036] Figure 2 This is a schematic diagram of the circuit structure of the precharge module used in the circuit for starting a DC-DC converter in the prior art;

[0037] Figure 3 This is a timing diagram of the setup of the precharge module and LDO in the circuit used to start a DC-DC converter in the prior art;

[0038] Figure 4 This is a schematic diagram of the LDO circuit with pre-charge function of the present invention;

[0039] Figure 5 This is the equivalent circuit diagram of the LDO circuit with pre-charge function of the present invention when the pre-charge module is working and the voltage regulator module is not working.

[0040] Figure 6 This is the equivalent circuit diagram of the LDO circuit with pre-charge function of the present invention when the pre-charge module is not working and the voltage regulator module is working;

[0041] Figure 7 This is the setup timing diagram of the LDO circuit with pre-charge function of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0043] Figure 1 This is a schematic diagram of the startup circuit of a DC-DC converter in the prior art. For example... Figure 1As shown, the startup circuit of a DC-DC converter in the prior art includes: a precharge module PREVDD, a bias module BIAS, and a low dropout linear regulator module LDO.

[0044] The PREVDD precharge module provides power to the LDO module and the BIAS bias module. Once the LDO module is established, the PREVDD module is turned off. The PREVDD module is connected to the chip's power supply voltage VIN and ground voltage VGND, respectively. It receives the enable signal EN, the bandgap reference establishment judgment signal BGOK, the enable judgment signal ENOK, and the LDO establishment status signal LDOOK, and outputs the precharge voltage.

[0045] The BIAS module is used to generate the reference voltage and reference current required by the DC-DC converter. The BIAS module is connected to the pre-charge voltage and ground voltage VGND, respectively, and outputs the bandgap reference voltage VBG and the bandgap reference establishment judgment signal BGOK.

[0046] The LDO is used to power other modules when the DC-DC converter is operating. The LDO is connected to the power supply voltage VIN and the ground voltage VGND, receives the precharge voltage, the bandgap reference voltage VBG, the enable signal ENOK, and the bandgap reference establishment signal BGOK, and generates the supply voltage VDD.

[0047] Furthermore, the enable signal EN controls the enabling of the entire chip. The enable judgment signal ENOK is a bidirectional input / output signal. EN generates the enable judgment signal ENOK through a comparator (for example, when the enable signal EN rises to 1.2V, the enable judgment signal ENOK goes high). ENOK then serves as an input signal to control other modules of the DC-DC converter, such as the precharge module PREVDD. The bandgap reference establishment judgment signal BGOK is a bidirectional input / output signal. When the bandgap reference voltage VBG rises to a set value, BGOK goes high. BGOK then serves as an input signal to control other modules of the DC-DC converter, such as the precharge module PREVDD. The LDO establishment status signal LDOOK is a bidirectional input / output signal. When the LDO output voltage rises to a predetermined value, LDOOK goes high. LDO then serves as an input signal to control other modules of the DC-DC converter, such as the precharge module PREVDD.

[0048] Specifically, this startup circuit employs a method of short-circuiting the output prevdd of the PREVDD module and the output VDD of the LDO module. Specifically, the voltage VDD output from the LDO module is divided into an analog signal and a digital signal, which power the analog and digital circuits respectively. The VDD signal is connected to the analog signal via a first resistor R1, and to the digital signal via a second resistor R2. The analog signal is directly connected to the output voltage prevdd of the PREVDD precharge module, while the digital signal... Figure 1 This is represented as DVDD. Furthermore, the output of the LDO module is grounded via a capacitor.

[0049] Because the output of PREVDD (i.e. Figure 1 The pre-charge module's (PREVDD) and VDD signals are connected via resistor R1 (12Ω). The LDO's output voltage VDD pin has a large 4.7uF capacitor. Since the power transistor size of the pre-charge module (PREVDD) is much smaller than that of the LDO, the charging current of the pre-charge module (PREVDD) is much smaller than that of the LDO. Therefore, the charging slope of the pre-charge module (PREVDD) is very slow, resulting in a slower build-up speed. This is the fundamental reason for the longer time from EN enable to the first switching action in the DC-DC converter.

[0050] The simplified circuit structure of the PREVDD precharge module used in the prior art is shown below. Figure 2As shown, the PREVDD precharge module includes two PMOS transistors MP1' and MP2', five NMOS transistors MN1' to MN5', eight resistors R1' to R8', and a bipolar junction transistor Q1'. The sources of MP1' and MP2' are connected to the chip's power supply voltage VIN. The drain of MP1' and the gates of both MP1' and MP2' are connected to the drain of MN4'. The drain of MP2' is connected to ground voltage VGND via R2'. The gate of MN4' is connected to ground voltage VGND via R7', and the source of MN4' is connected to the drain of MN1'. The source of MN1' is connected to ground voltage VGND via R8', and the gate of MN1' is connected to the enable signal EN via R1'. The emitter of Q1' is connected to ground voltage VGND, the base is connected to ground voltage VGND via R8', and the collector is connected to the gate of MN1'. The gate of MN5' is connected to the bandgap reference establishment judgment signal BGOK, its source is connected to the ground voltage VGND, and its drain is connected to the drain of MN1'. The gate of MN3' is connected to the precharge indication signal Prevdd_off, its source is connected to the ground voltage VGND, and its drain is connected to the gate of MN4'. The precharge indication signal Prevdd_off is obtained by ANDing the enable judgment signal ENOK and the LDO establishment status signal LDOOK. The two ends of R6' are connected to the power supply voltage VIN and the gate of MN4', respectively. The gate of MN2' is connected to the drain of MP2', its drain is connected to the power supply voltage VIN via R3', and its source is connected to the ground voltage VGND via R4'. The output of the precharge module PREVDD is led out from the source of MN2' and is used to output the precharge voltage prevdd.

[0051] When the power supply voltage VIN and the enable signal EN are powered on, causing MN2' to conduct, VIN charges the output of the precharge module PREVDD through MN2', and the precharge module PREVDD gradually builds up. According to the circuit structure, when VIN and EN are low, for example, when VIN is below 4.5V and EN is below 1.2V, the current of MOSFET MN1' is small, resulting in a very small gate-source voltage VGS of MN2', causing the precharge module PREVDD to build up very slowly.

[0052] Timing diagram for the precharge module PREVDD and LDO setup (below) Figure 3As shown. Because the output of the precharge module PREVDD is shorted to the output of the LDO, the power-on timing waveforms of the precharge module PREVDD and the LDO are consistent. After the power supply voltage VIN is applied, the precharge module PREVDD charges at a very slow rate (because the output terminal of the precharge module PREVDD is shorted to the power output terminal of the LDO and connected to a 4.7uF capacitor). Once the LDO starts working (i.e., after the LDO's output voltage reaches the predetermined value), the charging speeds up due to the addition of the LDO, until the output voltage reaches the fixed voltage of 5V.

[0053] Addressing the problem of existing start-up circuits for DC-DC converters—namely, the short circuit between the precharge module PREVDD and the LDO output causes the PREVDD to be affected by the 4.7uF capacitor, resulting in slow charging—this invention proposes an LDO circuit and chip with precharge functionality. The specific embodiments of this invention will be described in detail below.

[0054] like Figure 4 According to a first aspect of the present invention, an LDO circuit with a pre-charge function is provided, the LDO circuit comprising: a pre-charge module 401, a voltage regulator module 402, and a power transistor module 403.

[0055] The precharge module 401 receives an enable signal EN and a reference voltage establishment determination signal BGOK, and outputs a precharge voltage prevdd in response to the enable signal EN indicating that the reference voltage has been established and the reference voltage establishment determination signal BGOK indicating that the reference voltage has not been established; otherwise, it does not output a precharge voltage prevdd.

[0056] The reference voltage establishment determination signal BGOK is generated by the bias module BIAS, which can be charged by the supply voltage VDD output from the LDO circuit with pre-charge function of this invention. Specifically, the bias module BIAS can detect whether the bandgap reference voltage VBG it generates has reached or is within a predetermined range, and based on the detection result, assign a corresponding logic value to the output reference voltage establishment determination signal BGOK. For example, when the bandgap reference voltage VBG is detected to have reached or is within the predetermined range, the reference voltage establishment determination signal BGOK is at a high potential, indicating that the reference voltage has been established; when the bandgap reference voltage VBG is detected to have not reached or is not within the predetermined range, the reference voltage establishment determination signal BGOK is at a low potential, indicating that the reference voltage has not been established.

[0057] The voltage regulator module 402 receives the reference voltage establishment determination signal BGOK, and outputs the regulated voltage ldovdd in response to the reference voltage establishment determination signal BGOK indicating that the reference voltage has been established; otherwise, it does not output the regulated voltage ldovdd.

[0058] The power transistor module 403 outputs the supply voltage VDD based on the pre-charge voltage prevdd and the regulated voltage ldovdd.

[0059] The reference voltage establishment determination signal BGOK is generated by the bias module BIAS (wherein). Figure 4 The bias module BIAS (not shown in the figure) is powered by the supply voltage VDD.

[0060] Furthermore, the pre-charge module 401 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a transistor QN1, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. R1 and R2 are connected in series between the power supply voltage VIN and the ground voltage VGND. The source of the first NMOS transistor MN1 is connected to the ground voltage VGND via the fourth resistor R4, and the drain of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2. The drain of the second NMOS transistor MN2 outputs the pre-charge voltage, and the gate of the second NMOS transistor MN2 is connected to the junction of R1 and R2. One end of R3 is connected to the enable signal EN, and the other end of R3 is connected to the gate of the first NMOS transistor MN1 and the collector of the transistor QN1. The emitter of the transistor QN1 is connected to the ground voltage VGND, and the base of the transistor QN1 is connected to the source of the first NMOS transistor MN1. The gate of the third NMOS transistor MN3 is connected to the reference voltage establishment determination signal BGOK, and the drain and source of the third NMOS transistor MN3 are respectively connected to the gate of the first NMOS transistor MN1 and the ground voltage VGND.

[0061] Specifically, when the enable signal EN indicates that the circuit is enabled, the enable signal EN is at a high level and its value is greater than the threshold voltage Vth1 of the first NMOS transistor MN1. When the reference voltage establishment determination signal BGOK indicates that the reference voltage has been established, the reference voltage establishment determination signal BGOK is at a high level and its value is greater than the threshold voltage Vth3 of the third NMOS transistor MN3.

[0062] Furthermore, the voltage regulator module 402 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an amplifier EA. R5 and R6 are connected in series between the supply voltage and the ground voltage; the non-inverting input of amplifier EA is connected to the junction of R5 and R6, the inverting input of amplifier EA is connected to the reference voltage Vref, and the output of amplifier EA is connected in series with R7 to output a regulated voltage ldovdd. Amplifier EA also has a control terminal for receiving the reference voltage establishment determination signal BGOK.

[0063] Specifically, the amplifier EA is enabled in response to the reference voltage establishment determination signal BGOK indicating that the reference voltage has been established; otherwise, it is not enabled.

[0064] Furthermore, the power transistor module 403 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply voltage VIN. The drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3. The drain of the third PMOS transistor MP3 is connected to the pre-charge voltage and the regulated voltage. The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected together. The drain of the first PMOS transistor MP1 outputs the power supply voltage VDD.

[0065] It should be noted that in other embodiments, the first PMOS transistor MP1 in the power transistor module 403 can also be replaced with an NMOS transistor. In this case, to ensure that the loop of the LDO circuit with pre-charge function of the present invention is a negative feedback loop and to prevent the LDO from oscillating, the polarity of the positive and negative input terminals of the amplifier EA in the voltage regulator module 402 needs to be reversed, that is, the positive input terminal is connected to the source of the replaced NMOS transistor, and the negative input terminal is connected to the reference voltage VREF. Other circuit connections remain unchanged.

[0066] Furthermore, preferably, the output of the LDO circuit with pre-charge function is connected to ground voltage VGND via capacitor C. Capacitor C can, for example, have a capacitance of 4.7uF.

[0067] Preferably, the LDO circuit with pre-charge function further includes an eighth resistor R8 disposed between the power supply voltage VIN and the input terminal of the power transistor module 403. The function of the eighth resistor R8 is to provide a discharge path for the gate-source capacitance Cgs of the power transistor MP1, preventing overvoltage of the gate-source voltage Vgs of the power transistor MP1.

[0068] like Figure 5When the enable signal EN indicates activation (corresponding to a high level in this embodiment), the pre-charge module 401 is powered on by the power supply voltage VIN. At this time, the bandgap reference voltage output by the bias module BIAS (not shown) has not yet reached the predetermined value, so the reference voltage establishment determination signal BGOK is low, the pre-charge module 401 operates normally, and the amplifier EA in the voltage regulator module 402 does not operate. At this time, the first and second NMOS transistors MN1 and MN2, and the first to third PMOS transistors MP1, MP2 and MP3 all operate in the saturation region, and the bipolar junction transistor QN1 operates in the amplification region. Therefore, the pre-charge module 401 charges the output terminal through the power transistor module 403 to provide the supply voltage VDD.

[0069] like Figure 6 When the bandgap reference voltage output by the bias module reaches a predetermined value, the bias module BIAS (not shown) outputs a high-level reference voltage establishment determination signal BGOK. At this time, the amplifier EA is enabled, and the voltage regulator module 402 starts working. The first to third PMOS transistors MP1, MP2, and MP3 are still operating in the saturation region. Simultaneously, since the reference voltage establishment determination signal BGOK is high, the third NMOS transistor MN3 in the precharge module 401 is turned off, causing the bipolar junction transistor QN1 to stop working and thus be in the cutoff region. The first and second NMOS transistors MN1 and MN2 are also turned off, and the entire precharge module 401 stops working. In this way, the switching from the precharge module 401 to the voltage regulator module 402 is completed.

[0070] The power-on timing of the LDO with pre-charge function of the present invention is as follows: Figure 7 As shown. When the voltage of the enable signal EN is greater than the threshold voltage Vth1 of the first NMOS transistor, the pre-charge module 401 starts to work. The first NMOS transistor MN1 in the pre-charge module 401 starts to have current, the first PMOS transistor MP1 in the power transistor module 403 turns on, and the supply voltage VDD of the LDO with pre-charge function starts to rise. At this time, the charging slope of the pre-charge module 401 is much greater than that of the prior art. When the supply voltage VDD rises to the point that the reference voltage establishment determination signal BGOK turns high, the pre-charge module 401 is turned off by the third NMOS transistor MN3, the voltage regulator module 402 starts to work, the amplifier EA in it is enabled, MP1, MP2 and MP3 in the power transistor module turn on, and the supply voltage VDD continues to rise until it reaches a fixed voltage of 5V.

[0071] According to a second aspect of the present invention, the present invention also provides a chip. This chip includes the LDO circuit with pre-charge function described above according to the first aspect of the present invention.

[0072] The beneficial effects of this invention are that, compared with the prior art, by controlling the pre-charge module and the voltage regulator module to conduct with the power transistor module before and after the reference voltage is established by the enable signal and the reference voltage establishment determination signal, respectively, the pre-charge module and the voltage regulator module can share the same large power transistor module, which greatly speeds up the charging speed of the pre-charge module; at the same time, compared with the scheme of using different power transistors for the pre-charge module and the voltage regulator module, chip area is saved.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. An LDO circuit with pre-charge function, characterized in that, It includes a pre-charge module, a power transistor module, and a voltage regulator module; among which: The pre-charge module receives an enable signal and a reference voltage establishment determination signal, and outputs a pre-charge voltage in response to the enable signal indicating that the module is enabled and the reference voltage establishment determination signal indicating that the reference voltage is not established; otherwise, it does not output a pre-charge voltage. The voltage regulator module receives a reference voltage establishment determination signal and outputs a regulated voltage in response to the reference voltage establishment determination signal indicating that the reference voltage has been established; otherwise, it does not output a regulated voltage. The power transistor module outputs a supply voltage based on the pre-charge voltage and the regulated voltage; The reference voltage establishment determination signal is generated by the bias module, which is powered by the supply voltage.

2. The LDO circuit with pre-charge function according to claim 1, characterized in that: The pre-charge module includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; R1 and R2 are connected in series between the power supply voltage and the ground voltage; The source of the first NMOS transistor is connected to the ground voltage via a fourth resistor, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor. The drain of the second NMOS transistor is connected to the pre-charge voltage, and the gate of the second NMOS transistor is connected to the junction of R1 and R2. One end of R3 is connected to the enable signal, and the other end of R3 is connected to the gate of the first NMOS transistor and the collector of the transistor. The emitter of the transistor is connected to ground, and the base of the transistor is connected to the source of the first NMOS transistor. The gate of the third NMOS transistor is connected to the reference voltage to establish a determination signal, and the drain and source of the third NMOS transistor are respectively connected to the gate of the first NMOS transistor and the ground voltage.

3. The LDO circuit with pre-charge function according to claim 2, characterized in that, When the enable signal indicates that the signal is enabled, the enable signal is at a high potential and is greater than the threshold voltage of the first NMOS transistor.

4. The LDO circuit with pre-charge function according to claim 2, characterized in that, When the reference voltage establishment determination signal indicates that the reference voltage has been established, the reference voltage establishment determination signal is at a high potential and is greater than the threshold voltage of the third NMOS transistor.

5. The LDO circuit with pre-charge function according to claim 1, characterized in that, The voltage regulator module includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an amplifier; R5 and R6 are connected in series between the supply voltage and the ground voltage; The non-inverting input of the amplifier is connected to the junction of R5 and R6, the inverting input of the amplifier is connected to the reference voltage, the output of the amplifier is connected in series with R7 and outputs the regulated voltage, and the amplifier also has a control terminal for receiving the reference voltage establishment determination signal.

6. The LDO circuit with pre-charge function according to claim 5, characterized in that, The amplifier is enabled in response to the reference voltage establishment determination signal indicating that the reference voltage has been established; otherwise, it is not enabled.

7. The LDO circuit with pre-charge function according to claim 1, characterized in that, The power transistor module includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor: The sources of the first and second PMOS transistors are connected to the power supply voltage. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor; The drain of the third PMOS transistor is connected to the pre-charge voltage and the regulated voltage; The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together. The drain of the first PMOS transistor is led out and the supply voltage is output.

8. The LDO circuit with pre-charge function according to claim 1, characterized in that, The power supply voltage is connected to the ground voltage via a capacitor.

9. The LDO circuit with pre-charge function according to claim 1, characterized in that, The LDO circuit with pre-charge function also includes an eighth resistor R8 located between the power supply voltage and the input terminal of the power transistor module.

10. A chip comprising an LDO circuit with a pre-charge function according to any one of claims 1-9.

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