Apparatus and method for detecting loop count in delay locked loop

Abstract

Apparatuses and methods for detecting loop counts in a delay-locked loop are disclosed. An example apparatus includes a frequency divider configured to receive a signal and generate a first divided signal and a second divided signal complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enable period and generate a first count value, a second circuit configured to count the second divided signal during a second enable period and generate a second count value, and a summer configured to generate a third count value in response to the first and second count values.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on September 4, 2018, with application number 201880055609.5 and invention title "Apparatus and method for detecting loop counts in a delayed locking loop". Technical Field

[0003] This disclosure relates to an apparatus and method for detecting loop counts in a delayed-locked loop. Background Technology

[0004] Many high-speed electronic systems operate under critical timing requirements, which necessitate the generation of periodic clock waveforms with precise timing relationships to certain reference signals. Improvements in the performance of computing integrated circuits and the increasing prevalence of incorporating multiple computing devices on a single board present challenges to synchronizing the timeframes of all components.

[0005] While the operation of all components in the system should be highly synchronized—that is, the maximum time skew between the effective edges of the clocks generated internally by all components should be minimized—feeding the system's external clock to all components is insufficient. This is because different chips may have different manufacturing parameters, which, when combined with additional factors such as ambient temperature, voltage, and processing variations, can lead to significant phase differences in the clocks generated by the respective chips.

[0006] Synchronization can be achieved by using timing circuitry, such as a Digital Delay-Locked Loop (DDLL) circuit, to detect the phase difference between clock signals of the same frequency and generate a digital signal related to that phase difference. DDLL circuits may require a relatively large number of clock cycles for synchronization. In conjunction with a DLL circuit, an open-loop topology can be used, such as a Measurement Controlled Delay (MCD) circuit, where timing measurements directly control the variable delay. MCD circuits exhibit fast locking capability (e.g., within 1 to 4 clock cycles after initialization). The MCD circuit generates the initial measurement, and the DDLL takes over to maintain the lock and track changes over time. Summary of the Invention

[0007] Describing an example device. An example device may include: a frequency divider configured to receive a signal and generate a first frequency-divided signal and a second frequency-divided signal complementary to the first frequency-divided signal; a first circuit configured to count the first frequency-divided signal during a first enable cycle and generate a first count value; a second circuit configured to count the second frequency-divided signal during a second enable cycle and generate a second count value; and an adder configured to generate a third count value in response to the first and second count values. The signal received by the frequency divider may include a clock signal. The example device may further include a delay path configured to receive and propagate the clock signal, and to change the delay value of the clock signal in response to the third count value. The first enable cycle may be generated in response to the first frequency-divided signal. The second enable cycle may be generated in response to the second frequency-divided signal. The first and second enable cycles may be additionally generated in response to start and stop signals respectively indicating the start and end of a timing loop cycle. The third count value may correspond to the number of clock cycles in which a reference clock traverses the timing loop.

[0008] Another example device may include: a delay-locked loop configured to synchronize a clock signal inside a memory with an externally received clock signal; a measurement-controlled delay circuit configured to initialize the delay-locked loop by traversing it using a reference clock to determine a variable delay amount; and a loop counter coupled to a divided clock portion of the measurement-controlled delay circuit. The loop counter may have a first segment configured to count clock cycles on a first divided clock signal and a second segment configured to count clock cycles on a second divided clock signal. The first segment of the loop counter may be configured to count the first divided clock signal during a first enable cycle generated in response to the first divided clock signal. The second segment of the loop counter may be configured to count the second divided clock signal during a second enable cycle generated in response to the second divided clock signal. The first segment of the loop counter may include a first detection block coupled to a first ripple counter. The second segment of the loop counter may include a second detection block coupled to a second ripple counter. The first and second detection blocks can be enabled by start and stop signals, respectively indicating the start and end of traversing the delay-locked loop. The loop counter may include an adder coupled to the first and second ripple counters and may be configured to output a value N corresponding to the number of clock cycles the reference clock traverses the delay-locked loop. The example device may further include a delay path configured to receive and propagate the clock signal, and to change the delay value of the clock signal in response to the value N.

[0009] Describing an example method. An example method may include: receiving a signal and generating a first frequency-divided signal and a second frequency-divided signal complementary to the first frequency-divided signal; counting the first frequency-divided signal during a first enable cycle to generate a first count value; counting the second frequency-divided signal during a second enable cycle to generate a second count value; and adding the first and second count values ​​to generate a third count value. In some instances, the signal is a clock signal. The method may further include receiving the clock signal and propagating the clock signal, and changing a delay value of the clock signal in response to the third count value. The method may further include generating the first enable cycle in response to the first frequency-divided signal. The method may further include generating the second enable cycle in response to the second frequency-divided signal. The method may further include additionally generating the first and second enable cycles in response to start and stop signals respectively indicating the start and end of a timing loop cycle. In some instances, the third count value may correspond to the number of clock cycles in which a reference clock traverses the timing loop. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a portion of a memory according to an embodiment of the present invention.

[0011] Figure 2 This is in accordance with the embodiments of the present invention. Figure 1 The diagram shows the synchronization path of the memory.

[0012] Figure 3 This is in accordance with the embodiments of the present invention. Figure 1 A schematic diagram of a delay-locked loop for a memory device.

[0013] Figure 4 This is a schematic diagram of a delay-locked ring according to an embodiment of the present invention.

[0014] Figure 5 This is in accordance with the embodiments of the present invention. Figure 4 A schematic diagram of a synchronizer circuit with a delay-locked loop.

[0015] Figure 6 According to an embodiment of the present invention Figure 5 Timing diagrams for various signals during the operation of the synchronizer.

[0016] Figure 7 According to an embodiment of the present invention Figure 4 Timing diagrams for various signals during the operation of the delay-locked loop.

[0017] Figure 8 This is in accordance with the embodiments of the present invention. Figure 4A schematic diagram of a loop counter for a delay-locked loop.

[0018] Figure 9 According to an embodiment of the present invention Figure 7 A schematic diagram of various signals during the operation of a loop counter embodiment. Detailed Implementation

[0019] This invention relates to a system and method for detecting loop counts in a delay-locked loop (DLL) using a divided clock during measurement initialization. The DLL may be a component of a memory and may be used by the memory to synchronize an internal clock signal with an externally received clock. During operation, the DLL may be reset periodically to ensure proper synchronization under different operating conditions, after power-on, etc. As part of the reset process, the DLL may perform a measurement initialization process for setting the delay amount of a variable line. The variable delay line may be arranged in the forward path of a memory command. The variable delay may be a portion of the total delay encountered by the command as it traverses the forward command path. During the measurement initialization process, a loop counter may be used to count N, the number of clock cycles taken for the reference clock to traverse the feedback loop associated with the DLL. According to an embodiment using a divided clock in the timing path, the counter may contain separate N detection blocks for each portion of the divided clock.

[0020] Figure 1 This is a schematic diagram of a portion of a memory 100 according to an embodiment of the present invention. The memory 100 includes a memory cell array 104, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other type of memory cell. The memory 100 is generally configured to operate in conjunction with a larger digital system that includes at least a processor configured to communicate with the memory 100. In this description, "external" refers to signals and operations outside the memory 100, and "internal" refers to signals and operations within the memory 100. As an illustrative example, the memory 100 may be coupled to a microprocessor that provides external commands and clock signals to the memory 100. Although the examples in this description relate to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.

[0021] Memory 100 is typically configured to execute read and / or write commands received from an external device. A read command across data bus 108 provides data stored in array 104 to the external device. A write command across data bus 108 receives data from the external device and stores the data in memory array 104. The following discussion generally refers to the read command by way of example, not limitation. When processing a read command, memory 100 receives an external clock CLK and generates an internal clock to synchronize internal signals so as to provide output data on data bus 108 in appropriate timing. Here, memory device 100 uses a delay-locked loop 112 to synchronize internal signals, which includes generating a data strobe signal 114. The data strobe signal 114 is provided as an output to an external controller and is asserted when the requested read data is available on data bus 108 for capture by the external controller.

[0022] Memory system 100 includes a command decoder 116 that receives memory commands via a command bus 120. The command decoder 116 responds to memory commands applied to the command bus 120 by generating corresponding control signals to perform various operations on the memory array 104. For example, the command decoder 116 may generate internal control signals to read data from and / or write data to the memory array 104. Row and column address signals associated with a specific command are applied to memory 100 via an address bus 124. The address bus 124 provides the row and column address signals to an address register 128. The address register 128 then outputs individual column and row addresses to the memory array 104.

[0023] If possible Figure 1 As can be seen, the row and column addresses can be provided to the row address decoder 132 and column address decoder 136 respectively by the address register 128. The column address decoder 128 selects the bit line extending through array 104 corresponding to the respective column address. The row address decoder 132 includes or is coupled to a word line driver or similar component, which activates the corresponding row of the memory cell in array 104 corresponding to the received row address. The selected data line (e.g., bit line) corresponding to the received column address is coupled to read / write circuitry 140 to provide read data to a data output buffer or similar component via input-output data bus 108. Read / write circuitry 140 can receive a delay control signal from delay control 141. Write data is applied to memory array 104 through data input buffer or similar component and memory array read / write circuitry 140.

[0024] The timing of signals outside memory 100 can be determined by an external clock CLK. Operations within memory 100 are typically synchronized with external operations. Delay-locked loop 112 is typically configured to receive the external clock CLK and generate a synchronous internal clock signal. The synchronous internal clock signal generated by delay-locked loop 112 can be provided to various internal memory components to facilitate latching command, address, and data signals according to the external clock CLK. For example, data output can be placed on the data bus 104 of memory 100 in synchronization with the external clock CLK, so that memory device 100 outputs data in a manner that allows data to be captured by an external controller. To output data in an appropriate timing, delay-locked loop 112 generates an internal clock signal in response to the external clock signal and applies the internal clock signal to latches contained in memory device 100 to clock the data. Reference will now be made to... Figure 2 The general connections of the delay-locked ring 112 to other components of the memory 100 are described in more detail.

[0025] Figure 2 This is a block diagram illustrating the synchronization paths for various signals within the memory 200 according to the present invention. The memory 200 may correspond to... Figure 1 The memory 100. To simplify the accompanying drawings, from... Figure 2 Omit Figure 1 Some of the components described in the document. Figure 2 This describes the paths of various signals that propagate from the input to the output of the memory 200 during the process of performing a write or read operation on the memory 200. Figure 2 Includes a delayed locking ring 204, which can correspond to Figure 1 Delay-locked loop 112. Delay-locked loop 204 is typically configured to provide clock synchronization within memory 100. As used herein, the term synchronization includes both consistent signals and signals having a desired delay relative to each other.

[0026] Such as combination Figure 1 As described, memory 200 receives a CLK signal from an external source, such as a computing device coupled to memory device 200. Initially, the external CLK can be received as input at both delay-locked loop 204 and command decoder 208. Command decoder 208 is typically configured to receive external commands, decode the commands, and output separate internal control signals to perform various operations, such as read operations, write operations, etc. Command decoder 208 may correspond to Figure 1 Command decoder 116. Output drive memory array ( Figure 1 (as shown), so as to provide the read data to the delay control 212. Figure 2 The delay control 212 can correspond to Figure 1 The delay control 141 in the middle, and can be generated by the shift register and Figure 1Other components are used to construct it. Once read data is received at delay control 212, delay control 212 can provide the data outside of data bus 220, which provides the interface between memory 200 and external controller. This path to data bus 220 is typically in Figure 2 This is referred to as clock and command tree 216. When the requested read data is present on data bus 220, memory 200 can assert data strobe line 224 to indicate to an external controller that the data is available for capture.

[0027] Figure 2 Additionally, a delay component 228 is shown, which is typically arranged close to the output of the command decoder 208. The delay component 228 is coupled to a delay-locked loop 204 and is typically configured to provide a copy of the delay present in the delay-locked loop 204. As part of providing clock synchronization within the memory 200, the delay-locked loop 204 adjusts the amount of delay provided by the delay component 228. Here, the delay-locked loop 204 controls the amount of delay provided by the delay component 228 to ensure that the read command delay reaches an amount that causes the read command timing to be synchronized with the internal clock output from the delay-locked loop 204.

[0028] Usually in Figure 2 The output clock provided by the delay-locked loop (DLL) is identified as DllClk. The DLL 204 is typically configured to generate the DllClk signal based on an external clock CLK received as input. Figure 2 As shown, DllClk is coupled to delay control 212 and clock and command tree 216. By controlling the amount of delay present in the DllClk signal, delay-locked loop 204 provides an approximate delay that closely matches the phase difference between the input (CLK) clock signal and the output (DllClk) clock signal. Delay-locked loop 204 introduces the corresponding delay amount into the command path via delay component 228. In this way, when a command arrives at components such as delay control 212 and clock and command tree 216 (which are in the DllClk domain), the command is synchronized with the DllClk clock. Reference will now be made to... Figure 3 The operation of the delayed locking ring is described in more detail.

[0029] Figure 3 This is a schematic diagram of a delay-locked loop 300 used to provide an approximate delay that closely matches the phase difference between the input clock signal and the output clock signal. The delay-locked loop 300 can correspond to... Figure 1 Delayed locking ring 112 and / or Figure 2 The delay-locked loop 204. The delay-locked loop 300 uses a feedback configuration, which operates to feed back a signal related to the phase difference to control one or more delay lines (e.g., variable delay line 304) to advance or delay the timing of one clock signal to "lock" to a second clock signal.

[0030] An external clock CLK is initially applied to circuit 300 and received by input buffer 304, which provides a buffered clock signal ClkRef to delay-locked loop circuit 300. The ClkRef signal is delayed relative to the external clock CLK, due to the propagation delay of input buffer 308. The ClkRef signal is then applied to a variable delay line 304 comprising several delay stages. The variable delay line 304 may include a shift register or similar component that selects the delay stages to apply the measured delay for adjusting the phase of the ClkRef signal. The shift register or other component controls the adjustment of the variable delay line 304 by providing a shift control signal in response to a control signal received from phase detector 312.

[0031] In response to the shift control signal, the variable delay line 304 applies the measured delay to adjust the phase of the ClkRef signal to near the desired phase to achieve the phase-locked condition. The variable delay line 304 generates an output signal DllClk. The DllClk signal is provided to the model delay circuit 316, which replicates the inherent delay added to the applied external clock signal as it propagates through the delay loop, such as the input buffer 304 plus the output path delay 320 that may occur after the delay-locked loop 300.

[0032] The model delay circuit 316 then provides the feedback signal ClkFb to the phase detector 312. The phase detector 312 compares the phases of the ClkRef signal and the ClkFb signal to generate a shift selection signal to the shift register to control the variable delay line 304. The shift selection signal instructs the shift register to increase the delay of the variable delay line 304 when the ClkFb signal leads the ClkRef signal, or vice versa. The delay can be increased or decreased by adding or subtracting the number of stages used in the variable delay line 304, which contains a number of delay stages. In this way, the delay-locked loop 300 can synchronize the internal clock signal DllClk with the external clock CLK.

[0033] The measured delay, applied to adjust the phase of the ClkRef signal, is typically determined through a "measurement initialization" process performed periodically by the memory to ensure proper synchronization under different operating conditions, after power-on, etc. As described above, DLL 300 may take a certain amount of time to achieve the "lock-in" condition. This time can be reduced if the variable delay line 304 is initially set to approximately the expected delay required to synchronize the internal clock signal with the external clock signal. Minimum delay may be preferred for locking purposes due to lower power consumption. To provide this initial delay, some DLL circuits may include measurement initialization capabilities. Reference will now be made to... Figure 4 The measurement initialization process will be described in more detail.

[0034] Figure 4 This is a simplified block diagram of the delay locking ring 400 according to the present invention. Figure 4 It includes a measurement-controlled delay circuit 420 and a loop counter 460. The measurement-controlled delay circuit 420 is typically configured to determine an appropriate variable delay amount to be applied under given conditions to ensure proper synchronization of signals in the memory. The measurement-controlled circuit 420 operates during the "measurement initialization" process used to configure the delay-locked loop 400. Therefore, measurement initialization typically occurs before the memory, of which the delay-locked loop 400 is a part, begins executing read or write commands.

[0035] Loop counter 460 also executes during this initial configuration process to detect N, which in this document refers to the number of clock cycles that occur during the measurement initialization process. More specifically, N refers to the number of clock cycles taken for the reference clock to traverse the feedback loop constituting delay-locked loop 400. After the value N is measured by loop counter 460 during the measurement process, the memory uses the value N in several ways. On the one hand, the memory uses N for further timing adjustments to ensure that the memory meets specified latency requirements. These further timing adjustments may take the form of adjusting timing amounts through shifters or the like associated with components downstream of delay-locked loop 400. On the other hand, the value N detected by loop counter 460 may be provided to the phase detector of the delay-locked loop to ensure that subsequent timing adjustments performed within delay-locked loop 400 occur at an effective rate.

[0036] In the following discussion, both the measurement-controlled delay circuit 420 and the loop counter 460 are addressed. The measurement-controlled delay circuit 420 is discussed first. The loop counter 460 is then discussed. Although this embodiment is described with reference to a measurement-controlled delay circuit used to establish initial synchronization between the input clock signal and the output clock signal, the scope of these embodiments is not so limited. Other types of synchronization circuits, including synchronization mirror delay circuits and phase-locked loop circuits, can be used.

[0037] Reference Figure 4 The delay-locked loop 400 includes a measurement delay array 405, a measurement circuit 410, and a forward delay array 415, which are combined to form a measurement-controlled delay circuit 420. An external clock CLK is provided to a buffer circuit 425, which is in turn coupled to the forward delay array 415. The buffer circuit 425 represents the input circuitry of the memory 100 (see [link]). Figure 1 It may contain one or more buffers and / or other logic circuits.

[0038] Multiplexer 430 is coupled to receive input from buffer 425 and forward delay array 415. During the measurement initialization loop, multiplexer 430 is controlled to bypass forward delay array 415 until the timing signal has propagated through delay-locked loop 400 and the measurement-controlled delay circuit 420 can be locked, as will be described in more detail below. After the measurement initialization loop, multiplexer 430 is controlled to select the output of forward delay array 415 as its input.

[0039] The output of multiplexer 430 is provided to buffer circuit 435, and buffer circuit 435 is coupled to another buffer circuit 440. Buffer circuit 440 represents the output circuitry of memory 100 (i.e., output driver, slew rate control device, etc.) and may include one or more buffers and / or other logic circuits. The output of buffer circuit 440 represents the output clock signal DllClk used by memory 100.

[0040] Phase detector 445 is coupled to buffer 425 to receive a reference clock signal ClkRef and to model delay circuit 450 to receive a feedback clock signal ClkFb. Phase detector 445 measures the phase difference between the ClkRef signal provided by buffer circuit 425 and the ClkFb signal exiting model delay circuit 450. Phase detector 445 controls the amount of delay imposed by forward delay array 415 in response to the measured phase difference.

[0041] The model delay circuit 450 models the delay introduced into the external clock CLK by the output circuit (d3) of the buffer circuit 425 (d1) and the memory 100 (e.g., buffer circuit 440) to generate a feedback clock signal ClkFb. The modeled delays are referred to as d1' and d3' to correspond to the actual delays d1 and d3, respectively. The output of the buffer 435 is provided to the model delay circuit 450. Because the output of the buffer circuit 435 is fed to the model delay circuit 450, its delay (d2) does not need to be modeled by the model delay circuit 450. The output of the phase detector 445 is provided to the forward delay array 415 for controlling synchronization after the measurement initialization loop is completed.

[0042] The feedback clock signal ClkFb generated by the model delay circuit 450 is coupled to provide a clock signal to the first clock divider 464. The first clock divider 464 receives the uncordered clock ClkFb as input and provides the divided clock as output. (As can be...) Figure 4As can be seen, the first clock divider 464 provides outputs including a first signal line labeled ClkFbDiv and a second output line labeled ClkFbDivF. The first clock divider 464 drives these two signal lines based on the ClkFb signal, such that the periods of ClkFbDiv and ClkFbDivF are each twice the period of ClkFb. One output signal (e.g., ClkFbDiv) is in phase with ClkFb. The other output signal ClkFbDivF is inverted by ClkFbDiv. ClkFbDiv and ClkFbDivF can be coupled to a measurement trigger 465 that generates a feedback clock enable signal MsDyClk, which is provided as an input to the delay array 420 to initiate a measurement of the forward delay (N*tCK-(d2+d1'+d3')).

[0043] The reference clock signal ClkRef generated by buffer 425 is coupled to provide a clock signal to the second clock divider 454. The second clock divider 454 receives the uncordered clock ClkRef as input and provides the divided clock as output. Figure 4 As can be seen, the second clock divider 454 provides outputs including a first signal line labeled ClkRefDiv and a second output line labeled ClkRefDivF. The second clock divider 454 drives these two signal lines based on the ClkRef signal, such that the periods of ClkRefDiv and ClkRefDivF are each twice the period of ClkRef. One output signal (e.g., ClkRefDiv) is in phase with ClkRef. The other output signal, ClkRefDivF, is inverted by ClkRefDiv. ClkRefDiv and ClkRefDivF can be coupled to a start trigger 455 that generates a count start signal FbClkEn, which is provided as a start signal to the counter 460. ClkRefDiv and ClkRefDivF additionally provide clock inputs to the counter 460 at Clock and ClockF, respectively.

[0044] The MsDyClk signal is provided to delay element 470. Delay element 470 provides a fixed minimum delay to allow delay-locked loop 415 to operate under a wide range of conditions. The amount of delay provided by delay element 470 may vary depending on the specific implementation. Delay element 470 is coupled to synchronizer 475, which is clocked by ClkRefDiv and / or ClkRefDivF signals, to generate a measurement pulse signal MStrobe. The MStrobe signal is coupled to counter 460 as a stop input. The MStrobe signal is also provided to measurement circuit 410 to trigger synchronization between the input clock signal and the output clock signal.

[0045] After discussing synchronizer 475, the operation of delay-locked loop 400 will be described in more detail.

[0046] Figure 5 This is a circuit diagram containing an example configuration for synchronizer 508. Synchronizer 508 may correspond to... Figure 4 Synchronizer 475. Synchronizer 508 comprises two chains of bistable multivibrators connected in series. Synchronizer 508 comprises a chain of two upper bistable multivibrators 528 and 532 connected in series and a chain of two lower bistable multivibrators 536 and 540 connected in series. ClkRefDivF is coupled to synchronizer 508 and provides clock input for the upper bistable multivibrators 528 and 532. ClkRefDivF is coupled to synchronizer 508 and provides clock input for the lower bistable multivibrators 536 and 540.

[0047] Synchronizer 508 is configured to provide an Mstrobe signal as its output. Synchronizer 508 provides the output signal via NAND gates of two series-connected bistable multivibrators coupled to the synchronizer. Synchronizer 508 includes NAND gate 548, which receives the output signal Q from the first upper bistable multivibrator 532. D1F As the first input, the output signal Q from the second bistable multivibrator 540. D2F The second input is provided to NAND gate 548. The Mstrobe signal is provided as the output of NAND gate 548 from synchronizer 508.

[0048] Synchronizer 508 is configured to provide a clock edge on its output, which is delayed by three clock cycles relative to the undivided clock signal. Figure 6 This is a timing diagram that provides an illustration of the synchronizer's behavior by referencing the signals of synchronizer 508 in an example rather than a restriction manner. Figure 6 Includes signal traces for ClkRefDiv and ClkRefDivF, showing a 180-degree out-of-phase relationship between the signal traces of ClkRefDiv and ClkRefDivF. Figure 6 It also includes the signal traces for the undivided clock ClkRef. As can be seen, the periods of ClkRefDiv and ClkRefDivF are twice that of ClkRef. Figure 6 Includes trigger signals for D synchronizer, Q D1F The output and Q of the upper bistable multivibrator chain D2F Signal traces of the output of the lower bistable multivibrator chain and the output of the Mstrobe synchronizer 508.

[0049] Once the D signal is asserted, it propagates through the upper bistable multivibrators 528 and 532 and the lower bistable multivibrators 536 and 540. The upper bistable multivibrators 528 and 532 are clocked at the rising edge of ClkRefDiv. The lower bistable multivibrators 536 and 540 are clocked at the rising edge of ClkRefDivF. Because these clock signals are 180 degrees out of phase, the D signal will appear at the end of the bistable multivibrator chain at different times. For example, if the rising edge of the D signal occurs between the falling and rising edges of ClkRefDiv, then the D signal will appear from the upper bistable multivibrators 528 and 532 before the lower bistable multivibrators 536 and 540. Conversely, if the rising edge of the D signal occurs between the falling edge and the rising edge of ClkRefDivF, then the D signal will appear from the lower bistable multivibrator 536, 540 before the D signal appears from the upper bistable multivibrator 528, 532.

[0050] Figure 6 The following describes a later instance where the D signal first appears from the lower bistable multivibrator 536. Here, the rising edge of the D signal occurs at time point A. The first rising clock edge after time point A occurs in ClkRefDivF at point B. Therefore, at time point B, when the first bistable multivibrator 536 is clocked by ClkRefDivF, the D signal begins to propagate through the lower bistable multivibrator chain. The D signal does not propagate through the upper bistable multivibrator chain until the first bistable multivibrator 528 is clocked by ClkRefDiv at time point C. The second lower bistable multivibrator 540 is clocked by ClkRefDivF at time point D, at which point QD2F is asserted via a falling edge. Q is asserted at a later time (time point E) after the second upper bistable multivibrator 532 is clocked by ClkRefDiv. D1F MStrobe is powered by Q D1F and Q D2F The NAND gate 548 is used as input. Therefore, the rising edge of the MStrobe will appear in Q. D1F The falling edge or Q D2F The descending edge. In Figure 6 In the example, Q D2F The descending edge first appears at point D. Therefore, this point also corresponds to the ascending edge of MStrobe.

[0051] If possible Figure 6It can be seen that three clock cycles of the undivided clock ClkRef occur between the rising edge of the D signal and the rising edge of the MStrobe. The number of bistable multivibrators used in synchronizer 508 can vary depending on the specific implementation, resulting in different timing measurements by the undivided clock ClkRef. In the illustrated embodiment, the three clock cycles of the undivided clock are used to allow the feedback path to be filled with the clock signal and stabilized before synchronizing the clock signal.

[0052] Refer again Figure 4 The operation of the delay-locked loop 400 will now be described in more detail. Before synchronization, the control multiplexer 430 bypasses the forward delay array 415. Therefore, the feedback clock signal ClkFb, after its journey through the multiplexer 430, buffer 435, and model delay circuit 450, is merely a reference clock signal ClkRef. When the clock signal begins to change, the ClkRef signal, now divided into ClkRefDiv and ClkRefDivF, clocks the data bistable multivibrator of the start-up trigger 455. At a later point in time, the ClkRef signal propagates through the feedback path and a rising edge is seen in the ClkFb signal, which clocks the bistable multivibrator of the measurement trigger 465 as divided clocks ClkFbDiv and ClkFbDivF.

[0053] After three clock cycles of the unddivided clock, which occur as described above via the operation of start triggers 455 and 508, the FbClkEn signal is asserted, and counter 460 begins counting each pulse on the ClkRefDiv and ClkRefDivF signals. The ClkFbDiv and ClkFbDivF signals clock the bistable multivibrator of the measurement trigger 465, and after three pulses of the unddivided clock, the MsDyClk signal is asserted, which clocks the measurement delay array 405. The MsDyClk signal generated by the measurement trigger 465 propagates through the measurement delay array 405 until the measurement circuit 410 is triggered. The measurement circuit 410 includes a series of latches (not shown) triggered by the MStrobe signal. The specific latch triggered is the latch corresponding to the pulse position in the measurement delay array 405.

[0054] Subsequently, the MsDyClk signal travels through delay element 470 and is latched in synchronizer 475 after the next rising edge of the ClkRef signal, thus generating the MStrobe signal. The MStrobe signal stops counter 460 and latches measurement circuit 410, thereby configuring forward delay array 415 to synchronize the CLK signal with the DllClk signal. The START and STOP signals provided to counter 460 are synchronized with the rising edges of the ClkRefDiv and ClkRefDivF signals. The value of counter 460, LoopCount, represents the number of clock signals required for the reference clock signal to propagate through the feedback path.

[0055] After configuring the forward delay array 415, the multiplexer 430 is configured to select the forward delay array 415 as its input. The output of the forward delay array 415 then travels through the buffer 435 and the model delay circuit 450, becoming the source for the feedback clock signal ClkFb provided to the phase detector 445. The phase detector 445 then controls the forward delay array 415 to maintain synchronization of the CLK and DllClk signals. The ClkFb signal is synchronized with the ClkRef signal, having a multi-clock cycle difference N*tCK. The LoopCount output of the counter 460 represents the value N. Typically, a higher frequency clock signal results in a larger value for N.

[0056] Turn now Figure 7 A timing diagram illustrating the operation of the delay-locked loop 400 is provided. The reference clock ClkRef and corresponding feedback clock ClkFb are explained. The MeasureInit signal indicates the mode of the measurement circuit 410. The measurement-controlled delay circuit 420 operates during the measurement initialization mode, and the delay-locked loop operates in other ways. The measurement strobe MStrobe, feedback clock enable FbClkEn, and measurement delay clock MsDyClk signals are also explained. A counter signal is provided to illustrate the time period for enabling the counter 460. The counter signal is not the actual signal used in the delay-locked loop 400, but rather a combination of the FbClkEn and MStrobe signals for starting and stopping the counter 460.

[0057] At time point A, the reference clock signal begins to change. Delay-locked loop 400 operates in measurement initialization mode, therefore the MeasureInit signal is asserted, and multiplexer 430 is configured to bypass forward delay array 415. At time point B, the bistable multivibrator of start-up trigger 455 latches either ClkRefDiv or ClkRefDivF onto the third cycle of the undivided clock ClkRef, thus asserting the FbClkEn signal and starting counter 460. At time point C, the third cycle of the ClkFb signal is latched by measurement trigger 465, indicating that the reference clock has propagated the feedback path and causing the MsDyClk signal to be asserted. The MsDyClk signal pulses the measurement delay array 405.

[0058] At time point D, the MsDyClk signal, delayed by delay element 470, is latched in bistable multivibrator 475, thereby triggering an assertion in the MStrobe signal. The MStrobe signal activates measurement circuit 410 to determine the position of the previous MsDyClk pulse in measurement delay array 405 and stops counter 460. The delay in forward delay array 415 is set by the latched position in forward delay array 415 to synchronize the reference clock signal with the feedback clock signal.

[0059] At time point E, the MeasureInit signal is deasserted, and multiplexer 430 is configured to use the signal traveling through forward delay array 415 for the output clock signal DllClk. At time point F, the signal traveling through forward delay array 415 to buffer 435 propagates through the feedback path to model delay circuit 450 to become the ClkFb signal. The ClkRef and ClkFb signals are provided to phase detector 445 for subsequent synchronization control. Subsequent changes in the relative phase of the ClkRef and ClkFb signals will cause phase detector 445 to adjust the delay provided by forward delay array 415 to maintain synchronization.

[0060] The LoopCount value, determined by counter 460, represents the value N, which identifies the number of clock cycles in which the output clock is offset from the input clock. The LoopCount value has various uses. For example, the LoopCount value is useful for establishing read latency in memory devices. An exemplary apparatus employing LoopCount is described in U.S. Patent No. 6,687,185, entitled "METHOD AND APPARATUS FOR SETTING AND COMPENSATING READ LATENCY IN A HIGHSPEED DRAM," which is assigned to the assignee of this application, and the entire contents thereof are incorporated herein by reference.

[0061] Figure 8 This is a circuit diagram for a loop counter 800 according to the present invention. The loop counter 800 may correspond to... Figure 4 The loop counter 460. The loop counter 800 is typically configured to counter delay-locked loops (in... Figures 1 to 4 The loop counter 800 counts the number of clock cycles N that occur during the initialization period (as shown in the diagram). The loop counter 800 includes an upper N-detection block 802 and a lower N-detection block 804. Each N-detection block 802, 804 is configured for partial counting of the total number of clock cycles N. In this respect, each N-detection block is coupled to a ripple counter, and each ripple counter is coupled to an adder. More specifically, the upper N-detection block 802 is coupled to an upper ripple counter 806. The lower N-detection block 804 is coupled to a lower ripple counter 808. The upper ripple counter 806 and the lower ripple counter 808 are each coupled to an adder 810 that provides the output of the loop counter 800.

[0062] The loop counter 800 includes multiple signal paths through which input received at the loop counter 800 propagates. The loop counter 800 includes an upper clock path 812 and a lower clock path 814. The upper clock path 812 causes ClkRefDiv and ClkRefDivF to propagate through the upper N-detection block 802. Similarly, the lower clock path 814 causes ClkRefDiv and ClkRefDivF to propagate through the lower N-detection block 804. The upper clock path 812 is coupled to an upper NAND gate 820 and a lower NAND gate 822. Similarly, the lower clock path 814 is coupled to an upper NAND gate 826 and a lower NAND gate 828. In each clock path, the upper NAND gates 820 and 826 are configured to pass the output signal to the corresponding ripple counters 806 and 808. The lower NAND gates 822 and 828 are configured to provide signal termination without further signal propagation.

[0063] The arrangement of ClkRefDiv and ClkRefDivF in the first clock path 812 is the reverse of that in the second clock path 814. Therefore, in the upper clock path 812, ClkRefDiv is coupled to the upper NAND gate 820 to generate the input of the upper ripple counter 806. Here, ClkRefDivF is coupled to the lower NAND gate 822 and terminates. In the lower clock path 814, ClkRefDivF is coupled to the upper NAND gate 826 to generate the input of the lower ripple counter 808. Here, ClkRefDiv is coupled to the lower NAND gate 828 and terminates. This arrangement of ClkRefDiv and ClkRefDivF facilitates the counting of different clock cycles by ripple counters 806 and 808. As described in more detail below, the number of clock cycles counted by ripple counters 806 and 808 can be summed to obtain the total number of clock cycles that occur during the initialization of the delay-locked loop.

[0064] The loop counter 800 additionally includes an upper enable path 830 and a lower enable path 832. The upper enable path 830 allows the START and STOP signals to propagate through the upper N detection block 802. Similarly, the lower enable path 832 allows the START and STOP signals to propagate through the lower N detection block 804. (As in...) Figure 4 As shown, the START signal corresponds to the FbClkEn signal provided as the output from the start trigger 455. The STOP signal corresponds to the Mstrobe signal provided as the output from the synchronizer 475. The upper enable path 830 is coupled to NAND gate 836, which provides a single output to the bistable multivibrator 840. Similarly, the lower enable path 832 is coupled to NAND gate 844, which provides a single output to the bistable multivibrator 846.

[0065] Bistable multivibrators 840 and 846 provide coupling between clock paths 812 and 814 and enable paths 830 and 832 in a manner that facilitates the clock counting function of each N-detection block 802 and 804. Here, bistable multivibrators 840 and 846 include two additional inputs from clock signal paths 802 and 804. In this arrangement, bistable multivibrators 840 and 846 are configured to provide enable signals to upper NAND gates 820 and 826 located at downstream points in the N-detection blocks 802 and 804. The bistable multivibrator 840 of the upper N-detection block 802 produces an output, which... Figure 8 The output is marked as ClockEn. The bistable multivibrator 846 of the lower N-detection block 804 produces an output, which in... Figure 8 It is marked as ClockEn1.

[0066] The output of the first N-detection block 802 is coupled to the upper ripple counter 806. The upper N-detection block 802 asserts its output as it counts the clock cycles. This output causes the upper ripple counter 806 to count the number of signal assertions generated by the upper N-detection block 802. The lower ripple counter 808 operates in a similar manner to count the number of signal assertions generated by the lower N-detection block 804. The adder 810 sums the inputs from the ripple counters 806 and 808 to produce a total value at the output of the counter 800.

[0067] Figure 9 It provides a reference through examples rather than restrictions. Figure 8 A timing diagram illustrating the behavior of the loop counter 800. Figure 9 Includes signal traces for ClkRefDiv and ClkRefDivF, as can be seen, the signal traces of ClkRefDiv and ClkRefDivF are 180 degrees out of phase. Figure 9 It also includes signal traces for the START and STOP signals. As indicated by the FbClkEn signal, the rising edge of the START signal corresponds to the start of the measurement initialization cycle. The rising edge of the STOP signal corresponds to the end of the measurement initialization cycle, as indicated by the Mstrobe signal. Figure 9 It also includes signal traces for the ClockEn and ClockEn1 signals. The rising edge of the ClockEn signal corresponds to the upper N-detection block 802 being enabled, as indicated by the output of the bistable multivibrator 840. The rising edge of the ClockEn1 signal corresponds to the lower N-detection block 804 being enabled, as indicated by the output of the bistable multivibrator 846. Figure 9 It also includes signal traces for the Enabled ClkDR and EnabledClkDF signals. Enabled ClkDR corresponds to the output of the upper N detection block 802. EnabledClkDR corresponds to the output of the lower N detection block 804.

[0068] The START and STOP signals define a time period during which counter 800 counts clock cycles. In operation, counter 800 counts the clock cycles between the rising edge of the START signal and the rising edge of the STOP signal. During this time period, the upper N-detection block 802 and the lower N-detection block 804 are enabled by ClockEn and ClockEn1, respectively. When both counters 800 are active, ClockEn goes high, as indicated by the START and STOP signals, and a rising edge appears on the ClkRefDivF signal. Similarly, when both counters 800 are active, ClockEn1 goes high, as indicated by the START and STOP signals, and a rising edge appears on the ClkRefDiv signal.

[0069] ClockEn enables the upper N-detection block 802 to count the clock signal of ClkRefDiv. Similarly, ClockEn1 enables the lower N-detection block 804 to count the clock signal of ClkRefDivF. When the upper N-detection block 802 is enabled as indicated by the ClockEn signal, the upper N-detection block 802 counts the clock cycles on the rising edge of ClkRefDiv. Similarly, when the lower N-detection block 804 is enabled as indicated by the ClockEn1 signal, the lower N-detection block counts the clock cycles on the rising edge of ClkRefDivF. Enable ClkDR and Enable ClkDF are the outputs obtained from the occurrence of the upper N-detection block 802 and the lower N-detection block 804.

[0070] exist Figure 9 In this example, the operation of counter 800 begins at time point A with the rising edge of the START signal. The rising edge of the START signal corresponds to the start of the measurement initialization cycle. The rising edge of the ClkRefDiv signal also occurs at time point A. The combination of counter 800 being in operation and the rising edge of the ClkRefDiv signal causes the next N detection block 804 to be enabled, as indicated by the rising edge of ClockEn1 at time point A.

[0071] At time point B, the rising edge of ClkRefDivF occurs. The combination of counter 800 being in operation and the rising edge of the ClkRefDivF signal causes the upper N-detection block 802 to be enabled, as indicated by the rising edge of ClockEn at time point B. Furthermore, at time point B, the combination of enabling the lower N-detection block 804 as indicated by the rising edge of the ClkRefDivF signal and the rising edge of the ClockEn1 signal causes the lower N-detection block 804 to count clock cycles. This counting is indicated by the rising edge of the Enabled ClkDF signal.

[0072] At time point C, the rising edge of ClkRefDiv occurs. At time point C, the combination of the rising edge of the upper N-detection block 802 and the ClkRefDiv signal, as indicated by the ClockEn signal, causes the upper N-detection block 802 to count clock cycles. This count is indicated by the rising edge of the Enabled ClkDR signal.

[0073] At time point D, a rising edge of ClkRefDivF occurs. At time point D, enabling the combination of the rising edge of the lower N detection block 804 and the ClkRefDivF signal, as indicated by the ClockEn1 signal, causes the lower N detection block 804 to count clock cycles. This count is indicated by the rising edge of the Enabled ClkDF signal. A rising edge of the STOP signal also occurs at point D. The rising edge of the STOP signal corresponds to the end of the measurement initialization cycle. This rising edge causes counter 460 to stop operating. With counter 460 operation paused, clock cycle counting will not continue through point D. This behavior can be seen at point E where the rising edge of ClkRefDiv occurs, but no clock cycle counting occurs on the Enabled ClkDR line.

[0074] The Enabled ClkDR and Enabled ClkDF signals correspond to the outputs of the upper N-detection block 802 and the lower N-detection block 804, respectively. As described above, the output signals drive ripple counters 806 and 808, which store the counts of the clock cycles generated by the N-detection blocks 802 and 804. The outputs from the ripple counters are received at adder 810, which adds the two count values ​​together and outputs the resulting value N on the CNT signal line. Knowing the value of N through the operation of loop counter 800, N can then be used for various purposes as described herein. For example, a memory can use N for further timing adjustments in the form of shifters and the like associated with components downstream of the delay-locked loop. The phase detector can also employ the N value to ensure that any changes to the delay applied to the forward delay array are propagated through the feedback path and reflected in the feedback signal before another phase comparison is performed.

[0075] For example, a loop counter 800 can use a divided clock to calculate the value of N (=tFP / tCK). tFP is the forward path delay, and tCK is the clock frequency. According to... Figure 8 The loop counter 800 uses two ripple counters to count the rising and falling pulses of the divided clock, respectively. The loop counter 800 then sums the values ​​obtained from the respective ripple counters. This method increases the settling time (Ts) by using a divided clock, thereby increasing the MTBF (Mean Time Between Failures) value.

[0076] The foregoing description, examples, and data provide a complete description of the structure and use of exemplary embodiments of the invention as defined in the claims. Although various embodiments have been described above with some degree of specificity or reference to one or more individual embodiments, numerous modifications can be made to the disclosed embodiments by those skilled in the art without departing from the spirit or scope of the invention. Therefore, other embodiments are contemplated. It is intended that all content contained in the foregoing description and shown in the accompanying drawings be interpreted as illustrative of particular embodiments only and not as limiting. Changes in detail or structure may be made without departing from the essential elements defined in the appended claims.

[0077] The foregoing description has broad applications. The discussion of any embodiments is merely illustrative and is not intended to imply that the scope of the invention, including the claims, is limited to these examples. In other words, although illustrative embodiments of the invention have been described in detail herein, the inventive concept may be embodied and employed in other ways, and the appended claims are intended to be construed as including such variations, unless limited by prior art.

Claims

1. A device for detecting loop counts, comprising: A delay-locked loop, configured to synchronize the internal clock signal of the memory with an externally received clock signal; A controlled delay circuit is measured, which is configured to initialize the delay-locked loop by traversing the delay-locked loop using a reference clock to determine a variable delay amount; and A loop counter coupled to the frequency-divided clock portion of the measurement-controlled delay circuit, the loop counter having a first segment configured to count clock cycles on a first frequency-divided clock signal and a second segment configured to count clock cycles on a second frequency-divided clock signal.

2. The device of claim 1, wherein the first segment of the loop counter is configured to count the first frequency-divided clock signal during a first enable period generated in response to the first frequency-divided clock signal.

3. The device of claim 2, wherein the second segment of the loop counter is configured to count the second frequency-divided clock signal during a second enable period generated in response to the second frequency-divided clock signal.

4. The device of claim 1, wherein the first segment of the loop counter includes a first detection block coupled to the first ripple counter.

5. The device of claim 4, wherein the second segment of the loop counter includes a second detection block coupled to a second ripple counter.

6. The device of claim 5, wherein the first detection block and the second detection block are enabled by start and stop signals respectively indicating the start and end of traversing the delay-locked loop.

7. The device of claim 5, wherein the loop counter includes an adder coupled to the first ripple counter and the second ripple counter, and is configured to output a value N corresponding to the number of clock cycles through the delay-locked loop by the reference clock.

8. The device according to claim 7, further comprising: A delay path configured to receive and propagate the clock signal, and to change the delay value of the clock signal in response to the value N.

9. A device for detecting loop counts, comprising: A delay-locked loop configured to synchronize the output clock signal with the input clock signal; A first clock divider circuit is configured to divide a reference clock signal into multiple parts, the reference clock signal being based on the input clock signal; A second clock divider circuit is configured to divide the feedback signal, wherein the output clock signal is based on the feedback signal; A synchronizer circuit configured to provide a measurement pulse signal based on the frequency-divided feedback signal and the frequency-divided reference clock signal; and A loop counter circuit configured to start counting based on a frequency-divided reference clock signal and to stop counting based on a measurement pulse signal, the loop counter circuit including an adder configured to sum the counts for each portion of the frequency-divided reference clock signal.

10. The device of claim 9, further comprising a variable delay component configured to delay a command signal stored based on the count provided by the loop counter circuit.

11. The device of claim 9, further comprising a measurement control delay circuit configured to apply a certain amount of delay to the reference clock signal.

12. The apparatus of claim 11, further comprising a multiplexer configured to provide the reference clock signal as the feedback signal for a first number of cycles of the input clock signal after initialization, and then provide the delayed input clock signal provided by the measurement control delay circuit.

13. The device of claim 11, further comprising a phase detector circuit configured to measure the difference between the feedback signal and the reference clock signal, wherein the delay of the measurement control delay circuit has a delay partially based on the difference measured by the phase detector circuit.

14. The device of claim 9, wherein the loop counter circuit includes a first clock path configured to count a first portion of the frequency-divided reference clock signal and a second clock path configured to count a second portion of the frequency-divided reference clock signal.

15. A method for detecting loop counts, comprising: A delay-locked loop is used to synchronize the internal clock signal of the memory with the externally received clock signal; The delay-locked loop is initialized using a measurement-controlled delay circuit to determine the variable delay amount by traversing the delay-locked loop using a reference clock; and The reference clock is divided into multiple parts; and Each of the multiple parts of the reference clock is counted using different sections of a loop counter.

16. The method of claim 15, further comprising summing the counts of each of the plurality of portions of the reference clock to determine a value N, the value N corresponding to the number of clock cycles traversing the delay-locked loop for the reference clock.

17. The method of claim 16, further comprising adjusting the value of the delay time in the delay path, wherein the delay path receives the clock signal and propagates the clock signal after the delay time.

18. The method of claim 15, further comprising starting the counting based on the reference clock and stopping the counting based on a feedback clock that has traversed the delay-locked loop and the reference clock.

19. The method of claim 15, wherein counting each of the plurality of portions of the reference clock comprises propagating each of the plurality of portions to a corresponding one of the plurality of ripple counters along a corresponding one of the plurality of clock paths.

20. The method of claim 15, wherein counting each of the plurality of portions of the reference clock includes counting each of the plurality of portions during a respective enable cycle.

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