A two-step column-level analog-to-digital converter for CMOS image sensors

Abstract

The present application relates to the technical field of analog-digital converter, more particularly to a two-step column-level analog-digital converter for CMOS image sensor. The two-step column-level analog-digital converter comprises a common switch module, a slope generator and N column-level circuit units with the same structure. The present application combines flash ADC and single-ramp ADC in circuit structure and function. On one hand, the signal voltage Vsig is coarsely quantized based on the functional state of flash ADC and stored in a storage capacitor, and the high 2-bit digital code conversion result is stored in a latch. On the other hand, the signal voltage Vsig is finely quantized based on the functional state of single-ramp ADC to obtain a low 10-bit digital code and store it in a static memory, thereby completing the entire conversion of 12 bits. The converter of the present application can shorten the quantization time and improve the conversion speed, solving the problems of low conversion speed, long quantization time and long conversion period of the existing traditional single-ramp ADC.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more specifically, to a two-step column-level analog-to-digital converter for CMOS image sensors. Background Technology

[0002] A CMOS image sensor is an image sensor manufactured using CMOS technology. It converts optical images into electrical signals, thereby achieving digital image acquisition. One of the most important modules in a CMOS image sensor is the analog-to-digital converter (ADC), which is responsible for converting analog signals from the sensor into digital signals for subsequent digital signal processing and image generation. The performance of the ADC directly affects key performance indicators of the image sensor, such as dynamic range, signal-to-noise ratio, resolution, and data transmission speed. Therefore, researching high-speed, low-power, and small-area ADCs is of great significance for improving the performance of CMOS image sensors.

[0003] In the readout circuits of image sensors, three common ADC architectures are used: pixel-level ADC, chip-level ADC, and column-level ADC. Pixel-level ADC directly converts the analog signal of each pixel into a digital signal. The advantage of this architecture is that it can directly acquire the digital signal of each pixel, but it has a larger area and consumes more power. Chip-level ADC converts the analog signal of the entire pixel array into a digital signal. The advantage of this architecture is excellent uniformity, but it requires a higher ADC speed. Column-level ADC converts the analog signal of a column of pixels into a digital signal. The advantages of this architecture are fast conversion speed, smaller area, and lower power consumption, but it requires additional circuitry to perform serial-to-parallel conversion of the digital signal for each column of pixels.

[0004] Therefore, for large pixel arrays, column-level ADCs can achieve higher conversion speeds and lower power consumption and area. Among various column-level ADCs, single-slope ADCs are the most widely used due to their small area and simple structure. However, traditional single-slope ADCs suffer from low conversion speeds, requiring 2... N The quantification and conversion cycles are both relatively long.

[0005] As the number of pixels continues to increase, the requirements for the conversion speed of ADCs are also constantly increasing. Therefore, research on improving the conversion speed of single-slope ADCs has become a research hotspot in CMOS image sensors. Summary of the Invention

[0006] Based on this, it is necessary to address the problems of low conversion speed, long quantization time, and long conversion cycle of traditional single-slope ADCs, and to provide a two-step column-level analog-to-digital converter for CMOS image sensors.

[0007] This invention is achieved using the following technical solution:

[0008] This invention discloses a two-step column-level analog-to-digital converter for CMOS image sensors, comprising: a common switch module, a ramp generator, and N column-level circuit units with the same structure.

[0009] The ramp generator is used to provide two continuous, upward ramp signals Vramp; the two ramp signals Vramp include a small ramp Vramp1 and a large ramp Vramp2, both with a starting voltage value of VL.

[0010] N identical column-level circuit units are used to process several pixel signals; each pixel signal is 12 bits. The nth column-level circuit unit is used to process 3 pixel signals; the 3 pixel signals include the 3n+1th pixel signal, the 3n+2nd pixel signal, and the 3n+3rd pixel signal; n∈[1,N].

[0011] The nth column-level circuit unit includes: PGA module, sample and hold module, storage capacitor module, built-in switch module, resistor array module, comparator module, transcoding module, counter module, static memory module, and latch module.

[0012] The built-in switch module works in conjunction with the common switch module to sequentially switch the functional states of the nth column-level circuit unit, including reset, quantization reset voltage Vrst, flash ADC coarse quantization signal voltage Vsig, and single-slope ADC fine quantization signal voltage Vsig.

[0013] The PGA module is used to amplify the input three-channel pixel signals and perform first-level correlation double sampling to obtain the reset voltage Vrst and signal voltage Vsig.

[0014] The sample-and-hold module is used to sample and store the reset voltage Vrst and the signal voltage Vsig.

[0015] The storage capacitor module is used to form a voltage difference ΔV based on the reference voltage VL' and the reference voltage VL during reset, and to store the coarsely quantized voltage Vsig' obtained after the flash ADC coarsely quantizes the signal voltage Vsig; where VL' = VL + ΔV, ΔV > 0.

[0016] The comparator module outputs corresponding signals based on the different input voltages under different functional states. Specifically, when quantizing the reset voltage Vrst, the comparator module outputs a level signal based on the voltage difference ΔV, the small ramp Vramp1, and the reset voltage Vrst. When coarsely quantizing the signal voltage Vsig in the flash ADC, the comparator module outputs a thermometer code based on the signal voltage Vsig. When finely quantizing the signal voltage Vsig in the single-ramp ADC, the comparator module outputs a level signal based on the large ramp Vramp2, the signal voltage Vsig, and the coarse quantization voltage Vsig'.

[0017] The resistor array module is located between the storage capacitor module and the comparator module, and is used to divide the reference voltage VH and the reference voltage VL.

[0018] The transcoding module includes a decoding submodule and an encoding submodule. The decoding submodule is used to convert the thermometer code output by the comparator module into a 4-bit binary code; the encoding submodule is used to convert the 4-bit binary code into the high 2 bits of the digital code.

[0019] The latch module is used to store the high 2 bits of the code.

[0020] The counter module is used to count based on the level signal output by the comparator module.

[0021] The static memory module is used to store the count in the counter module as the lower 10 bits of digital code when the single-slope ADC fine-quantizes the signal voltage Vsig.

[0022] This two-step column-level analog-to-digital converter for CMOS image sensors implements a method or process according to embodiments of this disclosure.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] This invention integrates the circuit structure and function of a flash ADC and a single-slope ADC. On one hand, based on the functional state of the flash ADC, the signal voltage Vsig is coarsely quantized and stored in a storage capacitor, and the conversion result of the high 2 bits of digital code is stored in a latch. On the other hand, based on the functional state of the single-slope ADC, the signal voltage Vsig is finely quantized to obtain the low 10 bits of digital code and stored in static memory, thereby completing the entire 12-bit conversion. Compared with the traditional single-slope ADC, which requires 12-bit quantization of the signal voltage Vsig, the converter of this invention can shorten the quantization time and improve the conversion speed. Attached Figure Description

[0025] Figure 1 This is a simplified structural diagram of the two-step column-level analog-to-digital converter used in a CMOS image sensor according to Embodiment 1 of the present invention;

[0026] Figure 2 for Figure 1 The specific circuit diagram of the analog-to-digital converter;

[0027] Figure 3 for Figure 2 Connection diagram of the nth column-level circuit unit with the common switch module and ramp generator;

[0028] Figure 4 for Figure 3 Enlarged view of the left area;

[0029] Figure 5 for Figure 3 Enlarged view of the right area;

[0030] Figure 6 for Figure 3 Timing diagram of analog-to-digital conversion performed by the nth column-level circuit unit. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] Example 1

[0035] Please see Figure 1 This embodiment 1 demonstrates a two-step column-level analog-to-digital converter for a CMOS image sensor, which includes: a common switch module, a ramp generator, and N column-level circuit units with the same structure.

[0036] N identical column-level circuit units are used to process several pixel signals; each pixel signal is 12 bits. A common switch module and a ramp generator are shared components among the N column-level circuit units. The common switch module works in conjunction with the built-in switch modules within the column-level circuit units. The ramp generator provides two consecutive, upward ramp signals Vramp; each Vramp signal consists of a small ramp Vramp1 and a large ramp Vramp2, both with a starting voltage value of VL.

[0037] Taking the nth column-level circuit unit out of N as an example: the nth column-level circuit unit is used to process 3 pixel signals; the 3 pixel signals include the 3n+1th pixel signal, the 3n+2nd pixel signal, and the 3n+3rd pixel signal; n∈[1,N]. That is to say, 3N+3 pixel signals can be processed in N column-level circuit units.

[0038] For the nth column-level circuit unit, it is divided into 10 modules according to function, including: built-in switch module, PGA module, sample and hold module, storage capacitor module, resistor array module, comparator module, transcoding module, counter module, static memory module, and latch module.

[0039] The functions of each module are described below:

[0040] 1. The built-in switch module works in conjunction with the common switch module to sequentially switch the nth column-level circuit unit between four functional states. The four functional states are reset, quantization reset voltage Vrst, flash ADC coarse quantization signal voltage Vsig, and single-slope ADC fine quantization signal voltage Vsig.

[0041] 2. The PGA module is used to amplify the input three-channel pixel signals and perform first-level correlation double sampling to obtain the reset voltage Vrst and the signal voltage Vsig.

[0042] 3. The sample-and-hold module is used to sample and store the reset voltage Vrst and the signal voltage Vsig.

[0043] 4. The storage capacitor module is used for: ① forming a voltage difference ΔV based on the reference voltage VL' and the reference voltage VL during reset; ② storing the coarsely quantized voltage Vsig' obtained after the flash ADC coarsely quantizes the signal voltage Vsig. Wherein, VL'=VL+ΔV, ΔV>0.

[0044] 5. The comparator module is used to output corresponding signals according to the different input voltages under different functional states.

[0045] Specifically:

[0046] ① When quantizing the reset voltage Vrst, the comparator module outputs a level signal based on the voltage difference ΔV, the small ramp Vramp1, and the reset voltage Vrst;

[0047] ② When the flash ADC coarsely quantizes the signal voltage Vsig, the comparator module outputs the thermometer code based on the signal voltage Vsig;

[0048] ③ When the single-slope ADC fine-quantizes the signal voltage Vsig, the comparator module outputs a level signal based on the large slope Vramp2, the signal voltage Vsig, and the coarse-quantization voltage Vsig'.

[0049] 6. The resistor array module is located between the storage capacitor module and the comparator module, and is used to divide the reference voltage VH and the reference voltage VL.

[0050] 7. The transcoding module includes a decoding submodule and an encoding submodule. The decoding submodule is used to convert the thermometer code output by the comparator module into a 4-bit binary code; the encoding submodule is used to convert the 4-bit binary code into the high 2 bits of the digital code.

[0051] 8. The latch module is used to store the high 2 bits of the digital code.

[0052] 9. The counter module is used to count based on the level signal output by the comparator module.

[0053] 10. The static memory module is used to store the count in the counter module as the lower 10 bits of digital code when the single-slope ADC fine-quantizes the signal voltage Vsig.

[0054] See Figure 2 It showed Figure 1 The specific circuit diagram of a two-step column-level analog-to-digital converter for CMOS image sensors.

[0055] The specific connection relationships of each module are explained below:

[0056] 1. The common switch module includes switches SS7 and S8. The first terminal of SS7 is connected to the output terminal of the ramp generator, and the second terminal is connected to the first terminal of S8. The second terminal of SS8 is connected to the reference voltage VL'.

[0057] 2. The PGA module includes three programmable gain amplifiers. The input of the first programmable gain amplifier is used to input the (3n+1)th pixel signal; the input of the second programmable gain amplifier is used to input the (3n+2)th pixel signal; and the input of the third programmable gain amplifier is used to input the (3n+3)th pixel signal.

[0058] The programmable gain amplifier has two functions: 1. to amplify the pixel signal to reduce the impact of comparator noise and quantization noise introduced by the subsequent ADC on the readout circuit; 2. to implement the first-stage correlated double sampling (CDS), change the swing direction of the pixel signal, and obtain the reset voltage Vrst and the signal voltage Vsig.

[0059] 3. The sample-and-hold module includes three sample-and-hold circuits. The input of the first sample-and-hold circuit is connected to the output of the first programmable gain amplifier; the output of the second sample-and-hold circuit is connected to the output of the second programmable gain amplifier; and the output of the third sample-and-hold circuit is connected to the output of the third programmable gain amplifier.

[0060] Each sample-and-hold circuit includes two sampling capacitors (not shown in the figure) to sample the reset voltage Vrst and the signal voltage Vsig obtained after passing through a programmable gain amplifier, respectively.

[0061] 4. The built-in switch module includes switches S1-S7, S9-S11, SS1-SS6, SC1-SC3, and SF1-SF8. The comparator module includes comparators Comp1-Comp3. The counter module includes three counters.

[0062] The first terminals of S1, S2, S3, and S4 are connected together, and then connected to the second terminals of S5, S6, and S7. The second terminal of S1 is connected to the first terminal of SF1. The second terminal of S2 is connected to the first terminal of SF2. The second terminal of S3 is connected to the first terminal of SF3. The second terminal of S4 is connected to the reference voltage VL. The first terminal of S5 is connected to the second terminal of SC1. The first terminal of S6 is connected to the second terminal of SC2. The first terminal of S7 is connected to the second terminal of SC3.

[0063] The output of the first sample-and-hold circuit is connected to the first terminal of S9 and the first terminal of SS1; the output of the second sample-and-hold circuit is connected to the first terminal of S10 and the first terminal of SS2; the output of the third sample-and-hold circuit is connected to the first terminal of S11 and the first terminal of SS3.

[0064] Furthermore, referring to Figure 4, the output of the first sample-and-hold circuit is regarded as Vin1, the output of the second sample-and-hold circuit is regarded as Vin2, and the output of the third sample-and-hold circuit is regarded as Vin3.

[0065] The second terminals of S9, S10, and S11 are connected together and connected to the second terminal of SS1, the first terminal of SF4, and the non-inverting input terminal of Comp1; the second terminal of SS2 is connected to the second terminal of SF4, the first terminal of SF5, and the non-inverting input terminal of Comp2; the second terminal of SS3 is connected to the second terminal of SF5 and the non-inverting input terminal of Comp3.

[0066] See Figure 4 The outputs of the second terminals of S9, S10, and S11 are considered as Vin.

[0067] The second terminal of SF1 is connected to the inverting input terminal of Comp1; the second terminal of SF2 is connected to the inverting input terminal of Comp2; and the second terminal of SF3 is connected to the inverting input terminal of Comp3.

[0068] See Figure 5 The inverting input of Comp1 is considered as V1, the inverting input of Comp2 is considered as V2, and the inverting input of Comp3 is considered as V3.

[0069] The output of Comp1 is connected to the first terminal of SS4 and the first terminal of SF6; the output of Comp2 is connected to the first terminal of SS5 and the first terminal of SF7; the output of Comp3 is connected to the first terminal of SS6 and the first terminal of SF8; the second terminals of SF6, SF7 and SF8 are connected to the transcoding module.

[0070] See Figure 5 The output of Comp1 is considered as Cout1, the output of Comp2 is considered as Cout2, and the output of Comp3 is considered as Cout3.

[0071] The control terminals of the first, second, and third counters are connected to the CLK signal; the input terminal of the first counter is connected to the second terminal of SS4; the input terminal of the second counter is connected to the second terminal of SS5; and the input terminal of the third counter is connected to the second terminal of SS6.

[0072] It should be noted that the switching states of S1 to S4 are based on the binary code output by the decoding submodule.

[0073] 5. The storage capacitor module includes capacitors C1 to C3. The upper plate of C1 is connected to the first end of S5, and the lower plate is connected to the first end of S8; the upper plate of C2 is connected to the first end of S6, and the lower plate is connected to the first end of S8; the upper plate of C3 is connected to the first end of S7, and the lower plate is connected to the first end of S8.

[0074] It should be noted that C1, C2, and C3 have the same capacitance, which makes it easy to form the same voltage difference ΔV across the capacitors during reset.

[0075] 6. The resistor array module includes resistors R1 to R4. One end of R1 is connected to the reference voltage VH, and the other end is connected to the second end of S1; one end of R2 is connected to the other end of R1, and the other end is connected to the second end of S2; one end of R3 is connected to the other end of R2, and the other end is connected to the second end of S3; one end of R4 is connected to the other end of R3, and the other end is connected to the reference voltage VL.

[0076] It should be noted that the resistance values ​​of R1, R2, R3, and R4 are equal, achieving uniform voltage distribution.

[0077] 7. The latch module includes three latches. The inputs of the first latch, the second latch, and the third latch are connected to the encoding submodule.

[0078] 8. The static memory module includes three static memories. The input of the first static memory is connected to the output of the first counter; the input of the second static memory is connected to the output of the second counter; and the input of the third static memory is connected to the output of the third counter.

[0079] Based on the above functional modules and circuit structure, the principle of analog-to-digital conversion of 12-bit pixel signals in this invention is as follows, that is, an analog-to-digital conversion method is disclosed, including the following steps:

[0080] 1. First, perform a reset: During the reset, S4 to S8 are closed; other switches are open.

[0081] The upper plates of capacitors C1, C2, and C3 are connected to a reference voltage VL, and the lower plates are connected to a reference voltage VL'. Thus, C1, C2, and C3 are charged, and the voltage difference between the upper and lower plates is ΔV (the voltage of the lower plate is VL', and the voltage of the upper plate is VL).

[0082] 2. Next, quantize the reset voltage Vrst: When quantizing the reset voltage Vrst, SC1~SC3 and SS1~SS7 are closed; the remaining switches are open.

[0083] All three sample-and-hold circuits output a reset voltage Vrst = VL. (See also...) Figure 6 At this point, Vin1 = Vin2 = Vin3 = Vrst = VL. VL serves as the non-inverting input voltage of the three comparators; the ramp generator produces a small ramp Vramp1.

[0084] In the initial stage, the lower plates of C1, C2, and C3 are connected to the ramp generator. Since Vramp1 starts from VL, and based on charge conservation, the voltage across the upper plates of C1, C2, and C3 is VL-ΔV, which serves as the voltage at the inverting input of the three comparators. See [link / reference] Figure 6 At this time, V1 = V2 = V3 = VL - ΔV.

[0085] In this way, the voltage at the inverting input of the three comparators is less than the voltage at the non-inverting input, so all three output a high level, and the three counters count down during this stage.

[0086] As the ramp Vramp1 increases, its voltage value gradually increases, and the voltages at the inverting inputs of the three comparators also rise accordingly. When the voltages at the inverting inputs of the three comparators are greater than the voltages at the non-inverting inputs, they all output a low level, causing the three counters to stop counting. At this time, the three counters record the negative code corresponding to the reset voltage Vrst.

[0087] Specifically, the first counter stores the negative code corresponding to Vin1 and uses it as the first base number; the second counter stores the negative code corresponding to Vin2 and uses it as the second base number; the third counter stores the negative code corresponding to Vin3 and uses it as the third base number; thus, the quantization reset voltage Vrst is completed.

[0088] 3. Then perform coarse quantization of the signal voltage Vsig using a flash ADC:

[0089] When the flash ADC coarsely quantizes the signal voltage Vsig, SF1-SF8 and S8 are closed, while SS1-SS7, SC1, SC2, and SC3 are open. The first sample-and-hold circuit outputs signal voltage Vsig1, the second sample-and-hold circuit outputs signal voltage Vsig2, and the third sample-and-hold circuit outputs signal voltage Vsig3. (See also...) Figure 6 At this point, Vin1 = Vsig1, Vin2 = Vsig2, Vin3 = Vsig3; VL <Vsig1<VL+(VH-VL) / 4,VL+(VH-VL) / 4<Vsig2<VL+(VH-VL) / 2,VL+(VH-VL) / 2<Vsig2<VL+3(VH-VL) / 4。

[0090] Vsig1, Vsig2, and Vsig3 are processed sequentially according to the timing sequence:

[0091] First, S5 and S9 are closed, and S6, S7, S10, and S11 are open. Vsig1 generates the first thermometer code through the resistor array module and comparator module. The first thermometer code is converted into the first binary code by the decoding submodule. The first binary code controls the switching state of S1, S2, S3, and S4 to store the coarse quantized voltage Vsig1' of Vsig1 in C1. The first binary code is converted into the high 2 bits of digital code by the encoder module and stored in the first latch.

[0092] Second, S6 and S10 are closed, and S5, S7, S10, and S11 are open. Vsig2 generates a second thermometer code through the resistor array module and comparator module. The second thermometer code is converted into a second binary code by the decoding submodule. The second binary code controls the switching states of S1, S2, S3, and S4 to store the coarse quantized voltage Vsig2' of Vsig2 in C2. The second binary code is converted into the high 2 bits of digital code by the encoder module and stored in the second latch.

[0093] Third, S7 and S11 are closed, and S5, S6, S9, and S10 are open. Vsig3 generates a third thermometer code through the resistor array module and comparator module. The third thermometer code is converted into a third binary code by the decoding submodule. The third binary code controls the switching states of S1, S2, S3, and S4 to store the coarse quantization voltage Vsig3' of Vsig3 in C3. The third binary code is converted into the high 2 bits of digital code by the encoder module and stored in the third latch.

[0094] In this way, the three coarse quantization voltages Vsig1' to Vsig3' are stored in C1, C2, and C3; at the same time, the high 2 bits of the three pixel signals are stored in three latches.

[0095] 4. Finally, perform fine quantization of the signal voltage Vsig using a single-slope ADC:

[0096] When the single-slope ADC refines the signal voltage Vsig, SC1~SC3 and SS1~SS7 are closed; other switches are open.

[0097] The first sample-and-hold circuit outputs a signal voltage Vsig1, which is used as the non-inverting input voltage of the first comparator; the second sample-and-hold circuit outputs a signal voltage Vsig2, which is used as the non-inverting input voltage of the second comparator; the third sample-and-hold circuit outputs a signal voltage Vsig3, which is used as the non-inverting input voltage of the third comparator. (See also...) Figure 6 At this point, Vin1 = Vsig1, Vin2 = Vsig2, and Vin3 = Vsig3. The ramp generator produces a large ramp, Vramp2.

[0098] In the initial stage, the voltage at the inverting input of the first comparator is Vramp2 + Vsig1', the voltage at the inverting input of the second comparator is Vramp2 + Vsig2', and the voltage at the inverting input of the third comparator is Vramp2 + Vsig3'; see [link to documentation]. Figure 6At this point, V1 = Vramp2 + Vsig1', V2 = Vramp2 + Vsig2', and V3 = Vramp2 + Vsig3'. The voltages at the inverting inputs of the three comparators are less than the voltages at the non-inverting inputs, so all three output a high level. During this stage, the three counters count upwards based on the negative code.

[0099] Specifically, the first counter performs superposition counting on the base number one; the second counter performs superposition counting on the base number two; and the third counter performs superposition counting on the base number three.

[0100] As the ramp Vramp2 increases, its voltage value gradually increases, and the voltage at the inverting inputs of the three comparators also increases accordingly. When the voltage at the inverting inputs of the three comparators is greater than the voltage at the non-inverting inputs, they all output a low level, causing the three counters to stop counting. At this time, the three static memories store the counts of the three counters as the lower 10 bits of the digital code.

[0101] Specifically, the first static memory stores the last count value of the first counter and stores it as the lower 10 bits of the digital code; the second static memory stores the last count value of the second counter and stores it as the lower 10 bits of the digital code; the third static memory stores the last count value of the third counter and stores it as the lower 10 bits of the digital code.

[0102] After fine quantization, the analog-to-digital conversion is complete. The final conversion output is obtained by combining the high 2 bits of the latch with the low 10 bits of the static memory.

[0103] Specifically, the high 2 bits of the first latch and the low 10 bits of the first static memory are combined to serve as the conversion output of the (3n+1)th pixel signal; the high 2 bits of the second latch and the low 10 bits of the second static memory are combined to serve as the conversion output of the (3n+2)th pixel signal; and the high 2 bits of the third latch and the low 10 bits of the third static memory are combined to serve as the conversion output of the (3n+3)th pixel signal.

[0104] Because a 2-bit flash ADC is used to coarsely quantize the signal voltage in the above process, the number of quantization bits of the single-slope ADC becomes 10 bits. The coarse quantization process is very fast. Compared with directly using a 12-bit single-slope ADC, the speed is increased by 4 times. Therefore, the circuit as a whole can improve the conversion speed and shorten the quantization time.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A two-step column-level analog-to-digital converter for CMOS image sensors, characterized in that, Common switch module; A ramp generator is used to provide two continuous, upward ramp signals Vramp; wherein the two ramp signals Vramp include a small ramp Vramp1 and a large ramp Vramp2, both with a starting voltage value of VL; as well as N identical column-level circuit units are used to process several pixel signals; each pixel signal is 12 bits; the nth column-level circuit unit is used to process 3 pixel signals; the 3 pixel signals include the 3n+1th pixel signal, the 3n+2nd pixel signal, and the 3n+3rd pixel signal; n∈[1,N]; The nth column-level circuit unit includes: PGA module, sample and hold module, storage capacitor module, built-in switch module, resistor array module, comparator module, transcoding module, counter module, static memory module, and latch module; The built-in switch module works in conjunction with the common switch module to sequentially switch the functional states of the nth column-level circuit unit: reset, quantization reset voltage Vrst, flash ADC coarse quantization signal voltage Vsig, and single-slope ADC fine quantization signal voltage Vsig. The PGA module amplifies the input three-channel pixel signals and performs first-level correlation double sampling to obtain the reset voltage Vrst and signal voltage Vsig. The sample-and-hold module samples and stores the reset voltage Vrst and signal voltage Vsig. The storage capacitor module forms a voltage difference ΔV based on the reference voltage VL' and the reference voltage VL during reset, and stores the coarse quantization voltage Vsig' obtained after flash ADC coarse quantization of the signal voltage Vsig; where VL' = VL + ΔV, ΔV > 0. The comparator module outputs a corresponding signal based on the different input voltages under different functional states; specifically, when quantizing the reset voltage Vrst, the comparator module outputs a signal based on the voltage difference... The comparator module outputs a level signal based on ΔV, small ramp Vramp1, and reset voltage Vrst. When the coarse quantization signal voltage Vsig is in the fast-slope ADC, the comparator module outputs a thermometer code based on the signal voltage Vsig. When the fine quantization signal voltage Vsig is in the single-slope ADC, the comparator module outputs a level signal based on the large ramp Vramp2, the signal voltage Vsig, and the coarse quantization voltage Vsig'. The resistor array module is located between the storage capacitor module and the comparator module and is used to divide the reference voltages VH and VL. The transcoding module includes a decoding submodule and an encoding submodule. The decoding submodule converts the thermometer code output by the comparator module into a 4-bit binary code. The encoding submodule converts the 4-bit binary code into the high 2 bits of a digital code. The latch module stores the high 2 bits of the digital code. The counter module counts based on the level signal output by the comparator module. The static memory module stores the count in the counter module as the low 10 bits of a digital code when the fine quantization signal voltage Vsig is in the single-slope ADC.

2. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 1, characterized in that, The common switch module includes: switches SS7 and S8; wherein... The first end of SS7 is connected to the output end of the ramp generator, and the second end is connected to the first end of S8. The second terminal of SS8 is connected to the reference voltage VL'.

3. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 2, characterized in that, The PGA module includes three programmable gain amplifiers; among which, The input of the first programmable gain amplifier is used to input the (3n+1)th pixel signal; The input of the second programmable gain amplifier is used to input the 3n+2th pixel signal; The input of the third programmable gain amplifier is used to input the (3n+3)th pixel signal; The sample-and-hold module includes three sample-and-hold circuits; wherein... The input of the first sample-and-hold circuit is connected to the output of the first programmable gain amplifier; The output of the second acquisition and hold circuit is connected to the output of the second programmable gain amplifier; The output of the third acquisition and hold circuit is connected to the output of the third programmable gain amplifier.

4. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 3, characterized in that, The built-in switch module includes switches S1-S7, S9-S11, SS1-SS6, SC1-SC3, and SF1-SF8; the comparator module includes comparators Comp1-Comp3; and the counter module includes three counters. The switching states of S1 to S4 are based on the binary code output by the decoding submodule; The first terminals of S1, S2, S3, and S4 are connected together, and then connected to the second terminals of S5, S6, and S7; the second terminal of S1 is connected to the first terminal of SF1; the second terminal of S2 is connected to the first terminal of SF2; the second terminal of S3 is connected to the first terminal of SF3; the second terminal of S4 is connected to the reference voltage VL; the first terminal of S5 is connected to the second terminal of SC1; the first terminal of S6 is connected to the second terminal of SC2; and the first terminal of S7 is connected to the second terminal of SC3. The output of the first sample-and-hold circuit is connected to the first terminal of S9 and the first terminal of SS1; the output of the second sample-and-hold circuit is connected to the first terminal of S10 and the first terminal of SS2; the output of the third sample-and-hold circuit is connected to the first terminal of S11 and the first terminal of SS3. The second terminals of S9, S10, and S11 are connected together and connected to the second terminal of SS1, the first terminal of SF4, and the non-inverting input terminal of Comp1; the second terminal of SS2 is connected to the second terminal of SF4, the first terminal of SF5, and the non-inverting input terminal of Comp2; the second terminal of SS3 is connected to the second terminal of SF5 and the non-inverting input terminal of Comp3. The second terminal of SF1 is connected to the inverting input terminal of Comp1; the second terminal of SF2 is connected to the inverting input terminal of Comp2; the second terminal of SF3 is connected to the inverting input terminal of Comp3. The output of Comp1 is connected to the first terminal of SS4 and the first terminal of SF6; the output of Comp2 is connected to the first terminal of SS5 and the first terminal of SF7; the output of Comp3 is connected to the first terminal of SS6 and the first terminal of SF8; the second terminals of SF6, SF7 and SF8 are connected to the transcoding module. The control terminals of the first, second, and third counters are connected to the CLK signal; the input terminal of the first counter is connected to the second terminal of SS4; the input terminal of the second counter is connected to the second terminal of SS5; and the input terminal of the third counter is connected to the second terminal of SS6.

5. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 4, characterized in that, The storage capacitor module includes capacitors C1 to C3; wherein... The upper electrode plate of C1 is connected to the first end of S5, and the lower electrode plate is connected to the first end of S8. The upper electrode plate of C2 is connected to the first end of S6, and the lower electrode plate is connected to the first end of S8. The upper electrode plate of C3 is connected to the first end of S7, and the lower electrode plate is connected to the first end of S8. The resistor array module includes resistors R1 to R4; wherein... One end of R1 is connected to the reference voltage VH, and the other end is connected to the second end of S1; One end of R2 is connected to the other end of R1, and the other end is connected to the second end of S2; One end of R3 is connected to the other end of R2, and the other end is connected to the second end of S3; One end of R4 is connected to the other end of R3, and the other end is connected to the reference voltage VL.

6. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 5, characterized in that, The latch module includes three latches; among which, The input terminals of the first latch, the second latch, and the third latch are connected to the encoding submodule; The static memory module includes three static memories; among them, The input of the first static memory is connected to the output of the first counter; The input of the second static memory is connected to the output of the second counter; The input of the third static memory is connected to the output of the third counter.

7. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 6, characterized in that, During reset, S4 to S8 are closed; the upper plates of C1, C2, and C3 are connected to the reference voltage VL, and the lower plates are connected to the reference voltage VL'; C1, C2, and C3 are charged, and the voltage difference between the upper and lower plates is ΔV.

8. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 7, characterized in that, When the reset voltage Vrst is quantized, SC1~SC3 and SS1~SS7 are closed; all three sample-and-hold circuits output the reset voltage Vrst=VL; VL serves as the non-inverting input voltage of the three comparators; the ramp generator produces a small ramp Vramp1; In the initial stage, the voltage of the upper plate of C1, C2, and C3 is VL-ΔV, which serves as the voltage of the inverting input of the three comparators. Since the voltage of the inverting input of the three comparators is less than the voltage of the non-inverting input, they all output a high level. During this stage, the three counters count down. As the ramp Vramp1 rises, the voltage at the inverting input of the three comparators also rises. When the voltage at the inverting input of the three comparators is greater than the voltage at the non-inverting input, they all output a low level, causing the three counters to stop counting. At this time, the three counters record the negative code corresponding to the reset voltage Vrst.

9. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 8, characterized in that, When the flash ADC coarse quantization signal voltage Vsig is reached, SF1~SF8 and S8 are closed, SS1~SS7, SC1, SC2 and SC3 are open, the first sample-and-hold circuit outputs the signal voltage Vsig1, the second sample-and-hold circuit outputs the signal voltage Vsig2, and the third sample-and-hold circuit outputs the signal voltage Vsig3. Vsig1, Vsig2, and Vsig3 are processed sequentially according to time order; among them, When S5 and S9 are closed and S6, S7, S10, and S11 are open, Vsig1 generates the first thermometer code through the resistor array module and comparator module. The first thermometer code is converted into the first binary code by the decoding submodule. The first binary code controls the switching states of S1, S2, S3, and S4 to store the coarse quantized voltage Vsig1' of Vsig1 in C1. The first binary code is converted into the high 2 bits of digital code by the encoder module and stored in the first latch. When S6 and S10 are closed and S5, S7, S10, and S11 are open, Vsig2 generates a second thermometer code through the resistor array module and comparator module. The second thermometer code is converted into a second binary code by the decoding submodule. The second binary code controls the switching states of S1, S2, S3, and S4 to store the coarse quantized voltage Vsig2' of Vsig2 in C2. The second binary code is converted into the high 2 bits of digital code by the encoder module and stored in the second latch. When S7 and S11 are closed and S5, S6, S9, and S10 are open, Vsig3 generates a third thermometer code through the resistor array module and comparator module. The third thermometer code is converted into a third binary code by the decoding submodule. The third binary code controls the switching states of S1, S2, S3, and S4 to store the coarse quantization voltage Vsig3' of Vsig3 in C3. The third binary code is converted into the high 2 bits of digital code by the encoder module and stored in the third latch.

10. The two-step column-level analog-to-digital converter for CMOS image sensors according to claim 9, characterized in that, When the single-slope ADC refines the signal voltage Vsig, SC1~SC3 and SS1~SS7 are closed; the first sample-and-hold circuit outputs the signal voltage Vsig1, which is used as the non-inverting input voltage of the first comparator; The second sample-and-hold circuit outputs a signal voltage Vsig2, which is used as the non-inverting input voltage of the second comparator; the third sample-and-hold circuit outputs a signal voltage Vsig3, which is used as the non-inverting input voltage of the third comparator; the ramp generator produces a large ramp Vramp2; In the initial stage, the voltage at the inverting input of the first comparator is Vramp2 + Vsig1', the voltage at the inverting input of the second comparator is Vramp2 + Vsig2', and the voltage at the inverting input of the third comparator is Vramp2 + Vsig3'. The voltage at the inverting input of each of the three comparators is less than the voltage at the non-inverting input, so all three output a high level. During this stage, the three counters count upwards based on the negative code. As the ramp Vramp2 increases, the voltage at the inverting input of the three comparators also increases. When the voltage at the inverting input of the three comparators is greater than the voltage at the non-inverting input, they all output a low level, causing the three counters to stop counting. At this time, the three static memories store the counts of the three counters as the lower 10 bits of the digital code.

Images