Successive approximation analog-to-digital conversion circuit and method with optimized linearity

Abstract

The present application provides a successive approximation analog-to-digital conversion circuit with optimized linearity, comprising a control circuit, a capacitor array and a comparator, wherein the capacitor array comprises a low-bit capacitor array, a high-bit capacitor array and a capacitor enabling circuit. The low-bit capacitor array comprises low-bit capacitors. The high-bit capacitor array comprises a residue capacitor and a unit capacitor. In an initial mode, the control circuit sorts the unit capacitors according to their unit capacitor values, and configures the unit capacitors and the residue capacitor as high-bit capacitors with linearity parameters within a preset range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, the comparator generates a comparison result according to the analog output signal, and the control circuit generates an enabling signal according to the comparison result through a successive approximation mechanism, so as to selectively enable the high-bit and low-bit capacitors to be connected to the reference voltage through the capacitor enabling circuit, and further generate a digital output signal according to a final comparison result.

Description

Technical Field

[0001] This invention relates to analog-to-digital conversion technology, and more particularly to a successive approximation analog-to-digital conversion circuit and method with optimized linearity. Background Technology

[0002] An analog-to-digital converter (ADC) is a device used to convert continuous analog signals into discrete digital signals. Among these, the successive approximation ADC is a mainstream and common design.

[0003] In existing successive approximation analog-to-digital converter (ADC) designs, most utilize capacitor arrays. However, the capacitors in these arrays often deviate from ideal values ​​due to manufacturing processes or environmental temperature variations, resulting in suboptimal linearity in the ADC. Achieving high resolution hinges on the accuracy of the relative proportions between these capacitors. Mitigating the nonlinearity caused by capacitor mismatch presents a significant challenge. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a successive approximation analog-to-digital converter circuit and method with optimized linearity to improve the prior art.

[0005] This invention includes a successive approximation analog-to-digital converter circuit with optimized linearity, comprising: a control circuit, at least one capacitor array, and a comparator. The capacitor array includes: a low-order capacitor array, a high-order capacitor array, and a capacitor enable circuit. The low-order capacitor array includes multiple low-order capacitors. The high-order capacitor array includes multiple unit capacitors, each unit capacitor having approximately equal unit capacitance values. The comparator is electrically coupled between the capacitor array and the control circuit. In an initial mode, the control circuit sorts the multiple unit capacitors according to their capacitance values ​​to generate a sorting result, and configures the multiple unit capacitors as multiple high-order capacitors according to the sorting result, so that the linearity parameter among the high-order capacitors is within a preset range. In an operating mode, the capacitor array receives an analog input signal and multiple reference voltages to generate an analog output signal. The comparator generates a comparison result based at least on the analog output signal. The control circuit generates an enable signal based on the comparison result through a successive approximation mechanism, selectively enabling the high-order and low-order capacitors through the capacitor enable circuit, thereby connecting each capacitor to one of the multiple reference voltages, and further generating a digital output signal based on the final comparison result.

[0006] The present invention also includes a successive approximation analog-to-digital conversion method with optimized linearity, applied in a successive approximation analog-to-digital conversion circuit. The successive approximation analog-to-digital conversion includes a control circuit, at least one capacitor array, and a comparator. The capacitor array includes a low-order capacitor array, a high-order capacitor array, and a capacitor enable circuit. The low-order capacitor array includes multiple low-order capacitors, and the high-order capacitor array includes multiple unit capacitors, each of which has approximately equal unit capacitance values. The comparator is electrically coupled between the capacitor array and the control circuit. The successive approximation analog-to-digital conversion method includes: in an initial mode, a control circuit sorts multiple unit capacitors according to their capacitance values ​​to generate a sorting result; in the initial mode, the control circuit configures the multiple unit capacitors as multiple high-order capacitors according to the sorting result, so that the linearity parameter between the high-order capacitors is within a preset range; in an operating mode, a capacitor array receives an analog input signal and multiple reference voltages to generate an analog output signal, and a comparator generates a comparison result based at least on the analog output signal; and in the operating mode, the control circuit generates an enable signal based on the comparison result through a successive approximation mechanism, so as to selectively enable high-order and low-order capacitors through a capacitor enable circuit, thereby connecting each capacitor to one of the multiple reference voltages, and further generating a digital output signal based on the final comparison result.

[0007] The features, practical operation, and technical effects of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1A According to a single-ended architecture embodiment of the present invention, a circuit diagram of a successive approximation analog-to-digital converter circuit with optimized linearity is shown.

[0009] Figure 1B According to a differential architecture embodiment of the present invention, a circuit diagram of a successive approximation analog-to-digital converter circuit with optimized linearity is shown.

[0010] Figure 2A It shows Figure 1A A detailed circuit diagram of one embodiment of a capacitor array;

[0011] Figure 2B It shows Figure 2A The equivalent circuit diagram of the capacitor array;

[0012] Figures 3A to 3D This diagram illustrates a procedure in which the control circuit sorts unit capacitors according to their unit capacitance values, according to one embodiment of the present invention; and

[0013] Figure 4 A flowchart of a successive approximation analog-to-digital conversion method with optimized linearity is shown according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 200: Low-level capacitor array; 210: High-level capacitor array; 220: Capacitor enable circuit

[0016] ANI: Analog input signal; ANO: Analog output signal; AS1~AS7: Distribution signals

[0017] CD1~CD2: Residual capacitance; CH1~CH3: High-level capacitance; CL1~CL4: Low-level capacitance

[0018] CU1~CU7: Unit capacitance; EH1~EH3: High-order enable signal; EL1~EL4: Low-order enable signal

[0019] EN: Enable signal; LE1~LE4: Low-order enable circuit; MU1~MU7: Multiplexer

[0020] RE1~RE2: Residual capacitance enabling; UU1~UU7: Unit capacitance enabling.

[0021] Circuit Circuit Detailed Implementation

[0022] One object of the present invention is to provide a successive approximation analog-to-digital converter circuit and method with optimized linearity, wherein the unit capacitor is sorted by a control circuit and then configured with the corresponding residual capacitor so that the resulting high-order capacitor has better linearity.

[0023] Please refer to Figure 1A . Figure 1A According to a single-ended architecture embodiment of the present invention, a circuit diagram of a successive approximation analog-to-digital converter circuit 100 with optimized linearity is shown.

[0024] The single-ended successive approximation analog-to-digital converter circuit 100 includes a control circuit 110, a capacitor array 120, and a comparator 130. The comparator 130 is electrically coupled between the capacitor array 120 and the control circuit 110.

[0025] The single-ended successive approximation analog-to-digital converter circuit 100 can operate in both initial mode and operating mode.

[0026] In the initial mode, the control circuit 110 processes the capacitance values ​​of the multiple capacitors in the capacitor array 120 to determine the configuration of the capacitor array 120.

[0027] In operation, the single-ended capacitor array 120 receives an analog input signal ANI and multiple reference voltages VREF. The reference voltages VREF may include a positive reference voltage and / or ground voltage. Control circuit 110 generates an enable signal EN to enable or disable the multiple capacitors included in the capacitor array 120, causing the capacitor array 120 to connect to one of different reference voltages VREF based on the enabled / disabled capacitor combinations, generating an analog output signal ANO. Comparator 130 further compares the analog output signal ANO with the virtual ground potential VGND to generate a comparison result CR.

[0028] The control circuit 110 uses a successive approximation mechanism to generate an enable signal EN based on the comparison result CR, and then adjusts the capacitor array 120 until the final comparison result CR shows that the analog output signal ANO and the virtual ground potential VGND are approximately equal. At this point, the set of digital codes corresponding to the enable signal EN is the analog-to-digital conversion result of the analog input signal ANO, and is output as the digital output signal DOUT.

[0029] It should be noted that, in one embodiment, the term "approximately equal" as used above can, in actual operation, mean that the difference between the analog output signal ANO and the reference voltage VREF is less than a preset level, and this preset level can be, for example, but not limited to, the amount of the least significant bit (LSB).

[0030] Please refer to Figure 1B . Figure 1B According to a differential architecture embodiment of the present invention, a circuit diagram of a successive approximation analog-to-digital converter circuit 100' with optimized linearity is shown.

[0031] The differential architecture successive approximation analog-to-digital converter circuit 100' includes: a control circuit 110, capacitor arrays 120A and 120B, and a comparator 130. The comparator 130 is electrically coupled between the capacitor arrays 120A and 120B and the control circuit 110.

[0032] The successive approximation analog-to-digital converter circuit 100' with differential architecture can also operate in initial mode and operating mode.

[0033] In the initial mode, the control circuit 110 processes the capacitance values ​​of multiple capacitors in the capacitor arrays 120A and 120B to determine the configuration of the capacitor arrays 120A and 120B.

[0034] In operation, differential capacitor arrays 120A and 120B receive analog input signals ANIA and ANIB, and one or more reference voltages VREF, respectively. Control circuit 110 generates an enable signal EN to enable or disable multiple capacitors in capacitor arrays 120A and 120B, causing capacitor arrays 120A and 120B to be connected to one of different reference voltages VREF based on the enabled / disabled capacitor combinations, generating analog output signals ANOA and ANOB. Comparator 130 further compares the analog output signals ANOA and ANOB to generate a comparison result CR.

[0035] The control circuit 110 uses a successive approximation mechanism to generate an enable signal EN based on the comparison result CR, and then adjusts the capacitor arrays 120A and 120B until the final comparison result CR shows that the analog output signals ANOA and ANOB are approximately equal. At this time, the set of digital codes corresponding to the enable signal EN is the analog-to-digital conversion result of the analog input signals ANIA and ANIB, and is output as a digital output signal DOUT. It should be noted that, in one embodiment, the term "approximately equal" can, in actual operation, mean that the difference between the analog output signals ANOA and ANOB is less than a preset level, and this preset level can be, for example, but not limited to, the least significant bit.

[0036] The following paragraphs will be in the format of Figure 1A Using capacitor array 120 as an example, the structure of capacitor array 120 and the processing and control of capacitor array 120 by control circuit 110 are described in detail. Figure 1B The capacitor arrays 120A and 120B have the same architecture and operation as the capacitor array 120, and will not be described in detail here.

[0037] Please refer to the following at the same time Figure 2A as well as Figure 2B . Figure 2A It shows Figure 1A A detailed circuit diagram of one embodiment of the capacitor array 120. Figure 2B It shows Figure 2A The equivalent circuit diagram of capacitor array 120 is shown below. Those skilled in the art can follow... Figures 2A-2B Derivation Figure 1B Examples of capacitor arrays 120A / 120B.

[0038] The capacitor array 120 includes: a low-level capacitor array 200, a high-level capacitor array 210, and a capacitor enable circuit 220.

[0039] The low-side capacitor array 210 includes multiple low-side capacitors CL1 to CL4, each with a different low-side capacitance value.

[0040] like Figure 2AAs shown, the high-level capacitor array 220 includes multiple residual capacitors CD1 to CD2 and multiple unit capacitors CU1 to CU7, and is configured to form Figure 2B In this structure, there are multiple high-level capacitors CH1 to CH3, each with different high-level capacitance values. Among them, each unit capacitor CU1 to CU7 has approximately equal unit capacitance values. It should be noted that, ideally, each unit capacitor CU1 to CU7 should have exactly equal unit capacitance values. Therefore, the term "approximately equal" means that due to process variations or temperature variations, the unit capacitance values ​​of each unit capacitor CU1 to CU7 will have a reasonable margin of error.

[0041] In one embodiment, the residual capacitance values ​​of each residual capacitor CD1 to CD2 are less than or equal to the unit capacitance values ​​of each unit capacitor CU1 to CU7. The low-level capacitance values ​​of each low-level capacitor CL1 to CL4 are less than or equal to the high-level capacitance values ​​of the high-level capacitors CH1 to CH3.

[0042] In one numerical example, the unit capacitors CU1 to CU7 have approximately equal unit capacitance values ​​of 7C. The residual capacitors CD1 to CD2 have residual capacitance values ​​of 1C. The low-level capacitors CL1 to CL4 have low-level capacitance values ​​of 6C, 3C, 2C, and 1C, respectively. It should be noted that in this example, the low-level capacitance values ​​of CL1 to CL4 are all less than the capacitance values ​​of the unit capacitors CU1 to CU7. However, in practice, the low-level capacitance values ​​of CL1 to CL4 may be greater than or equal to the capacitance values ​​of the unit capacitors CU1 to CU7.

[0043] It should be noted that the above embodiments are based on the premise that the residual capacitance values ​​of each residual capacitor are equal and the low-level capacitance values ​​of each low-level capacitor are different. However, in other embodiments, the residual capacitance values ​​of each residual capacitor may be different, and the low-level capacitance values ​​of each low-level capacitor may be the same.

[0044] In the initial mode, Figure 1A Control circuit 110 determines Figure 2A The configuration of unit capacitors CU1 to CU7 and residual capacitors CD1 to CD2 forms an equivalent to Figure 2B The multiple high-level capacitors CH1 to CH3 are present.

[0045] More specifically, in the initial mode, Figure 1A Control circuit 110 Figure 2A The unit capacitors CU1 to CU7 are sorted according to their unit capacitance values, generating a sorting result. The unit capacitors CU1 to CU7 and the residual capacitors CD1 to CD2 are then configured according to the sorting result to form... Figure 2BThere are multiple high-level capacitors CH1 to CH3, and each of the high-level capacitors CH1 to CH3 has a different high-level capacitance value.

[0046] In one embodiment, each high-level capacitor CH1 to CH3 includes at least one of the unit capacitors CU1 to CU7 and selectively includes one of the residual capacitors CD1 to CD2.

[0047] For example, when the high-level capacitor values ​​of CH1 to CH3 are set to 29C, 14C and 8C respectively, the control circuit 110 can configure four unit capacitors and one residual capacitor as high-level capacitor CH1 (7×4+1=29), two unit capacitors as high-level capacitor CH2 (7×2=14), and one unit capacitor and one residual capacitor as high-level capacitor CH3 (7+1=8) according to the sorting result.

[0048] According to the configuration based on the sorting results, the linearity parameters of the high-order capacitors CH1 to CH3 will be within a preset range.

[0049] In order for the capacitor array 120 to operate in the manner described above, Figure 1A The control circuit 110 needs to perform a sorting procedure first, and then enable the capacitors according to the sorting results. The following will explain (1) the operation of the sorting procedure, (2) the capacitor enabling method, and (3) the improvement of the linearity parameter in sequence.

[0050] (1) How the sorting procedure works: First, the working method of the sorting procedure will be explained in the following paragraphs.

[0051] The sorting procedure performed by the control circuit 110 on the unit capacitors CU1 to CU7 includes K sorting stages, each corresponding to multiple items to be processed, where K is an integer greater than or equal to 1, and the item to be processed corresponding to the first sorting stage is the unit capacitance value of the unit capacitor.

[0052] The control circuit 110 performs sorting and combination actions on the items to be processed in K sorting stages.

[0053] In a preferred embodiment, the sorting action may be to sort the sum of the capacitance values ​​of the unit capacitors included in the items to be processed from largest to smallest or smallest to largest to generate multiple sorted items. The combining action may be to combine sorted items greater than or equal to the median and sorted items less than or equal to the median in pairs to generate multiple combined items. The combined items generated in each of the first K-1 sorting stages are the items to be processed in the next sorting stage, and the combined items generated in the Kth sorting stage are multiple items to be assigned.

[0054] After the sorting action is completed in each of the K sorting stages, the control circuit 110 determines from the high-order capacitors to be configured which require an odd number of sorting items to be allocated, and assigns them as the odd-numbered capacitors for this sorting stage. If there is more than one odd-numbered capacitor in this stage, the multiple unit capacitors corresponding to at least one of the middle sorting items are selected from the sorting items and allocated to the odd-numbered capacitors, and then the combination action is performed.

[0055] The control circuit 110 allocates the unit capacitor corresponding to the item to be allocated generated in the Kth sorting stage to the remaining multiple non-odd capacitors.

[0056] In one embodiment, the control circuit 110 further performs a combination operation on the remaining final sorting items to generate multiple combined items, and assigns the combined items to the remaining non-odd capacitors.

[0057] In one embodiment, whether the combination action is performed on the sorted items in the first K-1 sorting stages or on the remaining final sorted items after the Kth sorting stage, the combination action performed by the control circuit 110, when the number of multiple items to be combined is N, is as follows: A increases from 1 to... In the case of pairing the A-th and N+1-A-th items sequentially, where N is a positive integer, This is the floor function.

[0058] The following will be paired Figures 3A to 3D The usage scenarios are explained step by step to illustrate the actual operation process of the sorting program.

[0059] Please refer to Figures 3A to 3D . Figures 3A to 3D The diagram illustrates a procedure in which the control circuit 110 sorts unit capacitors CU1 to CU7 according to their unit capacitance values, according to an embodiment of the present invention. Each unit capacitor CU1 to CU7 is represented by a rectangle, and the length of the rectangle represents the size of the unit capacitance value.

[0060] like Figure 3A As shown, the unit capacitance values ​​of unit capacitors CU1 to CU7 before sorting are not arranged regularly.

[0061] The control circuit 110 is configured to perform a first-stage sorting of the unit capacitors CU1 to CU7. In this embodiment, the sorting action of the first-stage sorting is to sort the items to be processed (the capacitance values ​​of unit capacitors CU1 to CU7) from smallest to largest, generating a result such as... Figure 3B The sorting items are shown below. More specifically, the sorting items include the capacitance values ​​of the unit capacitance CU6, CU3, CU1, CU7, CU5, CU4, and CU2, ordered from smallest to largest, and there are 7 of them (N=7).

[0062] Control circuit 110 determines that only the high-order capacitor CH3 needs to be allocated an odd number of unit capacitors corresponding to sorted items (i.e., it needs to be allocated 1 unit capacitor), and determines that the high-order capacitor CH3 is an odd-numbered capacitor. The other high-order capacitors CH1 and CH2 are non-odd-numbered capacitors. At this time, control circuit 110 will select the middle unit capacitor CU7 and allocate it to the high-order capacitor CH3.

[0063] The control circuit 110 further performs combination operations to sequentially combine the first sorting item (A=1) with the seventh sorting item (N+1-A=7), combine the second sorting item (A=2) with the sixth sorting item (N+1-A=6), and finally combine the third sorting item... Combined with the 5th sorted item (N+1-A=5), it produces Figure 3C The combined items in the text. More specifically, these combined items include unit capacitors CU6 and CU2, unit capacitors CU3 and CU4, and unit capacitors CU1 and CU5.

[0064] When the sorting procedure includes only one sorting stage (K=1), the combined items generated in the first sorting stage are the items to be assigned. The control circuit 110 assigns the items to be assigned, in an arbitrary or specified manner, these three combined items, which together contain 6 unit capacitors, to the high-order capacitor CH1, which requires 4 unit capacitors, and the high-order capacitor CH2, which requires 2 unit capacitors.

[0065] On the other hand, when the sorting procedure includes two sorting stages (K=2), the combined items generated in the first sorting stage become the items to be processed in the second sorting stage. The sorting action in the second sorting stage sorts the items to be processed (the sum of the capacitance values ​​of unit capacitors CU6 and CU2, the sum of the capacitance values ​​of unit capacitors CU3 and CU4, and the sum of the capacitance values ​​of unit capacitors CU1 and CU5) from smallest to largest, producing items such as... Figure 3D The sorted items are shown below. More specifically, these sorted items include the capacitance values ​​of unit capacitors CU3 and CU4, CU6 and CU2, and CU1 and CU5, sorted from smallest to largest.

[0066] Since each sorting item includes two unit capacitors, among the remaining high-order capacitors CH1 and CH2 to be configured (high-order capacitor CH3 has already been allocated in the first sorting stage), high-order capacitor CH1 requires two unit capacitors corresponding to sorting items (a total of four unit capacitors), and high-order capacitor CH2 requires one unit capacitor corresponding to a sorting item (a total of two unit capacitors). Therefore, the control circuit 110 determines that high-order capacitor CH2 is an odd-numbered capacitor, while high-order capacitor CH1 is a non-odd-numbered capacitor.

[0067] As mentioned above, the control circuit 110 will select the middle sorting item (the capacitance values ​​of unit capacitors CU6 and CU2) and allocate the unit capacitors CU6 and CU2 corresponding to this sorting item to the high-order capacitor CH2.

[0068] The control circuit 110 further performs a combination operation to combine the first sorting item with the third sorting item to generate a combination item that includes the capacitance values ​​of unit capacitors CU3, CU4, CU1, and CU5, and this combination item is the item to be assigned. The control circuit 110 assigns the unit capacitors CU3, CU4, CU1, and CU5 corresponding to this item to be assigned to the high-order capacitor CH1.

[0069] The following examples illustrate how the sorting program operates with different numbers of capacitors.

[0070] In the first use case, the number of high-order capacitors is 4 (e.g., CH1 to CH4), requiring 4, 4, 2, and 1 unit capacitors respectively, totaling 11 unit capacitors. Therefore, after the sorting action of the first sorting procedure, the high-order capacitor CH4 will be determined as an odd-numbered capacitor and assigned to the middle sorting item (the 6th sorting item) with 1 unit capacitor. After the combination action of the first sorting procedure, the remaining 10 unit capacitors are combined into 5 groups of 5. When the sorting procedure includes only one sorting stage, the 5 group of 5 groups of 5 will be assigned as items to be allocated in any or specified manner, sequentially assigning the corresponding two groups of 4, two groups of 4, and one group of 2 unit capacitors to the high-order capacitors CH1 to CH3.

[0071] When the sorting procedure includes two sorting stages, the five combined items will be sorted as items to be processed in the second sorting stage. At this time, the high-order capacitors CH1 to CH3 require 2, 2, and 1 unit capacitors corresponding to the sorting items in this stage (each sorting item corresponds to 2 unit capacitors). The middle sorting item (the third sorting item) is assigned to the high-order capacitor CH3, which has an odd number of capacitors in this stage. The remaining sorting items are then used to generate two combined items (a set of 4 unit capacitors) in the manner of the first and fifth combinations and the second and fourth combinations, respectively. These are then assigned as items to be allocated, and the corresponding two combined items are sequentially assigned to the high-order capacitors CH1 to CH2 in any or specified manner.

[0072] In the second use case, the number of high-order capacitors is 5 (e.g., CH1 to CH5), requiring 4, 3, 3, 2, and 1 unit capacitors respectively, totaling 13 unit capacitors. Therefore, after the sorting action of the first sorting procedure, the high-order capacitors CH2, CH3, and CH5 will be determined as odd-numbered capacitors and will be allocated 1 unit capacitor to each of the three middle sorting items (sorting items 6 to 8) in an arbitrary or specified manner. The high-order capacitors CH1 to CH5 will also require 4, 2, 2, 2, and 0 unit capacitors respectively. After the combination action of the first sorting procedure, the remaining 10 unit capacitors will be combined into 5 combination items in pairs. When the sorting procedure includes only one sorting stage, the 5 combination items will be assigned as items to be allocated in an arbitrary or specified manner, sequentially allocating two groups of 4 unit capacitors to the high-order capacitor CH1 and one group of 2 unit capacitors to the high-order capacitors CH2 to CH4 respectively.

[0073] When the sorting procedure includes two sorting stages, the five combined items will be sorted as items to be processed in the second sorting stage. At this time, the high-order capacitors CH1 to CH4 require 2, 1, 1, and 1 unit capacitors corresponding to sorting items in this stage (each sorting item corresponds to 2 unit capacitors). The two unit capacitors corresponding to the three middle sorting items (the 2nd to 4th sorting items) are allocated to the high-order capacitors CH2 to CH4, which have an odd number of capacitors in this stage, in any or a specified manner. The remaining sorting items are then combined into a combined item (a group of 4 unit capacitors) using the 1st and 5th combination method, and this combined item is assigned to the high-order capacitor CH1 as an item to be allocated.

[0074] In the third use case, the number of high-order capacitors is 4 (e.g., CH1 to CH4), requiring 5, 4, 3, and 2 unit capacitors respectively, totaling 14 unit capacitors. Therefore, after the sorting action of the first sorting procedure, high-order capacitors CH1 and CH3 will be determined as odd-numbered capacitors and will be allocated 1 unit capacitor to each of the two middle sorting items (sorting items 7 and 8) in an arbitrary or specified manner. High-order capacitors CH1 to CH4 will also require 4, 4, 2, and 2 unit capacitors respectively. After the combination action of the first sorting procedure, the remaining 12 unit capacitors will be combined into 6 combination items in pairs. When the sorting procedure includes only one sorting stage, the 6 combination items will be assigned as items to be allocated in an arbitrary or specified manner, sequentially allocating the corresponding two groups of 4 unit capacitors to high-order capacitors CH1 to CH2, and one group of 2 unit capacitors to high-order capacitors CH3 to CH4 respectively.

[0075] When the sorting procedure includes two sorting stages, the six combined items will be sorted as items to be processed in the second sorting stage. At this time, the high-order capacitors CH1 to CH4 require 2, 2, 1, and 1 unit capacitors corresponding to the sorting items in this stage, respectively (each sorting item corresponds to 2 unit capacitors). The two unit capacitors corresponding to the two middle sorting items (the 3rd and 4th sorting items) are allocated to the high-order capacitors CH3 to CH4, which have an odd number of capacitors in this stage, in any or a specified manner. The remaining sorting items are then used to generate two combined items (a group of 4 unit capacitors) in the manner of the 1st and 6th combinations and the 2nd and 5th combinations, respectively, and one combined item is allocated to each of the high-order capacitors CH1 to CH2 as items to be assigned.

[0076] In the fourth use case, the number of high-order capacitors is 6 (e.g., CH1 to CH6), requiring 8, 5, 4, 3, 2, and 2 unit capacitors respectively, totaling 24 unit capacitors. Therefore, after the sorting action of the first sorting procedure, high-order capacitors CH2 and CH4 will be determined as odd-numbered capacitors and will be allocated 1 unit capacitor to each of the two middle sorting items (sorting items 12 and 13) in an arbitrary or specified manner. High-order capacitors CH1 to CH6 will also require 8, 4, 4, 2, 2, and 2 unit capacitors respectively. After the combination action of the first sorting procedure, the remaining 22 unit capacitors will be combined into 11 combination items. When the sorting procedure includes only one sorting stage, the 11 combination items will be allocated as items to be assigned in an arbitrary or specified manner, sequentially allocating four groups of 8 unit capacitors to high-order capacitor CH1, two groups of 4 unit capacitors to high-order capacitors CH2 to CH3, and one group of 2 unit capacitors to high-order capacitors CH4 to CH6 respectively.

[0077] When the sorting procedure includes two sorting stages, the 11 combined items will be sorted as items to be processed in the second sorting stage. At this time, the high-order capacitors CH1 to CH4 require 4, 2, 2, 1, 1, and 1 unit capacitors corresponding to sorting items in this stage (each sorting item corresponds to 2 unit capacitors). The 2 unit capacitors corresponding to the three middle sorting items (sorting items 5 to 7) are allocated to the high-order capacitors CH4 to CH6, which are odd-numbered capacitors in this stage, in any or a specified manner. The remaining sorting items generate four combined items (each group of 4 unit capacitors) using the combinations of the 1st and 11th, 2nd and 10th, 3rd and 9th, and 4th and 8th combinations, respectively. These are then assigned as items to be allocated, with two groups of combined items allocated to the high-order capacitor CH1 and one group of combined items allocated to the high-order capacitors CH2 to CH3.

[0078] When the sorting procedure includes three sorting stages, the four combined items will be sorted as items to be processed in the second sorting stage. At this time, the high-order capacitors CH1 to CH3 require 2, 1, and 1 unit capacitors corresponding to the sorting items in this stage, respectively (each sorting item corresponds to 4 unit capacitors). The 4 unit capacitors corresponding to the two middle sorting items (the 2nd and 3rd sorting items) are allocated to the high-order capacitors CH2 to CH3, which have an odd number of capacitors in this stage, in any or a specified manner. The remaining sorting items are then combined into a combined item (a group of 8 unit capacitors) using the first and fourth combination methods, and this combined item is assigned to the high-order capacitor CH1 as an item to be allocated.

[0079] (2) Capacitor Enabling Method: After explaining how the sorting procedure works, the capacitor enabling method will also be discussed in conjunction with... Figure 1A as well as Figure 2A The following paragraphs will provide an explanation.

[0080] Please refer to Figure 1A In operation, capacitor array 120 receives analog input signal ANI to generate analog output signal ANO. Figure 1A The comparator 130 generates a comparison result CR based on the analog output signal ANO and the virtual ground potential VGND. The control circuit 110 generates an enable signal EN based on the comparison result CR through a successive approximation mechanism. This enables the high-level capacitors CH1 to CH3 and the low-level capacitors CL1 to CL4 to be selectively enabled by the capacitor enable circuit 220. The control circuit 110 then generates a digital output signal DOUT based on the final comparison result CR.

[0081] The enable signal EN includes multiple high-order enable signals EH1 to EH3, each having an enable state and a disable state, and multiple low-order enable signals EL1 to EL4. The high-order enable signals EH1 to EH3 correspond to one of the high-order capacitors CH1 to CH3, and the low-order enable signals EL1 to EL4 correspond to one of the low-order capacitors CL1 to CL4.

[0082] like Figure 2A As shown, the capacitor enable circuit 220 may include: multiple low-level enable circuits LE1 to LE4, multiple residual capacitor enable circuits RE1 to RE2, multiple multiplexers MU1 to MU7, and multiple unit capacitor enable circuits UU1 to UU7.

[0083] The low-level enable circuits LE1 to LE4 are respectively configured to receive one of the low-level enable signals EL1 to EL4 to control one of the low-level capacitors CL1 to CL4.

[0084] Control circuit 110 can enable or disable low-level capacitors CL1 to CL4 to connect them to different reference voltages VREF. In one embodiment, the reference voltage VREF may include an ungrounded potential voltage NGND and a grounded potential voltage GND. Control circuit 110 can enable at least one of the low-level enable signals EL1 to EL4 to enable the corresponding low-level capacitors CL1 to CL4, connecting them to the ungrounded potential voltage NGND. Conversely, control circuit 110 can disable at least one of the low-level enable signals EL1 to EL4 to disable the corresponding low-level capacitors CL1 to CL4, connecting them to the grounded potential voltage GND.

[0085] Residual capacitor enabling circuits RE1 to RE2 are each configured to receive one of the high-level enable signals to control one of the residual capacitors CD1 to CD2 to connect to different reference voltages VREF (e.g., enabling to connect to the ungrounded potential voltage NGND, and disabling to connect to the ground potential voltage GND) according to the enabled and disabled states of the high-level enable signal. Since residual capacitor CD1 is connected to high-level capacitor CH1, residual capacitor enabling circuit RE1 receives the high-level enable signal EH1. Since residual capacitor CD2 is connected to high-level capacitor CH3, residual capacitor enabling circuit RE2 receives the high-level enable signal EH3.

[0086] Multiplexers MU1 to MU7 are configured to receive high-order enable signals EH1 to EH3 and receive one of multiple allocation signals AS1 to AS7 to select one of the high-order enable signals EH1 to EH3 for output. The allocation signals AS1 to AS7 are generated by the control circuit 110 according to the sorting result.

[0087] Unit capacitor enable circuits UU1 to UU7 are respectively configured to receive one of the high-order enable signals EH1 to EH3 output by one of the multiplexers MU1 to MU7, so as to control one of the unit capacitors CU1 to CU7.

[0088] by Figures 3A to 3D Taking the implementation method as an example, when the sorting procedure includes only two sorting stages, the high-order capacitor CH1 is configured by unit capacitors CU3, CU4, CU1 and CU5. The control circuit 110 will generate distribution signals AS3, AS4, AS1 and AS5 so that multiplexers MU3, MU4, MU1 and MU5 all select the high-order enable signal EH1 for output.

[0089] The high-level capacitor CH2 is composed of unit capacitors CU6 and CU2. The control circuit 110 will generate distribution signals AS6 and AS2 to cause multiplexers MU6 and MU2 to both select the high-level enable signal EH2 for output.

[0090] The high-level capacitor CH3 is configured from the unit capacitor CU7. The control circuit 110 will generate the distribution signal AS7 to cause the multiplexer MU7 to select the high-level enable signal EH3 for output.

[0091] Therefore, when the control circuit 110 wants to enable the high-level capacitor CH1, the high-level enable signal EH1 will be in an enabled state, causing multiplexers MU3, MU4, MU1, and MU5 to output the high-level enable signal EH1. Unit capacitors CU3, CU4, CU1, and CU5, as well as the residual capacitor CD1, are enabled (connected to the ungrounded potential voltage NGND) to be configured as the high-level capacitor CH1. Conversely, when the control circuit 110 wants to disable the high-level capacitor CH1, the high-level enable signal EH1 will be in a disabled state, and the unit capacitors CU3, CU4, CU1, and CU5, as well as the residual capacitor CD1, will be disabled (connected to the grounded potential voltage GND) through the aforementioned transmission mechanism.

[0092] When control circuit 110 wants to enable the high-level capacitor CH2, the high-level enable signal EH2 will be in an enabled state, causing multiplexers MU6 and MU2 to output the high-level enable signal EH2, and unit capacitors CU6 and CU2 will be enabled to be configured as high-level capacitor CH2. Conversely, when control circuit 110 wants to disable the high-level capacitor CH2, the high-level enable signal EH2 will be in a disabled state, and unit capacitors CU6 and CU2 will be disabled through the above transmission mechanism.

[0093] When control circuit 110 wants to enable the high-level capacitor CH3, the high-level enable signal EH3 will be in an enabled state, causing multiplexer MU7 to output a high-state high-level enable signal EH3. The unit capacitor CU7 and the residual capacitor CD2 are then enabled and configured as the high-level capacitor CH3. Conversely, when control circuit 110 wants to disable the high-level capacitor CH3, the high-level enable signal EH3 will be in a disabled state, and the unit capacitor CU7 and the residual capacitor CD2 will be disabled through the aforementioned transmission mechanism.

[0094] (3) Improvement of linearity parameters: In one embodiment, the linearity parameters are integral nonlinearity (INL), effective number of bits (ENOB), differential nonlinearity (DNL), signal-to-noise-and-distortion ratio (SNDR), or spurious-free dynamic range (SFDR).

[0095] For example, in the case where each of the seven unit capacitors exhibits a random drift of 2% Gaussian distribution, after two-stage sorting compared to the unsorted state, the integral nonlinearity error can be reduced from 0.87 least significant bits (LSB) to 0.67 LSB. The average number of significant bits can be increased by 0.4 bits, and the minimum number of significant bits can be increased by 0.55 bits.

[0096] In summary, through the operation of the sorting procedure and the capacitor enabling method, the high-order capacitors of the capacitor array have better linearity.

[0097] It should be noted that the number and value of each capacitor mentioned above can vary according to actual needs and are not limited to the numbers and values ​​described above. For example, the number of unit capacitors required for the high-level capacitor can be determined by the required high-level capacitor value and the unit capacitor value, while the residual capacitor value can be determined by the required high-level capacitor value and the total capacitance value of the corresponding unit capacitors. Each reconfigured high-level capacitor may include at least one unit capacitor and at least one residual capacitor, or it may not include any residual capacitor.

[0098] Furthermore, the sorting method described above is merely an example. The present invention is not limited thereto.

[0099] In one embodiment, the measurement of the unit capacitance value of each unit capacitor can be performed by the control circuit 110 enabling only one of the unit capacitors before the sorting procedure in the initial mode, and selectively enabling the lower-order capacitors through a successive approximation mechanism to generate a digital output signal DOUT to measure the relative capacitance value. Since the successive approximation analog-to-digital converter circuit 100 itself is equipped with a comparator 130, no additional circuitry is required to measure the unit capacitance value.

[0100] In other embodiments, the control circuit 110 may select to enable one unit capacitor and disable another unit capacitor in the initial state, so that the ANO terminal of the capacitor array 120 outputs a differential voltage for the comparator 130 to determine whether it is greater than or less than the virtual ground voltage, thereby obtaining the relative size relationship of the capacitance values ​​of the plurality of capacitors.

[0101] Figure 4 A flowchart of a successive approximation analog-to-digital conversion method 400 with optimized linearity is shown according to an embodiment of the present invention. The successive approximation analog-to-digital conversion method 400 is applied in, for example, but not limited to, [various applications]. Figure 1A or Figure 1B In the successive approximation analog-to-digital converter circuit 100, an embodiment of the successive approximation analog-to-digital converter method 400 is, for example... Figure 4 As shown, it includes the following steps.

[0102] In step S410, in the initial mode, the control circuit 110 generates a sorting result by sorting the unit capacitors CU1 to CU7 according to their unit capacitance values.

[0103] In step S420, in the initial mode, the control circuit 110 configures the unit capacitors CU1 to CU7 into multiple high-level capacitors CH1 to CH3 according to the sorting result, so that the linearity parameter between the high-level capacitors CH1 to CH3 is within a preset range.

[0104] In step S430, in the operating mode, the capacitor array 120 receives the analog input signal ANI and the reference voltage VREF to generate the analog output signal ANO, and the comparator 130 generates a comparison result CR based at least on the analog output signal ANO.

[0105] In step S440, in the operating mode, the control circuit 110 generates an enable signal EN based on the comparison result CR through a successive approximation mechanism, so as to selectively enable one of the high-level capacitors CH1 to CH3 and the low-level capacitors CL1 to CL4 connected to the reference voltage VREF through the capacitor enable circuit 220, and further generates a digital output signal DOUT based on the final comparison result CR.

[0106] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0107] In summary, the successive approximation analog-to-digital converter circuit and method with optimized linearity in this invention can achieve better linearity by sorting the unit capacitors and configuring them with the corresponding residual capacitors through the control circuit described above.

[0108] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of patent protection defined in this specification.

Claims

1. A successive approximation analog-to-digital converter circuit with optimized linearity, characterized in that, include: One control circuit; At least one capacitor array, including: A low-level capacitor array, comprising multiple low-level capacitors; A high-order capacitor array comprising a plurality of unit capacitors, each unit capacitor having an approximately equal one-unit capacitance value; and A capacitor-enabled circuit; and A comparator is electrically coupled between the capacitor array and the control circuit; In one initial mode, the control circuit performs a sorting procedure on the unit capacitors according to their unit capacitance values ​​to generate a sorting result, and configures the unit capacitors as multiple high-order capacitors according to the sorting result, so that a linearity parameter among the high-order capacitors is within a preset range; wherein: The sorting procedure performed by the control circuit on the unit capacitor includes K sorting stages, each corresponding to multiple items to be processed, where K is an integer greater than or equal to 1, and the item to be processed corresponding to the first sorting stage is the unit capacitance value of the unit capacitor. The control circuit performs a sorting action and a combination action on the items to be processed in each of the K sorting stages. The sorting action is used to sort the sum of the capacitance values ​​of the unit capacitors included in the items to be processed from largest to smallest or smallest to largest to generate multiple sorted items. The combination action is used to combine the sorted items greater than or equal to a median and the sorted items less than or equal to the median in pairs to generate multiple combined items. The combined items generated in each of the first K-1 sorting stages are the items to be processed in the next sorting stage, and the combined items generated in the Kth sorting stage are multiple items to be assigned. In one operating mode, the capacitor array receives an analog input signal and multiple reference voltages to generate an analog output signal. The comparator generates a comparison result based on at least the analog output signal. The control circuit generates a matching signal based on the comparison result through a successive approximation mechanism to selectively enable the high-order capacitor and the low-order capacitor connected to one of the reference voltages through the capacitor enabling circuit. Furthermore, a digital output signal is generated based on the final comparison result.

2. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that, The control circuit is also configured to enable only one of the unit capacitors and to selectively enable the low-order capacitors through the successive approximation mechanism to generate the digital output signal to measure the unit capacitance value.

3. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that, After the sorting action is completed in each of the K sorting stages, the control circuit determines from the high-order capacitors to be configured which need to be allocated an odd number of sorting items, and that is an odd number of capacitors in the sorting stage. If there is more than one odd-numbered capacitor in the sorting stage, the unit capacitor corresponding to at least one of the middle sorting items is selected from the sorting items and assigned to the odd-numbered capacitor, and then the combination action is performed.

4. The successive approximation analog-to-digital converter circuit according to claim 3, characterized in that, The control circuit allocates the unit capacitor corresponding to the item to be allocated generated in the Kth sorting stage to the remaining multiple non-odd capacitors.

5. The successive approximation analog-to-digital converter circuit according to claim 4, characterized in that, When the number of sorted items is N, the combined action, in the case that A increases from 1 to ⌊N / 2⌋, sequentially pairs the Ath and N+1-Ath sorted items, where N is a positive integer.

6. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that, The enabling signal includes multiple high-order enabling signals and multiple low-order enabling signals, each having a uniform energy state and a suppression state. The high-order enabling signals correspond to one of the high-order capacitors, and the low-order enabling signals correspond to one of the low-order capacitors. The capacitor enabling circuit includes: Multiple low-level enable circuits are configured to receive one of the low-level enable signals to control one of the low-level capacitors to be connected to one of the reference voltages; Multiple multiplexers are configured to receive the high-order enable signal and to receive one of multiple allocation signals to select one of the high-order enable signals for output, wherein the allocation signal is generated by the control circuit according to the sorting result; and Multiple unit capacitor enable circuits are configured to receive one of the high-level enable signals output by one of the multiplexers, so as to control one of the unit capacitors to be connected to one of the reference voltages.

7. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The high-level capacitor array further includes at least one residual capacitor having a residual capacitance value less than or equal to the unit capacitance value. The control circuit is configured to configure the unit capacitor and the residual capacitor as the high-level capacitors according to the sorting result, wherein each of the high-level capacitors includes at least one of the unit capacitors. The capacitor enable circuit further includes at least one residual capacitor enable circuit configured to receive one of the high-level enable signals to control the residual capacitor to be connected to one of the reference voltages.

8. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that, When the at least one capacitor array comprises only one single-ended capacitor array, the comparator compares the analog output signal with a virtual ground potential to produce the comparison result. When the at least one capacitor array includes a two differential capacitor array, the comparator compares the analog output signal of the two differential capacitor arrays to produce the comparison result.

9. A successive approximation analog-to-digital conversion method with optimized linearity, used in a successive approximation analog-to-digital conversion circuit, characterized in that, The successive approximation analog-to-digital conversion includes a control circuit, at least one capacitor array, and a comparator. The capacitor array includes a low-order capacitor array, a high-order capacitor array, and a capacitor enable circuit. The low-order capacitor array includes multiple low-order capacitors, and the high-order capacitor array includes multiple unit capacitors, each of which has an approximately equal unit capacitance value. The comparator is electrically coupled between the capacitor array and the control circuit. The successive approximation analog-to-digital conversion method includes: In an initial mode, the control circuit performs a sorting procedure on the unit capacitors according to their unit capacitance values ​​to generate a sorting result; wherein: The sorting procedure performed by the control circuit on the unit capacitor includes K sorting stages, each corresponding to multiple items to be processed, where K is an integer greater than or equal to 1, and the item to be processed corresponding to the first sorting stage is the unit capacitance value of the unit capacitor. The control circuit performs a sorting action and a combination action on the items to be processed in each of the K sorting stages. The sorting action is used to sort the sum of the capacitance values ​​of the unit capacitors included in the items to be processed from largest to smallest or from smallest to largest to generate multiple sorted items. The combination action is used to combine the sorted items that are greater than or equal to a median and the sorted items that are less than or equal to the median in pairs to generate multiple combined items. The combined items generated in each of the first K-1 sorting stages are the items to be processed in the next sorting stage, and the combined items generated in the Kth sorting stage are multiple items to be assigned. In the initial mode, the control circuit configures the unit capacitor into multiple high-order capacitors according to the sorting result, so that a linearity parameter between the high-order capacitors is within a preset range. In one operating mode, the capacitor array receives an analog input signal and a plurality of reference voltages to generate an analog output signal, and the comparator generates a comparison result based at least on the analog output signal; and In the operating mode, the control circuit generates a consistent energy signal based on the comparison result through a successive approximation mechanism, so as to selectively enable the high-order capacitor and the low-order capacitor connected to one of the reference voltages through the capacitor enable circuit, and further generates a digital output signal based on the final comparison result.

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