Cryptographic device and cryptographic method thereof

Abstract

The application discloses a cipher device and a cipher method thereof. The cipher device is applied to a memory device, and includes a judging unit, a transposition unit and a cipher unit. The judging unit judges whether a memory address is located in a protection area or not, and selects a key and a random number. The transposition unit transposes a binary code according to the key and the memory address to generate a transposed code. The binary code includes the random number and the memory address. The cipher unit generates a key stream according to the key and the transposed code. The application can provide better data protection capability.

Description

Technical Field

[0001] This invention relates to a cryptographic device and a cryptographic method thereof, and more particularly to a cryptographic device and a cryptographic method thereof using a transposition function. Background Technology

[0002] In cryptography, encryption refers to the process of transforming plaintext into ciphertext, which is difficult to understand, thereby protecting its content. Only a device with a decryption method can restore the ciphertext to its readable form through the decryption process. Ideally, only authorized personnel should be able to read the information conveyed by the ciphertext. Encryption itself cannot prevent the interception of information transmission, but it can prevent the interceptor from understanding the content of the information. Summary of the Invention

[0003] This invention proposes a cryptographic device and method for generating a key stream instantaneously when a memory control device operates on a memory array. Compared to counter cryptography, the cryptographic device and method proposed in this invention use a different input data encoding method, which makes it more difficult for attackers to build a power analysis module, thereby providing better data protection capabilities.

[0004] This invention provides a cryptographic device applicable to a memory device. The cryptographic device includes a determination unit, a transposition unit, and a cryptographic unit. The determination unit determines that a memory address is located in a protected area and selects a key and a random number. The transposition unit transposes a binary code according to the key and the memory address to generate a transposition code, wherein the binary code includes the random number and the memory address. The cryptographic unit generates a keystream according to the key and the transposition code.

[0005] According to an embodiment of the present invention, the memory device includes a first bus interface, a controller, and a memory array. When the first bus interface receives the memory address and an operation instruction, the first bus interface sends the memory address to the determination unit and the operation instruction to the controller, causing the controller to read encrypted read data and / or write write data to the memory array according to the memory address and the operation instruction. When the cryptographic unit generates the key stream, the cryptographic unit simultaneously generates a valid signal. The controller, based on the valid signal, uses the key stream to decrypt the encrypted read data and encrypt the written data.

[0006] According to one embodiment of the present invention, the cryptographic device further includes a register, a second bus interface, and a first multiplexer. The register stores the start and end addresses of the memory address of the protected region, as well as the key and random number corresponding to the memory address of the protected region. A user sets the key and random number corresponding to the memory address of the protected region stored in the register via the second bus interface. The first multiplexer selects the key and random number corresponding to the memory address based on a judgment signal, wherein the judgment signal is generated when the judgment unit determines that the memory address is located within the protected region.

[0007] According to one embodiment of the present invention, the transposition unit includes a plurality of transposition logic units, a selection logic unit, and a second multiplexer. Each of the plurality of transposition logic units has a transposition logic, and transposes the binary code according to the transposition logic to generate the transposition code, wherein the transposition logic corresponding to each of the plurality of transposition logic units is different. The selection logic unit generates a selection code according to the key and the memory address. The second multiplexer outputs the transposition code generated by one of the plurality of transposition logic units according to the selection code.

[0008] According to an embodiment of the present invention, one of the plurality of transposition logic units divides the binary code into at least a first part and a second part according to the transposition logic, and generates the transposition code by changing the order of the first part and the second part.

[0009] According to an embodiment of the present invention, the selection logic unit performs an addition operation on each bit of the key and the corresponding bit of the memory address to generate the selection code.

[0010] According to another embodiment of the present invention, the selection logic unit performs a mutual exclusion OR operation on each bit of the key and the corresponding bit of the memory address to generate the selection code.

[0011] The present invention further proposes a cryptographic method applicable to a memory array. The cryptographic method includes determining that a memory address is located in a protected region and selecting a key and a random number; generating a binary code, wherein the binary code includes the random number and the memory address; transposing the binary code according to the key and the memory address to generate a transposed code; and generating a key stream according to the key and the transposed code.

[0012] According to an embodiment of the present invention, the cryptographic method further includes reading encrypted read data from a memory array and / or writing write data into the memory array based on the memory address and an operation instruction; and decrypting the encrypted read data and encrypting the written data using the key stream.

[0013] According to an embodiment of the present invention, the cryptographic method further includes storing the start address and end address of the memory address of the protected region, as well as the key and the random number corresponding to the memory address of the protected region, in a temporary register, wherein a user sets the key and the random number corresponding to the memory address of the protected region stored in the temporary register through a bus interface; and when it is determined that the memory address is located in the protected region, selecting the key and the random number corresponding to the memory address from the temporary register.

[0014] According to an embodiment of the present invention, the step of transposing the binary code according to the key and the memory address to generate the transposed code further includes generating a selection code according to the key and the memory address; selecting a transposition logic according to the selection code; and transposing the binary code according to the transposition logic to generate the transposed code.

[0015] According to an embodiment of the present invention, the step of transposing the binary code based on the transposition logic to generate the transposed code further includes dividing the binary code into at least a first part and a second part; and changing the order of the first part and the second part to generate the transposed code.

[0016] According to an embodiment of the present invention, the step of generating the selection code based on the key and the memory address further includes performing an addition operation on each bit of the key and the corresponding bit of the memory address to generate the selection code.

[0017] According to another embodiment of the present invention, the step of generating the selection code based on the key and the memory address further includes performing a mutual exclusion OR operation on each bit of the key and the corresponding bit of the memory address to generate the selection code. Attached Figure Description

[0018] Figure 1 This is a block diagram showing an encryption device according to an embodiment of the present invention;

[0019] Figure 2 It is a table showing the correspondence between memory address, key, and random number according to an embodiment of the present invention;

[0020] Figure 3This is a block diagram showing an encryption device according to another embodiment of the present invention;

[0021] Figure 4 This is a block diagram showing a transposition unit according to an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram illustrating the transposition logic according to an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram illustrating the transposition logic according to another embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram illustrating the transposition logic according to another embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram showing a selection logic unit according to an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram showing a selection logic unit according to another embodiment of the present invention;

[0027] Figure 10 This is a flowchart illustrating a cryptographic method according to an embodiment of the present invention.

[0028] Figure Labels

[0029] 100, 300: Encryption device

[0030] 110, 310: Memory control device

[0031] 111: First bus interface

[0032] 112: Controller

[0033] 113: Buffer

[0034] 114: First Logic Gate

[0035] 115: Second Logic Gate

[0036] 120: Memory Array

[0037] 130,330: Cryptographic device

[0038] 131: Temporary Register

[0039] 132,332: Judgment Unit

[0040] 133: First Multiplexer

[0041] 134: Cryptographic Unit

[0042] 200: Correspondence Table

[0043] 334: Cryptographic Unit

[0044] 335,400: Transposition unit

[0045] 336: Second bus interface

[0046] 410_1: First transposition logic unit

[0047] 410_2: Second transposition logic unit

[0048] 410_M: The Mth permutation logic unit

[0049] 420: Select Logic Unit

[0050] 430: Multiplexer

[0051] 500, 600, 700: Transposition Logic

[0052] 800: Adder

[0053] 900: Mutex OR gate

[0054] 1000: Password Method

[0055] BUS: Bus

[0056] INS: Operation Instructions

[0057] WDATA: Write data

[0058] RDATA: Read data

[0059] ADDR: Memory address

[0060] ADDR1: First memory address

[0061] ADDR2: Second memory address

[0062] ADDRN: Nth memory address

[0063] SADDR1: First starting address

[0064] EADDR1: First End Address

[0065] SADDR2: Second starting address

[0066] EADDR2: Second End Address

[0067] SADDRN: Starting address of the Nth node

[0068] EADDRN: End address of the Nth node

[0069] EWDATA: Encrypted data writing

[0070] ERDATA: Encrypted data reading

[0071] KEY: Key

[0072] KEY1: First Key

[0073] KEY2: Second key

[0074] KEYN: The Nth key

[0075] KS: Key Stream

[0076] EN: Enable signal

[0077] DET: Determine Signal

[0078] NONCE: Random Number

[0079] NONCE1: First random number

[0080] NONCE2: Second random number

[0081] NONCEN: The Nth random number

[0082] VALID: Valid signal

[0083] L1: First transposition logic

[0084] L2: Second transposition logic

[0085] LM: Mth transposition logic

[0086] CRA: Transposition Code

[0087] CRA1: First transposition code

[0088] CRA2: Second transposition code

[0089] CRAM: Mth transposition code

[0090] CSEL: Selection Code

[0091] CB: Binary code

[0092] CB[127:x],CB[31:0],CB[7:0]: Part 1

[0093] CB[(x-1):0],CB[63:32],CB[15:8]: Part Two

[0094] CB[95:64],CB[23:16]: Part Three

[0095] CB[127:96],CB[31:24]: Part Four

[0096] CB[39:32]: Part Five

[0097] CB[47:40]: Part Six

[0098] CB[55:48]: Part Seven

[0099] CB[63:56]: Part 8

[0100] CB[71:64]: Part Nine

[0101] CB[79:72]: Part Ten

[0102] CB[87:80]: Part Eleven

[0103] CB[95:88]: Part Twelve

[0104] CB[103:96]: Part Thirteen

[0105] CB[111:104]: Part Fourteen

[0106] CB[119:112]: Part Fifteen

[0107] CB[127:120]: Part Sixteen

[0108] ADD: Addition operation

[0109] XOR: Mutual exclusion OR operation

[0110] S110~S150: Procedure Flow Detailed Implementation

[0111] The following description illustrates embodiments of the present invention. Its purpose is to demonstrate the general principles of the invention and should not be construed as limiting the invention. The scope of the invention is defined by the claims.

[0112] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments of this application.

[0113] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including direct contact between the features, or additional features formed between the features, such that the features are not in direct contact.

[0114] Figure 1 This is a block diagram showing an encryption device according to an embodiment of the present invention. Figure 1 As shown, the encryption device 100 includes a memory control device 110 and a memory array 120. The memory control device 110 includes a first bus interface 111, a controller 112, a buffer 113, a first logic gate 114, a second logic gate 115, and a cryptographic device 130.

[0115] The first bus interface 111 receives the operation command INS, write data WDATA and memory address ADDR from the bus BUS, and transmits the operation command INS and memory address ADDR to the controller 112, so that the controller 112 operates the memory array 120 according to the operation command INS and memory address ADDR.

[0116] According to one embodiment of the present invention, when the controller 112 performs a write operation on the memory array 120 according to the operation instruction INS, the first logic gate 114 performs a mutual exclusion OR operation on the write data WDATA and the key stream KS to generate encrypted write data EWDATA, and temporarily stores the encrypted write data EWDATA in the buffer 113 in the controller 112. Then, the controller 112 writes the encrypted write data EWDATA temporarily stored in the buffer 113 into the memory array 120 according to the memory address ADDR.

[0117] According to another embodiment of the present invention, when the controller 112 performs a read operation on the memory array 120 according to the operation instruction INS, the controller 112 temporarily stores the encrypted read data ERDATA from the memory address ADDR of the memory array 120 in the buffer 113, and performs a mutual exclusion OR logic operation on the encrypted read data ERDATA and the key stream KS through the second logic gate 115 to generate read data RDATA, and transmits it to the host through the first bus interface 111 and the bus BUS.

[0118] like Figure 1 As shown, the cryptographic device 130 includes a temporary register 131, a judgment unit 132, a first multiplexer 133, and a cryptographic unit 134. The temporary register 131 is used to store multiple memory addresses of the protected area of ​​the memory array 120, and to store the key KEY and random number NONCE corresponding to each of the multiple memory addresses of the protected area.

[0119] Figure 2 This is a table showing the correspondence between memory addresses, keys, and random numbers according to an embodiment of the present invention. The correspondence table 200 records the relationship between the memory address ADDR, key KEY, and random number NONCE of the protected area. For example... Figure 2 As shown in the embodiment, the protected area of ​​the memory array 120 includes a first memory address ADDR1, a second memory address ADDR2, ... and an Nth memory address ADDRN, wherein the first memory address ADDR1 includes a first start address SADDR1 and a first end address EADDR1, the second memory address ADDR2 includes a second start address SADDR2 and a second end address EADDR2, and the Nth memory address ADDRN includes an Nth start address SADDRN and an Nth end address EADDRN.

[0120] In other words, when performing read and write operations on the memory addresses between the first start address SADDR1 and the first end address EADDR1, between the second start address SADDR2 and the second end address EADDR2, ... and between the Nth start address SADDRN and the Nth end address EADDRN of the memory array 120, the encrypted read data ERDATA must be decrypted and the write data WDATA must be encrypted.

[0121] like Figure 2As shown, each of the first memory address ADDR1, the second memory address ADDR2, ..., and the Nth memory address ADDRN has a corresponding first key KEY1, a second key KEY2, ..., and an Nth key KEYN, and a corresponding first random number NONCE1, a second random number NONCE2, ..., and an Nth random number NONCEN. According to one embodiment of the present invention, the user can set the first memory address ADDR1, the second memory address ADDR2, ..., and the Nth memory address ADDRN of the protected area via the bus BUS and the first bus interface 111, and can also set the first random number NONCE1, the second random number NONCE2, ..., and the Nth random number NONCEN stored in the register 131. According to other embodiments of the present invention, the user can set the first key KEY1, the second key KEY2, ..., and the Nth key KEYN stored in the register 131 via the bus BUS and the first bus interface 111.

[0122] Back Figure 1 When the judgment unit 132 receives the memory address ADDR from the first bus interface 111, the judgment unit 132 accesses the correspondence table 200 stored in the temporary register 131 and determines whether the memory address ADDR is located in any one of the first memory address ADDR1, the second memory address ADDR2, ... and the Nth memory address ADDRN in the correspondence table 200, and provides the memory address ADDR to the password unit 134.

[0123] According to an embodiment of the present invention, when the judgment unit 132 determines that the received memory address ADDR matches the second memory address ADDR2 corresponding to the table 200, the judgment unit 132 generates a judgment signal DET, and the first multiplexer 133 selects the second key KEY2 and the second random number NONCE2 corresponding to the second memory address ADDR2 and outputs them according to the judgment signal DET.

[0124] Next, the cryptographic unit 134 uses counter mode to generate a key stream KS based on the key KEY output by the first multiplexer 133, the random number NONCE, and the memory address ADDR provided by the judgment unit 132. According to an embodiment of the present invention, the encryption device 100 is an on-the-fly cryptographic architecture. In other words, when the memory control device 110 operates the memory array 120 according to the operation instruction INS and the memory address ADDR, the cryptographic device 130 simultaneously generates the key stream KS based on the memory address ADDR.

[0125] Because the instantaneous cryptographic architecture of the counter cipher mode ensures that the input data for the encryption / decryption engine is identical when accessing the same external memory address (ADDR), regardless of the associated key, attackers can easily use a known key to encrypt large amounts of input data to build a power analysis module. They can then have the encryption / decryption engine perform the same encryption operation again with an unknown user key, ultimately using the previously established power analysis module to steal the user's key. Therefore, alternative cryptographic architectures are needed to enhance data protection capabilities.

[0126] Figure 3 This is a block diagram showing an encryption device according to another embodiment of the present invention. Figure 3 As shown, the encryption device 300 includes a memory control device 310, a memory array 120, and a cryptographic device 330. The memory control device 310 includes a first bus interface 111, a controller 112, a first logic gate 114, and a second logic gate 115, and operates the memory array 120. The first bus interface 111, controller 112, first logic gate 114, second logic gate 115, and memory array 120 are... Figure 1 The details are explained in the text and will not be repeated here.

[0127] Encryption device 300 and Figure 1 Compared to the encryption device 100, the memory control device 310 and the cryptographic device 330 are independent of each other, while Figure 1 The cryptographic device 130 is located within the memory control device 110. According to an embodiment of the present invention, the encryption device 300 is an on-the-fly cryptographic architecture. In other words, when the memory control device 310 operates the memory array 120 according to the operation instruction INS and the memory address ADDR, the cryptographic device 330 simultaneously generates a key stream KS according to the memory address ADDR.

[0128] According to an embodiment of the present invention, when the memory address ADDR is located at Figure 2 The cryptographic device 330 will only be activated when the first starting address SADDR1 and the first ending address EADDR1, the second starting address SADDR2 and the second ending address EADDR2, ... or the Nth starting address SADDRN and the Nth ending address EADDRN.

[0129] The cryptographic device 330 includes a temporary register 131, a judgment unit 332, a first multiplexer 133, a cryptographic unit 334, a transposition unit 335, and a second bus interface 336. The temporary register 131 and... Figure 1The temporary register 131 is the same as that used to store the correspondence table 200 of memory address ADDR, key KEY, and random number NONCE, which will not be described again here. The judgment unit 332 receives memory address ADDR from the first bus interface 111 and accesses the correspondence table 200 of the temporary register 131, and determines whether memory address ADDR is located in one of the first memory address ADDR1, second memory address ADDR2, ... and Nth memory address ADDRN in the protection area of ​​the correspondence table 200.

[0130] When the judgment unit 332 determines that the memory address ADDR is located in the protected area, the judgment unit 332 enables the cryptographic unit 334 using the enable signal EN, and generates a judgment signal DET so that the multiplexer 133 outputs the key KEY and random number NONCE corresponding to the memory address ADDR. According to an embodiment of the present invention, when the judgment unit 332 determines that the memory address ADDR is located in the second memory address ADDR2 corresponding to the table 200, the judgment unit 332 enables the cryptographic unit 334 and controls the first multiplexer 133 to select and output the second key KEY2 and the second random number NONCE2 corresponding to the second memory address ADDR2.

[0131] According to another embodiment of the present invention, when the determination unit 132 determines that the memory address ADDR is not located in any of the first memory address ADDR1, the second memory address ADDR2, ... and the Nth memory address ADDRN in the corresponding table 200, the determination unit 332 uses the enable signal EN to turn off the password unit 334 to reduce power consumption.

[0132] The transposition unit 335 generates the binary code CB ( Figure 3 (Not shown), and based on the key KEY output by the first multiplexer 133 and the memory address ADDR, the binary code CB is transposed to generate the transposition code CRA, where the binary code CB includes the random number NONCE and the memory address ADDR. Next, the cryptographic unit 334 generates the key stream KS based on the key KEY and the transposition code CRA.

[0133] According to an embodiment of the present invention, when the cryptographic unit 334 generates a key stream KS, the cryptographic unit 334 simultaneously provides a valid signal VALID to the judgment unit 332. The judgment unit 332 provides the valid signal VALID to the controller 112 through the first bus interface 111, so that the controller 112 uses the key stream KS to encrypt the written data WDATA and / or decrypt the encrypted read data ERDATA.

[0134] Users can set the first start address SADDR1 and the first end address EADDR1 of the first memory address ADDR1 of the protected area, the second start address SADDR2 and the second end address EADDR2 of the second memory address ADDR2, ... and the Nth start address SADDRN and the Nth end address EADDRN of the Nth memory address ADDRN through the bus BUS and the second bus interface 336. Users can also set the first random number NONCE1, the second random number NONCE2, ... and the Nth random number NONCEN stored in the register 131 corresponding to the table 200.

[0135] According to other embodiments of the present invention, the user can also set the first key KEY1, the second key KEY2, ... and the Nth key KEYN stored in the temporary register 131 through the bus BUS and the second bus interface 336.

[0136] Figure 4 This is a block diagram showing a transposition unit according to an embodiment of the present invention. For example... Figure 4 As shown, the transposition unit 400 includes a first transposition logic unit 410_1, a second transposition logic unit 410_2, ..., an Mth transposition logic unit 410_M, a selection logic unit 420, and a multiplexer 430. According to an embodiment of the present invention, the binary code CB is composed of a random number NONCE and a memory address ADDR.

[0137] The first transposition logic unit 410_1, the second transposition logic unit 410_2, ... and the Mth transposition logic unit 410_M each have a first transposition logic L1, a second transposition logic L2, ... and an Mth transposition logic LM. Each of the first transposition logic unit 410_1, the second transposition logic unit 410_2, ... and the Mth transposition logic unit 410_M transposes the binary code CB according to the corresponding transposition logic to generate a first transposition code CRA1, a second transposition code CRA2, ... and an Mth transposition code CRAM, respectively. According to an embodiment of the present invention, the first transposition logic L1, the second transposition logic L2, ... and the Mth transposition logic LM are different from each other.

[0138] The selection logic unit 420 generates a selection code CSEL based on the key KEY and the memory address ADDR. The second multiplexer 430 selects one output of the first transposition code CRA1, the second transposition code CRA2, ..., and the Mth transposition code CRAM as the transposition code CRA based on the selection code CSEL. According to an embodiment of the present invention, the transposition unit 400 includes a first transposition logic unit 410_1, a second transposition logic unit 410_2, ..., and an Mth transposition logic unit 410_M, and the selection code CSEL is W = ceil(log₂M) bits. That is, the number of bits in the selection code CSEL is equal to the integer obtained by rounding up (ceiling) log₂M.

[0139] Figure 5 This is a schematic diagram illustrating the transposition logic according to an embodiment of the present invention. Figure 5 As shown, the transposition logic 500 divides the 128-bit binary code CB into a first part CB[127:x] and a second part CB[(x-1):0], where x is any integer between 127 and 0. Furthermore, the transposition logic 500 further transposes the first part CB[127:x] and the second part CB[(x-1):0] to generate a transposition code CRA, where the order of the first part CB[127:x] and the second part CB[(x-1):0] in the transposition code CRA is different from the order of the first part CB[127:x] and the second part CB[(x-1):0] in the binary code CB. According to some embodiments of the present invention, the transposition logic 500 corresponds to... Figure 4 The first transposition logic L1, the second transposition logic L2, ... and any one of the Mth transposition logic LM.

[0140] Figure 6 This is a schematic diagram illustrating the transposition logic according to another embodiment of the present invention. Figure 6 As shown, the transposition logic 600 divides the 128-bit binary code CB into groups of 32 bits each, generating a first part CB[31:0], a second part CB[63:32], a third part CB[95:64], and a fourth part CB[127:96]. Furthermore, the transposition logic 600 further swaps the order of the first part CB[31:0], the second part CB[63:32], the third part CB[95:64], and the fourth part CB[127:96] to generate a transposition code CRA, where the order in the transposition code CRA is the third part CB[95:64], the first part CB[31:0], the fourth part CB[127:96], and the second part CB[63:32]. According to some embodiments of the present invention, the transposition logic 600 corresponds to... Figure 4 The first transposition logic L1, the second transposition logic L2, ... and any one of the Mth transposition logic LM.

[0141] Figure 7 This is a schematic diagram illustrating the transposition logic according to another embodiment of the present invention. Figure 7 As shown, the transposition logic 700 divides the 128-bit binary code CB into groups of 8 bits each, generating the first part CB[7:0], the second part CB[15:8], the third part CB[23:16], the fourth part CB[31:24], the fifth part CB[39:32], the sixth part CB[47:40], the seventh part CB[55:48], the eighth part CB[63:56], the ninth part CB[71:64], the tenth part CB[79:72], the eleventh part CB[87:80], the twelfth part CB[95:88], the thirteenth part CB[103:96], the fourteenth part CB[111:104], the fifteenth part CB[119:112], and the sixteenth part CB[127:120].

[0142] The transposition logic 700 further swaps the order of the first part CB[7:0], the second part CB[15:8], the third part CB[23:16], the fourth part CB[31:24], the fifth part CB[39:32], the sixth part CB[47:40], the seventh part CB[55:48], the eighth part CB[63:56], the ninth part CB[71:64], the tenth part CB[79:72], the eleventh part CB[87:80], the twelfth part CB[95:88], the thirteenth part CB[103:96], the fourteenth part CB[111:104], the fifteenth part CB[119:112], and the sixteenth part CB[127:120] to generate the transposition code CRA. According to some embodiments of the present invention, the transposition logic 700 corresponds to... Figure 4 The first transposition logic L1, the second transposition logic L2, ... and any one of the Mth transposition logic LM.

[0143] According to other embodiments of the present invention, the transposition unit 400 divides the binary code CB into at least a first part and a second part according to transposition logic, and swaps the order of the first part and the second part to generate a transposition code CRA, wherein the first part and the second part have the same or different number of bits. Furthermore, Figure 5 , Figure 6 , Figure 7 This explanation is based on 128-bit binary code CB, and is not limited to this in any other way.

[0144] Figure 8 This is a schematic diagram showing a selection logic unit according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 4The selection logic unit 420 is an adder 800. For example... Figure 8 As shown, adder 800 performs an addition operation ADD on each bit of the key KEY and the corresponding bit of the memory address ADDR to generate the selection code CSEL. According to some embodiments of the present invention, the key KEY and the memory address ADDR are both M bits, and the selection code CSEL is W (where, ) bit, used to select Figure 4 The first transposition code CRA1, the second transposition code CRA2, ... and the Mth transposition code CRAM are used as the transposition code CRA.

[0145] Figure 9 This is a schematic diagram showing a selection logic unit according to another embodiment of the present invention. According to another embodiment of the present invention, Figure 4 The selection logic unit 420 is a mutex OR gate 900. For example... Figure 9 As shown, the mutex gate 900 performs a mutual exclusion OR operation (XOR) on each bit of the key KEY and the corresponding bit of the memory address ADDR to generate the selection code CSEL. According to some embodiments of the present invention, the selection logic unit 900 corresponds to... Figure 4 The selection logic unit 420, the key KEY and the memory address ADDR are M bits, and the selection code CSEL is W (where, The first bit is used to select one of the M first transposition codes CRA1, second transposition codes CRA2, ... and the Mth transposition code CRAM as the transposition code CRA.

[0146] According to an embodiment of the present invention, Figure 4 The selection logic unit 420 can use addition, mutual exclusion, OR operations and their combinations to perform operations on each bit of the key KEY and the corresponding bit of the memory address ADDR to generate a selection code CSEL, which is used to select one of the M first transposition codes CRA1, second transposition codes CRA2, ... and the Mth transposition code CRAM as the transposition code CRA.

[0147] Figure 10 This is a flowchart illustrating a cryptographic method according to an embodiment of the present invention. The following is directed at... Figure 10 Password method 1000 will be combined Figure 3 The encryption device 300 is described in detail below.

[0148] The determination unit 332 determines whether the received memory address ADDR is located in the protected area (step S110). When the memory address ADDR is located in the protected area, the determination unit 332 selects a key KEY and a random number NONCE (step S120). When the memory address ADDR is not located in the protected area, the process returns to step S110. According to an embodiment of the present invention, when the memory address ADDR is located in the protected area, the determination unit 332 selects a key KEY and a random number NONCE for the corresponding memory address ADDR according to the correspondence table 200 stored in the temporary register 131.

[0149] Next, the transposition unit 335 generates a binary code CB (step S130), where the binary code CB includes a random number NONCE and a memory address ADDR. Furthermore, the transposition unit 335 transposes the binary code CB according to the key KEY and the memory address ADDR to generate a transposition code CRA (step S140). Next, the cryptographic unit 334 generates a key stream KS according to the key KEY and the transposition code CRA (step S150).

[0150] According to some embodiments of the present invention, utilizing Figure 5 The transposition logic 500 Figure 6 The transposition logic 600 Figure 7 The transposition logic 700 and its combinations transpose the binary code CB to generate the transposition code CRA. According to some embodiments of the present invention, the key KEY and each bit of the memory address ADDR are added, mutually exclusive, or combined to generate the selection code CSEL, and one transposition code CRA is selected from multiple transposition codes according to the selection code CSEL, and combined with the key KEY of the corresponding memory address ADDR to generate the key stream KS.

[0151] This invention proposes a cryptographic device and method for generating a key stream instantaneously when a memory control device operates on a memory array. Compared to counter cryptography, the cryptographic device and method proposed in this invention use a different input data encoding method, which makes it more difficult for attackers to build a power analysis module, thereby providing better data protection capabilities.

[0152] While the embodiments and advantages of this application have been disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this application. Furthermore, the scope of protection of this application is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments herein. Those skilled in the art can understand from the disclosure of some embodiments of this application the current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of this application. Therefore, the scope of protection of this application includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this application also includes combinations of various claims and embodiments.

Claims

1. A cryptographic device, characterized in that, Suitable for a memory device, comprising: A judgment unit determines that a memory address is located in a protected area and selects a key and a random number accordingly; A transposition unit, based on the aforementioned key and the aforementioned memory address, transposes a binary code to generate a transposition code, wherein the binary code includes the aforementioned random number and the aforementioned memory address; and A cryptographic unit generates a key stream based on the aforementioned key and the aforementioned transposition code; The aforementioned transposition unit includes: Multiple transposition logic units, wherein each of the multiple transposition logic units has a transposition logic, and the binary code is transposed according to the transposition logic to generate the transposition code, wherein the transposition logic corresponding to each of the multiple transposition logic units is different. A selection logic unit generates a selection code based on the aforementioned key and the aforementioned memory address; and A second multiplexer, based on the selection code mentioned above, outputs the transposition code generated by one of the multiple transposition logic units.

2. The cryptographic device as described in claim 1, characterized in that, The aforementioned memory device includes a first bus interface, a controller, and a memory array. When the first bus interface receives the memory address and an operation instruction, the first bus interface sends the memory address to the determination unit and the operation instruction to the controller, causing the controller to read encrypted read data and / or write write data into the memory array according to the memory address and the operation instruction. When the cryptographic unit generates the key stream, the cryptographic unit also generates a valid signal. The controller uses the key stream to decrypt the encrypted read data and encrypt the written data according to the valid signal.

3. The cryptographic device as described in claim 1, characterized in that, Including: A temporary register is used to store the start address and end address of the memory address of the aforementioned protected area, the aforementioned key corresponding to the memory address of the aforementioned protected area, and the aforementioned random number. A second bus interface, through which a user sets the key and the random number stored in the register corresponding to the protected area; and A first multiplexer selects the key corresponding to the memory address and the random number according to a judgment signal, wherein the judgment unit generates the judgment signal when the judgment unit determines that the memory address is located in the protection area.

4. The cryptographic device as described in claim 1, characterized in that, One of the aforementioned multiple transposition logic units divides the aforementioned binary code into at least a first part and a second part according to the aforementioned transposition logic, and generates the aforementioned transposition code by changing the order of the aforementioned first part and the aforementioned second part.

5. The cryptographic device as described in claim 3, characterized in that, The selection logic unit performs an addition operation on each bit of the key and the corresponding bit of the memory address to generate the selection code.

6. A cryptographic method, characterized in that, Suitable for a memory array, including: Determine if a memory address is located in a protected region and select a key and a random number accordingly; Generate a binary code, wherein the binary code includes the random number and the memory address; A selection code is generated based on the aforementioned key and the aforementioned memory address; Based on the above selection code, one of multiple transposition logics is selected as a single transposition logic, wherein the above transposition logics are different from each other; The binary code is transposed using the aforementioned selection transposition logic to generate a transposed code; and Based on the aforementioned key and transposition code, a key stream is generated.

7. The cryptographic method as described in claim 6, characterized in that, Including: Based on the aforementioned memory address and an operation instruction, read encrypted read data from a memory array and / or write write data to the aforementioned memory array. as well as The aforementioned key stream is used to decrypt the encrypted read data and encrypt the aforementioned written data.

8. The cryptographic method as described in claim 6, characterized in that, Including: The start and end addresses of the memory address of the aforementioned protected region, along with the key and random number corresponding to the memory address of the aforementioned protected region, are stored in a temporary register. A user sets the key and random number corresponding to the memory address of the aforementioned protected region stored in the temporary register via a bus interface. When it is determined that the memory address is located in the protection area, the key and the random number corresponding to the memory address are selected from the temporary register.

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