Non-volatile semiconductor memory and method of manufacturing the same

Abstract

The application discloses a non-volatile semiconductor memory and a preparation method thereof, and belongs to the field of semiconductor memories. The device comprises a substrate, a control gate, a storage gate, a source region and a drain region. The substrate is located at the bottom and has a first doping type. The source region and the drain region are located above the substrate and are doped with a second doping type opposite to the first doping type. The region between the source region and the drain region is a channel region, which is divided into a channel region I and a channel region II. The control gate covers the channel region I, and a gate dielectric is located between the lower surface of the control gate and the upper surface of the channel region I. A ferroelectric layer is located above the channel region II. The ferroelectric layer is a thin film made of a material with ferroelectric characteristics. The storage gate is located directly above the ferroelectric layer. The control gate is connected with a word line, the drain region is connected with a bit line, the source region is connected with a common source line, the substrate is grounded, and the voltage of the storage gate is changed by the control gate to change the electric field of the ferroelectric layer. The polarization state of the ferroelectric layer is used to store "0" and "1". The application can realize random access, random writing and block erasing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memories, and in particular to a non-volatile semiconductor memory and its fabrication method. Background Technology

[0002] With the development of the semiconductor industry and the popularization of embedded applications such as specialized hardware and the Internet of Things, the industrial requirements for the performance of non-volatile memory, including power consumption, speed, storage density, reliability, and write resistance, are constantly increasing. Traditional non-volatile semiconductor memories are difficult to meet these requirements due to their high write voltage, slow write speed, and poor write resistance. Ferroelectric field-effect transistors (FeFETs) replace the gate oxide in the MOSFET structure with a ferroelectric thin film to regulate the channel's on / off state using the polarization of the ferroelectric thin film; by applying voltages of different polarities to the gate, the residual polarization of the ferroelectric layer can be controlled to switch between two directions, achieving the purpose of storing "0" and "1". FeFETs have advantages such as fast write speed, low operating voltage, high storage density, non-destructive readout, and strong ability to be repeatedly erased and rewritten. However, traditional FeFET structures still have the following two problems:

[0003] (I) Traditional 1T FeFET memory suffers from write crosstalk, leading to issues with storage density and reliability. Traditional memory array programming requires simultaneous voltage application to both the gate (word line) and drain (bit line). Therefore, in a cross-array structure, a specific memory cell at the intersection of a word line and a bit line can be selected and programmed individually. In contrast, 1T FeFETs, whose programming operation is only controlled by the voltage between the gate and the channel, cannot achieve cross-selection on their own. Constructing a cross-array structure requires additional gating devices, resulting in reduced integration density. A common approach is to connect the gate and bit line through an additional transistor or transmission gate, and control the switching of this transistor or transmission gate through the word line. While this method achieves cross-selection and avoids write crosstalk, it requires two or three transistors per memory cell, reducing storage density. Another design modifies the voltage difference between the gate and channel by applying voltages to the source, drain, and substrate, ensuring that only the selected memory cell has a voltage difference greater than the polarization threshold, thus enabling operation. While this method maintains storage density while achieving a cross-array structure, it cannot completely eliminate write crosstalk. Since the ferroelectric layer of unselected memory cells also experiences a certain electric field, its polarization state may change, and the stored data may become invalid, resulting in reduced data reliability.

[0004] (ii) Potential leakage current reduces memory data reliability and increases power consumption. Because FeFET threshold voltage fluctuates significantly and the device threshold voltage is low when the ferroelectric layer polarization is downward, threshold voltage shifts can cause the downward-polarized FeFET threshold voltage to drop below 0V, remaining on when not selected, significantly increasing leakage current and resulting in decreased reliability and increased power consumption. To mitigate the impact of leakage current, higher threshold voltages are often used in FeFET memory designs. However, a higher threshold voltage also results in a higher gate voltage during data reads, which induces a strong electric field in the ferroelectric layer, interfering with the ferroelectric layer polarization state; that is, the corresponding memory cell will be weakly programmed during data reads. Therefore, using a higher threshold voltage cannot effectively improve memory reliability. Summary of the Invention

[0005] The purpose of this invention is to propose a non-volatile semiconductor memory and its fabrication method. This memory can achieve random writing without gating devices, has high storage density, and improves problems such as write crosstalk, leakage current, and read interference. It also has high reliability, good data retention characteristics, low operating voltage, low power consumption, fast erase and write speed, and strong erase and write resistance.

[0006] The specific technical solution of this invention is as follows:

[0007] A non-volatile semiconductor memory, characterized by comprising a substrate, a control gate, a storage gate, a source region, and a drain region, wherein the substrate is located at the bottom and has a first doping type; the source and drain regions are located above the substrate, and the source and drain regions are doped with a second doping type opposite to the substrate doping type; the region between the source and drain regions is a channel, and an isolation region is located in the middle of the channel; the channel is divided into a first channel region and a second channel region; the control gate covers the first channel region, and a gate dielectric is formed between the lower surface of the control gate and the upper surface of the first channel region; a ferroelectric layer is covered above the second channel region, the ferroelectric layer being a thin film made of a material with ferroelectric properties; the storage gate is located directly above the ferroelectric layer; the control gate is connected to the word line; the drain region is connected to the bit line; the source region is grounded through a common source line; the substrate is grounded; the voltage of the control storage gate changes the electric field of the ferroelectric layer; and the polarization state of the ferroelectric layer is used to store "0" and "1". In specific use, the source and the substrate can be kept grounded. The control gate voltage V CG By controlling whether the channel beneath the ferroelectric layer is grounded through the source, it, together with the drain, controls the surface potential of the channel beneath the ferroelectric layer, thereby regulating the potential difference between the upper and lower ends of the ferroelectric layer. CG When the voltage is below the threshold voltage, the lower channel of CG is turned off, and the lower channel of MG is separated from the source; when the lower channel of MG is turned on, its surface potential is close to the drain voltage V. D Storage gate voltage V MGBy controlling the electric field of the underlying ferroelectric layer and regulating its polarization state, erase and write operations can be achieved. Using the ferroelectric layer polarization state to store "0" and "1" can accelerate the erase and write speed, reduce the operating voltage, and improve reliability and write tolerance. When the drain and storage gate are connected to the same positive voltage V... D =V MG At this time, the voltages at both ends of the ferroelectric layer are the same, the internal electric field is shielded, and the polarization state does not change with the MG gate voltage. CG Above the threshold voltage, the CG lower channel turns on, and the MG lower channel is grounded through the source; when the MG lower channel turns on, the surface potential of the main part is close to the source voltage of 0V. Storage gate voltage V MG The current falls onto the ferroelectric layer, inducing an electric field that causes the ferroelectric layer's polarization state to change according to the MG gate voltage. During the write operation, V is maintained. D =V MG V CG Then you can control V D =V MG Whether to change the polarization state of the ferroelectric layer to achieve cross-selection and eliminate write crosstalk. Meanwhile, V CG When the voltage is below the threshold voltage, the CG lower channel turns off, cutting off leakage current. Even if the MG threshold voltage is less than 0V, the device is not selected when V... CG Even if the value is 0, a large leakage current will still not be generated.

[0008] Furthermore, the substrate material may be silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium tin oxide, organic materials, or combinations thereof.

[0009] Furthermore, the ferroelectric layer material can be a single layer or a multilayer combination of any one of the following materials: hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, and lead titanate.

[0010] Furthermore, the storage gate or control gate may be made of doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, or metal silicide.

[0011] Furthermore, the gate dielectric layer may be made of silicon dioxide, silicon nitride, titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide.

[0012] Furthermore, the dielectric buffer layer may be made of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, HfAlO, HfSiO, Ta2O5 or TaSiO.

[0013] Furthermore, the sidewall insulation can be made of silicon dioxide or silicon nitride.

[0014] This invention further provides a method for fabricating a non-volatile semiconductor memory, comprising the following steps:

[0015] 1) Substrate doping and channel region one and channel region two are formed through diffusion, ion implantation and other methods;

[0016] 2) The gate dielectric of the control gate is formed using LPCVD, PECVD, HDP-CVD, and ALD deposition techniques;

[0017] 3) Ferroelectric layer materials are deposited using atomic layer deposition, physical vapor deposition, low-pressure chemical vapor deposition, and plasma-enhanced chemical deposition techniques;

[0018] 4) Deposit memory gate materials using low-pressure chemical vapor deposition and plasma chemical deposition techniques;

[0019] 5) At the second location of the channel region, the memory gate and ferroelectric layer pattern are defined on the photoresist using photolithography, and then patterned using wet etching and reactive ion etching techniques, followed by removal of the photoresist;

[0020] 6) Utilize LPCVD, PECVD, HDP-CVD chemical vapor deposition, physical vapor deposition, and atomic layer deposition to control gate materials;

[0021] 7) Planarize using chemical mechanical polishing;

[0022] 8) Define the control gate pattern on the photoresist at a location in the channel region using photolithography, pattern it using reactive ion etching technology, and then remove the photoresist to form the control gate;

[0023] 9) Use diffusion and ion implantation doping processes to heavily dopant, with the doping type being the opposite of the substrate doping type in step 1), to form isolation regions for the source, drain, and channel.

[0024] The technical effects of this invention are as follows:

[0025] 1) Cross-selection during programming is achieved using CG, eliminating the need for additional transistors or transmission gates for gating, resulting in high storage density; there is no write crosstalk during programming, ensuring high reliability.

[0026] 2) Using CG to cut off leakage current, it has high reliability and low power consumption.

[0027] 3) Lower threshold voltage, operating voltage, and reading voltage can be used; and the impact of reading operations on data is reduced, thus enhancing reliability.

[0028] 4) Utilizing the polarization state of the ferroelectric layer to store data, it has lower operating voltage and power consumption, faster erase and write speed, stronger erase and write resistance, and better data retention characteristics compared with traditional non-volatile memory. Attached Figure Description

[0029] Figure 1 This is an example diagram of the device structure of the present invention;

[0030] Figure 2 This is a schematic diagram illustrating the writing operation principle of the present invention;

[0031] Figure 3 This is a schematic diagram illustrating the principle of write crosstalk elimination for the semi-selected memory cell in this invention.

[0032] Figure 4 This is a schematic diagram of the preparation process in an embodiment of the present invention.

[0033] In the figure, 1—substrate; 2—source region; 3—drain region; 4—control gate; 5—gate dielectric; 6—memory gate; 7—ferroelectric layer; 8—dielectric buffer layer; 9—sidewall isolation; 10—channel doped region; 11—channel region one; 12—channel region two. Detailed Implementation

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0035] like Figure 1 The device comprises a substrate, a control gate (CG), a memory gate (MG), source regions, and drain regions. Below the MG is a ferroelectric layer composed of materials with ferroelectric properties such as hafnium zirconium oxide or hafnium oxide. A buffer material such as silicon dioxide can be added between the ferroelectric layer and the substrate. In practical applications, the CG can be connected to the word line (WL), the drain to the bit line (BL), and the MG can be connected to the same voltage as the BL. The source is grounded through the common source line (Common SL), and the substrate is grounded, forming a NOR-type cross-array structure. This type of memory enables random access, random writes, and block erasure. The substrate is a silicon substrate, located at the bottom, and is p-doped. The upper part contains the source and drain regions, which are N+ doped. The gate dielectric, control gate, memory gate, ferroelectric layer, and insulating layers are all stacked on top of the substrate. High-doped p-wells are formed in the substrate using ion implantation, and then the memory cells are isolated using shallow trench isolation (STI) and field oxide processes.

[0036] The region between the source and drain regions forms a channel, with an isolation region located in the middle of the channel. The channel is divided into channel region one and channel region two. The ferroelectric layer, a thin layer of hafnium zirconium oxide (HZO), is located on top. The lower surface of the ferroelectric layer is in contact with channel region two, and its upper surface is in contact with the storage gate. A thin layer of silicon dioxide may be provided between the lower surface of the ferroelectric layer and channel region two to improve interface properties. The ferroelectric layer is formed by atomic layer deposition (ALD).

[0037] The memory gate uses an N+ polysilicon gate, located directly above the ferroelectric layer and overlapping it vertically. Sidewall spacers separate the memory gate from the ferroelectric layer on both sides. First, a polysilicon thin film is deposited using low-pressure chemical vapor deposition (LPCVD), with in-situ N+ doping performed during deposition. Then, the memory gate pattern is defined on photoresist using photolithography, followed by reactive ion etching (RIE). The etching is stopped and the photoresist is removed when silicon dioxide is exposed. After the ferroelectric layer, memory gate, control gate, and insulating layer are all formed, a thin layer of silicon nitride is deposited using LPCVD, and then briefly etched using RIE until silicon dioxide is exposed, forming the sidewall spacers.

[0038] The control gate is also an N+ polysilicon gate, located above the substrate and gate dielectric, covering channel region one. A thin silicon dioxide layer lies between the lower surface of the control gate and the upper surface of channel region one, with sidewall isolation on both sides. First, a silicon dioxide thin layer is formed through thermal oxidation, followed by polysilicon film deposition using LPCVD, with in-situ doping during the process. Subsequently, planarization is achieved using chemical mechanical polishing (CMP), and the control gate pattern is defined using photolithography. After photolithography, RIE etching is used until the silicon substrate is exposed, and the photoresist is removed to form the control gate. The control gate can be formed after the memory gate is formed but before the sidewall isolation is formed. The materials and formation methods for the sidewall isolation have already been described.

[0039] The source and drain regions are located on both sides of the channel and are N+ doped. After the gate stack is formed, low-concentration ion implantation and halo implantation are performed first to form source and drain epitaxy. After the sidewall isolation is formed, self-aligned ion implantation is used to form the doped regions mentioned above.

[0040] During programming, a positive voltage greater than the polarization switching threshold is applied to the memory cell MG to be written and the drain (where it is located, BL), and a positive voltage greater than the threshold voltage is applied to CG (where it is located, WL), the latter of which can be a logic high level.

[0041] like Figure 2 At this point, the channel of the selected memory cell is fully open, and the positive drain voltage drops to the drain end of the channel. Except for the junction with the drain, the surface potential of the main part of the channel is close to the source voltage of 0V. The voltage on the upper surface of the ferroelectric layer is the positive voltage of MG, and the voltage on the lower surface is the channel surface potential of 0V. The large positive voltage applied to MG drops into the ferroelectric layer, and there is a downward-directed and strong electric field in the ferroelectric layer, which changes the polarization state. After the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the cell is written with "1".

[0042] like Figure 3The remaining cells sharing the polarization transition layer (BL) with the programmed memory cell are half-selected. A positive voltage greater than the polarization reversal threshold is applied to the MG and drain, while the CG voltage is 0. At this time, there is no inversion layer under CG, but inversion occurs under MG. The inversion layer under MG is only connected to the drain, and its potential is close to the drain's positive voltage. The voltage on the upper surface of the ferroelectric layer is the positive voltage of MG, and the voltage on the lower surface is the positive voltage of the drain. Because the voltages applied to MG and the drain are the same during use, the electric field inside the ferroelectric layer is very weak. The large positive voltage applied to MG and the drain drops onto the reverse-biased PN junction between the drain, the inversion layer, and the substrate. The ferroelectric layer is shielded by the inversion layer below, and its polarization state remains unchanged. Therefore, the memory cell half-selected by the BL is unaffected.

[0043] For the remaining memory cells, the voltages of MG, drain, and source are all 0V. Therefore, regardless of whether a positive voltage is applied to CG, the voltages on the upper and lower surfaces of the ferroelectric layer are all 0V, the polarization state remains unchanged, and the memory cells are unaffected.

[0044] During erasure, a strong negative voltage with an amplitude greater than the polarization reversal threshold is applied to the memory cell MG to be erased. At this time, the potential of the upper surface of the ferroelectric layer is the negative voltage applied by MG, and the voltage of the lower surface is the substrate voltage of 0V, and it is subjected to a strong upward electric field; after the voltage is removed, the ferroelectric layer retains the residual polarization pointing upward, and the cell is erased to "0". Since the erasure is only controlled by the MG voltage, the voltage on the entire BL is erased.

[0045] During reading, a voltage greater than the threshold voltage is applied to CG, and a read voltage is applied to MG; the read voltage is between the threshold voltages corresponding to the two ferroelectric polarization states. If the ferroelectric layer polarization direction is downward, the MG voltage is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off, and "0" is read.

[0046] Figure 4 This is a schematic diagram of the preparation process of an embodiment of the present invention, which specifically includes the following steps:

[0047] 1) Substrate doping and channel region one and channel region two are formed through diffusion, ion implantation and other methods;

[0048] 2) The control gate dielectric is formed using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD;

[0049] 3) Ferroelectric layer materials are deposited using techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), and plasma chemical deposition (PECVD);

[0050] 4) Deposit memory gate materials using techniques such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical deposition (PECVD);

[0051] 5) At the second location of the channel region, the memory gate and ferroelectric layer pattern are defined on the photoresist using photolithography. The pattern is then created using etching techniques such as wet etching (WE) and reactive ion etching (RIE), and the photoresist is subsequently removed.

[0052] 6) Deposit control gate materials using technologies such as LPCVD, PECVD, HDP-CVD, chemical vapor deposition, physical vapor deposition (PVD), and atomic layer deposition (ALD);

[0053] 7) Planarization using techniques such as chemical mechanical polishing (CMP);

[0054] 8) Define the control gate pattern on the photoresist at a location in the channel region using photolithography, pattern it using etching techniques such as reactive ion etching (RIE), and then remove the photoresist to form the control gate;

[0055] 9) Deposit sidewall isolation material using CVD, ALD and other technologies, and then etch it using dry etching, RIE and other technologies until the substrate described in step 1 is exposed to form sidewall isolation;

[0056] 10) Use diffusion, ion implantation or other doping processes to heavily dopant, with the doping type being the opposite of the substrate doping type described in step 1, to form an isolation region between the source and drain regions and the channel.

[0057] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A nonvolatile semiconductor memory, characterized by comprising: The system includes a substrate, a control gate, a storage gate, a source region, and a drain region. The substrate is located at the bottom and has a first doping type. The source and drain regions are located above the substrate and are doped with a second doping type opposite to that of the substrate. The area between the source and drain regions is a channel, and an isolation region is located in the middle of the channel. The channel is divided into a first channel region and a second channel region. The control gate covers the first channel region, and a gate dielectric layer is located between the lower surface of the control gate and the upper surface of the first channel region. A ferroelectric layer is covered above the second channel region. The ferroelectric layer is a thin film made of a material with ferroelectric properties. The storage gate is located directly above the ferroelectric layer. The control gate is connected to the word line, the drain region is connected to the bit line, the source region is grounded through a common source line, and the substrate is grounded. The voltage of the control storage gate changes the electric field of the ferroelectric layer, and the polarization state of the ferroelectric layer is used to store "0" and "1".

2. The non-volatile semiconductor memory as described in claim 1, characterized in that, A dielectric buffer layer is provided between the ferroelectric layer and the second channel region.

3. The non-volatile semiconductor memory as described in claim 1, characterized in that, The control gate and the gate dielectric layer are respectively provided with sidewalls for isolation on both sides, as are the storage gate and the ferroelectric layer.

4. The non-volatile semiconductor memory as described in claim 1, characterized in that, The substrate material is made of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium tin oxide, organic materials, or combinations thereof.

5. The non-volatile semiconductor memory as described in claim 1, characterized in that, The ferroelectric layer material is a single layer or a multilayer combination of any one of the following materials: hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, and lead titanate.

6. The non-volatile semiconductor memory as described in claim 1, characterized in that, The storage gate or control gate is made of doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, or metal silicide.

7. The non-volatile semiconductor memory as described in claim 1, characterized in that, The gate dielectric layer is made of silicon dioxide, silicon nitride, titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide.

8. The non-volatile semiconductor memory as described in claim 2, characterized in that, The dielectric buffer layer is made of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, HfAlO, HfSiO, Ta2O5 or TaSiO.

9. The non-volatile semiconductor memory as described in claim 3, characterized in that, The sidewall insulation is made of silicon dioxide or silicon nitride.

10. A method for fabricating a non-volatile semiconductor memory as described in claim 1, comprising the following steps: 1) Substrate doping and channel region one and channel region two are formed by diffusion and ion implantation; 2) The gate dielectric of the control gate is formed using LPCVD, PECVD, HDP-CVD, and ALD deposition techniques; 3) Ferroelectric layer materials are deposited using atomic layer deposition, physical vapor deposition, low-pressure chemical vapor deposition, and plasma-enhanced chemical deposition techniques; 4) Deposit memory gate materials using low-pressure chemical vapor deposition and plasma chemical deposition techniques; 5) At the second location of the channel region, the memory gate and ferroelectric layer pattern are defined on the photoresist using photolithography, and then patterned using wet etching and reactive ion etching techniques, followed by removal of the photoresist; 6) Utilize LPCVD, PECVD, HDP-CVD chemical vapor deposition, physical vapor deposition, and atomic layer deposition to control gate materials; 7) Planarize using chemical mechanical polishing; 8) Define the control gate pattern on the photoresist at a location in the channel region using photolithography, pattern it using reactive ion etching technology, and then remove the photoresist to form the control gate; 9) Use diffusion and ion implantation doping processes to heavily dopant, with the doping type being the opposite of the substrate doping type in step 1), to form isolation regions for the source, drain, and channel.

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