Method of patterning organic semiconductor thin films and organic semiconductor patterned arrays
By employing electron beam lithography and thermal annealing techniques, the problem of insufficient stability in existing organic semiconductor thin films has been solved, enabling the fabrication of high-resolution organic semiconductor arrays with high efficiency and environmental friendliness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN UNIV
- Filing Date
- 2023-10-20
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies struggle to fabricate high-resolution patterned arrays of organic semiconductors, and traditional methods lack stability for organic semiconductor thin films, failing to meet the demands for high resolution.
Electron beam lithography is used to expose and pattern organic semiconductor thin films, and unstable organic semiconductors are removed by thermal annealing, leaving stable patterned regions to form a high-resolution organic semiconductor array.
The fabrication of high-resolution organic semiconductor arrays has been achieved, exhibiting high temperature stability and pattern tunability. This reduces solvent usage and cleaning steps, thereby improving fabrication efficiency and resource utilization.
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Figure CN117377364B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of organic electronics and relates to the patterning of organic semiconductor thin films. Specifically, it includes a new method for high-resolution patterning of organic semiconductor thin films, and in particular, a method for patterning organic semiconductor thin films and an organic semiconductor patterning array. Background Technology
[0002] Organic semiconductors, due to their inherent flexibility and tunable molecular structure, hold significant promise for applications in novel circuits that complement silicon-based circuits, such as human-computer interaction, the Internet of Things, and flexible wearable electronics. The most basic unit of a circuit is a patterned semiconductor layer used to further fabricate patterned basic circuit units. Compared to inorganic semiconductors, organic semiconductors have weaker intermolecular forces and are more easily destroyed by solvents. Therefore, current mature methods for fabricating patterned semiconductors, such as photolithography, are not suitable for fabricating patterned organic semiconductor thin film arrays. Thus, developing a new method for fabricating high-resolution organic semiconductor patterned arrays is the most critical technical challenge in organic circuit fabrication.
[0003] Organic semiconductors, as an emerging electronic material, are solids formed by the periodic spatial arrangement of molecules through intermolecular forces. Currently, commonly used methods for preparing organic semiconductor thin films include: (1) Vacuum thermal deposition: By controlling the thermal evaporation temperature of organic molecules, the evaporated molecules diffuse throughout the cavity and are then deposited on the substrate to form a film; (2) Splice coating method: By selecting a suitable solvent and a coating rate, large-area organic semiconductor thin films can be obtained.
[0004] However, the methods described above only produce large-area thin films. If further applications are desired, new methods for patterning are needed.
[0005] In the prior art, CN101420015A discloses a method for fabricating an organic thin-film transistor with a patterned active layer. After the metal source and drain electrodes are fabricated, photoresist is used as a mask to first fabricate an organic semiconductor thin film layer using vacuum evaporation. Then, a protective layer is fabricated on top using room temperature PECVD. The sum of the thicknesses of the organic layer and the protective layer is made less than the thickness of the metal electrodes to ensure that the resist strip does not come into contact with the organic layer and damage the properties of the organic semiconductor thin film when removing the photoresist mask. This method ultimately completes the fabrication of an organic thin-film transistor with a patterned active layer. Specifically, the method includes the following steps: Step 101: Form an insulating gate layer on a conductive substrate; Step 102: Form the source electrode and drain electrode on the insulating gate layer; Step 103: Form a photoresist mask on the source electrode, drain electrode, and insulating gate layer; Step 104: Form a first organic semiconductor thin film layer and a second organic semiconductor thin film layer on the insulating gate layer and the photoresist mask; Step 105: Form a first protective layer and a second protective layer on the first organic semiconductor thin film layer and the second organic semiconductor thin film layer; Step 106: Strip the photoresist mask, the organic semiconductor in the non-active region, and the second protective layer on the organic semiconductor in the photoresist solvent to form a patterned first organic semiconductor thin film layer with a protective layer. In step 106, when stripping the photoresist mask, the organic semiconductor in the non-active region, and the second protective layer on the organic semiconductor, a stripping technique is used to strip the photoresist mask to obtain a patterned organic semiconductor thin film layer. The sum of the thicknesses of the organic semiconductor thin film layer and the protective layer is less than the thickness of the metal source and drain electrodes to ensure that the properties of the organic semiconductor thin film in the active region are not damaged by the photoresist and the photoresist stripping solution.
[0006] The patented technology mentioned above is based on a mask method to achieve patterning, but the semiconductor thin film prepared by this method is not very stable and cannot obtain a high-resolution organic semiconductor patterned array. Summary of the Invention
[0007] To address the gaps in existing methods for fabricating high-resolution patterned organic semiconductor arrays, this invention aims to develop a rapid and efficient new method for fabricating high-resolution patterned organic semiconductor arrays. This method leverages the characteristics of organic semiconductor thin films, including numerous grain boundaries, dislocations, stacking faults, and relatively weak intermolecular van der Waals forces. Therefore, organic semiconductor molecules readily migrate and desorb at high temperatures. By utilizing the stabilizing effect of a high-energy electron beam region on the organic semiconductor thin film, and through thermal annealing, unstable aggregated structures in the semiconductor thin film are removed, thereby achieving high-resolution patterning of the organic semiconductor thin film.
[0008] The objective of this invention is achieved through the following technical solution.
[0009] A first aspect of the present invention provides a method for patterning organic semiconductor thin films, comprising the following steps: Organic semiconductor thin films are fabricated on a carrier material. The organic semiconductor thin film is exposed and patterned using electron beam lithography to form a patterned stable region on the organic semiconductor thin film. The exposed organic semiconductor thin film is then subjected to thermal annealing to volatilize the unstable organic semiconductor.
[0010] Furthermore, a smooth surface is used as the carrier material.
[0011] Furthermore, the load material carrier is SiO2 / Si.
[0012] Furthermore, methods for preparing organic semiconductor thin films on a carrier substrate include one of vacuum thermal evaporation, blade coating, and solution processing.
[0013] Furthermore, the raw materials used to prepare organic semiconductor thin films on the support material substrate are one of DNTT, DPA, pentacene, and ruberene.
[0014] Furthermore, the electron beam includes one of high-energy ionizing radiation, electron beam irradiation, high-energy ray irradiation, and laser exposure.
[0015] In another aspect of the present invention, an organic semiconductor patterned array is provided, obtained according to the method for patterning organic semiconductor thin films as described above.
[0016] The beneficial effects of this invention are: The method in this invention utilizes the high-temperature instability of polycrystalline thin films and leverages the stabilizing effect of electron beams on organic semiconductor thin films. Stable and unstable organic semiconductor regions are fabricated on the same organic semiconductor thin film using electron beam lithography. Furthermore, taking advantage of the high-temperature volatility and migration of the unstable organic semiconductor film, a high-temperature thermal annealing process is used to distinguish the stable organic semiconductor film. Due to their high stability, the patterned organic semiconductors remain on the substrate after high-temperature annealing. This process produces a high-resolution organic semiconductor array with high high-temperature stability, tunable patterns, and requires less solvent, making it more efficient and simpler. Compared to photolithography for fabricating organic semiconductor arrays, this method eliminates the need for extensive solvent selection and complex cleaning steps, requiring only two steps to obtain high-resolution patterned semiconductors, significantly reducing energy consumption and resource waste. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below.
[0018] Figure 1 This is a schematic diagram of the preparation of a patterned organic semiconductor array in an embodiment of the present invention, where a represents a pre-prepared organic semiconductor polycrystalline thin film, b represents the state process of direct electron beam lithography patterning, and c represents the organic semiconductor patterned array obtained by thermal annealing. Figure 2 The DNTT polycrystalline thin film grown in the embodiments of the present invention; Figure 3 The image shown is a patterned optical image of DNTT obtained in an embodiment of the present invention. Figure 4These are atomic force microscope images of the DNTT patterned array obtained in an embodiment of the present invention; Figure 5 These are high-resolution array atomic force microscope images obtained in the embodiments of the present invention; Figure 6 The electrical performance of the DNTT array grown in the embodiments of the present invention; Figure 7 This is an optical image of the DPA array grown in an embodiment of the present invention.
[0019] Figure 8 This is an optical image of a pentacene array grown in an embodiment of the present invention. Implementation
[0020] The following examples are merely illustrative of the invention, and the scope of the invention is not limited to the embodiments described. Therefore, any non-essential modifications and adjustments made by those skilled in the art based on the above description to other embodiments are still within the scope of protection of this invention.
[0021] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0022] Organic semiconductor molecules: DNTT
[0023] Purity: 99% Source: Shanghai Daran Chemical Co., Ltd. DPA (2,6-diphenylanthracene):
[0024] Purity: 99% Source: Shanghai Daran Chemical Co., Ltd. Pentabenzene:
[0025] Purity: 99% Source: Shanghai Daran Chemical Co., Ltd. The following examples illustrate how this method can be used to prepare different organic semiconductor thin film arrays.
[0026] Figure 1 This is a flowchart of a method for fabricating organic semiconductor thin film arrays. This invention provides a method for patterning organic semiconductor thin films, such as... Figure 1As shown, the pre-prepared polycrystalline thin film is first patterned using electron beam lithography to obtain stable and patterned regions. Then, the unstable semiconductor film is removed by thermal annealing after patterning, and finally, an organic semiconductor patterned array can be directly obtained on the substrate.
[0027] It should be noted that any patterned electron beam can be a high-energy electron beam, such as high-energy ionizing radiation, electron beam irradiation, high-energy ray irradiation, laser exposure, and a series of other high-energy electron beams. This embodiment does not impose any specific restrictions on it. Example
[0028] There are various methods for preparing organic semiconductor thin films on substrates, such as thermal evaporation and blade coating, which are traditional commercial and commonly used methods for mass production of organic semiconductor thin films. This example uses thermal evaporation to directly construct a 20 nm DNTT polycrystalline film on the surface of silicon dioxide modified with octadecyltrichlorosilane (OTS).
[0029] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 20 nm DNTT thin film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared DNTT thin film was then subjected to electron beam exposure. The patterned DNTT semiconductor thin film was then thermally annealed to remove unstable DNTT semiconductors, leaving thermally stable DNTT semiconductors, thus forming a patterned DNTT semiconductor array.
[0030] Figure 2 This is a DNTT semiconductor thin film before electron beam patterning. After electron beam patterning and thermal annealing, a high-resolution organic semiconductor array can be obtained on a silicon wafer. Figure 3 A regular rectangular array of DNTT semiconductors can be seen. Figure 4 Atomic force microscopy images confirm that the minimum size of the DNTT matrix obtained by this method can reach 2µm*4µm. This is related to the electron beam source used and is not the limit for semiconductor matrices. Figure 5 Atomic force microscopy images show that the obtained DNTT semiconductor patterning achieves a resolution on the order of hundreds of nanometers. Figure 6 The electrical performance test can further prove that the obtained DNTT semiconductor matrix still has relatively high electrical performance. Example
[0031] A silicon wafer with dimensions of 1cm × 1cm was selected, containing 300nm silicon dioxide and 500µm heavily doped silicon. The 500µm heavily doped silicon was used as the gate, and octadecyltrichlorosilane (OTS) was modified on the 300nm silicon dioxide by vacuum vapor deposition at 120 degrees Celsius for 1 hour. The 300nm silicon dioxide and OTS were used as the dielectric layer.
[0032] A 20 nm DPA thin film was deposited on OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared DPA thin film was then subjected to electron beam exposure. The patterned DPA semiconductor film was then thermally annealed to remove unstable DPA semiconductors, leaving thermally stable DPA semiconductors, thereby forming a patterned DPA semiconductor array. Figure 7 This is a high-resolution optical image of the DPA semiconductor array.
[0033] Therefore, the method of this invention is simple, requiring only two steps to obtain a high-resolution patterned organic semiconductor array. This method does not require the use of organic reagents during the fabrication of the patterned organic semiconductors, thus avoiding significant resource waste and environmental pollution. The patterned organic semiconductors exhibit excellent high-temperature stability, and the patterned size is as small as 2µm*4µm, with a resolution between organic semiconductors less than 1µm, smaller than the resolution reported by all currently available technologies. Example
[0034] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 20 nm DPA thin film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared DPA thin film was then subjected to electron beam lithography. The patterned DPA semiconductor film was then thermally annealed to remove unstable DPA semiconductors, leaving thermally stable DPA semiconductors, thus forming a patterned DPA semiconductor array. Example
[0035] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 20 nm pentacene thin film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared pentacene thin film was then subjected to electron beam exposure. The patterned pentacene semiconductor film was then thermally annealed to remove unstable pentacene semiconductors, leaving thermally stable pentacene semiconductors, thus forming a patterned pentacene semiconductor array. Figure 8 Optical image of a pentacene semiconductor array. Example
[0036] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 20 nm fluorene film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared fluorene film was then subjected to electron beam exposure. The patterned fluorene semiconductor film was then thermally annealed to remove unstable fluorene semiconductors, leaving only thermally stable fluorene semiconductors, thus forming a patterned fluorene semiconductor array. Example
[0037] A silicon wafer with dimensions of 1cm × 1cm was selected, containing 300nm silicon dioxide and 500μm heavily doped silicon. Using the 500μm heavily doped silicon as the gate, OTS was modified onto the 300nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300nm silicon dioxide and OTS. A 20nm DNTT thin film was then prepared on the OTS-modified silicon dioxide using a blade coating method. The prepared DNTT thin film was then subjected to electron beam exposure. The patterned DNTT semiconductor thin film was then thermally annealed to remove unstable DNTT semiconductors, leaving thermally stable DNTT semiconductors, thus forming a patterned DNTT semiconductor array. Example
[0038] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 15 nm DNTT thin film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared DNTT thin film was then subjected to electron beam exposure. The patterned DNTT semiconductor thin film was then thermally annealed to remove unstable DNTT semiconductors, leaving thermally stable DNTT semiconductors, thus forming a patterned DNTT semiconductor array. Example
[0039] A silicon wafer with dimensions of 1 cm × 1 cm was selected, containing 300 nm silicon dioxide and 500 μm heavily doped silicon. Using the 500 μm heavily doped silicon as the gate, OTS was modified onto the 300 nm silicon dioxide using a vacuum vapor deposition method at 120°C for 1 hour, forming a dielectric layer of 300 nm silicon dioxide and OTS. A 25 nm DNTT thin film was then deposited on the OTS-modified silicon dioxide at a deposition rate of 0.05 Å / s. The prepared DNTT thin film was then subjected to electron beam exposure. The patterned DNTT semiconductor thin film was then thermally annealed to remove unstable DNTT semiconductors, leaving thermally stable DNTT semiconductors, thus forming a patterned DNTT semiconductor array.
[0040] The above exemplary description of the present invention should be understood to mean that any simple modifications, alterations, or other equivalent substitutions that can be made by those skilled in the art without creative effort without departing from the core of the present invention fall within the protection scope of the present invention.
[0041] The organic molecules include, but are not limited to, the organic semiconductor molecules mentioned in this example, and there are many different methods for preparing organic semiconductor thin films, not limited to the traditional commercial and commonly used methods for mass production of organic semiconductor thin films, such as thermal evaporation and blade coating.
[0042] The high-energy ion beam irradiation technique mentioned in this example for stabilizing organic semiconductor thin films includes, but is not limited to, electron beams. It can also include deep high-energy ionizing radiation, electron beam irradiation, high-energy ray irradiation, high-energy lasers, and other techniques to stabilize organic semiconductors.
[0043] The substrate mentioned in this example includes, but is not limited to, SiO2 / Si; any substrate capable of supporting organic semiconductors can be used.
[0044] The thickness of the organic semiconductor thin film mentioned in this example includes, but is not limited to, 20 nm.
[0045] The dielectric layer modification method mentioned in this example is not limited to modifying the dielectric layer; any smooth and flat substrate can be used.
[0046] Using this method to pattern organic semiconductor thin films, any method and possibility of using this method to pattern active layers should fall within the protection scope of this invention.
Claims
1. A method for patterning organic semiconductor thin films, characterized in that, Includes the following steps: Organic semiconductor thin films are fabricated on a carrier material. The organic semiconductor thin film is exposed and patterned using an electron beam to form a patterned stable region on the organic semiconductor thin film. The exposed organic semiconductor thin film is then subjected to thermal annealing to volatilize the unstable organic semiconductor.
2. The method for patterning organic semiconductor thin films as described in claim 1, characterized in that, A smooth surface is used as the load material carrier.
3. The method for patterning organic semiconductor thin films as described in claim 1, characterized in that, The load material carrier is SiO2 / Si.
4. The method for patterning organic semiconductor thin films as described in claim 1, characterized in that, Methods for preparing organic semiconductor thin films on a carrier substrate include one of the following: vacuum thermal evaporation, blade coating, and solution method.
5. The method for patterning organic semiconductor thin films as described in claim 1 or 4, characterized in that, The raw materials for preparing organic semiconductor thin films on a support material substrate are one of DNTT, DPA, pentacene, and ruberene.
6. The method for patterning organic semiconductor thin films as described in claim 1, characterized in that, The electron beam includes one of the following: high-energy ionizing radiation, electron beam irradiation, high-energy ray irradiation, and laser exposure.
7. The organic semiconductor patterned array obtained by the method of patterning organic semiconductor thin films according to any one of claims 1 to 6.