Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, a method for manufacturing the same, and a display device thereof. The display substrate includes a substrate (100) and a semiconductor layer (200) and a conductive layer (400) located on the substrate (100). The semiconductor layer (200) includes a channel region (310) and a doped region pattern (320) of a transistor (300); the conductive layer (400) is stacked on the semiconductor layer (200) and located on the side of the semiconductor layer (200) away from the substrate (100). The conductive layer (400) includes a data line (410) and a first electrode (301) and a second electrode (302) of the transistor (300). The first electrode (301) is electrically connected to the data line (410). The overlapping portion of the semiconductor layer (200) and the data line (410) extends in the same direction as the data line (410). The semiconductor layer (200) includes a first protrusion (210) that is not covered by the data line (410) and protrudes relative to the edge of the data line (410). The first protrusion (210) is disposed at the edge of the data line (410), and the dimension (S1) between the edge of the first protrusion (210) away from the edge of the data line (410) and the edge of the data line (410) is greater than 0 and less than 3.0 micrometers. By reducing the dimension (S1) of the first protrusion (210) protruding relative to the edge of the data line (410) of the semiconductor layer (200), it is beneficial to improve product performance.

Description

Technical Field

[0001] This disclosure relates to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] Currently, amorphous silicon (A-Si) thin-film transistors (TFTs) are widely used in the driving backplanes of liquid crystal display devices. In order to improve production cycle, the active semiconductor layer and the source / drain metal layer are often formed by a half-exposure process using the same mask. Summary of the Invention

[0003] This disclosure provides a display substrate, a method for manufacturing the same, and a display device.

[0004] This disclosure provides a display substrate, including a substrate and a semiconductor layer and a conductive layer disposed on the substrate. The semiconductor layer is located on the substrate and includes a channel region and a doped region pattern of a transistor. The conductive layer is stacked on the semiconductor layer and located on the side of the semiconductor layer away from the substrate. The conductive layer includes a data line and a first electrode and a second electrode of the transistor electrically connected to the doped region pattern, the first electrode being electrically connected to the data line. The overlapping portion of the semiconductor layer and the data line extends in the same direction as the data line. The semiconductor layer includes a first protrusion not covered by the data line and protruding relative to the edge of the data line. The first protrusion is disposed at the edge of the data line, and the distance between the edge of the first protrusion away from the data line and the edge of the data line is a first dimension, which is greater than 0 and less than 3.0 micrometers.

[0005] For example, according to an embodiment of the present disclosure, the portion of the edge of the semiconductor layer that protrudes relative to the edge of the first electrode is a second protrusion, the second protrusion is disposed at the edge of the first electrode, and the dimension of the distance between the edge of the second protrusion away from the edge of the first electrode and the edge of the first electrode is a second dimension, the second dimension being larger than the first dimension.

[0006] For example, according to an embodiment of this disclosure, the first protrusion includes a first step and a second step stacked together, the first step being located between the second step and the substrate, and the dimension between the edge of the first step and the edge of the data line is the first step dimension, and the dimension between the edge of the second step and the edge of the data line is the second step dimension; the ratio of the first step dimension to the second step dimension is in the range of 2-25.

[0007] For example, according to an embodiment of this disclosure, the material of the first step includes amorphous silicon, and the material of the second step includes doped amorphous silicon.

[0008] For example, according to an embodiment of the present disclosure, the data line includes at least one conductive layer, and the angle between the sidewall of the data line and the surface of the second step away from the substrate ranges from 30 to 80 degrees.

[0009] For example, according to an embodiment of this disclosure, the second protrusion includes a third step and a fourth step stacked together, the third step being located between the fourth step and the substrate, and the distance between the edge of the third step and the edge of the first electrode is the third step size, and the distance between the edge of the fourth step and the edge of the first electrode is the fourth step size; the first step size is smaller than the third step size.

[0010] For example, according to embodiments of this disclosure, the material of the third step includes amorphous silicon, and the material of the fourth step includes doped amorphous silicon.

[0011] For example, according to an embodiment of this disclosure, the ratio of the first step size to the second step size is less than the ratio of the third step size to the fourth step size.

[0012] For example, according to an embodiment of the present disclosure, the transistor further includes a gate located between the semiconductor layer and the substrate, wherein the orthographic projection of the second protrusion on the substrate is located within the orthographic projection of the film layer containing the gate on the substrate.

[0013] For example, according to embodiments of this disclosure, the display substrate further includes: a plurality of sub-pixels, each sub-pixel including a pixel electrode, the pixel electrode being located on the side of the conductive layer away from the substrate. The second electrode is electrically connected to the pixel electrode; the semiconductor layer further includes a third protrusion overlapping the second electrode and protruding relative to the edge of the second electrode, the third protrusion surrounding at least a portion of the edge of the second electrode, the minimum interval between the edge of the third protrusion away from the second electrode and the edge of the second electrode being a third dimension, the third dimension being larger than the first dimension.

[0014] For example, according to an embodiment of this disclosure, the display substrate further includes: a gate line, which is disposed on the same layer as the gate and electrically connected to the gate. The plurality of sub-pixels are arranged in an array along the row and column directions, with two adjacent columns of sub-pixels forming a sub-pixel column group; the data line extends along the column direction, and the gate line extends along the row direction, the gate line including multiple first sub-gate lines and multiple second sub-gate lines; the data line is located between two adjacent sub-pixel column groups, and two columns of sub-pixels in the sub-pixel column group are electrically connected to the same data line; the sub-pixel column group includes multiple rows of sub-pixels, and along the column direction, the first sub-gate line and the second sub-gate line are respectively disposed on both sides of each sub-pixel row, and adjacent sub-pixel rows include a gate line pair composed of the first sub-gate line and the second sub-gate line.

[0015] For example, according to an embodiment of this disclosure, the ratio of the second step size to the fourth step size is 0.8 to 1.2.

[0016] This disclosure provides a display device including the above-described display substrate.

[0017] This disclosure provides a method for fabricating a display substrate, comprising: providing a substrate; forming a semiconductor material layer on the substrate; forming a conductive material layer on a side of the semiconductor material layer away from the substrate; and forming an etching mask on the side of the conductive material layer away from the semiconductor material layer. The etching mask includes a first mask portion, which includes a first sub-mask portion and a second sub-mask portion. The second sub-mask portion is located on at least one side of the first sub-mask portion and is located at the edge of the first mask portion along a direction perpendicular to the substrate. The thickness of the first sub-mask portion is greater than the thickness of the second sub-mask portion. After forming the etching mask, the fabrication method further includes: using the first mask portion as a mask to pattern the conductive material layer and the semiconductor material layer to form a data line and a first semiconductor pattern located between the data line and the substrate, wherein the first semiconductor pattern includes a first protrusion that is not covered by the data line and protrudes relative to the edge of the data line, the first protrusion is disposed at the edge of the data line, and the dimension between the edge of the first protrusion away from the data line and the edge of the data line is a first dimension; the first dimension is greater than 0 and less than 3.0 micrometers.

[0018] For example, according to an embodiment of this disclosure, patterning the conductive material layer and the semiconductor material layer using the first mask portion as a mask includes: etching the conductive material layer using the first mask portion as a mask to form a data line pattern; and after forming the data line pattern, etching the semiconductor material layer using the first mask portion as a mask to form a first semiconductor pattern layer.

[0019] For example, according to an embodiment of this disclosure, patterning the conductive material layer and the semiconductor material layer using the first mask portion as a mask includes: wet etching the conductive material layer using the first mask portion as a mask to form the data line pattern, and dry etching the semiconductor material layer using the first mask portion as a mask so that the edges of the first mask portion and the edges of the semiconductor material layer are etched simultaneously.

[0020] For example, according to an embodiment of this disclosure, the etching mask further includes a second mask portion, the second mask portion including a third sub-mask portion located at the edge, along a direction perpendicular to the substrate, the thickness of the third sub-mask portion being the same as the thickness of the first sub-mask portion; after forming the etching mask, the fabrication method further includes: using the second mask portion as a mask to pattern the conductive material layer and the semiconductor material layer to form a first electrode and a second electrode of a transistor and a second semiconductor pattern located between the first electrode and the second electrode of the transistor and the substrate, wherein the second semiconductor pattern includes a channel region and a doped region pattern of the transistor, a protruding portion of the edge of the second semiconductor pattern protruding relative to the edge of the first electrode is a second protrusion, both the first electrode and the second electrode are electrically connected to the doped region pattern, the first electrode is electrically connected to the data line, and the minimum distance between the edge of the second protrusion away from the first electrode and the edge of the first electrode is a second dimension, the second dimension being larger than the first dimension.

[0021] For example, according to an embodiment of this disclosure, patterning the conductive material layer and the semiconductor material layer using the second mask portion as a mask includes: etching the conductive material layer using the second mask portion as a mask to form a transistor source-drain pattern; and after forming the transistor source-drain pattern, etching the semiconductor material layer using the second mask portion as a mask to form a second semiconductor pattern layer.

[0022] For example, according to embodiments of this disclosure, after etching the semiconductor material layer using the first mask portion and the second mask portion as masks to form the first semiconductor pattern layer and the second semiconductor pattern layer, the fabrication method further includes: simultaneously performing an ashing process on the first mask portion and the second mask portion. In the direction perpendicular to the substrate, the thickness of the ashing first mask portion is less than the thickness of the un-ashing first sub-mask portion.

[0023] For example, according to an embodiment of this disclosure, after simultaneously performing ashing treatment on the first mask portion and the second mask portion, the fabrication method further includes: etching the data line pattern using the ashing first mask portion as a mask to form the data line; after forming the data line, etching the edge of the first semiconductor pattern layer using the ashing first mask portion as a mask to form a first step and a second step. The first semiconductor pattern includes a first step and a second step, the first step is located between the second step and the substrate, and the dimension between the edge of the first step and the edge of the data line is the first step dimension, and the dimension between the edge of the second step and the edge of the data line is the second step dimension; the ratio of the first step dimension to the second step dimension is in the range of 2-25.

[0024] For example, according to embodiments of this disclosure, the first mask portion in the etched mask is formed using a halftone mask or a slot mask. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 This is a partial planar structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure;

[0027] Figure 2 For along Figure 1 A schematic diagram of the local cross-sectional structure intercepted by line AA';

[0028] Figure 3 For along Figure 1 A schematic diagram of the local cross-sectional structure intercepted by line BB';

[0029] Figure 4 This is a partial planar structure schematic diagram of a display substrate provided according to an example of an embodiment of the present disclosure;

[0030] Figure 5 This is a partial planar structure schematic diagram of a display substrate provided according to another example of an embodiment of the present disclosure;

[0031] Figures 6A to 6C To make along Figure 1 A schematic diagram of the method for showing a partial cross-sectional structure of the display substrate cut by the DD' line;

[0032] Figure 6D include Figure 6B as well as Figure 7B The diagram shows the planar structure of the slit mask.

[0033] Figures 7A to 7C To make along Figure 1 A schematic diagram of the method for showing a partial cross-sectional structure of the display substrate cut by the EE' line;

[0034] Figure 8 For another production along Figure 1 A schematic diagram of the method for showing a partial cross-sectional structure of the display substrate cut by the EE' line;

[0035] Figure 9 This is a schematic diagram showing the patterning of a data line using the first mask portion as a mask.

[0036] Figure 10 This is a schematic diagram of forming transistor source and drain patterns using the second mask portion as a mask;

[0037] Figure 11 This is a schematic diagram of patterning a semiconductor material layer to form a first semiconductor pattern layer using a first mask portion as a mask;

[0038] Figure 12 This is a schematic diagram of patterning a semiconductor material layer to form a second semiconductor pattern layer using a second mask portion as a mask;

[0039] Figure 13 This is a schematic diagram of the first mask portion after etching and ashing.

[0040] Figure 14 This is a schematic diagram of the etched second mask portion after ashing.

[0041] Figure 15 This is a schematic diagram showing the data line pattern after etching using the first ashing mask as a mask.

[0042] Figure 16 This is a schematic diagram showing the etching of the transistor source and drain patterns using the ashing second mask as a mask.

[0043] Figure 17 This is a schematic diagram showing the etching of the first semiconductor pattern layer using the ashing first mask portion as a mask; and

[0044] Figure 18 This is a schematic diagram showing the etching of the second semiconductor pattern layer using the ashing second mask portion as a mask. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0047] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0048] In their research, the inventors of this application discovered that the channel fabrication of thin-film transistors using the data layer half-exposure (SDT) process involves two wet etching processes and two dry etching processes (2W2D). The 2W2D process can easily result in long active layer protrusions (which can be referred to as active layer tails) at the edges of the source and drain metal layer patterns (such as data lines). If the size of these active layer protrusions exceeds 2 micrometers, it may affect the size of the product design margin and product performance.

[0049] When the size of the active layer protrusion is long, it can easily lead to an increase in the parasitic capacitance between the signal line that overlaps with the data line and the data line, causing signal transmission delay (RC Delay), and can also easily lead to adverse phenomena such as line retention and insufficient charging rate.

[0050] When the aforementioned active layer protrusions are illuminated (e.g., by a backlight), they generate photogenerated carriers and become conductors. When not illuminated, they act as insulating layers. The different current values ​​generated by the active layer protrusions in dark and illuminated states can easily affect product stability. Under AC backlighting, the varying illumination of different locations of the active layer protrusions can easily lead to water ripple defects in the display device.

[0051] This disclosure provides a display substrate and a method for manufacturing the same, as well as a display device. The display substrate includes a substrate and a semiconductor layer and a conductive layer disposed on the substrate. The semiconductor layer includes a channel region and a doped region pattern of a transistor. The conductive layer is stacked on top of the semiconductor layer and is located on the side of the semiconductor layer away from the substrate. The conductive layer includes a data line and a first electrode and a second electrode of a transistor electrically connected to the doped region pattern. The first electrode is electrically connected to the data line. The extension direction of the overlapping portion of the semiconductor layer and the data line is the same as the extension direction of the data line. The semiconductor layer includes a first protrusion that is not covered by the data line and protrudes relative to the edge of the data line. The first protrusion is disposed at the edge of the data line. The distance between the edge of the first protrusion away from the data line and the edge of the data line is a first dimension, which is greater than 0 and less than 3.0 micrometers. By setting the size of the first protrusion protruding from the edge of the semiconductor layer relative to the edge of the data line to be greater than 0 and less than 3 micrometers, this disclosure helps to reduce the size of the product design margin, improve product performance, and reduce the probability of display defects in the display device. Furthermore, in this case, the semiconductor layer and the data line overlap in the same direction as the data line. That is, a semiconductor layer with the same extension direction as the data line is also provided between the data line and the substrate. In terms of process, the semiconductor layer and the data line layer can be made using a single photomask, saving photomasks and improving production efficiency.

[0052] The display substrate, its manufacturing method, and the display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0053] Figure 1 This is a partial planar structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 2 For along Figure 1 The diagram shows a partial cross-sectional structure intercepted by line AA'. Figure 1 and Figure 2As shown, the display substrate includes a substrate 100 and a semiconductor layer 200 and a conductive layer 400 located on the substrate 100. The semiconductor layer 200 is located on the substrate 100 and includes a channel region 310 of a transistor 300 and a doped region pattern 320. The conductive layer 400 is stacked with the semiconductor layer 200 and is located on the side of the semiconductor layer 200 away from the substrate 100. The conductive layer 400 includes a data line 410 and a first electrode 301 and a second electrode 302 of the transistor 300 electrically connected to the doped region pattern 320. The first electrode 301 is electrically connected to the data line 410. The semiconductor layer 200 extends in the same direction as the data line 410 at the overlapping portion. The semiconductor layer 200 includes a first protrusion 210 that is not covered by the data line 410 and protrudes relative to the edge of the data line 410. The first protrusion 210 is disposed at the edge of the data line 410. The distance between the edge of the first protrusion 210 away from the edge of the data line 410 and the edge of the data line 410 is a first dimension S1, which is greater than 0 and less than 3.0 micrometers. By setting the size of the first protrusion protruding from the edge of the semiconductor layer relative to the edge of the data line to be greater than 0 and less than 2 micrometers, this embodiment of the present disclosure helps to reduce the size of the product design margin, improve product performance, and reduce the probability of display defects in the display device.

[0054] For example, a smaller size of the first protrusion protruding from the edge of the semiconductor layer relative to the edge of the data line helps reduce the impact of the first protrusion protruding from the edge of the data line on other structures. Furthermore, by reducing the size of the first protrusion, the probability of it generating charge carriers when illuminated by the backlight can be minimized, thus improving the stability of the display substrate.

[0055] For example, such as Figure 1 As shown, the portion of the semiconductor layer 200 that overlaps with the data line 410 has the same extending direction as the data line 410. This portion of the semiconductor layer is disposed on the same layer as the channel region 310 and the doped region pattern 320 of the transistor 300, but with a different shape.

[0056] For example, Figure 1 The schematic diagram shows that the conductive layer 400 within the area circled by the dashed line is the first electrode 301 of the transistor 300. The first electrode 301 can be electrically connected to the data line 410 through the connection portion 330. For example, the data line 410, the first electrode 301, and the connection portion 330 can be an integrated structure. For example, the first electrode 301 and the second electrode 302 of the transistor 300 are spaced apart, and the semiconductor layer 200 between the first electrode 301 and the second electrode 302 can be a channel region, referred to as the channel region.

[0057] For example, such as Figure 1 and Figure 2As shown, the surface of the conductive layer 400 is in contact with the surface of the semiconductor layer 200.

[0058] For example, such as Figure 1 and Figure 2 As shown, at least a portion of the data line 410 is projected onto the substrate 100 in the same direction as the semiconductor layer 200 on the substrate 100. For example, the extension direction of the overlapping portion of the semiconductor layer 200 and the data line 410 can both be the Y direction as shown in the figure.

[0059] For example, such as Figure 1 As shown, the channel region 310 and the doped region pattern 320 of the transistor 300 can be an integrated structure. For example, the doped region pattern 320 may include a source region and a drain region, with one of the first electrode 301 and the second electrode 302 electrically connected to the source region, and the other of the first electrode 301 and the second electrode 302 electrically connected to the drain region. For example, the doped region pattern 320 may be covered by the first electrode 301 and the second electrode 302, thus increasing the ohmic contact between the doped region pattern and the first and second electrodes. In this embodiment, the source region and the drain region of the transistor may be structurally identical, so their source and drain regions may be structurally indistinguishable and therefore interchangeable as needed.

[0060] For example, such as Figure 1 and Figure 2 As shown, the semiconductor layer 200 overlapping with the data line 410 includes a middle portion covered by the data line 410 and an edge portion not covered by the data line 410. The edge portion not covered by the data line 410 includes a first protrusion 210. For example, the first protrusion 210 is located outside the edge of the data line 410.

[0061] For example, such as Figure 1 and Figure 2 As shown, there can be multiple data lines 410, each extending along the Y direction, and the multiple data lines 410 are arranged along the X direction. The first protrusion 210 may include a portion located on at least one side of the data line 410 in the X direction, or it may include a portion located on at least one side of the data line 410 in the Y direction. For example, the first protrusion 210 may include portions located on both sides of the data line 410 in the X direction, and these two portions may have the same or different widths in the X direction. For example, the first protrusion 210 may include portions located on both sides of the data line 410 in the Y direction, and these two portions may have the same or different widths in the Y direction. The X direction and Y direction described above can be interchanged.

[0062] For example, such as Figure 1 and Figure 2As shown, the first protrusion 210 can extend along the Y direction, and the width of the first protrusion 210 in the X direction can be a first dimension S1. For example, the first protrusion 210 can extend along the X direction, and the width of the first protrusion 210 can be a first dimension S1.

[0063] For example, the first size S1 can be 0.5 to 3 micrometers. For example, the first size S1 can be 1 to 2 micrometers. For example, the first size S1 is not greater than 1.8 micrometers. For example, the first size S1 is not greater than 1.6 micrometers. For example, the first size S1 is not greater than 1.4 micrometers. For example, the first size S1 is not greater than 1.3 micrometers.

[0064] Figure 3 For along Figure 1 The diagram shows a partial cross-sectional structure intercepted by line BB'. For example, as shown... Figures 1 to 3 As shown, the portion of the edge of the channel region 310 that protrudes relative to the edge of the first electrode 301 of the transistor 300 is a second protrusion 220. The second protrusion 220 is disposed at the edge of the first electrode 301, and the distance between the edge of the second protrusion 220 away from the first electrode 301 and the edge of the first electrode 301 is a second dimension S2, which is larger than the first dimension S1. In this embodiment, by setting the size of the first protrusion protruding relative to the edge of the data line to be smaller than the size of the second protrusion protruding relative to the edge of the first electrode of the transistor, the size of the first protrusion at the edge of the data line can be minimized without affecting the normal operation of the transistor. This helps to reduce the size of the product design edge, solve the problems of water ripples and afterimages caused by the long first protrusion, and thus improve product performance. The semiconductor layer of the transistor is covered by the gate (described later), which can block the light from the backlight from affecting the semiconductor layer at the transistor position. However, the semiconductor layer overlapping with the data line is not blocked by the film layer where the gate is located and is easily illuminated by the light from the backlight, which affects the electrical performance of the semiconductor layer. In the display substrate provided in this embodiment, setting the size of the first protrusion to be smaller than the size of the second protrusion does not change the morphology of the semiconductor layer in the transistor, but reduces the length of the semiconductor layer under the data line relative to the protruding part of the data line, thereby reducing the impact of backlight on the semiconductor layer.

[0065] For example, such as Figures 1 to 3 As shown, the orthographic projection of the first electrode 301 of the transistor 300 onto the substrate 100 falls completely within the orthographic projection of the semiconductor layer 200 onto the substrate 100.

[0066] For example, such as Figures 1 to 3As shown, the planar shape of the first electrode 301 of the transistor 300 includes a U-shape, and the planar shape of the second electrode 302 of the transistor 300 includes an elongated shape inserted into the opening of the U-shape, with the second protrusion 220 surrounding the periphery of the U-shape. For example, the second dimension S2 of the second protrusion 220 can be the dimension of the second protrusion 220 in a direction parallel to the width of the first electrode 301.

[0067] For example, such as Figures 1 to 3 As shown, the semiconductor layer 200 overlapping with the first electrode 301 of the transistor 300 includes a portion covered by the first electrode 301 and two portions not covered by the first electrode 301. The two portions not covered by the first electrode 301 include a portion located inside the first electrode 301 and a portion located outside the first electrode 301. The second protrusion 220 is the portion of the semiconductor layer 200 not covered by the first electrode 301 located outside the first electrode 301.

[0068] For example, such as Figures 1 to 3 As shown, the second protrusion 220 includes a portion located at least one edge of the first electrode 301 of the transistor 300. For example, the second protrusion 220 may include two portions located at the two edges of the first electrode 301 of the transistor 300, and the widths of these two portions may be the same or different.

[0069] For example, such as Figures 1 to 3 As shown, the second dimension S2 is greater than 3 micrometers. For example, the second dimension S2 is greater than 2 micrometers. For example, the second dimension S2 is 2 to 2.6 micrometers. For example, the second dimension S2 is 3 to 5 micrometers.

[0070] For example, such as Figure 1 and Figure 2 As shown, the first protrusion 210 includes a first step 211 and a second step 212 stacked together. The first step 211 is located between the second step 212 and the substrate 100. The distance between the edge of the first step 211 and the edge of the data line 410 is the first step size, i.e., the first size S1. The distance between the edge of the second step 212 and the edge of the data line 410 is the second step size S11. The first step size is larger than the second step size S11.

[0071] For example, such as Figure 2 As shown, the ratio of the first step dimension to the second step dimension ranges from 2 to 25. For example, the ratio ranges from 3 to 20. For example, the ratio ranges from 5 to 15. For example, the ratio ranges from 8 to 12.

[0072] For example, such as Figure 1 and Figure 2As shown, the first step 211 and the second step 212 can be an integrated structure. For example, the material of the first step 211 may include amorphous silicon (a-Si), and the material of the second step 212 may include doped amorphous silicon. For example, the second step 212 may be N-type doped amorphous silicon (N+a-Si), or it may be doped with phosphorus. Doping with amorphous silicon can effectively reduce the contact resistance between the amorphous silicon (a-Si) and the film layer containing the data line, forming a good ohmic contact.

[0073] For example, such as Figure 2 As shown, along a direction perpendicular to the main surface of the substrate 100 (also referred to as the direction perpendicular to the substrate 100), such as the Z direction, the thickness of the first step 211 is greater than the thickness of the second step 212.

[0074] For example, such as Figure 2 As shown, the sidewall of the first step 211 away from the data line 410 can be an inclined sidewall, and the sidewall of the second step 212 away from the data line 410 can also be an inclined sidewall. The angles of the sidewalls of the first step 211 and the second step 212 relative to the main surface (the surface perpendicular to the Z direction) of the substrate 100 are different. The first step includes a surface that is substantially parallel to the substrate and a surface that has a certain angle with the substrate. The sidewall of the first step can refer to the surface of the first step that has a certain angle with the substrate. The second step includes a surface that is substantially parallel to the substrate and a surface that has a certain angle with the substrate. The sidewall of the second step can refer to the surface of the second step that has a certain angle with the substrate.

[0075] For example, such as Figure 2 As shown, the angle between the sidewall of the first step 211 and the substrate 100 is greater than the angle between the sidewall of the second step 212 and the substrate 100. However, it is not limited to this; the angle between the sidewall of the first step 211 and the substrate 100 may also be smaller than the angle between the sidewall of the second step 212 and the substrate 100.

[0076] For example, such as Figure 2As shown, the angle between the sidewall of the first step 211 and the substrate 100 can be 40–60 degrees, and the angle between the sidewall of the second step 212 and the substrate 100 can be 20–40 degrees. For example, the angle between the sidewall of the first step 211 and the substrate 100 can be 45–55 degrees, and the angle between the sidewall of the second step 212 and the substrate 100 can be 30–38 degrees. For example, the angle between the sidewall of the first step 211 and the substrate 100 can be 50–52 degrees, and the angle between the sidewall of the second step 212 and the substrate 100 can be 35–37 degrees.

[0077] For example, such as Figure 2 As shown, the data line 410 includes at least one conductive layer. The cross-section of the data line 410, when cut parallel to the XZ plane, can be trapezoidal, and the sides of the trapezoid can be lines formed by cutting the sidewalls of the data line 410 parallel to the XZ plane. For example, the angle between the sidewall of the data line 410 and the surface of the second step 212 away from the substrate 100 ranges from 30 to 80 degrees. For example, the angle between the sidewall of the data line 410 and the surface of the second step 212 away from the substrate 100 ranges from 40 to 70 degrees. For example, the angle between the sidewall of the data line 410 and the surface of the second step 212 away from the substrate 100 ranges from 50 to 60 degrees.

[0078] For example, such as Figure 2 As shown, the data line 410 includes a first metal layer 411, a second metal layer 412, and a third metal layer 413 sequentially stacked along a direction perpendicular to the substrate 100. The first metal layer 411 is located between the second metal layer 412 and the substrate 100, and the material of the first metal layer 411 is the same as that of the third metal layer 413, while the materials of the first metal layer 411 and the second metal layer 412 are different. For example, the materials of the first metal layer 411 and the third metal layer 413 can both be molybdenum, and the material of the second metal layer 412 can be aluminum. This embodiment is not limited to this; the data line can also be made of metals such as copper.

[0079] For example, such as Figure 2 As shown, the thickness of the first metal layer 411 and the thickness of the third metal layer 413 are both less than the thickness of the second metal layer 412. For example, the thickness of the third metal layer 413 is greater than the thickness of the first metal layer 411. For example, the thickness of the data line 410 is 2000–6000 angstroms.

[0080] For example, such as Figure 2 As shown, the thickness of the semiconductor layer 200 is less than the thickness of the conductive layer 400. For example, the thickness of the semiconductor layer 200 can be 1000 to 5000 angstroms. For example, the thickness of the semiconductor layer 200 can be 1000 to 2000 angstroms.

[0081] For example, such as Figure 3 As shown, the second protrusion 220 includes a third step 221 and a fourth step 222 stacked together. The third step 221 is located between the fourth step 222 and the substrate 100. The distance between the edge of the third step 221 and the edge of the first electrode 301 of the transistor 300 is the third step size, i.e., the second size S2. The distance between the edge of the fourth step 222 and the edge of the first electrode 301 is the fourth step size S21. The fourth step size S21 is smaller than the third step size.

[0082] For example, such as Figure 1 and Figure 3 As shown, the third step 221 and the fourth step 222 can be an integrated structure. For example, the material of the third step 221 may include amorphous silicon (a-Si), and the material of the fourth step 222 may include doped amorphous silicon. For example, the fourth step 222 can be N-type doped amorphous silicon (N+a-Si), or it may be doped with phosphorus. Doping with amorphous silicon can effectively reduce the contact resistance between the amorphous silicon (a-Si) and the film layer containing the data line, forming a good ohmic contact.

[0083] For example, such as Figure 3 As shown, along a direction perpendicular to the substrate 100, such as the Z direction, the thickness of the third step 221 is greater than the thickness of the fourth step 222.

[0084] For example, such as Figures 1 to 3 As shown, the first step 211 and the third step 221 can be made of the same material, and the second step 212 and the fourth step 222 can be made of the same material. For example, the first step 211 and the third step 221 can have the same thickness, and the second step 212 and the fourth step 222 can have the same thickness.

[0085] For example, such as Figures 1 to 3 As shown, the size of the first step is smaller than the size of the third step.

[0086] For example, the first step size can be 0.5–2 micrometers. For example, the first step size is no greater than 1.8 micrometers. For example, the first step size is no greater than 1.6 micrometers. For example, the first step size is no greater than 1.4 micrometers. For example, the first step size is no greater than 1.3 micrometers. For example, the first step size is no greater than 1.3 micrometers. For example, the first step size is greater than 0.5 micrometers. For example, the first step size is greater than 1 micrometer. For example, the third step size is greater than 2 micrometers. For example, the third step size is 2–2.6 micrometers. For example, the third step size is 3–4 micrometers.

[0087] For example, such as Figures 1 to 3As shown, the ratio of the first step dimension to the second step dimension S11 is less than the ratio of the third step dimension to the fourth step dimension S21.

[0088] For example, such as Figures 1 to 3 As shown, the ratio of the second step size S11 to the fourth step size S21 is 0.8 to 1.2. For example, the ratio of the second step size S11 to the fourth step size S21 is 0.9 to 1.1. For example, the second step size S11 and the fourth step size S21 are the same. For example, the second step size S11 and the fourth step size S21 can be 0.1 to 0.5 micrometers.

[0089] This embodiment of the present disclosure sets the second step size in the first protrusion and the fourth step size in the second protrusion to be the same, and sets the first step size in the first protrusion to be smaller than the third step size in the second protrusion. This can reduce the size of the semiconductor layer at the edge of the data line without affecting the contact area between the doped amorphous silicon material and the conductive layer, thereby reducing the impact of the semiconductor layer protruding relative to the edge of the data line on product performance.

[0090] For example, such as Figure 1 As shown, the connection portion 330, configured to connect the data line 410 and the first electrode 301 of the transistor 300, is also stacked with the semiconductor layer 200. The extension direction of the overlapping portion of the semiconductor layer 200 and the connection portion 330 is the same as the extension direction of the connection portion 330. This portion of the semiconductor layer includes a protrusion 240 that is not covered by the connection portion 330 and protrudes relative to the edge of the connection portion 330. The protrusion 240 is disposed on at least one side edge of the connection portion 330. The distance between the edge of the protrusion 240 away from the connection portion 330 and the edge of the connection portion 330 can be the same as the first dimension of the first protrusion 210, so as to minimize the impact of the semiconductor layer protruding relative to the edge of the connection portion on the product performance.

[0091] For example, such as Figure 1 and Figure 3 As shown, the transistor 300 also includes a gate 303, which is located between the semiconductor layer 200 and the substrate 100. The orthographic projection of the second protrusion 220 on the substrate 100 lies within the orthographic projection of the film layer containing the gate 303 on the substrate 100. For example, the gate 303 may overlap with one of the first electrode 301 and the second electrode 302 of the transistor 300 to form a storage capacitor.

[0092] For example, such as Figure 2 and Figure 3 As shown, the display substrate also includes a gate insulating layer 101 located between the semiconductor layer 200 and the substrate 100, and on the side of the gate 303 away from the substrate 100. For example, the thickness of the gate insulating layer 101 can be 2500 to 4000 angstroms.

[0093] Figure 4 This is a partial planar structure schematic diagram of a display substrate provided according to an example of an embodiment of the present disclosure. Figure 1 for Figure 4 The image shown is an enlarged view of a portion C of the display substrate. For example, as... Figures 1 to 4 As shown, the display substrate includes a plurality of sub-pixels 10, each sub-pixel 10 including a pixel electrode 11, which is located on the side of the conductive layer 400 away from the substrate 100. The second electrode 302 of the transistor 300 is electrically connected to the pixel electrode 11. For example, the pixel electrode 11 can be made of indium tin oxide. For example, the thickness of the pixel electrode 11 can be 400 to 1100 angstroms. For example, a passivation layer can also be disposed between the pixel electrode 11 and the second electrode 302 of the transistor 300, and the thickness of the passivation layer can be 1000 to 6000 angstroms.

[0094] For example, the display substrate may also include a common electrode. For example, the common electrode may be located on the side of the pixel electrode away from the substrate, and multiple sub-pixels may share the common electrode. For example, the common electrode may be located between the pixel electrode and the substrate. For example, one of the pixel electrode and the common electrode may be a plate-shaped electrode, and the other may be a slit electrode. For example, the common electrode may be disposed on the same layer as the pixel electrode. For example, the display substrate may be an array substrate, and the common electrode may be disposed on a counter substrate disposed opposite to the display substrate. The embodiments of this disclosure do not limit the positional relationship or shape of the common electrode and the pixel electrode, and can be configured according to product requirements.

[0095] For example, such as Figure 1 As shown, the semiconductor layer 200 further includes a third protrusion 230 that overlaps with the second electrode 302 of the transistor 300 and protrudes relative to the edge of the second electrode 302. The third protrusion 230 surrounds at least a portion of the edge of the second electrode 302. The minimum distance between the edge of the third protrusion 230 away from the edge of the second electrode 302 and the edge of the second electrode 302 is a third dimension, which is larger than the first dimension. For example, the third dimension can be equal to the second dimension. Of course, the embodiments of this disclosure are not limited to the third dimension being larger than the first dimension; the third dimension can also be equal to the first dimension. For example, in the embodiments of this disclosure, there is an overlap between the extended portion of the second electrode 302 of the transistor and the gate line 500 in the direction perpendicular to the substrate, that is, there is also an overlap between the semiconductor layer corresponding to this portion and the gate line. The existing overlapping portion forms a storage capacitor, which is beneficial to improving the display effect.

[0096] For example, such as Figure 1As shown, the second electrode 302 of the transistor 300 includes a portion extending into the U-shaped opening of the first electrode 301 of the transistor 300 and another portion configured to be electrically connected to the pixel electrode 11. For example, the other portion of the second electrode 302 of the transistor 300 configured to be electrically connected to the pixel electrode 11 is stacked with the semiconductor layer 200, and the edge of this portion of the semiconductor layer 200 protrudes relative to the edge of the second electrode 302 to form a third protrusion 230.

[0097] For example, along a direction perpendicular to the substrate 100, a portion of the second electrode 302 of the transistor 300 overlaps with the film layer containing the gate 303. For example, along a direction perpendicular to the substrate 100, a portion of the second electrode 302 of the transistor 300 overlaps with the doped region pattern 320 of the semiconductor layer 200, and another portion of the second electrode 302 overlaps with a portion of the semiconductor layer 200 excluding the channel region 310 and the doped region pattern 320.

[0098] For example, such as Figure 1 and Figure 4 As shown, the display substrate also includes a gate line 500, which is disposed on the same layer as the gate 303 of the transistor 300 and is electrically connected to the gate 303. For example, the gate 303 may be integrally disposed with the gate line 500 which is electrically connected to it.

[0099] For example, such as Figure 1 and Figure 4 As shown, the display substrate includes a plurality of sub-pixels 10 arranged in an array along the row and column directions. The embodiment of this disclosure schematically shows the X direction as the row direction and the Y direction as the column direction, but is not limited thereto, and the row and column directions can be interchanged.

[0100] For example, such as Figure 4 As shown, two adjacent sub-pixel columns form a sub-pixel column group 010. The display substrate includes multiple sub-pixel column groups 010 arranged along the row direction, and each sub-pixel column group 010 includes two adjacent sub-pixel columns.

[0101] For example, the multiple sub-pixels 10 may include multiple sub-pixels that emit different colors of light. For example, the multiple sub-pixels 10 may include multiple red sub-pixels that emit red light, multiple green sub-pixels that emit green light, and multiple blue sub-pixels that emit blue light. The red sub-pixels, green sub-pixels, and blue sub-pixels may be arranged in a row-wise repeating pattern. The sub-pixels arranged in the column-wise pattern may be sub-pixels that emit the same color of light, but are not limited to this. The sub-pixels arranged in the column-wise pattern may also be red sub-pixels, green sub-pixels, and blue sub-pixels arranged in a row-wise repeating pattern.

[0102] For example, such as Figure 1 and Figure 4As shown, data lines 410 extend along the column direction, and gate lines 500 extend along the row direction. The term "data lines 410 extending along the column direction" can mean that the overall extension direction of each data line 410 is along the column direction; each data line 410 can be a straight line extending along the column direction or a broken line extending along the column direction. Similarly, the term "gate lines 500 extending along the row direction" can mean that the overall extension direction of each gate line 500 is along the row direction; each gate line 500 can be a straight line extending along the row direction or a broken line extending along the row direction.

[0103] For example, such as Figure 1 and Figure 4 As shown, the gate line 500 includes multiple first sub-gate lines 510 and multiple second sub-gate lines 520. For example, the multiple first sub-gate lines 510 and multiple second sub-gate lines 520 are arranged alternately along the column direction.

[0104] For example, such as Figure 4 As shown, the data line 410 is located between two adjacent sub-pixel column groups 010, and the two columns of sub-pixels in the sub-pixel column group 010 are electrically connected to the same data line 410.

[0105] For example, such as Figure 4 As shown, the sub-pixel column group 010 includes multiple rows of sub-pixel lines. Along the column direction, a first sub-gate line 510 and a second sub-gate line 520 are respectively disposed on both sides of each sub-pixel row, and adjacent sub-pixel rows include a gate line pair composed of the first sub-gate line 510 and the second sub-gate line 520. An example of an embodiment of this disclosure provides a display substrate that can employ dual-gate technology. Dual-gate technology is a driving technology that reduces the number of data lines in a display device by half and doubles the number of gate lines. That is, it halves the number of source driver integrated circuits (ICs) connected to the data lines and doubles the number of gate driver integrated circuits connected to the gate lines. Since the unit price of the gate driver integrated circuit is cheaper than that of the source driver integrated circuit, cost reduction is achieved.

[0106] For example, such as Figure 4 As shown, sub-pixel 10 also includes a common electrode, and the display substrate also includes a common electrode line 600 connected to the common electrode. The common electrode line 600 can be zigzag-shaped. In the cell alignment process of a liquid crystal display device, the zigzag-shaped common electrode line can guide the rotation of the liquid crystal during the liquid crystal rubbing process. For example, spacers can be correspondingly provided at the wider positions on the common electrode line 600.

[0107] Figure 5 This is a schematic diagram of a partial planar structure of a display substrate provided according to another example of an embodiment of the present disclosure. For example, Figure 5 The display substrate in the example shown is Figures 1 to 4 The difference in the display substrate shown in the example is that the positional relationship between the first electrode 301 of the transistor 300 and the data line 410 is different. Only one gate line is set between adjacent sub-pixel rows, and a data line is set between any adjacent sub-pixel columns. The dual gate line technology is not used. Figure 5 The first protrusion 210 of the semiconductor layer 200 protruding relative to the edge of the data line 410, the second protrusion 220 of the semiconductor layer 200 protruding relative to the edge of the first electrode 301, the data line 410, the gate line 500, and the pixel electrode 11 in the display substrate shown can be connected to... Figure 1 The first protrusion 210, the second protrusion 220, the data line 410, the gate line 500, and the pixel electrode 11 in the display substrate shown may have the same features, and will not be described in detail here.

[0108] For example, such as Figure 5 As shown, the first electrode 301 of transistor 300 and data line 410 can be an integrated structure, without employing... Figure 1 The connecting part 330 shown is electrically connected.

[0109] For example, the display substrate provided in this embodiment can be an array substrate.

[0110] For example, another embodiment of this disclosure provides a display device that includes the display substrate provided in any of the above examples.

[0111] For example, the display device may also include a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

[0112] For example, the display device can be a liquid crystal display device, or any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the liquid crystal display device. This embodiment is not limited to this.

[0113] Another embodiment of this disclosure provides a forming Figures 1 to 4 The method for manufacturing the display substrate shown. Figures 6A to 6C To make along Figure 1 A schematic diagram illustrating the method of constructing a partial cross-sectional structure of the display substrate as shown by the DD' line. (See diagram for reference.) Figure 1 , Figures 6A to 6C As shown, the method for fabricating a display substrate includes providing a substrate 100; forming a semiconductor material layer 20 on the substrate 100; forming a conductive material layer 40 on the side of the semiconductor material layer 20 away from the substrate 100; and forming an etching mask 800 on the side of the conductive material layer 40 away from the semiconductor material layer 20. Figure 1 , Figures 6A to 6CAs shown, the etching mask 800 includes a first mask portion 810, which includes a first sub-mask portion 811 and a second sub-mask portion 812. The second sub-mask portion 812 is located on at least one side of the first sub-mask portion 811 and is located at the edge of the first mask portion 810 along a direction perpendicular to the substrate 100. The thickness of the first sub-mask portion 811 is greater than the thickness of the second sub-mask portion 812. After forming the etching mask 800, the fabrication method further includes: using the first mask portion 810 as a mask to pattern the conductive material layer 40 and the semiconductor material layer 20 to form a data line 410 and a first semiconductor pattern 23 located between the data line 410 and the substrate 100 (e.g., ...). Figure 17 The first semiconductor pattern 23 shown includes a first protrusion 210 that is not covered by the data line 410 and protrudes relative to the edge of the data line 410. The first protrusion 210 is disposed at the edge of the data line 410, and the distance between the edge of the first protrusion 210 away from the edge of the data line 410 and the edge of the data line 410 is a first dimension S1; the first dimension S1 is greater than 0 and less than 3.0 micrometers. In this embodiment, a first mask portion with a different thickness is used as a mask patterning to form the data line and the first semiconductor pattern overlapping with the data line, which is beneficial to reduce the size of the first protrusion, thereby improving product performance and reducing the probability of display defects in the display device.

[0114] For example, such as Figures 6A to 6C As shown, the first sub-mask portion 811 and the second sub-mask portion 812 are an integrated structure.

[0115] For example, such as Figure 6A As shown, a first mask portion 810 of an etched mask 800 can be formed by patterning a halftone mask (HTM Mask) 910 as a mask.

[0116] For example, the etching mask 800 may include photoresist, and the etching mask layer is directly patterned using a halftone mask process to form a first mask portion 810 with different thicknesses. That is, the first mask portion 810 includes a first sub-mask portion 811 and a second sub-mask portion 812 with different thicknesses. For example, the second sub-mask portion 812 is located on both sides of the first sub-mask portion 811.

[0117] For example, such as Figure 6AAs shown, the halftone mask 910 includes a high-transmittance portion 911, a low-transmittance portion 912, and a light-shielding portion 913. The halftone mask 910 utilizes the characteristic that the transmittance varies at different locations to form a first mask portion 810 with different thicknesses. For example, in one example, an etch mask layer is first formed, and then the etch mask layer is exposed using the halftone mask 910. A fully exposed region 901 is formed at the edge of the etch mask layer where the conductive material layer 40 needs to be exposed, a partially exposed region 902 is formed at the location where the second sub-mask portion 812 needs to be formed, and no exposure is performed in the region 903 where the first sub-mask portion 811 needs to be formed. Then, the exposed etch mask layer is developed to form the first mask portion 810 with different thicknesses. This example is described using a material including a positive photoetchant for the etch mask layer; however, this example is not limited to this, and materials including a negative photoetchant can also be used.

[0118] For example, such as Figure 6B As shown, a first mask portion 810 of an etched mask 800 can be formed by patterning a slit mask (SSM Mask) 920 as a mask.

[0119] For example, the etching mask 800 may include photoresist, and the etching mask layer is directly patterned using a slot mask process to form a first mask portion 810 with different thicknesses. That is, the first mask portion 810 includes a first sub-mask portion 811 and a second sub-mask portion 812 with different thicknesses. For example, the second sub-mask portion 812 is located on both sides of the first sub-mask portion 811.

[0120] Figure 6D include Figure 6B as well as Figure 7B The diagram shows the planar structure of the slit mask. For example, as shown... Figure 6B and Figure 6D As shown, the slit mask 920 includes a light-transmitting portion 921 and a light-blocking portion 922. The light-transmitting portion 921 may include a slit. The slit mask 920 utilizes light diffraction to achieve a lower light transmittance in a portion 904 than in another portion 905. Region 905 can be a partially exposed region. For example, the slits may be located on both sides of the slit mask 920 near the edges to form a partially exposed region near the edges of the slit mask 920.

[0121] For example, in one example, an etch mask layer is first formed, and then the etch mask layer is exposed using a slit mask 920. Fully exposed areas are formed at the edges of the etch mask layer where the conductive material layer 40 needs to be exposed, partially exposed areas 905 are formed where the second sub-mask portion 812 needs to be formed, and no exposure is performed in the area 904 where the first sub-mask portion 811 needs to be formed. Then, the exposed etch mask layer is developed to form a first mask portion 810 with a different thickness. This example is described using a material including a positive photoetchant for the etch mask layer; however, this example is not limited to this, and materials including a negative photoetchant could also be used.

[0122] For example, such as Figure 6B and Figure 6D As shown, the width s1 of the slit included in the slit mask 920 can be 0.8 to 3 micrometers. For example, the width s1 of the slit included in the slit mask 920 can be 1 to 2 micrometers. For example, the width w1 of the light-shielding portion 922 on the side of the slit away from the center of the slit mask 920 can be 0.5 to 3 micrometers. For example, the width w1 of the light-shielding portion 922 on the side of the slit away from the center of the slit mask 920 can be 1 to 2 micrometers.

[0123] For example, Figure 6C The illustration schematically shows a first mask portion 810 of an etch mask 800 patterned using a halftone mask (HTM Mask) 910 as the mask, but is not limited thereto; it can also be patterned using a slot mask (SSM Mask) 920 as the mask. Figure 6C The first mask portion 810 of the etched mask 800 shown. For example, the first mask portion 810, which is patterned using a halftone mask (HTMMask) 910 or a slot mask (SSM Mask) 920, can be formed as shown in the image. Figures 6A-6B The second sub-mask section 812, with its distinct slope, can also be formed as shown. Figure 6C The second sub-mask section 812 has a less pronounced slope. For example, as shown... Figure 6CAs shown, the slope angle of the second sub-mask portion 812 can be 10 to 30 degrees. For example, the slope angle of the second sub-mask portion 812 can be 15 to 25 degrees. The slope angle of the second sub-mask portion 812 can be 18 degrees. The slope angle of the second sub-mask portion 812 can refer to the angle between the tangent at the intersection of the curve intercepted by the XZ surface and the conductive material layer 40 and the X direction. For example, the angle between the tangent at the midpoint of the curve intercepted by the XZ surface and the X direction can be 26 to 46 degrees. For example, the angle between the tangent at the midpoint of the curve intercepted by the XZ surface and the X direction can be 30 to 40 degrees. For example, the angle between the tangent at the midpoint of the curve intercepted by the XZ surface and the X direction can be 36 degrees.

[0124] For example, such as Figures 6A to 6C As shown, the thickness H1 of the first sub-mask portion 811 can be 1.5 to 3.0 micrometers. For example, the thickness H2 of the second sub-mask portion 812 can be 0.2 to 1.5 micrometers.

[0125] For example, such as Figures 6A to 6C As shown, the material of the semiconductor material layer 20 may include amorphous silicon and doped amorphous silicon. For example, the doped amorphous silicon may be located on the side of the amorphous silicon facing the conductive material layer 40. For example, the thickness of the semiconductor material layer 20 may be 1000 to 5000 angstroms. For example, the thickness of the semiconductor material layer 20 may be 1000 to 2000 angstroms.

[0126] For example, such as Figures 6A to 6C As shown, the conductive material layer 40 may include at least one film layer. For example, the material of the conductive material layer 40 may include metallic materials such as molybdenum, aluminum, and copper.

[0127] For example, such as Figures 6A to 6C As shown, before forming the semiconductor material layer 20, a gate metal layer can be deposited on the substrate 100. After performing processes such as exposure and etching on the gate metal layer, a semiconductor material layer can be formed. Figure 1 , Figure 3 and Figure 4 The gate 303 and gate line 500 are shown.

[0128] For example, such as Figures 6A to 6C As shown, after forming the gate 303 and the gate line 500, a gate insulating layer 101 is deposited on the side of the gate line 500 away from the substrate.

[0129] Figures 7A to 7C To make along Figure 1 This is a schematic diagram illustrating a method for depicting a partial cross-sectional structure of the display substrate as shown by the EE' line. For example, as... Figure 1 , Figures 6A to 7CAs shown, the etching mask 800 also includes a second mask portion 820, which includes a third sub-mask portion 821 located at an edge position. Along a direction perpendicular to the substrate 100, the thickness of the third sub-mask portion 821 is the same as the thickness of the first sub-mask portion 811. For example, as... Figure 7A and Figure 7B As shown, the second mask portion 820 has a third sub-mask portion 821 at both sides of its edge. The third sub-mask portion 821 does not have a structure with a thickness less than that of the second mask portion 820 at its edge away from the second mask portion 820.

[0130] For example, such as Figures 7A to 7C As shown, the second mask portion 820 further includes a fourth sub-mask portion 822, the thickness of which is less than the thickness of the third sub-mask portion 821. For example, as Figures 7A to 7C As shown, the second mask portion 820 includes three third sub-mask portions 821 and two fourth sub-mask portions 822, with the third sub-mask portions 821 and the fourth sub-mask portions 822 arranged alternately along the Y direction.

[0131] For example, such as Figures 7A to 7C As shown, the thickness H3 of the third sub-mask portion 821 can be 1.5 to 3.0 micrometers, and the thickness H4 of the fourth sub-mask portion 822 can be 0.2 to 1.5 micrometers.

[0132] For example, such as Figure 1 , Figures 7A to 7C As shown, the first electrode 301 and the second electrode 302 of the transistor 300 can be formed using the third sub-mask portion 821 as a mask, and the channel region of the transistor 300 can be formed using the fourth sub-mask portion 822 as a mask.

[0133] For example, such as Figure 7A As shown, a second mask portion 820 of an etched mask 800 can be formed by patterning a halftone mask (HTM Mask) 930 as a mask.

[0134] For example, the etching mask 800 may include photoresist, and the etching mask layer may be directly patterned using a halftone mask process to form a second mask portion 820 with different thicknesses. That is, the second mask portion 820 includes a third sub-mask portion 821 and a fourth sub-mask portion 822 with different thicknesses.

[0135] For example, such as Figure 7AAs shown, the halftone mask 930 includes a high-transmittance portion 931, a low-transmittance portion 932, and a light-shielding portion 933. The halftone mask 930 utilizes the characteristic that the transmittance varies at different locations to form a second mask portion 820 with different thicknesses. For example, in one example, an etch mask layer is first formed, and then the etch mask layer is exposed using the halftone mask 930. A fully exposed region 901 is formed at the edge of the etch mask layer where the conductive material layer 40 needs to be exposed, a partially exposed region 902 is formed at the location where the fourth sub-mask portion 822 needs to be formed, and no exposure is performed in the region 903 where the third sub-mask portion 821 needs to be formed. Then, the exposed etch mask layer is developed to form the second mask portion 820 with different thicknesses. This example is described using a material including a positive photoetchant for the etch mask layer; however, this example is not limited to this, and materials including a negative photoetchant can also be used.

[0136] For example, such as Figure 7B As shown, a second mask portion 820 of an etched mask 800 can be formed by patterning a slit mask (SSM Mask) 940 as a mask.

[0137] For example, the etching mask 800 may include photoresist, and the etching mask layer may be directly patterned using a halftone mask process to form a second mask portion 820 with different thicknesses. That is, the second mask portion 820 includes a third sub-mask portion 821 and a fourth sub-mask portion 822 with different thicknesses.

[0138] For example, such as Figure 6D and Figure 7B As shown, the slit mask 940 includes a light-transmitting portion 941 and a light-shielding portion 942. The light-transmitting portion 941 may include a slit. The slit mask 940 utilizes light diffraction to achieve a lower light transmittance in a portion of region 904 compared to another portion of region 905. Region 905 can be a partially exposed region, while region 904 can be a non-exposed region. For example, the slit may be located at a non-edge position of the slit mask 940. Larger light-shielding portions 942 are provided in the middle region and the two side edge regions of the slit mask 940 to form non-exposed regions in the middle region and the two side edge regions of the slit mask 940, a partially exposed region in the middle of the two non-exposed regions of the slit mask 940, and a fully exposed region on the side of the non-exposed region located at the edge that is away from the partially exposed region.

[0139] For example, in one example, an etch mask layer is first formed, and then the etch mask layer is exposed using a slit mask 940. Fully exposed areas are formed at the edges of the etch mask layer where the conductive material layer 40 needs to be exposed, partially exposed areas 905 are formed where the fourth sub-mask portion 822 needs to be formed, and areas 904 where the third sub-mask portion 821 needs to be formed are not exposed. Then, the exposed etch mask layer is developed to form a second mask portion 820 with a different thickness. This example is described using a material including a positive photoetchant for the etch mask layer; however, this example is not limited to this, and materials including a negative photoetchant could also be used.

[0140] For example, such as Figure 7B and Figure 6D As shown, the width s2 (e.g., the dimension of the slit along the Y direction) of each slit included in the slit mask 940 can be greater than 3 micrometers. For example, the width s2 of each slit included in the slit mask 940 can be 3 to 6 micrometers. For example, the width s2 of each slit included in the slit mask 940 can be 4.7 to 5.2 micrometers. For example, the width w2 of the larger light-shielding portion 942 located between two adjacent slits can be 1.5 to 3 micrometers. For example, the width w2 of the larger light-shielding portion 942 located between two adjacent slits can be 2.1 to 2.3 micrometers.

[0141] For example, Figure 7C The diagram schematically illustrates the formation of a second mask portion 820 of an etch mask 800 using a halftone mask (HTM Mask) 930 as a mask, but is not limited to this; it can also be patterned using a slot mask (SSM Mask) 940 as a mask. Figure 7C The second mask portion 820 of the etched mask 800 shown. For example, the second mask portion 820, which is patterned using a halftone mask (HTMMask) 930 or a slot mask (SSM Mask) 940, can be formed as shown in the image. Figure 7A-8 The edge intercepted by the YZ plane shown in B is approximately a straight line. The second mask portion 820 can also be formed as shown in... Figure 7C The second mask portion 820 shown is curved, with its edge intercepted by the YZ plane. For example, as... Figure 7C As shown, the slope angle of the curve intercepted by the YZ plane on the second mask portion 820 can be 35 to 55 degrees. For example, the slope angle of the curve intercepted by the YZ plane on the second mask portion 820 can be 40 to 50 degrees. For example, the slope angle of the curve intercepted by the YZ plane on the second mask portion 820 can be 45 degrees. The slope angle of the second mask portion 820 can refer to the angle between the tangent line at the intersection of the curve intercepted by the YZ plane and the conductive material layer 40 and the Y direction.

[0142] Figure 8For another production along Figure 1 A schematic diagram of the method for constructing a partial cross-sectional structure of the display substrate as shown by the EE' line. Figure 8 and Figure 7A and Figure 7C The difference is that the third sub-mask portion 821 in the second mask portion 820 is not located at the edge position, and a fifth sub-mask portion 833 is provided at the edge position of the third sub-mask portion 821. Along the direction perpendicular to the substrate 100, the thickness of the third sub-mask portion 821 is the same as the thickness of the first sub-mask portion 811, and the thickness of the fifth sub-mask portion 833 is the same as the thickness of the second sub-mask portion.

[0143] For example, such as Figure 8 As shown, the thickness H5 of the fifth sub-mask portion 823 can be 0.2 to 1.5 micrometers.

[0144] For example, such as Figure 8 As shown, a halftone mask (HTM Mask) 940 can be used to pattern the second mask portion 820 of the etch mask 800. However, the embodiments disclosed herein are not limited to using a halftone mask for mask patterning. Figure 8 The second mask portion 820 shown can also be patterned using a slit mask. Figure 8 The second mask portion 820 is shown.

[0145] For example, the etching mask 800 may include photoresist, and the etching mask layer may be directly patterned using a halftone mask process to form a second mask portion 820 with different thicknesses. That is, the second mask portion 820 includes a third sub-mask portion 821, a fourth sub-mask portion 822 and a fifth sub-mask portion 823 with different thicknesses.

[0146] For example, such as Figure 8 As shown, the halftone mask 950 includes a high-transmittance portion 951, a low-transmittance portion 952, and a light-shielding portion 953. The halftone mask 950 utilizes the characteristic that the transmittance varies at different locations to form a second mask portion 820 with different thicknesses. For example, in one example, an etch mask layer is first formed, and then the etch mask layer is exposed using the halftone mask 950. A fully exposed region 901 is formed at the edge of the etch mask layer where the conductive material layer 40 needs to be exposed, a partially exposed region 902 is formed at the locations where the fourth sub-mask portion 822 and the fifth sub-mask portion 823 need to be formed, and no exposure is performed in the region 903 where the third sub-mask portion 821 needs to be formed. Then, the exposed etch mask layer is developed to form a second mask portion 820 with different thicknesses. This example is described using a material including a positive photoetchant for the etch mask layer; however, this example is not limited to this, and materials including a negative photoetchant can also be used.

[0147] For example, with adoption Figure 7A The difference between the semiconductor layer at the transistor formed in the second mask portion 820 shown is that: Figure 8 After the second mask portion 820 shown, with Figure 8 The second mask portion 820 shown is a semiconductor layer at a transistor formed by mask patterning, where the second protrusion has the same second dimension as the first protrusion described above. (Using...) Figure 8 The method steps for patterning the second mask portion to form the subsequent structure can be referred to. Figure 10 , Figure 12 , Figure 14 , Figure 16 as well as Figure 18 The structure formed by the corresponding method will not be described in detail here.

[0148] Optional, see Figure 8 In this case, the length of the second protrusion corresponding to the location of the transistor in the semiconductor layer is greater than the length of the first protrusion corresponding to the location of the semiconductor below the data line, i.e., the distance between the edge of the data line layer and the edge of the semiconductor. Optionally, at least one of the locations of the transistor corresponding to the semiconductor layer and the semiconductor below the data line can be configured as follows: Figure 8 The fabrication method shown uses a halftone mask or an SSM mask to create a stepped shape in the mask portion where the semiconductor layer extends beyond the data line layer.

[0149] Figure 9 This is a schematic diagram showing the patterning of a data line using the first mask portion as a mask. Figure 10 This is a schematic diagram of forming transistor source and drain patterns using a second mask portion as a mask. For example, as shown... Figure 6A , Figure 6B as well as Figure 9 As shown, patterning the conductive material layer 40 using the first mask portion 810 as a mask includes etching the conductive material layer 40 using the first mask portion 810 as a mask to form a data line pattern 41. For example, patterning the conductive material layer 40 using the first mask portion 810 as a mask includes wet etching the conductive material layer 40 using the first mask portion 810 as a mask to form the data line pattern 41. For example, wet etching can be isotropic etching (e.g., etching in the X, Y, and Z directions as shown in the figure), and the edge of the conductive material layer 40 is recessed by a certain dimension relative to the edge of the first mask portion 810.

[0150] For example, such as Figure 7A , Figure 7B as well as Figure 10As shown, the conductive material layer 40 is patterned using the second mask portion 820 as a mask to form the transistor source / drain pattern 42. For example, the conductive material layer 40 is etched using the second mask portion 820 as a mask to form the transistor source / drain pattern 42. For example, the conductive material layer 40 is wet-etched using the second mask portion 820 as a mask to form the transistor source / drain pattern 42. For example, the wet etching can be isotropic etching, and the edge of the conductive material layer 40 is recessed by a certain dimension relative to the edge of the second mask portion 820.

[0151] For example, such as Figure 9 and Figure 10 As shown, the data line pattern 41 and the transistor source-drain pattern 42 are formed by simultaneous etching.

[0152] Figure 11 This is a schematic diagram of patterning a semiconductor material layer to form a first semiconductor pattern layer using a first mask portion as a mask. Figure 12 This is a schematic diagram illustrating the patterning of a semiconductor material layer to form a second semiconductor pattern layer using a second mask portion as a mask. For example, as... Figure 9 and Figure 11 As shown, after forming the data line pattern 41, the semiconductor material layer 20 is etched using the first mask portion 810 as a mask to form the first semiconductor pattern layer 21. For example, as... Figure 9 and Figure 11 As shown, patterning the semiconductor material layer 20 using the first mask portion 810 as a mask includes: dry etching the semiconductor material layer 20 using the first mask portion 810 as a mask so that the edges of the first mask portion 810 and the edges of the semiconductor material layer 20 are etched simultaneously. For example, dry etching can be anisotropic etching (e.g., etching is mainly performed in the Z direction as shown in the figure, while the etching rate in other lateral directions such as the X direction is smaller), and while the edges of the semiconductor material layer 20 are etched using the dry etching process, the edges of the first mask portion 810 are also etched simultaneously.

[0153] For example, such as Figure 9 and Figure 11 As shown, while the semiconductor material layer 20 is etched using a dry etching process, the thinner second sub-mask portion 812 is simultaneously etched. Compared to an etching mask that does not include a first sub-mask portion and a second sub-mask portion of different thicknesses, this embodiment employs an etching mask with a thinner second sub-mask portion at its edge. This allows for a larger etching amount on the thinner second sub-mask portion located at the edge of the etching mask while the semiconductor material layer is etched using a dry etching process. This results in a larger edge size of the semiconductor material layer etched away using the second sub-mask portion as a mask, thereby providing a process basis for the subsequent formation of a first semiconductor pattern with a smaller first protrusion.

[0154] For example, such as Figure 11As shown, the edge position of the first semiconductor pattern layer 21 can be approximately the edge position of the first protrusion (Act tail) in the subsequently formed first semiconductor pattern. Therefore, the etching mask of the second sub-mask portion with a smaller edge thickness will affect the size of the first protrusion.

[0155] For example, compared to the process of first ashing the first mask portion and then etching the semiconductor material layer to form the first semiconductor pattern layer, the method of simultaneously etching the semiconductor material layer and the first mask portion using a dry etching process in the embodiments of this disclosure not only provides a process basis for the subsequent formation of the first semiconductor pattern with a smaller first protrusion, but also saves a step of ashing process.

[0156] For example, such as Figure 9 and Figure 11 As shown, while the semiconductor material layer 20 is etched using a dry etching process, the first sub-mask portion 811, which has a larger thickness, is also etched simultaneously.

[0157] For example, such as Figure 9 and Figure 11 As shown, the first mask portion 810 is obtained by simultaneously etching the semiconductor material layer 20 using a dry etching process. For example, the thickness of the etched first mask portion 810' at each location is smaller than that of the first mask portion 810 (…). Figure 11 The thickness at the corresponding position (shown by the dashed line).

[0158] For example, such as Figure 11 As shown, while etching to form the first semiconductor pattern layer 21, a portion of the thickness of material is also etched away from the edge of the gate insulating layer 101 on the side away from the substrate 100.

[0159] For example, such as Figure 10 and Figure 12 As shown, patterning the semiconductor material layer 20 using the second mask portion 820 as a mask includes: after forming the transistor source-drain pattern 42, etching the semiconductor material layer 20 using the second mask portion 820 as a mask to form a second semiconductor pattern layer 22. For example, patterning the semiconductor material layer 20 using the second mask portion 820 as a mask includes: dry etching the semiconductor material layer 20 using the second mask portion 820 as a mask so that the edges of the second mask portion 820 and the edges of the semiconductor material layer 20 are etched simultaneously.

[0160] For example, such as Figure 10 and Figure 12 As shown, the second mask portion 820 is etched simultaneously with the semiconductor material layer 20 using a dry etching process to obtain the etched second mask portion 820'. For example, the thickness of the etched second mask portion 820' at each location is smaller than that of the second mask portion 820 (…). Figure 12The thickness at the corresponding position (shown by the dashed line).

[0161] For example, such as Figure 11 and Figure 12 As shown, the first semiconductor pattern layer 21 and the second semiconductor pattern layer 22 are formed by simultaneous etching. For example, the first mask portion 810 and the second mask portion 820 are simultaneously etched to form the etched first mask portion 810' and the etched second mask portion 820', respectively.

[0162] Figure 13 This is a schematic diagram showing the ashing process after etching the first mask portion. Figure 14 This is a schematic diagram showing the ashing process after etching the second mask portion. For example, as shown... Figures 9 to 14 As shown, after etching the semiconductor material layer 20 using the first mask portion 810 and the second mask portion 820 as masks to form the first semiconductor pattern layer 21 and the second semiconductor pattern layer 22, the fabrication method further includes simultaneously performing an ashing process on the first mask portion 810 and the second mask portion 820. For example, the first mask portion 810 (such as...) Figure 13 The ashing process (shown in the dashed box) includes ashing the etched first mask portion 810' to form the ashing first mask portion 810'. For example, for the second mask portion 820 (as shown in the dashed box), the ashing process includes ashing the etched first mask portion 810' to form the ashing first mask portion 810'. Figure 14 (As shown in the dashed box) The ashing process includes ashing the etched second mask portion 820' to form the ashing second mask portion 820.

[0163] For example, the slope angle of the edge of the ashing first mask portion 810” can be 35 to 55 degrees. For example, the slope angle of the edge of the ashing first mask portion 810” can be 45 degrees. For example, the slope angle of the edge of the ashing second mask portion 820” can be 60 to 80 degrees. For example, the slope angle of the edge of the ashing second mask portion 820” can be 70 degrees.

[0164] For example, such as Figures 9 to 14 As shown, in the direction perpendicular to the substrate 100, the thickness of the ashing first mask portion 810” is less than the thickness of the unashed first sub-mask portion 811. For example, the thickness of the ashing first mask portion 810” is less than the thickness of the etched first sub-mask portion.

[0165] For example, such as Figure 13 As shown, the edge of the ashing first mask portion 810” obtained after ashing treatment of the etched first mask portion can be flush with the edge of the data line pattern 41.

[0166] For example, such as Figure 14As shown, the edge of the ashed first mask portion 820” obtained after ashing the etched second mask portion can be flush with the edge of the transistor source-drain pattern 42.

[0167] For example, such as Figures 9 to 14 As shown, in the direction perpendicular to the substrate 100, the thickness of the ashing second mask portion 820” is less than the thickness of the unashed third sub-mask portion 830. For example, the thickness of the ashing first mask portion 810” is less than the thickness of the etched third sub-mask portion.

[0168] For example, such as Figure 14 As shown, the ashing second mask portion 820" includes a plurality of sub-mask portions spaced apart, the spacing between adjacent sub-mask portions being configured to expose the channel region of the transistor, and each sub-mask portion being configured to block one of the first and second poles of the transistor.

[0169] Figure 15 This is a schematic diagram showing the data line pattern etched using the first ashing mask as a mask. Figure 16 This is a schematic diagram showing the etching of the transistor source and drain patterns using the ashing second mask as a mask. For example, as... Figure 13 and Figure 15 As shown, after simultaneously performing ashing treatment on the first mask portion and the second mask portion, the manufacturing method further includes: etching the data line pattern 41 using the ashing first mask portion 810” as a mask to form the data line 410. For example, etching the data line pattern 41 using the ashing first mask portion 810” as a mask to form the data line 410 includes: performing wet etching on the data line pattern 41 using the ashing first mask portion 810” as a mask to form the data line 410, wherein the edge of the data line 410 is recessed by a certain dimension relative to the edge of the ashing first mask portion 810”.

[0170] For example, such as Figures 13 to 16 As shown, while etching the data line pattern 41 to form the data line 410, the fabrication method also includes etching the transistor source and drain patterns 42 using the ashing second mask portion 820” as a mask to form the first electrode 301 and the second electrode 302 of the transistor. For example, the first electrode 301 and the second electrode 302 of the transistor can be formed by wet etching, and the edges of the first electrode 301 and the second electrode 302 are both recessed by a certain dimension relative to the edge of the ashing second mask portion 820”.

[0171] For example, such as Figure 16 As shown, the first electrode 301 and the second electrode 302 are spaced apart. For example, the gap between the first electrode 301 and the second electrode 302 is configured to expose a portion of the second semiconductor pattern layer 22.

[0172] Figure 17This is a schematic diagram showing the etching of the first semiconductor pattern layer using the ashing first mask portion as a mask. Figure 18 This is a schematic diagram showing the etching of the second semiconductor pattern layer using the ashing second mask portion as a mask. For example, as... Figure 15 and Figure 17 As shown, after the data line 410 is formed, the material of a portion of the thickness away from the substrate 10 at the edge of the first semiconductor pattern layer 21 is etched away using the ashing first mask portion 810” as a mask to form the first semiconductor pattern 23.

[0173] For example, such as Figure 2 and Figure 17 As shown, the first semiconductor pattern 23 includes a first step 211 and a second step 212. The first step 211 is located between the second step 212 and the substrate 100, and the distance between the edge of the first step 211 and the edge of the data line 410 is the first step dimension S1, and the distance between the edge of the second step 212 and the edge of the data line 410 is the second step dimension S11. The ratio of the first step dimension S1 to the second step dimension S11 is in the range of 2-25. For example, the ratio of the first step dimension to the second step dimension is in the range of 3-20. For example, the ratio of the first step dimension to the second step dimension is in the range of 5-15. For example, the ratio of the first step dimension to the second step dimension is in the range of 8-12.

[0174] For example, the first step 211 and the second step 212 can be an integrated structure. For example, the material of the first step 211 includes amorphous silicon (a-Si), and the material of the second step 212 includes doped amorphous silicon. For example, the second step 212 can be N-type doped amorphous silicon (N+a-Si), and the material of the second step 212 can be doped with phosphorus.

[0175] For example, the material of the portion of the first semiconductor patterned layer 21 that is etched away includes at least doped amorphous silicon. Alternatively, the material of the portion of the first semiconductor patterned layer 21 that is etched away may also include amorphous silicon.

[0176] For example, such as Figure 3 , Figures 7A-7B , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18As shown, after forming the etching mask, the fabrication method further includes: using the second mask portion 820 as a mask to pattern the conductive material layer 40 and the semiconductor material layer 20 to form the first electrode 301 and the second electrode 302 of the transistor 300, and a second semiconductor pattern 24 located between the first electrode 301 and the second electrode 302 of the transistor 300 and the substrate 100. For example, the second semiconductor pattern 24 includes the channel region 310 and the doped region pattern 320 of the transistor 300. The protruding portion of the edge of the second semiconductor pattern 24 relative to the edge of the first electrode 301 (such as the edge of the first electrode 301 away from the second electrode 302) is a second protrusion 220. The first electrode 301 and the second electrode 302 are both electrically connected to the doped region pattern 320. The first electrode 301 is electrically connected to the data line 410. The minimum distance between the edge of the second protrusion 220 away from the first electrode 301 and the edge of the first electrode 301 is a second dimension, which is larger than the first dimension. In this embodiment of the disclosure, by setting the size of the first protrusion protruding from the edge of the first semiconductor pattern relative to the edge of the data line to be smaller than the size of the second protrusion protruding from the edge of the second semiconductor pattern relative to the edge of the first electrode of the transistor, the size of the first protrusion at the edge of the data line can be reduced without affecting the normal operation of the transistor. This helps to solve the defects such as water ripples and afterimages caused by the long first protrusion, thereby improving product performance.

[0177] For example, such as Figure 3 and Figure 18 As shown, the second protrusion 220 includes a third step 221 and a fourth step 222 stacked together. The third step 221 is located between the fourth step 222 and the substrate 100. The distance between the edge of the third step 221 and the edge of the first electrode 301 of the transistor 300 is the third step size, i.e., the second size S2. The distance between the edge of the fourth step 222 and the edge of the first electrode 301 is the fourth step size S21. The fourth step size S21 is smaller than the third step size.

[0178] For example, such as Figure 1 and Figure 3 As shown, the third step 221 and the fourth step 222 can be an integrated structure. For example, the material of the third step 221 includes amorphous silicon (a-Si), and the material of the fourth step 222 includes doped amorphous silicon. For example, the fourth step 222 can be N-type doped amorphous silicon (N+a-Si), and the material of the fourth step 222 can be doped with phosphorus.

[0179] For example, the material of the etched portion in the second semiconductor pattern layer 22 may include at least doped amorphous silicon. Alternatively, the material of the etched portion in the second semiconductor pattern layer 22 may also include amorphous silicon.

[0180] Compared to directly forming a first mask portion without a second sub-mask portion, the display substrate fabrication method provided in this disclosure forms a first mask portion with a second sub-mask portion by using a halftone mask or a slit mask. This reduces the size of the first protrusion of the subsequently formed first semiconductor pattern without requiring additional masking processes, thus saving costs. Subsequently, the smaller first protrusion (ActTail) formed under two wet etching and two dry etching (2W2D) processes generates fewer photogenerated carriers under backlight illumination, which is beneficial for improving product performance.

[0181] In this embodiment, the etch mask edge for forming the semiconductor layer overlapping with the data line includes a second sub-mask portion with a smaller thickness (or the etch mask edge has a smaller slope angle), while the etch mask edge for forming the semiconductor layer at the transistor location does not include the sub-mask portion with a smaller thickness (or the etch mask edge has a larger slope angle). Therefore, the size of the second protrusion of the semiconductor layer at the transistor location protruding relative to the conductive layer is larger than the size of the first protrusion of the semiconductor layer overlapping with the data line protruding relative to the data line. The semiconductor layer of the transistor is covered by a gate, which can block the backlight from affecting the semiconductor layer at the transistor location. However, the semiconductor layer overlapping the data line is not blocked by the gate film layer and is easily illuminated by the backlight, affecting the electrical performance of the semiconductor layer. In the display substrate provided in this embodiment, setting the size of the first protrusion smaller than the size of the second protrusion does not change the morphology of the semiconductor layer in the transistor, but reduces the length of the semiconductor layer protruding relative to the data line, thereby reducing the impact of backlight on the semiconductor layer.

[0182] For example, such as Figure 16 and Figure 18 As shown, after forming the first semiconductor pattern 23 and the second semiconductor pattern 24, the fabrication method further includes removing the ashing etch mask to expose the data line 410 and the first electrode 301 and the second electrode 302 of the transistor.

[0183] For example, after removing the etch mask, a passivation layer is formed on the side of the film layer where the data line 410 is located away from the substrate 100. For example, after forming the passivation layer, the fabrication method further includes forming a pixel electrode on the side of the passivation layer away from the substrate.

[0184] The following points need to be explained:

[0185] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0186] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0187] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display device, comprising: Substrate; A semiconductor layer is located on the substrate, the semiconductor layer including a channel region and a doped region pattern of a transistor; A conductive layer is stacked on top of the semiconductor layer and located on the side of the semiconductor layer away from the substrate. The conductive layer includes data lines and a first electrode and a second electrode of the transistor electrically connected to the doped region pattern. The first electrode is electrically connected to the data lines. Wherein, the semiconductor layer and the data line overlap in the same direction as the data line. The semiconductor layer includes a first protrusion that is not covered by the data line and protrudes relative to the edge of the data line. The first protrusion is disposed at the edge of the data line. The distance between the edge of the first protrusion away from the data line and the edge of the data line is a first dimension, which is greater than 0 and less than 3.0 micrometers. The portion of the edge of the semiconductor layer that protrudes relative to the edge of the first electrode is a second protrusion. The second protrusion is disposed at the edge of the first electrode. The distance between the edge of the second protrusion away from the first electrode and the edge of the first electrode is a second dimension, which is greater than the first dimension. The display device further includes a plurality of sub-pixels, each sub-pixel including a pixel electrode, the pixel electrode being located on the side of the conductive layer away from the substrate, and the second electrode being electrically connected to the pixel electrode; Each sub-pixel also includes a common electrode, and the display device also includes a common electrode line connected to the common electrode. The common electrode line is in the form of a broken line, and a spacer is provided at the position where the width of the common electrode line is larger.

2. The display device according to claim 1, wherein, The first protrusion includes a first step and a second step stacked together. The first step is located between the second step and the substrate. The distance between the edge of the first step and the edge of the data line is the first step size, and the distance between the edge of the second step and the edge of the data line is the second step size. The ratio of the first step size to the second step size is in the range of 2-25.

3. The display device according to claim 2, wherein, The material of the first step includes amorphous silicon, and the material of the second step includes doped amorphous silicon.

4. The display device according to claim 2, wherein, The data line includes at least one conductive layer, and the angle between the sidewall of the data line and the surface of the second step away from the substrate ranges from 30 to 80 degrees.

5. The display device according to claim 2, wherein, The second protrusion includes a third step and a fourth step stacked together. The third step is located between the fourth step and the substrate. The distance between the edge of the third step and the edge of the first electrode is the third step size, and the distance between the edge of the fourth step and the edge of the first electrode is the fourth step size. The size of the first step is smaller than the size of the third step.

6. The display device according to claim 5, wherein, The material of the third step includes amorphous silicon, and the material of the fourth step includes doped amorphous silicon.

7. The display device according to claim 5, wherein, The ratio of the first step size to the second step size is less than the ratio of the third step size to the fourth step size.

8. The display device according to any one of claims 5-7, wherein, The ratio of the second step size to the fourth step size is 0.8 to 1.

2.

9. The display device according to any one of claims 1-7, wherein, The transistor further includes a gate located between the semiconductor layer and the substrate, and the orthographic projection of the second protrusion on the substrate is located within the orthographic projection of the film layer containing the gate on the substrate.

10. The display device according to claim 9, wherein, The semiconductor layer further includes a third protrusion that overlaps with the second electrode and protrudes relative to the edge of the second electrode, the third protrusion surrounding at least a portion of the edge of the second electrode, the minimum interval between the edge of the third protrusion away from the second electrode and the edge of the second electrode being a third dimension, the third dimension being larger than the first dimension.

11. The display device according to claim 10, further comprising: A gate line, wherein the gate line is disposed on the same layer as the gate and is electrically connected to the gate. The multiple sub-pixels are arranged in an array along the row and column directions, and two adjacent columns of sub-pixels form a sub-pixel column group. The data line extends along the column direction, the gate line extends along the row direction, and the gate line includes multiple first sub-gate lines and multiple second sub-gate lines; The data line is located between two adjacent sub-pixel columns, and the two columns of sub-pixels in the sub-pixel column are electrically connected to the same data line. The sub-pixel column group includes multiple sub-pixel rows, and along the column direction, the first sub-gate line and the second sub-gate line are respectively provided on both sides of each sub-pixel row, and adjacent sub-pixel rows include a gate line pair composed of the first sub-gate line and the second sub-gate line.

12. A method for manufacturing a display substrate, comprising: Provide substrates; A semiconductor material layer is formed on the substrate. A conductive material layer is formed on the side of the semiconductor material layer away from the substrate. as well as An etching mask is formed on the side of the conductive material layer away from the semiconductor material layer. The etching mask includes a first mask portion, which further includes a first sub-mask portion and a second sub-mask portion. The second sub-mask portion is located on at least one side of the first sub-mask portion and at the edge of the first mask portion along a direction perpendicular to the substrate. The thickness of the first sub-mask portion is greater than the thickness of the second sub-mask portion. After forming the etching mask, the fabrication method further includes: Using the first mask portion as a mask, the conductive material layer and the semiconductor material layer are patterned to form a data line and a first semiconductor pattern located between the data line and the substrate. The first semiconductor pattern includes a first protrusion that is not covered by the data line and protrudes relative to the edge of the data line. The first protrusion is disposed at the edge of the data line, and the dimension between the edge of the first protrusion away from the edge of the data line and the edge of the data line is a first dimension. The first dimension is greater than 0 and less than 3.0 micrometers. Patterning the conductive material layer and the semiconductor material layer using the first mask as a mask includes: The conductive material layer is etched using the first mask portion as a mask to form a data line pattern; After the data line pattern is formed, the semiconductor material layer is etched using the first mask portion as a mask to form the first semiconductor pattern layer; Patterning the conductive material layer and the semiconductor material layer using the first mask as a mask includes: The conductive material layer is wet-etched using the first mask as a mask to form the data line pattern, and the semiconductor material layer is dry-etched using the first mask as a mask so that the edges of the first mask and the edges of the semiconductor material layer are etched simultaneously. The etching mask further includes a second mask portion, which includes a third sub-mask portion located at the edge along a direction perpendicular to the substrate. The thickness of the third sub-mask portion is the same as the thickness of the first sub-mask portion. After forming the etching mask, the fabrication method further includes: Using the second mask portion as a mask, the conductive material layer and the semiconductor material layer are patterned to form a first electrode and a second electrode of a transistor, as well as a second semiconductor pattern located between the first electrode and the second electrode of the transistor and the substrate. The second semiconductor pattern includes a channel region and a doped region pattern of the transistor. A protruding portion of the edge of the second semiconductor pattern that protrudes relative to the edge of the first electrode is a second protrusion. Both the first electrode and the second electrode are electrically connected to the doped region pattern. The first electrode is electrically connected to the data line. The minimum distance between the edge of the second protrusion away from the edge of the first electrode and the edge of the first electrode is a second dimension, which is larger than the first dimension.

13. The manufacturing method according to claim 12, wherein, Patterning the conductive material layer and the semiconductor material layer using the second mask portion as a mask includes: Using the second mask portion as a mask, the conductive material layer is etched to form a transistor source and drain pattern; After forming the transistor source-drain pattern, the semiconductor material layer is etched using the second mask portion as a mask to form a second semiconductor pattern layer.

14. The manufacturing method according to claim 13, wherein, After etching the semiconductor material layer using the first mask portion and the second mask portion as masks to form the first semiconductor pattern layer and the second semiconductor pattern layer, the fabrication method further includes: Both the first mask portion and the second mask portion are simultaneously subjected to ashing treatment. In the direction perpendicular to the substrate, the thickness of the ashing first mask portion is less than the thickness of the unashed first sub-mask portion.

15. The manufacturing method according to claim 14, wherein, After simultaneously performing ashing treatment on the first mask portion and the second mask portion, the manufacturing method further includes: The data line pattern is etched using the ashing first mask portion as a mask to form the data line; After the data lines are formed, the edges of the first semiconductor pattern layer are etched using the ashing first mask as a mask to form a first-level step and a second-level step. The first semiconductor pattern includes a first-level step and a second-level step. The first-level step is located between the second-level step and the substrate. The distance between the edge of the first-level step and the edge of the data line is the first step size, and the distance between the edge of the second-level step and the edge of the data line is the second step size. The ratio of the first step size to the second step size is in the range of 2-25.

16. The manufacturing method according to claim 12, wherein, The first mask portion in the etched mask is formed using a halftone mask or a slot mask.

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