Dynamic cross-coupled regeneration for high-speed sense amplifiers

Abstract

The regeneration circuit includes a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, wherein a gate of the first transistor is configured to receive a first input signal, and a second transistor coupled to the input of the first inverter circuit, wherein a gate of the second transistor is configured to receive a second input signal. The regeneration circuit further includes a first switch coupled between the first transistor and the output of the first inverter circuit, wherein a control input of the first switch is configured to receive a timing signal, and a second switch coupled between the second transistor and the output of the second inverter circuit, wherein a control input of the second switch is configured to receive the timing signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional application serial number 17 / 321,005 filed on May 14, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if their entire contents and all applicable purposes were fully set forth below. Technical Field

[0003] This disclosure relates generally to amplifiers, and more specifically to sensing amplifiers. Background Technology

[0004] Sensing amplifiers are used in a wide range of applications, including memory, analog-to-digital converters, and data samplers in high-speed serializers / deserializers (SerDes). In the case of data samplers, the sensing amplifier may include regenerative circuitry that provides regenerative feedback to the sensing amplifier to quickly resolve incoming data bits from the data sampler. Increasing the regenerative gain of the regenerative circuitry is desirable to increase the speed and sensitivity of the sensing amplifier. Summary of the Invention

[0005] The following is a simplified summary of one or more embodiments to provide a basic understanding of these embodiments. This invention is not a broad overview of all contemplated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that follows.

[0006] A first aspect relates to a regenerative circuit. The regenerative circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regenerative circuit also includes a first transistor coupled to an input of the second inverting circuit, wherein the gate of the first transistor is configured to receive a first input signal, and the regenerative circuit also includes a second transistor coupled to an input of the first inverting circuit, wherein the gate of the second transistor is configured to receive a second input signal. The regenerative circuit also includes a first switch coupled between the first transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal, and the regenerative circuit also includes a second switch coupled between the second transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.

[0007] The second aspect relates to a sensing amplifier. The sensing amplifier includes an input circuit and a regeneration circuit. The input circuit includes a first transistor, wherein the gate of the first transistor is configured to receive a first input signal, and the drain of the first transistor is coupled to a first output of the input circuit. The input circuit also includes a second transistor, wherein the gate of the second transistor is configured to receive a second input signal, and the drain of the second transistor is coupled to a second output of the input circuit. The regeneration circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regeneration circuit further includes a third transistor coupled to the input of the second inverting circuit, wherein the gate of the third transistor is coupled to the second output of the input circuit. The regeneration circuit also includes a fourth transistor coupled to the input of the first inverting circuit, wherein the gate of the fourth transistor is coupled to the first output of the input circuit. The regeneration circuit further includes a first switch coupled between the third transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal. The regeneration circuit also includes a second switch coupled between the fourth transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.

[0008] A third aspect relates to a method for operating a regenerative circuit of a sensing amplifier. The regenerative circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The method includes: during a reset phase, decoupling the output of the first inverting circuit from the first transistor, and decoupling the output of the second inverting circuit from the second transistor. The method further includes: during a sensing phase, coupling the output of the first inverting circuit to the first transistor, and coupling the output of the second inverting circuit to the second transistor. Attached Figure Description

[0009] Figure 1 An example of a sense amplifier including input circuitry and regeneration circuitry according to certain aspects of this disclosure is shown.

[0010] Figure 2 An exemplary embodiment of a switch in a regenerative circuit according to certain aspects of this disclosure is shown.

[0011] Figure 3 The timing diagram is based on certain aspects of this disclosure and shows an example of the voltage output from the input circuit to the regenerative circuit.

[0012] Figure 4 The timing diagrams are based on certain aspects of this disclosure and illustrate an example of the output voltage of the regenerative circuit during the sensing and decision phases.

[0013] Figure 5An example of a regeneration circuit according to certain aspects of this disclosure is shown.

[0014] Figure 6A An exemplary embodiment of a switch in a regenerative circuit according to certain aspects of this disclosure is shown.

[0015] Figure 6B Another exemplary embodiment of a switch in a regenerative circuit according to certain aspects of this disclosure is shown.

[0016] Figure 7A An exemplary embodiment of an inverting circuit in a regenerative circuit according to certain aspects of this disclosure is shown.

[0017] Figure 7B An exemplary embodiment of a switch in an inverting circuit according to certain aspects of this disclosure is shown.

[0018] Figure 7C Indicates a device that is turned off in a regenerative circuit during a reset phase, according to certain aspects of this disclosure.

[0019] Figure 8 An example of a regenerative circuit including a pull-up transistor is shown according to certain aspects of this disclosure.

[0020] Figure 9 An exemplary embodiment of a switch in an input circuit according to certain aspects of this disclosure is shown.

[0021] Figure 10 Examples of systems in which aspects of this disclosure may be used, according to certain aspects of this disclosure, are shown.

[0022] Figure 11 This is a flowchart illustrating an exemplary method for operating a regenerative circuit of a sense amplifier according to certain aspects of this disclosure. Detailed Implementation

[0023] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configuration in which the concepts described herein can be practiced. The specific embodiments include particular details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these particular details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0024] Figure 1An example of a sense amplifier 110 according to certain aspects of this disclosure is shown. For example, the sense amplifier 110 can be used in a data sampler to sample and parse incoming data bits. The sense amplifier 110 includes input circuitry 115 and regeneration circuitry 140. Input circuitry 115 may also be referred to as an input stage, and regeneration circuitry 140 may also be referred to as a regeneration stage.

[0025] Input circuit 115 includes a first input transistor 120, a second input transistor 122, a first switch 116, a second switch 130, and a third switch 134. The second switch 130 is coupled between power supply rail 112 and the first input transistor 120, and the third switch 134 is coupled between power supply rail 112 and the second input transistor 122. The first input transistor 120 is coupled between the second switch 130 and node 117, and the second input transistor 122 is coupled between the third switch 134 and node 117. The first switch 116 is coupled between node 117 and ground 114.

[0026] exist Figure 1 In the example shown, the first input transistor 120 is implemented using a first n-type field-effect transistor (NFET), and the second input transistor 122 is implemented using a second NFET. In this example, a second switch 130 is coupled between the power supply rail 112 and the drain of the first input transistor 120, and a first switch 116 is coupled between the source of the first input transistor 120 and ground 114. Furthermore, a third switch 134 is coupled between the power supply rail 112 and the drain of the second input transistor 122, and a first switch 116 is coupled between the source of the second input transistor 122 and ground 114. It should be understood that the first input transistor 120 and the second input transistor 122 are not limited to NFETs and can be implemented using other types of transistors.

[0027] Input circuit 115 is configured to receive a differential input signal (e.g., a differential data signal) comprising a first input voltage (labeled "INP") and a second input voltage (labeled "INN"). The first input voltage INP is input to a first input 121 of input circuit 115, and the second input voltage INN is input to a second input 123 of input circuit 115, wherein the first input 121 is coupled to the gate of a first input transistor 120, and the second input 123 is coupled to the gate of a second input transistor 122. The differential input signal may have a small differential voltage (i.e., a small difference between the first input voltage INP and the second input voltage INN), wherein the polarity of the differential voltage represents the bit value. As discussed further below, sense amplifier 110 is configured to convert the small differential input voltage into a large differential output voltage to resolve the bit value.

[0028] The first switch 116 has a control input 118 driven by a first timing signal, the second switch 130 has a control input 132 driven by the first timing signal, and the third switch 134 has a control input 136 driven by the first timing signal. In one example, the first switch 116 is configured to be on when the first timing signal is high and off when the first timing signal is low, and each of the second switch 130 and the third switch 134 is configured to be on when the first timing signal is low and off when the first timing signal is high. Figure 1 In the example shown, the first timing signal is a clock signal (labeled "CLK"). As used herein, a "clock signal" is a periodic signal that oscillates between high and low logic states. In some respects, a high logic state (i.e., logic state 1) may correspond to a voltage approximately equal to the supply voltage VCC, and a low logic state (i.e., logic state 0) may correspond to a voltage approximately equal to ground.

[0029] As used herein, a switch's "control input" is an input that controls the switch's on / off state based on a signal (e.g., the voltage of the signal) at the control input. In the example of implementing a switch using a transistor, the control input is located at the transistor's gate.

[0030] Input circuit 115 has a first output 124 located at the node between the second switch 130 and the first input transistor 120, and a second output 126 located at the node between the third switch 134 and the second input transistor 122. As discussed further below, the voltage at the first output 124 (labeled "DINT") and the voltage at the second output 126 (labeled "NDINT") are output to regenerative circuit 140. Figure 1 In the example, the first output 124 is coupled to the drain of the first input transistor 120, and the second output 126 is coupled to the drain of the second input transistor 122.

[0031] The regenerative circuit 140 includes a first input transistor 142, a second input transistor 146, a switch 180, a first inverting circuit 150, and a second inverting circuit 160. As discussed further below, the first inverting circuit 150 and the second inverting circuit 160 are cross-coupled to provide regenerative feedback. As used herein, an "inverting circuit" is a circuit configured to invert the logic state (i.e., logic level or logic value) at the input of the inverting circuit and output the inverted logic state at the output of the inverting circuit. The logic state can be represented by a voltage, wherein a low voltage (e.g., close to ground) can represent logic state 0, and a high voltage (e.g., close to the supply voltage) can represent logic state 1. In some aspects, the inverting circuit has a threshold voltage, wherein when the voltage at the input of the inverting circuit drops below the threshold voltage, the output of the inverting circuit changes from low to high, and when the voltage at the input of the inverting circuit rises above the threshold voltage, the output of the inverting circuit changes from high to low. An inverting circuit may also be referred to as an inverter, an inverting circuit, or another term.

[0032] The regeneration circuit 140 has a first input 144 coupled to a second output 126 of the input circuit 115, and a second input 148 coupled to the first output 124 of the input circuit 115. Therefore, the first input 144 receives a voltage NDINT from the input circuit 115, and the second input 148 receives a voltage DINT from the input circuit 115. At this point, the voltage NDINT can be considered as a first input signal to the regeneration circuit 140, and the voltage DINT can be considered as a second input signal to the regeneration circuit 140.

[0033] The first inverter circuit 150 has an input 152, an output 154, a first power supply terminal 156, and a second power supply terminal 158. The second inverter circuit 160 has an input 162, an output 164, a first power supply terminal 166, and a second power supply terminal 168. To cross-couple the first inverter circuit 150 and the second inverter circuit 160, the input 152 of the first inverter circuit 150 is coupled to the output 164 of the second inverter circuit 160, and the input 162 of the second inverter circuit 160 is coupled to the output 154 of the first inverter circuit 150. This cross-coupling provides regeneration feedback to the regeneration circuit 140. The regeneration feedback allows the regeneration circuit 140 to perform regeneration to quickly resolve the value of the data bits, as discussed further below.

[0034] The first power supply terminal 156 of the first inverter circuit 150 and the first power supply terminal 166 of the second inverter circuit 160 are coupled to power supply node 185. The second power supply terminal 158 of the first inverter circuit 150 and the second power supply terminal 168 of the second inverter circuit 160 are coupled to ground 114. In this example, the first output 170 of the regeneration circuit 140 is coupled to the output 164 of the second inverter circuit 160, and the second output 175 of the regeneration circuit 140 is coupled to the output 154 of the first inverter circuit 150.

[0035] The first input transistor 142 is coupled between the output 154 of the first inverter circuit 150 and ground 114. The gate of the first input transistor 142 is coupled to the first input 144 of the regeneration circuit 140. Therefore, the gate of the first input transistor 142 is configured to receive a voltage NDINT (i.e., the first input signal to the regeneration circuit 140). In one example, the first input transistor 142 is configured to turn on when the voltage NDINT is higher than a threshold voltage of the first input transistor 142, and turn off when the voltage NDINT is lower than the threshold voltage of the first input transistor 142. Figure 1 In the example shown, the first input transistor 142 is implemented using an NFET, wherein the drain of the first input transistor 142 is coupled to the output 154 of the first inverting circuit 150, and the source of the first input transistor 142 is coupled to ground 114. However, it should be understood that the first input transistor 142 can be implemented using another type of transistor.

[0036] The second input transistor 146 is coupled between the output 164 of the second inverter circuit 160 and ground 114. The gate of the second input transistor 146 is coupled to the second input 148 of the regeneration circuit 140. Therefore, the gate of the second input transistor 146 is configured to receive a voltage DINT (i.e., the second input signal to the regeneration circuit 140). In one example, the second input transistor 146 is configured to turn on when the voltage DINT is higher than a threshold voltage of the second input transistor 146, and turn off when the voltage DINT is lower than the threshold voltage of the second input transistor 146. Figure 1 In the example shown, the second input transistor 146 is implemented using an NFET, wherein the drain of the second input transistor 146 is coupled to the output 164 of the second inverter circuit 160, and the source of the second input transistor 146 is coupled to ground 114. However, it should be understood that the second input transistor 146 can be implemented using another type of transistor.

[0037] Switch 180 is coupled between power rail 112 and power node 185. Switch 180 has a control input 182 driven by a second timing signal. In one example, the second timing signal is a complement to the first timing signal. For an example where the first timing signal is a clock signal CLK, the second timing signal can be a complementary clock signal (labeled "CLKb"), which can be generated by inverting the clock signal CLK using an inverting circuit (not shown). In one example, switch 180 is configured to be turned on when the second timing signal is low (e.g., the first timing signal is high) and turned off when the second timing signal is high (e.g., the first timing signal is low).

[0038] Figure 2 An example is shown in which a switch 180 is implemented using a PFET 210, wherein the source of the PFET 210 is coupled to a power rail 112, the gate of the PFET 210 is coupled to a control input 182, and the drain of the PFET 210 is coupled to a power node 185.

[0039] Exemplary operation of the sensing amplifier 110 will now be discussed in some respects.

[0040] When the first timing signal (e.g., clock signal CLK) is low, the sense amplifier 110 is in a reset phase. During the reset phase, the first switch 116 in the input circuit 115 is turned off. As a result, the first switch 116 decouples the first input transistor 120 and the second input transistor 122 from ground 114. The second switch 130 and the third switch 134 are turned on. As a result, the second switch 130 couples the first output 124 to the power rail 112, and the third switch 134 couples the second output 126 to the power rail 112. This pulls the first output 124 up to VCC (i.e., the power supply voltage on the power rail 112), and pulls the second output 126 up to VCC. Therefore, the voltage NDINT at the gate of the first input transistor 142 input to the regeneration circuit 140 and the voltage DINT at the gate of the second input transistor 146 input to the regeneration circuit 140 are both pulled up to VCC.

[0041] During the reset phase, switch 180 in regeneration circuit 140 is turned off because the second timing signal is complementary to the first timing signal and therefore high when the first timing signal is low. As a result, switch 180 decouples the first power supply terminal 156 of the first inverter circuit 150 from the power supply rail 112 and decouples the first power supply terminal 166 of the second inverter circuit 160 from the power supply rail 112. This disables current flow from the power supply rail 112 to the first power supply terminals 156 and 166 of the inverter circuits 150 and 160.

[0042] During the reset phase, both the first input transistor 142 and the second input transistor 146 of the regeneration circuit 140 are turned on because both voltages DINT and NDINT are pulled up to the power supply voltage VCC (assuming VCC is greater than the threshold voltage of the first input transistor 142 and the threshold voltage of the second input transistor 146). As a result, the first input transistor 142 pulls the output 154 of the first inverter circuit 150 to ground and the input 162 of the second inverter circuit 160 to ground, and the second input transistor 146 pulls the output 164 of the second inverter circuit 160 to ground and the input 152 of the first inverter circuit 150 to ground.

[0043] When the first timing signal (e.g., clock signal CLK) transitions from low to high, the sense amplifier 110 enters the sensing phase, during which the input circuit 115 senses the differential input signal (e.g., differential data signal) at inputs 121 and 123 of the input circuit 115. Figure 3 An example of voltages DINT and NDINT during the sensing phase is shown when the input voltage INP is higher than the input voltage INN (which can represent a bit value of 1). In this example, the first timing signal (e.g., the clock signal CLK) transitions from low to high at time T1. Furthermore, in this example, the first input transistor 142 and the second input transistor 146 have the same threshold voltage 310, which... Figure 3 It is shown in the middle.

[0044] At time Tl, the first switch 116 is turned on, and the second switch 130 and the third switch 134 are turned off. This allows the first input transistor 120 to pull down the voltage DINT at the first output 124 based on the input voltage INP driving the first input transistor 120, and allows the second input transistor 122 to pull down the voltage NDINT at the second output 126 based on the input voltage INN driving the second input transistor 122. In this example, the voltage DINT at the first output 124 is pulled down at a faster rate than the voltage NDINT at the second output 126. This is because, in this example, the first input transistor 120 is driven by a higher voltage than the second input transistor 122 (i.e., INP > INN).

[0045] At time T2, the voltage DINT drops below the threshold voltage 310, which turns off the second input transistor 146 of the regeneration circuit 140. The first input transistor 142 of the regeneration circuit 140 remains on at time T2 because the voltage NDINT is still above the threshold voltage at time T2. At time T2, the regeneration circuit 140 transitions from the sensing phase to the decision phase, in which the turn-off of the second input transistor 146 triggers regeneration feedback in the regeneration circuit 140, which is provided by the cross-coupling of inverting circuits 150 and 160, as discussed above. In this example, the regeneration feedback pulls up the first output 170 and pulls down the second output 175. Figure 4 The diagram illustrates an example of this situation. Figure 4 An example is shown of the output voltage OUTP at the first output 170 and the output voltage OUTN at the second output 175. For example... Figure 4 As shown, the regenerative feedback pulls up the first output 170 and pulls down the second output 175, which produces a large differential output voltage at outputs 170 and 175 of the regenerative circuit 140. This large differential output voltage represents the resolved bit value. In this example, the output voltage OUTP is higher than the output voltage OUTN, which can indicate that the bit decision is 1.

[0046] At time T3, the first timing signal transitions from high to low, causing the sense amplifier 110 to return to the reset phase, and each of the output voltages OUTP and OUTN returns to a reset voltage of approximately zero volts (i.e., ground). Just before time T3, latches (not shown) coupled to outputs 170 and 175 of the regeneration circuit 140 can latch the resolved bit value. The latches may include set-reset (SR) latches or another type of latch.

[0047] The sensing and decision phases were discussed above for the case where the input voltage INP is higher than the input voltage INN. When the input voltage INN is higher than the input voltage INP, during the sensing phase, the voltage NDINT at the second output 126 of the input circuit 115 drops below the threshold voltage 310 before the voltage DINT at the first output 124 of the input circuit 115, causing the first input transistor 142 to be turned off before the second input transistor 146. When this occurs, the sensing amplifier 110 transitions from the sensing phase to the decision phase, in which the turn-off of the first input transistor 142 triggers the regenerative feedback of the regenerative circuit 140. As described above, the regenerative feedback is provided by the cross-coupling of the inverting circuits 150 and 160. In this case, the regenerative feedback pulls up the second output 175 and pulls down the first output 170, resulting in a large differential output voltage where the output voltage OUTN is higher than the output voltage OUTP, which can indicate a bit decision of 0.

[0048] In the example above, the first switch 116 is turned on, the second switch 130 and the third switch 134 are turned off, and switch 180 is turned on during the sensing and decision phases. When one of the voltages DINT and NDINT drops below the threshold voltage 310 of the input transistors 142 and 146 (which triggers the regenerative feedback of the regenerative circuit 140 to resolve the bit value (i.e., make a bit decision)), the sensing amplifier 110 enters the decision phase, as discussed above.

[0049] When the first power supply terminals 156 and 166 of the inverter circuits 150 and 160 are coupled to the power supply rail 112 via switch 180, the cross-coupling of the inverter circuits 150 and 160 provides regenerative gain. During the sensing phase, the inverter circuits 150 and 160 can draw a large current from the power supply rail 112 via switch 180, resulting in a large current-resistive (IR) voltage drop across switch 180. This large IR voltage drop reduces the supply voltage (denoted as "Vp") at the first power supply terminals 156 and 166 of the inverter circuits 150 and 160. Figure 4 The diagram illustrates an example of this situation. Figure 4 An example is shown of the power supply voltage VCC at power supply rail 112 and the power supply voltage Vp at power supply node 185, which is coupled to the first power supply terminals 156 and 166 of the inverting circuits 150 and 160. Figure 4 As shown, at the start of the decision phase at time T2, the supply voltage Vp at power supply node 185 may be significantly lower than the supply voltage VCC at power supply rail 112 (e.g., more than 30% lower) due to the IR voltage drop across switch 180. This lower supply voltage Vp can significantly reduce the regeneration gain provided by the cross-coupled inverting circuits 150 and 160, which significantly slows down the bit decision process that the regeneration circuit 140 can perform and reduces the sensitivity of the sense amplifier 110.

[0050] To address the aforementioned problems, this disclosure provides a regenerative circuit including a first switch coupled between a first input transistor 142 and the output 154 of a first inverter circuit 150, and a second switch coupled between a second input transistor 146 and the output 164 of a second inverter circuit 160. As discussed further below, the first and second switches increase the regenerative gain of the cross-coupled inverter circuits 150 and 160 during the decision phase by eliminating the need for switch 180, and thus eliminating the reduction in power supply voltage at the first power supply terminals 156 and 166 of the inverter circuits 150 and 160 caused by the IR voltage drop across switch 180. Furthermore, the first switch is located outside the current path between the input 162 of the second inverter circuit 160 and the first input transistor 142, and the second switch is located outside the current path between the input 152 of the first inverter circuit 150 and the second input transistor 146. As discussed further below, this feature significantly reduces the current flowing through the first and second switches during the sensing and decision phases, which significantly reduces the performance degradation of the regeneration circuit 140 caused by the presence of the first and second switches.

[0051] Figure 5 An example of a regeneration circuit 140 according to certain aspects of this disclosure is shown. The regeneration circuit 140 can be coupled to... Figure 1 The exemplary input circuit 115 is shown. The regeneration circuit 140 includes the first inverter circuit 150, the second inverter circuit 160, the first input transistor 142, and the second input transistor 146 described above.

[0052] The input 162 of the second inverter circuit 160 is coupled to the first input transistor 142, and the input 152 of the first inverter circuit 150 is coupled to the second input transistor 146. In some aspects, the input 162 of the second inverter circuit 160 is directly coupled to the first input transistor 142 via a first metal wiring 530, and the input 152 of the first inverter circuit 150 is directly coupled to the second input transistor 146 via a second metal wiring 535. The first metal wiring 530 and the second metal wiring 535 may each include one or more metal layers on a chip, and one or more metal interconnect structures (e.g., vias) coupling the one or more metal layers. As used herein, the term "direct coupling" refers to coupling between two devices without intermediate devices (e.g., switches).

[0053] In the example where the first input transistor 142 is implemented using an NFET, the drain of the first input transistor 142 is coupled (e.g., directly coupled via the first metal wiring 530) to the input 162 of the second inverting circuit 160, the gate of the first input transistor 142 is coupled to the first input 144 of the regeneration circuit 140, and the source of the first input transistor 142 is coupled to ground 114. In the example where the second input transistor 146 is implemented using an NFET, the drain of the second input transistor 146 is coupled (e.g., directly coupled via the second metal wiring 535) to the input 152 of the first inverting circuit 150, the gate of the second input transistor 146 is coupled to the second input 148 of the regeneration circuit 140, and the source of the second input transistor 146 is coupled to ground 114. However, it should be understood that the first input transistor 142 and the second input transistor 146 are not limited to this example, and each of the first input transistor 142 and the second input transistor 146 may be implemented using a PFET or another type of transistor.

[0054] In this example, the first power supply terminal 156 of the first inverter circuit 150 and the first power supply terminal 166 of the second inverter circuit 160 are coupled to the power supply rail 112. In some aspects, the first power supply terminal 156 of the first inverter circuit 150 and the first power supply terminal 166 of the second inverter circuit 160 are directly coupled (e.g., via metal wiring) to the power supply rail 112, wherein Figure 1 and Figure 2 The switch 180 shown is omitted. (With) Figure 1 and Figure 2 Compared to the regenerative circuit 140, the direct coupling significantly increases the power supply voltages at the first power supply terminals 156 and 166 of the inverting circuits 150 and 160 by eliminating the reduction in power supply voltage at the first power supply terminals 156 and 166 of the inverting circuits 150 and 160 caused by the IR voltage drop across the switch 180. The second power supply terminal 158 of the first inverting circuit 150 and the second power supply terminal 168 of the second inverting circuit 160 are coupled to ground 114.

[0055] The regeneration circuit 140 also includes a first switch 510 and a second switch 520. The first switch 510 is coupled between the first input transistor 142 and the output 154 of the first inverting circuit 150, and the second switch 520 is coupled between the second input transistor 146 and the output 164 of the second inverting circuit 160. For the example where each of the input transistors 142 and 146 is implemented using an NFET, the first switch 510 is coupled between the drain of the first input transistor 142 and the output 154 of the first inverting circuit 150, and the second switch 520 is coupled between the drain of the second input transistor 146 and the output 164 of the second inverting circuit 160.

[0056] exist Figure 5 In the example, the first switch 510 has a control input 515 driven by a timing signal (e.g., a clock signal CLK), and the second switch 520 has a control input 525 driven by a timing signal. This timing signal can be used for control... Figure 1 The timing signals for switches 116, 130, and 134 in the exemplary input circuit 115 shown are the same, or may be different timing signals. In some aspects, the first switch 510 and the second switch 520 are configured to be off when the timing signal is in a first logic state (e.g., low) and on when the timing signal is in a second logic state (e.g., high). As discussed further below, the timing signal is in the first logic state during the reset phase and in the second logic state during the sensing and decision phases. Therefore, the first switch 510 and the second switch 520 are off during the reset phase and on during the sensing and decision phases.

[0057] The following will now be discussed in light of certain aspects of this disclosure. Figure 5 Exemplary operation of the exemplary regeneration circuit 140 shown in the figure.

[0058] When the timing signal (e.g., clock signal CLK) is in a first logic state (e.g., low), the regenerative circuit 140 is in a reset phase. During the reset phase, the timing signal turns off the first switch 510 and the second switch 520. Turning off the first switch 510 decouples the input 162 of the second inverter circuit 160 from the output 154 of the first inverter circuit 150, thus breaking the regenerative feedback path between the input 162 of the second inverter circuit 160 and the output 154 of the first inverter circuit 150. Turning off the second switch 520 decouples the input 152 of the first inverter circuit 150 from the output 164 of the second inverter circuit 160, thus breaking the regenerative feedback path between the input 152 of the first inverter circuit 150 and the output 164 of the second inverter circuit 160.

[0059] By disconnecting the regenerative feedback path during the reset phase, the first switch 510 and the second switch 520 disable the regenerative feedback of the regenerative circuit 140 during the reset phase. In contrast, in Figure 1 and Figure 2 In the reset phase, regenerative feedback is disabled by turning off switch 180. Switch 180 decouples the first power supply terminals 156 and 166 of inverting circuits 150 and 160 from power rail 112, and thus cuts off power from power rail 112 to inverting circuits 150 and 160. Therefore, the first switch 510 and the second switch 520 allow the timing signal to disable the regenerative feedback of regenerative circuit 140 during the reset phase without requiring Figure 1 and Figure 2Switch 180 in the middle. This eliminates the need for switch 180, which allows the first power supply terminals 156 and 166 of the inverter circuits 150 and 160 to be directly coupled to the power supply rail 112. As discussed further below, during the reset phase, the first switch 510 and the second switch 520 can also disable the flow of current from the power supply rail 112 to ground 114.

[0060] As described above, during the reset phase, the voltage NDINT at the first input 144 and the voltage DINT at the second input 148 of the regeneration circuit 140 are pulled up to VCC by the input circuit 115. As a result, voltage NDINT is higher than the threshold voltage of the first input transistor 142, and voltage DINT is higher than the threshold voltage of the second input transistor 146 (assuming VCC is higher than the threshold voltage of each of the first and second input transistors 142 and 146). This turns on the first input transistor 142 and pulls down the input 162 of the second inverter circuit 160 to ground 114, and turns on the second input transistor 146 and pulls down the input 152 of the first inverter circuit 150 to ground 114.

[0061] When a timing signal (e.g., clock signal CLK) transitions from a first logic state (e.g., low) to a second logic state (e.g., high), the regeneration circuit 140 enters the sensing phase, and the timing signal turns on the first switch 510 and the second switch 520. Turning on the first switch 510 couples the input 162 of the second inverter circuit 160 to the output 154 of the first inverter circuit 150 through the first switch 510, and turning on the second switch 520 couples the input 152 of the first inverter circuit 150 to the output 164 of the second inverter circuit 160 through the second switch 520. As a result, the first inverter circuit 150 and the second inverter circuit 160 are cross-coupled through switches 510 and 520. This enables regenerative feedback in the sensing phase of the regeneration circuit 140. Regenerative feedback allows the regeneration circuit 140 to perform regeneration.

[0062] As described above, the first power supply terminals 156 and 166 of the inverter circuits 150 and 160 can be directly coupled to the power supply rail 112, and... Figure 1 and Figure 2 Compared to the example shown (where the IR voltage drop across switch 180 significantly reduces the supply voltage at the first supply terminals 156 and 166 of inverting circuits 150 and 160), this significantly increases the supply voltage at the first supply terminals 156 and 166 of inverting circuits 150 and 160. The increased supply voltage at the first supply terminals 156 and 166 of inverting circuits 150 and 160 increases the regeneration gain of regeneration circuit 140, which increases the speed at which regeneration circuit 140 can perform bit decisions and increases the sensitivity of sense amplifier 110.

[0063] As described above, during the sensing phase, depending on the polarity of the differential signal (e.g., differential data signal) input to the input circuit 115, the input circuit 115 pulls down the voltage NDINT at the first input 144 and the voltage DINT at the second input 148 of the regeneration circuit 140 at different rates. When one of the voltages NDINT and DINT drops below the threshold voltage 310 of the first input transistor 142 and the second input transistor 146 (which triggers the regeneration feedback of the regeneration circuit 140 to make a bit decision), the regeneration circuit 140 transitions from the sensing phase to the decision phase. As described above, the regeneration feedback is enabled by the cross-coupling of the inverter circuits 150 and 160 via switches 510 and 520 (both of which are on). The regeneration feedback causes the regeneration circuit 140 to pull one of the outputs 170 and 175 high and pull the other of the outputs 170 and 175 low to resolve the bit value based on which of the voltages NDINT and DINT drops below the threshold voltage 310 first, as discussed above.

[0064] The presence of the first switch 510 and the second switch 520 may potentially cause a large voltage offset at the outputs 170 and 175 of the regeneration circuit 140, which degrades the performance of the regeneration circuit 140 and may need to be corrected. The large voltage offset can be caused by the difference between the IR voltage drop across the first switch 510 and the IR voltage drop across the second switch 520 during the sensing and decision phases, a difference amplified by the regeneration gain of the regeneration circuit 140. The difference in IR voltage drops across switches 510 and 520 may be due to, for example, a mismatch between the first switch 510 and the second switch 520. The voltage offset caused by the difference in IR voltage drops across switches 510 and 520 can be significantly reduced by significantly reducing the IR voltage drops across switches 510 and 520, as discussed further below.

[0065] like Figure 5 As shown, the first switch 510 is located outside the current path between the input 162 of the second inverter circuit 160 and the first input transistor 142. This is because the first switch 510 is coupled between the first input transistor 142 and the output 154 of the first inverter circuit 150. As a result, during the sensing and decision phases, the current flowing between the input 162 of the second inverter circuit 160 and the first input transistor 142 does not flow through the first switch 510, which significantly reduces the IR voltage drop across the first switch 510.

[0066] Similarly, the second switch 520 is located outside the current path between the input 152 of the first inverter circuit 150 and the second input transistor 146. This is because the second switch 520 is coupled between the second input transistor 146 and the output 164 of the second inverter circuit 160. As a result, the current flowing between the input 152 of the first inverter circuit 150 and the second input transistor 146 during the sensing and decision phases does not flow through the second switch 520, which significantly reduces the IR voltage drop across the second switch 520.

[0067] Therefore, positioning the first switch 510 outside the current path between the input 162 of the second inverter circuit 160 and the first input transistor 142, and positioning the second switch 520 outside the current path between the input 152 of the first inverter circuit 150 and the second input transistor 146, significantly reduces the current flowing through the first switch 510 and the second switch 520 during the sensing and decision phases. This reduction in current flowing through the first and second switches significantly reduces the IR voltage drop across them. This significant reduction in the IR voltage drop across the first and second switches significantly reduces the impact of the IR voltage drop on the voltage offset of the regeneration circuit 140, resulting in a significantly smaller voltage offset due to the difference in IR voltage drop.

[0068] Figure 6A An example is shown where a first switch 510 is implemented using a first NFET 610, and a second switch 520 is implemented using a second NFET 620. In this example, one of the source and drain of the first NFET 610 is coupled to a first input transistor 142 (e.g., the drain of the first input transistor 142), the other of the source and drain of the first NFET 610 is coupled to the output 154 of a first inverter circuit 150, and the gate of the first NFET 610 is coupled to a control input 515 to receive a timing signal (e.g., a clock signal CLK). One of the source and drain of the second NFET 620 is coupled to a second input transistor 146 (e.g., the drain of the second input transistor 146), the other of the source and drain of the second NFET 620 is coupled to the output 164 of a second inverter circuit 160, and the gate of the second NFET 620 is coupled to a control input 525 to receive a timing signal (e.g., the clock signal CLK).

[0069] In this example, the first switch 510 and the second switch 520 are turned off when the timing signal is low and turned on when the timing signal is high. Therefore, in this example, the regeneration circuit 140 is in a reset phase when the timing signal is low and in a sensing and decision phase when the timing signal is high.

[0070] It should be understood that the first switch 510 and the second switch 520 are not limited to Figure 6A The exemplary implementation shown can be implemented using a different type of transistor, transmission gate, or switch, and each of the first switch 510 and the second switch 520 can be implemented using a different type of transistor, transmission gate, or switch. For example, Figure 6B An example is shown in which the first switch 510 further includes a first PFET 630 coupled in parallel with the first NFET 610. In this example, the first NFET 610 and the first PFET 630 form a transmission gate (e.g., a complementary metal-oxide-semiconductor (CMOS) transmission gate), wherein the gate of the first PFET 630 is driven by a supplemental timing signal (e.g., a complementary clock signal CLKb). Furthermore, in this example, the second switch 520 also includes a second PFET 640 coupled in parallel with the second NFET 620. In this example, the second NFET 620 and the second PFET 640 form a transmission gate, wherein the gate of the second PFET 640 is driven by a supplemental timing signal (e.g., a complementary clock signal CLKb). In some implementations, NFETs 610 and 620 can be omitted from switches 510 and 520, wherein a first PFET 630 is coupled between a first input transistor 142 (e.g., the drain of the first input transistor 142) and the output 154 of the first inverter circuit 150, and a second PFET 640 is coupled between a second input transistor 146 (e.g., the drain of the second input transistor 146) and the output 164 of the second inverter circuit 160.

[0071] Figure 7A An exemplary embodiment of a first inverter circuit 150 and a second inverter circuit 160 according to certain aspects is shown. In this example, the first inverter circuit 150 includes a first switch 720 and a second switch 725. The first switch 720 is coupled between an output 154 of the first inverter circuit 150 and a second power supply terminal 158, and the second switch 725 is coupled between an output 154 of the first inverter circuit 150 and a first power supply terminal 156. A control input 722 of the first switch 720 and a control input 727 of the second switch 725 are coupled to an input 152 of the first inverter circuit 150.

[0072] In operation, when the voltage at input 152 is high (e.g., close to VCC), the first switch 720 is configured to turn on, and the second switch 725 is configured to turn off. In this case, the first switch 720 pulls output 154 low. When the voltage at input 152 is low (e.g., close to ground), the first switch 720 is configured to turn off, and the second switch 725 is configured to turn on. In this case, the second switch 725 pulls output 154 high. Each of switches 720 and 725 can be implemented using one or more transistors, transmission gates, or another type of switch.

[0073] In this example, the second inverter circuit 160 includes a first switch 730 and a second switch 735. The first switch 730 is coupled between the output 164 of the second inverter circuit 160 and the second power supply terminal 168, and the second switch 735 is coupled between the output 164 of the second inverter circuit 160 and the first power supply terminal 166. The control input 732 of the first switch 730 and the control input 737 of the second switch 735 are coupled to the input 162 of the second inverter circuit 160.

[0074] In operation, when the voltage at input 162 is high (e.g., close to VCC), the first switch 730 is configured to turn on, and the second switch 735 is configured to turn off. In this case, the first switch 730 pulls output 164 low. When the voltage at input 162 is low (i.e., close to ground), the first switch 730 is configured to turn off, and the second switch 735 is configured to turn on. In this case, the second switch 735 pulls output 164 high. Each of switches 730 and 735 can be implemented using one or more transistors, transmission gates, or another type of switch.

[0075] Figure 7B An exemplary embodiment of a first switch 720 and a second switch 725 in a first inverter circuit 150 is shown. In this example, the first switch 720 includes an NFET 740 and the second switch 725 includes a PFET 745. The drain of the NFET 740 is coupled to an output 154, the gate of the NFET 740 is coupled to a control input 722, and the source of the NFET 740 is coupled to a second power supply terminal 158. The source of the PFET 745 is coupled to a first power supply terminal 156, the drain of the PFET 745 is coupled to an output 154, and the gate of the PFET 745 is coupled to a control input 727.

[0076] Figure 7BAn exemplary embodiment of a first switch 730 and a second switch 735 in the second inverter circuit 160 is also shown. In this example, the first switch 730 includes an NFET 750 and the second switch 735 includes a PFET 755. The drain of the NFET 750 is coupled to an output 164, the gate of the NFET 750 is coupled to a control input 732, and the source of the NFET 750 is coupled to a second power supply terminal 168. The source of the PFET 755 is coupled to a first power supply terminal 166, the drain of the PFET 755 is coupled to an output 164, and the gate of the PFET 755 is coupled to a control input 737.

[0077] exist Figure 7A and Figure 7B In the example shown, the first switch 510 and the second switch 520 disable the current path from power rail 112 to ground 114 during the reset phase. Figure 7C The diagram illustrates an example of this situation. Figure 7C The "X" designation indicates each device in the regeneration circuit 140 that was turned off during the reset phase. For example... Figure 7C As shown, the first switch 510 and the second switch 520 are turned off. Furthermore, the first switch 720 (e.g., NFET 740) in the first inverter circuit 150 is turned off. This is because during the reset phase, the second input transistor 146 pulls the input 152 of the first inverter circuit 150 to ground 114, which turns off the first switch 720. The first switch 730 (e.g., NFET 750) in the second inverter circuit 160 is also turned off. This is because during the reset phase, the first input transistor 142 pulls the input 162 of the second inverter circuit 160 to ground 114, which turns off the first switch 730.

[0078] The first switch 720 in the first inverter circuit 150 and the first switch 510 prevent current from flowing from the first power supply terminal 156 of the first inverter circuit 150 to ground 114, and the second switch 730 in the second inverter circuit 160 and the second switch 520 prevent current from flowing from the first power supply terminal 166 of the second inverter circuit 160 to ground 114. As a result, during the reset phase, the first switch 510 and the second switch 520 disable current flow from the power supply rail 112 to ground 114, which reduces the power consumption of the regeneration circuit 140 during the reset phase. In contrast, in Figure 1 and Figure 2 In the example shown, the current flow from power rail 112 to ground 114 is disabled during the reset phase by turning off switch 180, which decouples the inverter circuits 150 and 160 from power rail 112.

[0079] It should be understood that the inverter circuits 150 and 160 are not limited to Figure 7A and Figure 7B The exemplary implementation shown is illustrated. Therefore, it should be understood that each of the inverting circuits 150 and 160 can be implemented using any of a variety of circuits configured to invert logic states (i.e., logic levels or logic values), and is therefore not limited to a particular implementation.

[0080] Figure 8 An example according to certain aspects of this disclosure is shown, wherein the regeneration circuit 140 further includes a first pull-up transistor 810 and a second pull-up transistor 820. As discussed further below, the first pull-up transistor 810 and the second pull-up transistor 820 increase the regeneration gain of the regeneration circuit 140.

[0081] exist Figure 8 In this example, the first pull-up transistor 810 is implemented using a first PFET, and the second pull-up transistor 820 is implemented using a second PFET. In this example, the source of the first pull-up transistor 810 is coupled to the power supply rail 112, the drain of the first pull-up transistor 810 is coupled to the input 152 of the first inverting circuit 150, and the gate of the first pull-up transistor 810 is coupled to the output 154 of the first inverting circuit 150. The source of the second pull-up transistor 820 is coupled to the power supply rail 112, the drain of the second pull-up transistor 820 is coupled to the input 162 of the second inverting circuit 160, and the gate of the second pull-up transistor 820 is coupled to the output 164 of the second inverting circuit 160.

[0082] When the voltage DINT drops faster than the voltage NDINT during the sensing phase (e.g., INP > INN at inputs 121 and 123 of input circuit 115), the second input transistor 146 turns off before the first input transistor 142. This triggers regenerative feedback in regenerative circuit 140, pulling up the first output 170 and pulling down the second output 175. The pull-down of the second output 175 turns on the first pull-up transistor 810 because its gate is coupled to the second output 175 via the first switch 510. When the first pull-up transistor 810 is on, it pulls up the input 152 of the first inverter circuit 150 to the power supply voltage VCC on the power rail 112, which helps drive the output 154 of the first inverter circuit 150 low. Since the output 154 of the first inverter circuit 150 is coupled to the second output 175 through the first switch 510, driving the output 154 of the first inverter circuit 150 low helps to pull down the second output 175, and thus improves the regeneration gain of the regeneration circuit 140.

[0083] When the voltage NDINT drops faster than the voltage DINT during the sensing phase (e.g., INN > INP at inputs 121 and 123 of input circuit 115), the first input transistor 142 turns off before the second input transistor 146. This triggers regenerative feedback in regenerative circuit 140, pulling up the second output 175 and pulling down the first output 170. The pull-down of the first output 170 turns on the second pull-up transistor 820, as its gate is coupled to the first output 170 via the second switch 520. When the second pull-up transistor 820 is on, it pulls up the input 162 of the second inverter circuit 160 to the power supply voltage VCC on the power rail 112, which helps drive the output 164 of the second inverter circuit 160 low. Since the output 164 of the second inverter circuit 160 is coupled to the first output 170 through the second switch 520, driving the output 164 of the second inverter circuit 160 low helps to pull down the first output 170 and thus increases the regeneration gain of the regeneration circuit 140.

[0084] Therefore, the first pull-up transistor 810 and the second pull-up transistor 820 enhance the regeneration gain of the regeneration circuit 140. For cases where the voltage DINT drops faster than the voltage NDINT during the sensing phase (e.g., INP > INN at inputs 121 and 123 of input circuit 115), the first pull-up transistor 810 enhances the regeneration gain by pulling up the input 152 of the first inverter circuit 150 to the power supply voltage VCC. For cases where the voltage NDINT drops faster than the voltage DINT during the sensing phase (e.g., INN > INP at inputs 121 and 123 of input circuit 115), the second pull-up transistor 820 enhances the regeneration gain by pulling up the input 162 of the second inverter circuit 160 to the power supply voltage VCC.

[0085] Figure 9 An exemplary embodiment of the first switch 116, the second switch 130, and the third switch 134 in the input circuit 115 of the sensing amplifier 110, according to certain aspects, is shown. Note that, for ease of illustration, Figure 9 Details of the regeneration circuit 140 are not shown. Figure 9 As shown, the first output 124 of the input circuit 115 is coupled to the second input 148 of the regeneration circuit 140, and the second output 126 of the input circuit 115 is coupled to the first input 144 of the regeneration circuit 140. The regeneration circuit 140 can utilize... Figures 5 to 8 Implemented in any of the exemplary embodiments shown.

[0086] exist Figure 9In the example, the first switch 116 is implemented using an NFET 910, wherein the drain of the NFET 910 is coupled to the source of input transistors 120 and 122, the gate of the NFET 910 is coupled to control input 118, and the source of the NFET 910 is coupled to ground. The second switch 130 is implemented using a first PFET 915, wherein the source of the first PFET 915 is coupled to power rail 112, the gate of the first PFET 915 is coupled to control input 132, and the drain of the first PFET 915 is coupled to the drain of the first input transistor 120. The third switch 134 is implemented using a second PFET 920, wherein the source of the second PFET 920 is coupled to power rail 112, the gate of the second PFET 920 is coupled to control input 136, and the drain of the second PFET 920 is coupled to the drain of the second input transistor 122.

[0087] The first switch 116, the second switch 130, and the third switch 134 in the input circuit 115 can be driven by the same timing signal (e.g., a clock signal CLK) as the first switch 510 and the second switch 520 in the regeneration circuit 140. In this example, when the timing signal is low, the first switch 116 is off, and the second switch 130 and the third switch 134 are on. When the timing signal is high, the first switch 116 is on, and the second switch 130 and the third switch 134 are off. In this example, the timing signal is low during the reset phase and high during the sensing and decision phases.

[0088] Figure 10 An example of a system 1005 that can utilize aspects of this disclosure is shown. In this example, system 1005 includes a first chip 1010 and a second chip 1015, wherein a SerDes can be used for communication between the first chip 1010 and the second chip 1015. The first chip 1010 includes a serializer 1020, a driver 1030, a first output pin 1040, and a second output pin 1042. The second chip 1015 includes a first receive pin 1050, a second receive pin 1052, a receiver 1060, a sense amplifier 110, a latch 1070, and a deserializer 1080.

[0089] In this example, the first chip 1010 and the second chip 1015 are coupled via a differential serial link including a first line 1044 and a second line 1046. The first line 1044 is coupled between a first output pin 1040 and a first receive pin 1050, and the second line 1046 is coupled between a second output pin 1042 and a second receive pin 1052. Each line 1044 and 1046 can be implemented using metal lines, wires, etc. on a substrate (e.g., a printed circuit board).

[0090] On the first chip 1010, a serializer 1020 is configured to receive a parallel data stream (e.g., from a processor on the first chip 1010) and convert the parallel data stream into a serial data stream, which is output at output 1025 of the serializer 1020. A driver 1030 has an input 1032 coupled to output 1025 of the serializer 1020, a first output 1034 coupled to a first output pin 1040, and a second output 1036 coupled to a second output pin 1042. The driver 1030 is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive lines 1044 and 1046 of a differential serial link using the differential data signal to transmit the differential signal to the second chip 1015. It should be understood that the first chip 1010 may include... Figure 10 Additional components not shown (e.g., impedance matching networks coupled to output pins 1040 and 1042, pre-drivers coupled between serializer 1020 and driver 1030, etc.).

[0091] On the second chip 1015, the receiver 1060 has a first input 1062 coupled to a first receive pin 1050, a second input 1064 coupled to a second receive pin 1052, a first output 1066 coupled to a first input 121 of the sense amplifier 110, and a second output 1068 coupled to a second input 123 of the sense amplifier 110. The receiver 1060 may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip 1010 and the second chip 1015). As described above, the sense amplifier 110 receives the differential signal from the receiver 1060 and makes a bit decision based on the differential signal.

[0092] exist Figure 10 In the example, the first output 170 of the sense amplifier 110 is coupled to the first input 1072 of the latch 1070, and the second output 175 of the sense amplifier 110 is coupled to the second input 1074 of the latch 1070. The latch 1070 has an output 1076 coupled to the input 1082 of the deserializer 1080. The latch 1070 is configured to latch a bit decision from the sense amplifier 110 and output the corresponding bit to the deserializer 1080. The deserializer 1080 is configured to convert the bit into a parallel data stream, which can be output to one or more components (not shown) on the second chip 1015 for further processing. It should be understood that the second chip 1015 may include... Figure 10 Additional components not shown (e.g., impedance matching networks coupled to receive pins 1050 and 1052, clock recovery circuitry, etc.).

[0093] exist Figure 10In the example, the second chip 1015 also includes a timing signal circuit 1090 configured to generate a timing signal (e.g., a clock signal CLK) for the sense amplifier 110 and output the timing signal at an output 1094. The output 1094 can be coupled to the control inputs of switches 116, 130, and 134 in the input circuit 115, and can also be coupled to the control inputs of switches 510 and 520 in the regeneration circuit 140 of the sense amplifier 110.

[0094] In some respects, the timing signal circuit 1090 can use clock data recovery to recover the timing signal (e.g., the clock signal CLK) based on the bit decision of the sense amplifier 110. The input 1092 of the timing signal circuit 1090 can be coupled to the output of the latch 1070 (in... Figure 10 (as shown in the example), or can be coupled to one or both of the outputs 170 and 175 of the sensing amplifier 110 to receive bit decisions.

[0095] In some aspects, the timing signal circuit 1090 may include a clock generator, which may include a phase-locked loop (PLL), a delay-locked loop (DLL), an oscillator, or any combination thereof, to generate a timing signal (e.g., a clock signal CLK). It should be understood that the timing signal circuit 1090 can be implemented using various types of clock generators.

[0096] exist Figure 10 In the example, the first input 1072 of latch 1070 is coupled to the first output 170 and thus to the drain of the second input transistor 146, and the second input 1074 of latch 1070 is coupled to the second output 175 and thus to the drain of the first input transistor 142. However, it should be understood that this disclosure is not limited to this example. In another example, the first input 1072 of latch 1070 may be coupled to the output 164 of the second inverter circuit 160, and the second input 1074 of latch 1070 may be coupled to the output 154 of the first inverter circuit 150.

[0097] Figure 11 A method 1100 for operating a regeneration circuit of a sense amplifier according to certain aspects is illustrated. The regeneration circuit (e.g., regeneration circuit 140) includes a first inverting circuit (e.g., first inverting circuit 150) having an input (e.g., input 152) and an output (e.g., output 154), a second inverting circuit (e.g., second inverting circuit 160) having an input (e.g., input 162) and an output (e.g., output 164), a first transistor (e.g., first input transistor 142) coupled to the input of the second inverting circuit, and a second transistor (e.g., second input transistor 146) coupled to the input of the first inverting circuit.

[0098] At block 1110, during the reset phase, the output of the first inverting circuit is decoupled from the first transistor. For example, the output of the first inverting circuit can be decoupled from the first transistor by turning off the first switch 510.

[0099] At block 1120, during the reset phase, the output of the second inverting circuit is decoupled from the second transistor. For example, the output of the second inverting circuit can be decoupled from the second transistor by turning off the second switch 520.

[0100] At block 1130, during the sensing phase, the output of the first inverting circuit is coupled to the first transistor. For example, the output of the first inverting circuit can be coupled to the first transistor by turning on the first switch 510.

[0101] At block 1140, during the sensing phase, the output of the second inverting circuit is coupled to the second transistor. For example, the output of the second inverting circuit can be coupled to the second transistor by turning on the second switch 520.

[0102] In some aspects, method 1100 may further include: driving the gate of a first transistor using a first input signal (e.g., voltage NDINT), and driving the gate of a second transistor using a second input signal (e.g., voltage DINT). The first and second input signals may be generated by input circuit 115 based on data signals input to input circuit 115 (e.g., differential data signals).

[0103] In some respects, during the reset phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor. In one example, the threshold voltage of the first transistor may be approximately the same as the threshold voltage of the second transistor.

[0104] In some aspects, during the sensing phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor. In some aspects, during the sensing phase, the first input signal (e.g., voltage NDINT) decreases at a first rate (i.e., decreases), and the second input signal (e.g., voltage DINT) decreases at a second rate (i.e., decreases), wherein the first rate and the second rate are different (e.g., based on the polarity of the data signal input to the input circuit 115).

[0105] Method 1100 may further include transitioning from a sensing phase to a decision phase when the first input signal drops below a threshold voltage of the first transistor or the second input signal drops below a threshold voltage of the second transistor. Method 1100 may further include resolving bit values ​​based on the first and second input signals during the decision phase. For example, resolving bit values ​​may include resolving a first bit value if the first input signal drops below a threshold voltage of the first transistor before the second input signal drops below a threshold voltage of the second transistor, and resolving a second bit value if the second input signal drops below a threshold voltage of the second transistor before the first input signal drops below a threshold voltage of the first transistor. The first bit value may be 1 and the second bit value may be 0, or vice versa. In some aspects, during the decision phase, the output of the first inverting circuit is coupled to the first transistor, and the output of the second inverting circuit is coupled to the second transistor, thus cross-coupling the first and second inverting circuits. This is because the first transistor is coupled to the input of the second inverting circuit, and the second transistor is coupled to the input of the first inverting circuit. This cross-coupling of the first and second inverting circuits provides regenerative feedback, which is beneficial for resolving bit values.

[0106] Examples of implementation methods are described in the following numbered clauses: 1. A regenerative circuit, comprising: The first inverting circuit has both input and output; The second inverting circuit has both input and output; A first transistor is coupled to the input of a second inverting circuit, wherein the gate of the first transistor is configured to receive a first input signal; The second transistor is coupled to the input of the first inverting circuit, wherein the gate of the second transistor is configured to receive the second input signal; A first switch, coupled between a first transistor and the output of a first inverting circuit, wherein the control input of the first switch is configured to receive a timing signal; and A second switch is coupled between the output of the second transistor and the second inverting circuit, wherein the control input of the second switch is configured to receive a timing signal.

[0107] 2. The regenerative circuit according to Clause 1, wherein: The first switch is coupled between the drain of the first transistor and the output of the first inverting circuit; and The second switch is coupled between the drain of the second transistor and the output of the second inverting circuit.

[0108] 3. The regenerative circuit according to Clause 2, wherein: The source of the first transistor is coupled to ground; and The source of the second transistor is coupled to ground.

[0109] 4. A regenerative circuit according to Clause 2 or 3, wherein the first transistor includes a first n-type field-effect transistor (NFET) and the second transistor includes a second NFET.

[0110] 5. A regenerative circuit according to any one of clauses 2 to 4, wherein: The drain of the first transistor is directly coupled to the input of the second inverting circuit; and The drain of the second transistor is directly coupled to the input of the first inverting circuit.

[0111] 6. A regenerative circuit according to any one of clauses 1 to 5, wherein: The first switch includes a third transistor having a gate configured to receive a timing signal; and The second switch includes a fourth transistor having a gate configured to receive a timing signal.

[0112] 7. The regenerative circuit according to Clause 6, wherein: One of the source and drain of the third transistor is coupled to the drain of the first transistor, and the other of the source and drain of the third transistor is coupled to the output of the first inverting circuit; and One of the source and drain of the fourth transistor is coupled to the drain of the second transistor, and the other of the source and drain of the fourth transistor is coupled to the output of the second inverting circuit.

[0113] 8. The regenerative circuit according to clause 6 or 7, wherein: The third transistor includes a first n-type field-effect transistor (NFET); and The fourth transistor includes a second NFET.

[0114] 9. The regenerative circuit according to any one of clauses 1 to 5 further includes: The third transistor is coupled between the input of the first inverting circuit and the power supply rail; and The fourth transistor is coupled between the input of the second inverting circuit and the power supply rail.

[0115] 10. The regenerative circuit according to Clause 9, wherein: The gate of the third transistor is coupled to the output of the first inverter circuit; and The gate of the fourth transistor is coupled to the output of the second inverting circuit.

[0116] 11. The regenerative circuit according to clause 9 or 10, wherein: The source of the third transistor is coupled to the power supply rail, and the drain of the third transistor is coupled to the input of the first inverting circuit; and The source of the fourth transistor is coupled to the power supply rail, and the drain of the fourth transistor is coupled to the input of the second inverting circuit.

[0117] 12. A regenerative circuit according to any one of clauses 9 to 11, wherein: The third transistor includes a first p-type field-effect transistor (PFET); and The fourth transistor includes a second PFET.

[0118] 13. A regenerative circuit according to any one of clauses 1 to 12, wherein the timing signal includes a clock signal.

[0119] 14. A regenerative circuit according to any one of clauses 1 to 13, wherein the control input of a first switch and the control input of a second switch are coupled to a timing signal circuit configured to generate a timing signal.

[0120] 15. A sensing amplifier, comprising: Input circuit, wherein the input circuit includes: A first transistor, wherein the gate of the first transistor is configured to receive a first input signal, and the drain of the first transistor is coupled to a first output of the input circuit; and A second transistor, wherein the gate of the second transistor is configured to receive a second input signal, and the drain of the second transistor is coupled to a second output of the input circuit; and Regeneration circuit, wherein the regeneration circuit includes: The first inverting circuit has both input and output; The second inverting circuit has both input and output; The third transistor is coupled to the input of the second inverting circuit, wherein the gate of the third transistor is coupled to the second output of the input circuit; The fourth transistor is coupled to the input of the first inverting circuit, wherein the gate of the fourth transistor is coupled to the first output of the input circuit; A first switch, coupled between the third transistor and the output of the first inverting circuit, wherein the control input of the first switch is configured to receive a timing signal; and A second switch is coupled between the fourth transistor and the output of the second inverting circuit, wherein the control input of the second switch is configured to receive a timing signal.

[0121] 16. The sensing amplifier according to Clause 15, wherein the input circuitry further includes: The third switch is coupled between the drain of the first transistor and the power supply rail; and The fourth switch is coupled between the drain of the second transistor and the power supply rail.

[0122] 17. The sensing amplifier according to Clause 16, wherein: The control input of the third switch is configured to receive a timing signal; and The control input of the fourth switch is configured to receive a timing signal.

[0123] 18. A sensing amplifier according to clause 16 or 17, wherein the input circuitry further includes a fifth switch coupled between the source of the first transistor and ground, and coupled between the source of the second transistor and ground.

[0124] 19. The sensing amplifier according to Clause 18, wherein: The control input of the third switch is configured to receive a timing signal; The control input of the fourth switch is configured to receive a timing signal; and The control input of the fifth switch is configured to receive a timing signal.

[0125] 20. A sensing amplifier according to any one of clauses 15 to 19, wherein: The first switch is coupled between the drain of the third transistor and the output of the first inverting circuit; and The second switch is coupled between the drain of the fourth transistor and the output of the second inverting circuit.

[0126] 21. The sensing amplifier according to Clause 20, wherein: The source of the third transistor is coupled to ground; and The source of the fourth transistor is coupled to ground.

[0127] 22. A sensing amplifier according to clause 20 or 21, wherein: The drain of the third transistor is directly coupled to the input of the second inverting circuit; and The drain of the fourth transistor is directly coupled to the input of the first inverting circuit.

[0128] 23. A sensing amplifier according to any one of clauses 15 to 22, wherein: The first switch includes a fifth transistor, the fifth transistor having a gate configured to receive a timing signal; and The second switch includes a sixth transistor having a gate configured to receive a timing signal.

[0129] 24. The regenerative circuit according to Clause 23, wherein: One of the source and drain of the fifth transistor is coupled to the drain of the third transistor, and the other of the source and drain of the fifth transistor is coupled to the output of the first inverting circuit; and One of the source and drain of the sixth transistor is coupled to the drain of the fourth transistor, and the other of the source and drain of the sixth transistor is coupled to the output of the second inverting circuit.

[0130] 25. A method of operating a regeneration circuit of a sense amplifier, wherein the regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, the method comprising: During the reset phase, Decouple the output of the first inverting circuit from the first transistor; and Decouple the output of the second inverting circuit from the second transistor; and During the sensing phase, Couple the output of the first inverting circuit to the first transistor; and The output of the second inverting circuit is coupled to the second transistor.

[0131] 26. The method pursuant to Clause 25 also includes: The gate of the first transistor is driven using the first input signal; and The gate of the second transistor is driven by the second input signal.

[0132] 27. According to the method of Clause 26, wherein: During the reset phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor.

[0133] 28. According to the method of Clause 27, wherein: During the sensing phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor.

[0134] 29. According to the method of Clause 28, wherein: During the sensing phase, the first input signal decreases at a first rate, the second input signal decreases at a second rate, and the first rate and the second rate are different.

[0135] 30. The method pursuant to Clause 29 also includes: When the first input signal drops below the threshold voltage of the first transistor or the second input signal drops below the threshold voltage of the second transistor, the process transitions from the sensing phase to the decision phase.

[0136] 31. The method pursuant to Clause 30 also includes: During the decision-making phase, bit values ​​are analyzed based on the first and second input signals.

[0137] 32. The method according to any one of clauses 25 to 31, wherein the regenerative circuit includes a first switch and a second switch, the first switch being coupled between the output of a first inverting circuit and a first transistor, and the second switch being coupled between the output of a second inverting circuit and a second transistor, and wherein: Decoupling the output of the first inverting circuit from the first transistor includes: turning off the first switch; Decoupling the output of the second inverting circuit from the second transistor includes: turning off the second switch; Couple the output of the first inverting circuit to the first transistor includes: turning on the first switch; and Coupling the output of the second inverting circuit to the second transistor includes turning on the second switch.

[0138] 33. The method according to any one of clauses 25 to 32, wherein the drain of the first transistor is directly coupled to the input of the second inverting circuit, and the drain of the second transistor is directly coupled to the input of the first inverting circuit.

[0139] 34. According to the method of Clause 33, wherein: Decoupling the output of the first inverting circuit from the first transistor includes: decoupling the output of the first inverting circuit from the drain of the first transistor; Decoupling the output of the second inverting circuit from the second transistor includes: decoupling the output of the second inverting circuit from the drain of the second transistor; Coupling the output of the first inverting circuit to the first transistor includes: coupling the output of the first inverting circuit to the drain of the first transistor; and Coupling the output of the second inverting circuit to the second transistor includes coupling the output of the second inverting circuit to the drain of the second transistor.

[0140] 35. The method according to clause 34, wherein the regenerative circuit includes a first switch and a second switch, the first switch being coupled between the output of a first inverting circuit and the drain of a first transistor, and the second switch being coupled between the output of a second inverting circuit and the drain of a second transistor, wherein: Decoupling the output of the first inverting circuit from the drain of the first transistor includes: turning off the first switch; Decoupling the output of the second inverting circuit from the drain of the second transistor includes: turning off the second switch; Coupling the output of the first inverting circuit to the drain of the first transistor includes: turning on the first switch; and Coupling the output of the second inverting circuit to the drain of the second transistor includes turning on the second switch.

[0141] 36. A system comprising: The sensing amplifier includes: Input circuit, wherein the input circuit includes: A first transistor, wherein the gate of the first transistor is configured to receive a first input signal, and the drain of the first transistor is coupled to a first output of the input circuit; and A second transistor, wherein the gate of the second transistor is configured to receive a second input signal, and the drain of the second transistor is coupled to a second output of the input circuit; and Regeneration circuit, wherein the regeneration circuit includes: The first inverting circuit has both input and output; The second inverting circuit has both input and output; The third transistor is coupled to the input of the second inverting circuit, wherein the gate of the third transistor is coupled to the second output of the input circuit; The fourth transistor is coupled to the input of the first inverting circuit, wherein the gate of the fourth transistor is coupled to the first output of the input circuit; A first switch, coupled between the third transistor and the output of the first inverting circuit, wherein the control input of the first switch is configured to receive a timing signal; and The second switch is coupled between the fourth transistor and the output of the second inverting circuit, wherein the control input of the second switch is configured to receive a timing signal; A latch having an input and an output, wherein the input of the latch is coupled to a sense amplifier; and A deserializer has an input that is coupled to the output of a latch.

[0142] 37. The system pursuant to Clause 36 also includes: A serializer with an output; A driver having inputs and outputs, wherein the input of the driver is coupled to the output of the serializer; and A receiver has an input and an output, wherein the input of the receiver is coupled to the output of the driver, and the output of the receiver is coupled to the sensing amplifier.

[0143] 38. A system pursuant to Clause 37, wherein the receiver output includes: The first output is coupled to the gate of the first transistor; and The second output is coupled to the gate of the second transistor.

[0144] 39. A system according to any one of clauses 36 to 38, wherein the inputs of the latch include: The first input is coupled to the drain of the fourth transistor or the output of the second inverting circuit; and The second input is coupled to the drain of the third transistor or the output of the first inverting circuit.

[0145] It should be understood that this disclosure is not limited to the exemplary terms used above to describe aspects of this disclosure. For example, input circuit 115 may also be referred to as sensing circuit or another term. Regeneration circuit 140 may also be referred to as decision circuit, cross-coupled latch or another term. Inverting circuit may also be referred to as inverter, inverting circuit or another term. Logic state may also be referred to as logic level, logic value or another term.

[0146] Any reference to elements in this document using names such as "first," "second," etc., generally does not restrict the number or order of these elements. Rather, these names are used in this document as a convenient way to distinguish between two or more elements or multiple instances of an element. Therefore, references to the first and second elements do not imply that only two elements can be used, or that the first element must precede the second element.

[0147] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. As used herein with respect to stated values ​​or properties, the term "about" is intended to mean within 10% of the stated value or property.

[0148] The foregoing description of this disclosure is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A regenerative circuit for a sensing amplifier, comprising: The first inverting circuit has both input and output; The second inverting circuit has both input and output; A first transistor is coupled to the input of the second inverting circuit via a first node, wherein the gate of the first transistor is configured to receive a first input signal; A second transistor is coupled to the input of the first inverting circuit via a second node, wherein the gate of the second transistor is configured to receive a second input signal; A first switch is coupled between the output of the first transistor and the first inverter circuit via the first node, wherein the control input of the first switch is configured to receive a timing signal, and the first switch is configured to decouple the output of the first inverter circuit from the input of the second inverter circuit when the timing signal turns off the first switch. as well as A second switch, coupled via the second node, is connected between the output of the second transistor and the output of the second inverter circuit. The control input of the second switch is configured to receive the timing signal, and the second switch is configured to decouple the output of the second inverter circuit from the input of the first inverter circuit when the timing signal turns off the second switch. The drain of the first transistor is coupled to the first node, the drain of the second transistor is coupled to the second node, and the sources of the first transistor and the second transistor are coupled to ground.

2. The regeneration circuit of claim 1, wherein the first transistor comprises a first n-type field-effect transistor (NFET), and the second transistor comprises a second NFET.

3. The regeneration circuit according to claim 1, wherein: The drain of the first transistor is directly coupled to the input of the second inverting circuit; and The drain of the second transistor is directly coupled to the input of the first inverting circuit.

4. The regeneration circuit according to claim 1, wherein: The first switch includes a third transistor having a gate configured to receive the timing signal; and The second switch includes a fourth transistor having a gate configured to receive the timing signal.

5. The regeneration circuit according to claim 4, wherein: One of the source and drain of the third transistor is coupled to the drain of the first transistor, and the other of the source and drain of the third transistor is coupled to the output of the first inverting circuit. and One of the source and drain of the fourth transistor is coupled to the drain of the second transistor, and the other of the source and drain of the fourth transistor is coupled to the output of the second inverting circuit.

6. The regeneration circuit according to claim 4, wherein: The third transistor includes a first n-type field-effect transistor (NFET); and The fourth transistor includes a second NFET.

7. The regenerative circuit according to claim 1, further comprising: The third transistor is coupled between the input of the first inverting circuit and the power supply rail; as well as A fourth transistor is coupled between the input of the second inverting circuit and the power supply rail.

8. The regeneration circuit according to claim 7, wherein: The gate of the third transistor is coupled to the output of the first inverter circuit; and The gate of the fourth transistor is coupled to the output of the second inverting circuit.

9. The regenerative circuit according to claim 7, wherein: The source of the third transistor is coupled to the power supply rail, and the drain of the third transistor is coupled to the input of the first inverting circuit; and The source of the fourth transistor is coupled to the power supply rail, and the drain of the fourth transistor is coupled to the input of the second inverting circuit.

10. The regeneration circuit according to claim 7, wherein: The third transistor includes a first p-type field-effect transistor (PFET); and The fourth transistor includes a second PFET.

11. The regeneration circuit according to claim 1, wherein the timing signal includes a clock signal.

12. The regeneration circuit of claim 1, wherein the control input of the first switch and the control input of the second switch are coupled to a timing signal circuit configured to generate the timing signal.

13. A sensing amplifier, comprising: Input circuit, wherein the input circuit includes: A first transistor, wherein the gate of the first transistor is configured to receive a first input signal, and the drain of the first transistor is coupled to a first output of the input circuit; and A second transistor, wherein the gate of the second transistor is configured to receive a second input signal, and the drain of the second transistor is coupled to a second output of the input circuit; and Regeneration circuit, wherein the regeneration circuit includes: The first inverting circuit has both input and output; The second inverting circuit has both input and output; A third transistor is coupled to the input of the second inverting circuit via a first node, wherein the gate of the third transistor is coupled to the second output of the input circuit; A fourth transistor is coupled to the input of the first inverting circuit via a second node, wherein the gate of the fourth transistor is coupled to the first output of the input circuit; A first switch, coupled via the first node between the third transistor and the output of the first inverting circuit, wherein the control input of the first switch is configured to receive a timing signal, and the first switch is configured to decouple the output of the first inverting circuit from the input of the second inverting circuit when the timing signal turns off the first switch; and A second switch, coupled via the second node between the fourth transistor and the output of the second inverting circuit, wherein the control input of the second switch is configured to receive the timing signal, and the second switch is configured to decouple the output of the second inverting circuit from the input of the first inverting circuit when the timing signal turns off the second switch. The drain of the third transistor is coupled to the first node, the drain of the fourth transistor is coupled to the second node, and the sources of the third transistor and the fourth transistor are coupled to ground.

14. The sensing amplifier of claim 13, wherein the input circuit further comprises: The third switch is coupled between the drain of the first transistor and the power supply rail; as well as A fourth switch is coupled between the drain of the second transistor and the power supply rail.

15. The sensing amplifier according to claim 14, wherein: The control input of the third switch is configured to receive the timing signal; and The control input of the fourth switch is configured to receive the timing signal.

16. The sensing amplifier of claim 14, wherein the input circuit further comprises a fifth switch coupled between the source of the first transistor and ground, and coupled between the source of the second transistor and ground.

17. The sensing amplifier according to claim 16, wherein: The control input of the third switch is configured to receive the timing signal; The control input of the fourth switch is configured to receive the timing signal; and The control input of the fifth switch is configured to receive the timing signal.

18. The sensing amplifier according to claim 13, wherein: The first switch is coupled between the drain of the third transistor and the output of the first inverting circuit; and The second switch is coupled between the drain of the fourth transistor and the output of the second inverting circuit.

19. The sensing amplifier according to claim 18, wherein: The source of the third transistor is coupled to ground; and The source of the fourth transistor is coupled to the ground.

20. The sensing amplifier according to claim 18, wherein: The drain of the third transistor is directly coupled to the input of the second inverting circuit; and The drain of the fourth transistor is directly coupled to the input of the first inverting circuit.

21. The sensing amplifier according to claim 13, wherein: The first switch includes a fifth transistor having a gate configured to receive the timing signal; and The second switch includes a sixth transistor having a gate configured to receive the timing signal.

22. The sensing amplifier according to claim 21, wherein: One of the source and drain of the fifth transistor is coupled to the drain of the third transistor, and the other of the source and drain of the fifth transistor is coupled to the output of the first inverting circuit. and One of the source and drain of the sixth transistor is coupled to the drain of the fourth transistor, and the other of the source and drain of the sixth transistor is coupled to the output of the second inverting circuit.

23. A method of operating a regeneration circuit of a sense amplifier, wherein the regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, the method comprising: The gate of the first transistor is driven using the first input signal; The gate of the second transistor is driven using the second input signal; During the reset phase, The output of the first inverter circuit is decoupled from the input of the first transistor and the second inverter circuit via the first switch; as well as The output of the second inverter circuit is decoupled from the input of the second transistor and the first inverter circuit via the second switch; as well as During the sensing phase, The output of the first inverter circuit is coupled to the input of the first transistor and the second inverter circuit; as well as The output of the second inverter circuit is coupled to the second transistor and the input of the first inverter circuit. The drain of the first transistor is coupled to the input of the second inverting circuit, the drain of the second transistor is coupled to the input of the first inverting circuit, and the sources of the first transistor and the second transistor are coupled to ground.

24. The method according to claim 23, wherein: During the reset phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor.

25. The method of claim 24, wherein: During the sensing phase, the first input signal is higher than the threshold voltage of the first transistor, and the second input signal is higher than the threshold voltage of the second transistor.

26. The method of claim 25, wherein: During the sensing phase, the first input signal decreases at a first rate, the second input signal decreases at a second rate, and the first rate is different from the second rate.

27. The method of claim 26, further comprising: When the first input signal drops below the threshold voltage of the first transistor or the second input signal drops below the threshold voltage of the second transistor, the process transitions from the sensing phase to the decision phase.

28. The method of claim 27, further comprising: During the decision-making phase, bit values ​​are resolved based on the first input signal and the second input signal.

29. The method of claim 23, wherein the regeneration circuit comprises a first switch and a second switch, the first switch being coupled between the output of the first inverting circuit and the first transistor, and the second switch being coupled between the output of the second inverting circuit and the second transistor, wherein: Decoupling the output of the first inverting circuit from the first transistor includes: turning off the first switch; Decoupling the output of the second inverting circuit from the second transistor includes: turning off the second switch; Couple the output of the first inverting circuit to the first transistor includes: turning on the first switch; and Coupling the output of the second inverting circuit to the second transistor includes turning on the second switch.

30. The method of claim 23, wherein the drain of the first transistor is directly coupled to the input of the second inverting circuit, and the drain of the second transistor is directly coupled to the input of the first inverting circuit.

31. The method of claim 30, wherein: Decoupling the output of the first inverting circuit from the first transistor includes: decoupling the output of the first inverting circuit from the drain of the first transistor; Decoupling the output of the second inverting circuit from the second transistor includes: decoupling the output of the second inverting circuit from the drain of the second transistor; Coupling the output of the first inverting circuit to the first transistor includes: coupling the output of the first inverting circuit to the drain of the first transistor; and Coupling the output of the second inverting circuit to the second transistor includes coupling the output of the second inverting circuit to the drain of the second transistor.

32. The method of claim 31, wherein the regeneration circuit comprises a first switch and a second switch, the first switch being coupled between the output of the first inverting circuit and the drain of the first transistor, and the second switch being coupled between the output of the second inverting circuit and the drain of the second transistor, wherein: Decoupling the output of the first inverting circuit from the drain of the first transistor includes: turning off the first switch; Decoupling the output of the second inverting circuit from the drain of the second transistor includes: turning off the second switch; Coupling the output of the first inverting circuit to the drain of the first transistor includes: turning on the first switch; and Coupling the output of the second inverting circuit to the drain of the second transistor includes turning on the second switch.

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