Driving method and driving device of semiconductor element, and power conversion device

Abstract

As for the semiconductor element, the conduction is controlled by controlling the gate voltage in accordance with the drive control signal (Ssw). In the turn-on operation in which the gate is charged from the first level (0) to the second level (1) in accordance with the drive control signal (Ssw), the gate is discharged by setting the drive signal (Sdr) to the first level (0) at the first time (tl) after the end of the mirror period (200) of the gate voltage (Vg), and a voltage reduction period (210) in which the gate voltage (Vg) is temporarily reduced is provided. At the second time (t2), the drive signal (Sdr) is set to the second level (1) again, and the charging of the gate is started.

Description

Technical Field

[0001] This disclosure relates to driving methods and driving devices for semiconductor elements, as well as power conversion devices. Background Technology

[0002] To enable the switching operation of voltage-driven semiconductor devices, such as MOS-FET (metal-oxide-semiconductor field-effect transistor) and IGBT (Insulated Gate Bipolar Transistor), a drive device is used to charge and discharge the gate of the semiconductor device according to a turn-on / turn-off control signal.

[0003] In the stable switching operation of such semiconductor devices, it is necessary to increase the switching speed in order to reduce the switching losses generated in the semiconductor device due to turning it on or off.

[0004] On the other hand, when an abnormality occurs in the circuit connecting semiconductor components, an overcurrent path may be formed, including the semiconductor component, due to the semiconductor component being turned on. In such cases, it is also necessary to turn the semiconductor component on and off to avoid damage to the semiconductor component due to the effects of overcurrent.

[0005] Specifically, in order to prevent the semiconductor device from breaking down even in the event of an overcurrent, the semiconductor device must be turned off before the time until breakdown (the so-called short-circuit withstand time) has elapsed, or the surge voltage that occurs during the overcurrent interruption process must be suppressed to below the withstand voltage capability of the semiconductor device. To meet this condition, contrary to stable switching operation, a low switching speed is preferable.

[0006] Thus, regarding the switching speed of semiconductor devices, there is a trade-off between reducing switching losses during stable operation and reducing the likelihood of semiconductor device breakdown during abnormal operation.

[0007] Japanese Patent Application Publication No. 2010-119184 (Patent Document 1) discloses a semiconductor driving device for effectively utilizing an active gate driving method even when the mirror period cannot be detected with high precision. In this active gate driving method, inrush current is suppressed by slowly turning on the gate before the mirror period, and switching losses are reduced by rapidly turning it on beyond the mirror period. Specifically, it describes reducing both inrush current and switching losses by performing PWM (Pulse Width Modulation) control on the gate input signal corresponding to the mirror period during on-time or off-time.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2010-119184 Summary of the Invention

[0011] The semiconductor driving device in Patent Document 1 is mainly used to reduce power loss and current surge during stable switching, but it does not address how to deal with situations where an overcurrent path is formed in response to the switching on of the semiconductor element. Therefore, there is a concern that the gate voltage control described in Patent Document 1 is not very effective in reducing the possibility of semiconductor element breakdown when an overcurrent anomaly occurs.

[0012] In short, in Patent Document 1, by employing PWM control, the overall turn-on or turn-off time becomes longer, thereby expecting the equivalent reduction in switching speed to help reduce the likelihood of semiconductor device breakdown during overcurrent. However, this reduction in switching speed increases the switching losses at steady state, so it cannot contribute to improving the trade-off between reducing switching losses at steady state and reducing the likelihood of semiconductor device breakdown during overcurrent anomalies, as described above.

[0013] This disclosure was made to solve such a problem, and the purpose of this disclosure is to control the switching of a semiconductor device in a way that reduces the possibility of breakdown during an overcurrent anomaly while suppressing the impact on switching losses under normal conditions.

[0014] In one aspect of this disclosure, a method for driving a semiconductor device is provided. The method for driving a semiconductor element to turn on or off according to a drive control signal includes the following steps: (a) in response to an on command that transitions the drive control signal from a first level to a second level, initiating an on operation to charge the gate of the off-state semiconductor element; (b) in response to an off command that transitions the drive control signal from a second level to a first level, initiating an off operation to discharge the gate of the on-state semiconductor element; and (c) configuring at least one of a voltage decrease period and a voltage rise period, wherein the voltage decrease period is set during a period after the on operation begins when the drive control signal is maintained at a second level, and the voltage rise period is set during a period after the off operation begins when the drive control signal is maintained at a first level. The voltage decrease period is configured to temporarily decrease the gate voltage by discharging the gate after the mirroring period ends. The voltage rise period is configured to temporarily increase the gate voltage by charging the gate during a period when the current of the semiconductor element decreases.

[0015] In another aspect of this disclosure, a driving device for a semiconductor element is provided. The driving device for turning a semiconductor element on or off according to a driving control signal includes a driving adjustment unit and a driving circuit. The driving adjustment unit generates a driving signal in response to an on command whereby the driving control signal transitions from a first level to a second level and an off command whereby the driving control signal transitions from a second level to a first level. The driving signal controls an on operation of charging the gate of a semiconductor element in an off state and an off operation of discharging the gate of a semiconductor element in an on state. The driving circuit charges or discharges the gate according to the driving signal. The driving adjustment unit generates the driving signal in a manner that configures at least one of a voltage drop period and a voltage rise period. The voltage drop period is set during the period after the on operation begins when the driving control signal is maintained at the second level, and the voltage rise period is set during the period after the off operation begins when the driving control signal is maintained at the first level. The voltage drop period is configured to temporarily decrease the gate voltage by discharging the gate after the mirroring period ends. The voltage rise period is configured to temporarily increase the gate voltage by charging the gate during the period when the current of the semiconductor element decreases.

[0016] In another aspect of this disclosure, a power conversion apparatus is provided. The power conversion apparatus includes: a main conversion circuit configured to include at least one semiconductor element, which converts input power and outputs it; and a control circuit that outputs control signals to the main conversion circuit. The control signals include drive control signals for each semiconductor element. The main conversion circuit also includes the aforementioned drive devices configured corresponding to each semiconductor element. The drive devices control the on / off state of each semiconductor element according to the drive control signals.

[0017] According to this disclosure, by temporarily setting a voltage drop period after the mirror period in the turn-on operation, the increase of the drain current of the semiconductor element under short-circuit conditions can be suppressed, and by temporarily setting a voltage rise period in the turn-off operation, the surge voltage generated when the semiconductor element is turned off under short-circuit conditions can be suppressed. Therefore, the switching of the semiconductor element can be controlled in a way that reduces the possibility of breakdown under overcurrent abnormalities while suppressing the impact on the switching losses under normal conditions. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating the function of the drive device according to this embodiment.

[0019] Figure 2 This is a typical waveform diagram of the normal switching operation of a semiconductor device.

[0020] Figure 3 This is a typical waveform diagram of the switching action when a semiconductor device malfunctions.

[0021] Figure 4 It is a graph illustrating the relationship between gate voltage and drain current when a short-circuit current flows through a semiconductor device.

[0022] Figure 5 This is a block diagram illustrating a structural example of the drive device in Embodiment 1.

[0023] Figure 6 This is a waveform diagram of the normal operation of a semiconductor element powered on by the driving device of Embodiment 1.

[0024] Figure 7 This is a waveform diagram of the operation of a semiconductor element when it is malfunctioning due to the drive device of Embodiment 1.

[0025] Figure 8 This is a waveform diagram of the operation of a semiconductor element when the drive device of a modified embodiment 1 is turned on in case of an abnormality.

[0026] Figure 9 This is a block diagram illustrating a structural example of the drive device in Embodiment 2.

[0027] Figure 10 This is a typical drain voltage-drain current characteristic diagram of a semiconductor device.

[0028] Figure 11 This is an operation waveform diagram used to illustrate the variable adjustment of the drain voltage as information during the decrease of the driving device in Embodiment 2.

[0029] Figure 12 This is a first flowchart illustrating the control process for variable adjustment during the reduction period in the drive device of Embodiment 2.

[0030] Figure 13 This is an operation waveform diagram used to illustrate the variable adjustment of the drain current as information during the reduction period in the drive device of Embodiment 2.

[0031] Figure 14 This is an explanation Figure 4 A graph showing the temperature dependence.

[0032] Figure 15 This is an operation waveform diagram used to illustrate the variable adjustment of the component temperature as information during the decrease of the drive device in Embodiment 2.

[0033] Figure 16 This is an operation waveform diagram used to illustrate the variable adjustment of the gate voltage as information quantity during the decrease of the driving device in Embodiment 2.

[0034] Figure 17 This is a second flowchart illustrating the control processing of variable adjustment during the reduction of information about the operating state of semiconductor elements in the drive device of Embodiment 2.

[0035] Figure 18 This is a typical waveform diagram of the disconnection action when a semiconductor device malfunctions.

[0036] Figure 19 This is a block diagram illustrating a structural example of the drive device in Embodiment 3.

[0037] Figure 20 This is a waveform diagram of the operation when the semiconductor element is disconnected by the drive device of Embodiment 3.

[0038] Figure 21 This is a block diagram illustrating a structural example of the drive device in Embodiment 4.

[0039] Figure 22 This is a flowchart illustrating the control process of variable adjustment during the rise of information about the operating state of a semiconductor element in the drive device of Embodiment 4.

[0040] Figure 23 This is a flowchart illustrating the control processing of the configuration during the voltage rise period in the drive device of Embodiment 4.

[0041] Figure 24 This is a block diagram illustrating the structure of the power conversion system using the power conversion device in Embodiment 5.

[0042] (Symbol Explanation)

[0043] 10: Semiconductor element; 11: Drain; 12: Source; 15: Gate; 18: Detector; 20, 255: Control circuit; 100, 100X, 101, 102, 103: Driving device; 110, 111, 112, 113: Driving adjustment unit; 120, 122: Edge detection unit; 130, 131, 132, 133: Delay circuit; 135: Memory; 140, 142: Insertion pulse generation unit; 145, 146: Signal synthesis unit; 150: Driving circuit; 151, 152: Transistor; 161, 162: Power node; 170: External interface circuit; 190: Power supply. ; 200: Mirroring period; 210: Voltage drop period; 211, 212: Divided drop period; 250: Power conversion device; 251: Main conversion circuit; 256: Control signal; 300: Load; 410: Voltage rise period; Id: Drain current; P1~P4: Pulse; Pof: Cutoff pulse signal; Pon: Turn-on pulse signal; Sdr: Drive signal; Ssw: Drive control signal; Tj: Component temperature; VH: Turn-on voltage; VL: Cut-off voltage; Vds: Drain voltage (drain / source voltage); Vg: Gate voltage (gate / source voltage); Vp: Mirroring voltage; Vth: Threshold voltage. Detailed Implementation

[0044] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, several embodiments will be described below; however, it is clear from the outset of this application that the structures described in each embodiment can be suitably combined to the extent that they do not create technical inconsistencies, including combinations not directly described in the specification. Additionally, the same or equivalent parts in the figures will be referred to by the same reference numerals, and their description will generally not be repeated.

[0045] Implementation method 1.

[0046] Figure 1 This is a block diagram illustrating the function of the drive device according to this embodiment.

[0047] The drive device 100 controls the conduction / cutoff, i.e., switching operation of the semiconductor element 10 connected between the high voltage terminal N1 and the low voltage terminal N2 according to the drive control signal Ssw from the control circuit 20.

[0048] Semiconductor element 10 has a drain 11 and a source 12 as main electrodes, and a gate 15 as a control electrode. The drain is connected to a high-voltage terminal N1, and the source 12 is connected to a low-voltage terminal N2. When semiconductor element 10 is turned on, a current path is formed including the semiconductor element 10 in the turned-on state and a load (not shown) electrically connected to either the high-voltage terminal N1 or the low-voltage terminal N2. In this embodiment, a MOS-FET is exemplified as the semiconductor element 10 with a gate, but the semiconductor element 10 can also be an IGBT. In this case, the collector and emitter are used as the main electrodes instead of the drain and source.

[0049] The semiconductor element 10 is controlled, based on the gate-source voltage (hereinafter also referred to as "gate voltage"), to either a connected state (on state) in which current is generated between the main electrodes, i.e., between the drain 11 and the source 12, or a cut-off state in which the drain 11 and the source 12 are cut off. The driving device 100 controls the gate voltage so that the semiconductor element 10 is turned on and off in accordance with the driving control signal Ssw.

[0050] The drive control signal Ssw is set to "1" during the period when the semiconductor element 10 should be turned on, and set to "0" during the period when the semiconductor element 10 should be turned off. That is, the drive control signal is a binary signal set to either "0" which corresponds to "first level" or "1" which corresponds to "second level". For example, the control circuit 20 can be configured as a PWM pulse output circuit for controlling the semiconductor element 10 to turn on / off according to pulse width modulation (PWM) control.

[0051] Semiconductor element 10 is turned on when the gate voltage becomes a positive voltage exceeding a predetermined threshold voltage Vth. Therefore, during the period when the drive control signal Ssw is "1", the drive device 100 drives the gate 15 in a manner that makes the gate voltage a positive voltage exceeding the threshold voltage Vth. On the other hand, during the period when the drive control signal Ssw is "0", the drive device 100 drives the gate 15 in a manner that makes the gate voltage a voltage below the threshold voltage, for example, 0 or a negative voltage.

[0052] When the drive control signal Ssw changes from "0" to "1", in order to perform the turn-on operation that changes the semiconductor element 10 from the off state to the on state, the drive device 100 drives the gate 15 in a manner that increases the gate voltage. That is, when turned on, the drive device 100 charges the gate 15.

[0053] In contrast, when the drive control signal Ssw changes from "1" to "0", in order to perform the disconnection operation that changes the semiconductor element 10 from the on state to the off state, the drive device 100 drives the gate 15 by reducing the gate voltage. That is, when disconnected, the drive device 100 discharges the gate 15.

[0054] It is known that during the switching operation (i.e., the on and off operations) of the semiconductor element 10, the semiconductor element 10 consumes energy. This energy consumption will be referred to as switching loss. Switching loss also contributes to the heating of the semiconductor element 10; therefore, the lower the switching loss, the better.

[0055] Figure 2 This is a general waveform diagram illustrating the normal switching operation of a semiconductor element. As the semiconductor element 10 is turned on, as described above, current flows through the semiconductor element 10 via a current path including a load (not shown). Furthermore, with... Figure 2 The voltages and currents in the following waveforms represent voltages and currents measured from the outside of the semiconductor element 10 via the gate terminal, drain terminal, and source terminal.

[0056] Reference Figure 2 Before time ts, semiconductor element 10 is in a cut-off state where the main electrodes (drain-source) are disconnected. The drain-source voltage Vds (hereinafter referred to as "drain voltage Vds"), which is the voltage between the main electrodes, is (Vdd-Vss), and the drain-source current Id (hereinafter referred to as "drain current Id"), which is the current between the main electrodes, is 0.

[0057] At time ts, in response to the drive control signal Ssw changing from "0" to "1", the drive device 100 begins charging the gate 15. That is, the turn-on operation begins from time ts. For example, during the period when Ssw = "1", the gate 15 is connected to the power supply node supplying the predetermined turn-on voltage VH. As a result, the gate voltage begins to rise from time ts.

[0058] At time ta, the gate voltage Vg exceeds the threshold voltage Vth, causing the drain voltage Vds to begin decreasing and the drain current Id to begin increasing. After time ta, the drain voltage Vds gradually decreases and the drain current Id gradually increases, causing the semiconductor device 10 to gradually turn on.

[0059] After time ts, the gate voltage Vg rises as the parasitic capacitance of gate 15 charges. Therefore, even if charging of gate 15 begins according to the change in the drive control signal Ssw, the gate voltage Vg does not rise immediately, but instead exhibits the following behavior: Figure 2 The voltage action shown.

[0060] It is known that the parasitic capacitance (gate capacitance) of gate 15 is not constant and is dependent on the drain voltage Vds. In particular, as the drain voltage Vds decreases, the capacitance between the gate and the drain, i.e., the feedback capacitance, is added to the gate capacitance as an apparent gate capacitance (the so-called mirror capacitance).

[0061] The aforementioned mirror capacitance exhibits drain voltage dependence, increasing as the drain voltage Vds decreases, but ceasing to increase once Vds has sufficiently decreased, and not increasing further beyond that point. Therefore, the gate voltage Vg does not change uniformly. During the period tb to tc, which corresponds to the time before the mirror capacitance stops increasing, a period known as the mirror period 200 occurs where the gate voltage Vg does not rise. That is, the start and end times of the mirror period are times tb and tc, respectively. Hereinafter, the gate voltage Vg during the mirror period 200 will also be referred to as the mirror voltage Vp.

[0062] During the mirroring period 200, the drain voltage Vds continues to decrease, but approximately becomes Vds = 0 at the end of the mirroring period 200. Therefore, at the time tc at the end of the mirroring period 200, the main electrodes of the semiconductor element 10 are switched on (drain-source), and the switching ends. After the mirroring period 200 ends, the gate voltage Vg continues to rise, and then reaches a predetermined voltage (the charging voltage provided by the driving device 100) and saturates.

[0063] Both the drain current Id and the drain voltage Vds have finite values, so when switched on, the semiconductor element 10 consumes power equivalent to their product (Vds·Id). Before time ta (before switching on), the drain current Id is cut off (Id = 0), so the switching power Psw = 0. However, after time ta, (Vds·Id) > 0, resulting in power loss. Figure 2 In this context, the integral value of the power loss during connection is expressed as "occurrence loss". This occurrence loss is equivalent to the switching loss mentioned above.

[0064] After the mirror period 200 ends, the drain voltage Vds = 0, so it becomes (Vds·Id) = 0 again. Therefore, it can be understood that the switching loss Lsw, obtained by integrating (Vds·Id) over the time period ta to tc, is the energy consumed during the switching of semiconductor element 10. That is, after time tc when Vds = 0, i.e. after the mirror period 200, no power loss occurs.

[0065] exist Figure 3 The diagram shows a typical operating waveform in the case of an overcurrent occurring in response to the switching on of semiconductor element 10 (hereinafter also referred to as the switching operation under abnormal conditions). Figure 3In the example of overcurrent, the waveform of a short circuit path is shown when the semiconductor element 10 is turned on.

[0066] exist Figure 3 In the process, the behavior of the gate voltage Vg, drain voltage Vds, and drain current Id from time ts to time ta is related to... Figure 2 (Under normal conditions) the same, but the behavior of the gate voltage Vg after time ta is the same. Figure 2 (Under normal circumstances) significantly different. Specifically, after time ta, including... Figure 2 During the same time intervals tb to tc, the gate voltage Vg continues to rise until it reaches a predetermined voltage (using the charging voltage provided by the drive device 100).

[0067] The reason is that at time tb, semiconductor element 10 is switched on, forming a short circuit path, so the drain voltage Vds hardly changes, and no short circuit occurs. Figure 2 The mirror period is 200. That is, the feedback capacitance, which is the capacitance between the gate and the drain, does not change, so the parasitic capacitance (gate capacitance) of the gate 15 does not increase, but remains approximately constant. Therefore, the gate capacitance when a short circuit path is formed by turning on the semiconductor element 10 is compared to that during normal turn-on operation ( Figure 2 () is a smaller value.

[0068] exist Figure 4 The figure shows a graph illustrating the relationship between the gate voltage Vg and the drain current Id when a short-circuit current flows through the semiconductor element 10.

[0069] As from Figure 4 As understandable, the drain current Id varies depending on the gate voltage Vg. Specifically, it exhibits the characteristic that the drain current Id increases as the gate voltage Vg increases. Therefore, during the turn-on operation of semiconductor device 10 in case of an abnormality, as... Figure 3 As shown in the waveform example, as the gate voltage Vg increases during the continuous charging of the gate 15 using the drive circuit 150, the drain current Id also continuously increases. Furthermore, when the gate voltage Vg saturates, the drain current Id also saturates depending on the magnitude of the gate voltage Vg.

[0070] Therefore, as Figure 3 As shown, the loss of the semiconductor element when an overcurrent occurs due to the semiconductor element 10 being switched on is compared to... Figure 2 The normal switching operation shown becomes extremely large. If the energy loss at this time exceeds the breakdown energy of semiconductor element 10, semiconductor element 10 will break down.

[0071] Typically, a protection circuit is configured for semiconductor element 10 to prevent breakdown due to overcurrent. This protection circuit is used to disconnect or interrupt the path of short-circuit current in response to the detection of overcurrent. However, as mentioned above, in abnormal situations where the time from the start of switching on to the occurrence of losses reaching the breakdown energy of semiconductor element 10 is short, it is possible that semiconductor element 10 will break down before the protection circuit can effectively operate.

[0072] Furthermore, when semiconductor element 10 is normally switched on, the drain current Id does not... Figure 4 The dependence on gate voltage Vg is shown. Therefore, in Figure 2 In the operating waveform, after the mirror period 200, the gate voltage Vg rises, while the drain current Id does not increase, but maintains the current value during the mirror period 200.

[0073] exist Figure 2 During the normal switching operation shown, the higher the switching speed, the lower the power loss generated when the semiconductor element 10 is switched on. On the other hand, in Figure 3 During the abnormal turn-on operation shown, the higher the switching speed, the faster the gate voltage rises. As a result, the drain current Id increases, and therefore the rate of increase in losses also increases. Consequently, the higher the switching speed, the shorter the time from the start of turn-on to the time when losses occur and reach the breakdown energy of semiconductor element 10.

[0074] That is, increasing the switching speed of semiconductor element 10 reduces losses during normal operation, but on the other hand, it increases the likelihood of semiconductor element 10 breaking down during abnormal events accompanied by overcurrent. In Embodiment 1, a switching control during turn-on is described to improve this trade-off.

[0075] exist Figure 5 The diagram shows a block diagram illustrating a structural example of the drive device 100 according to Embodiment 1. Figure 6 In the middle, it is shown that by Figure 5 The diagram shows the waveform of the semiconductor element in normal turn-on operation when the drive device 100 performs conduction and cut-off control.

[0076] Reference Figure 5 The drive unit 100 has a drive adjustment section 110 and a drive circuit 150.

[0077] According to Figure 6 as well as Figure 2As can be understood from the comparison, when the drive control signal Ssw transitions from "0" to "1", the drive device 100 of Embodiment 1 drives the semiconductor element 10 in a manner that sets a voltage reduction period 210 during which the drive control signal Ssw is maintained at "1" while the drive signal Sdr is set to "0". Figure 6 As shown, during the voltage reduction period 210, the semiconductor element 10 is driven in a manner that causes the gate voltage Vg to decrease.

[0078] like Figure 5 As shown, the drive adjustment unit 110 generates a voltage drop period 210 based on the drive control signal Ssw. Figure 6 The drive signal Sdr is the driving signal. The drive adjustment unit 110 includes an edge detection unit 120, a delay circuit 130, a memory 135, an insertion pulse generation unit 140, and a signal synthesis unit 145. The functions of each element of the drive adjustment unit 110 can be implemented by dedicated electronic circuits (hardware) or by program processing (software).

[0079] Furthermore, memory 135 is a concept representing elements of recording time, as described later, pre-stored a predetermined length (time length) of elapsed time from the start of connection. Specifically, memory 135 is configured to store separately defined... Figure 6 The voltage drop period 210 is defined by the start and end timing durations Ta and Tb. Specifically, between Ta and Tb, the relationship Tb > Ta holds.

[0080] Furthermore, the memory 135 can be configured to include a digital circuit that stores Ta and Tb as digital values. Alternatively, the memory 135 can also be configured to include an analog circuit that imparts a delay time equivalent to Ta and Tb, determined by the circuit constants of passive components or the number of stages of the inverter.

[0081] When the drive control signal Ssw changes from "0" to "1" at time ts, the edge detection unit 120 detects the turn-on command and generates a single trigger pulse. That is, time ts corresponds to the start-on timing. The single trigger pulse from the edge detection unit 120 is input to the delay circuit 130. Then, the edge detection unit 120 transmits the drive control signal Ssw to the signal synthesis unit 145.

[0082] The delay circuit 130 generates a first pulse P1 that delays Ta from the single trigger pulse from the edge detection unit 120 and a second pulse P2 that delays Tb from the single trigger pulse from the edge detection unit 120, and inputs them to the insertion pulse generation unit 140.

[0083] The insertion pulse generation unit 140 can use the first pulse P1 and the second pulse P2 to detect the start and end timing of the voltage drop period 210, respectively. For example, during the turn-on operation, the insertion pulse generation unit 140 generates a cutoff pulse signal Pof, which is set to "0" during the period from the reception of the first pulse P1 to the reception of the second pulse, and set to "1" during other periods.

[0084] according to Figure 2 The waveform shown is the normal turn-on operation of semiconductor element 10 when the drive signal Sdr = "1" is fixed after time ts. The start and end timings of the voltage drop period 210 are set to lengths Ta and Tb, respectively. In Embodiment 1, it is determined that the voltage drop period 210 is set after the mirror period 200 (times tb to tc). Furthermore, the length of the voltage drop period 210, i.e., (Tb-Ta), is set in such a way that the gate voltage Vg transitions to a drop during the period.

[0085] Figure 5 The signal synthesis unit 145 generates a drive signal Sdr by performing a logical AND operation on the drive control signal Ssw and the cutoff pulse signal Pof from the insertion pulse generation unit 140. The result is as follows: Figure 6 As shown, the waveform is as follows: during the period from time ts to time t1 after time length Ta to time t2 after time length Tb, the drive signal Sdr is set to "0", and during other periods it is set to "1". Therefore, a voltage reduction period 210 is set for the drive signal Sdr.

[0086] Figure 5 The drive circuit 150 has a transistor 151 connected between a power supply node 161 and a gate 15, and a transistor 152 connected between the gate 15 and a power supply node 162. Power supply node 161 is supplied with a turn-on voltage VH (VH>Vth) as a positive voltage for charging the gate 15. Power supply node 162 is supplied with a cutoff voltage VL for turning off the semiconductor element 10. In this embodiment, the cutoff voltage VL is set to a negative voltage relative to the source, but a voltage Vss at the same potential as the source can also be used. Figure 1 That is, power node 162 corresponds to one embodiment of the "first voltage terminal", and power node 161 corresponds to one embodiment of the "second voltage terminal". In addition, the cutoff voltage VL and the turn-on voltage VH correspond to the "first voltage" and the "second voltage", respectively.

[0087] The gates of transistors 151 and 152 are connected together and are input with a drive signal Sdr from the drive adjustment unit 110. During the period when the drive signal Sdr = "1", transistor 151 is turned on, while transistor 152 is turned off, and gate 15 is connected to the power supply node 161 that supplies the on-state voltage VH. As a result, gate 15 is charged.

[0088] On the other hand, during the period when the drive signal Sdr = "0", transistor 152 is turned on, while transistor 151 is turned off, and gate 15 is connected to power node 162 supplying the cutoff voltage VL. Therefore, it can be understood that during the voltage drop period 210, gate 15 is temporarily discharged.

[0089] Next, use Figure 6 This describes the voltage and current waveforms of the semiconductor element 10 that is normally turned on by the drive device 100 of Embodiment 1.

[0090] During the period from time ts to time t1, which begins the voltage drop period 210, the drive signal Sdr is set to "1" according to the drive control signal Ssw. Therefore, during times ts to t1, the waveforms of the gate voltage Vg, drain voltage Vds, and drain current Id are similar to those of the previous period. Figure 2 The same. The result, even... Figure 6 In the middle, when in with Figure 2 When ts is turned on by the instruction at the same time, the gate voltage Vg is in the same position as... Figure 2 At the same time, ta exceeds the threshold voltage Vth, and in conjunction with... Figure 2 During the same time interval tb~tc (mirror period 200), the voltage remains constant, and then the forward conduction voltage VH rises.

[0091] Corresponding to such a shift in gate voltage Vg, and with Figure 2 Similarly, the drain voltage Vds begins to decrease from time ta, while the drain current Id begins to increase. Furthermore, at time tc, at the end of the mirror period 200, it decreases to Vds = 0. Therefore, the losses occurring up to this point are related to... Figure 2 Equivalent value.

[0092] exist Figure 6 During the voltage reduction period 210 set after the mirroring period 200, the drive signal Sdr is set to "0", so the drive circuit 150 discharges the gate 15 by turning on the transistor 152. As a result, the gate voltage Vg decreases during the period from time t1 to t2.

[0093] After time t2, the drive signal Sdr is set to "1" again, so the drive circuit 150 charges the gate 15 through the conduction of transistor 151. As a result, the gate voltage Vg rises again toward the conduction voltage VH.

[0094] Here, the voltage drop period 210 is set to a short duration such that the gate voltage Vg does not drop below the mirror voltage Vp during this period. As a result, the situation where the gate voltage Vg falls below the mirror voltage Vp and the semiconductor element 10 switches to a turn-off operation is avoided.

[0095] Therefore, in Figure 6 In the process, during the voltage drop period 210 (times t1 to t2) and after it ends (after time t2), the waveforms of the drain current Id and drain voltage Vds are also similar to those of the drain voltage Vds. Figure 2 same.

[0096] Thus, by adjusting the drain voltage Vds and drain current Id of the semiconductor element 10 normally turned on by the driving device 100 of Embodiment 1, the driving signal Sdr is maintained at "1" in the general case where the voltage drop period 210 is not provided. Figure 2 The same applies. As a result, it is understandable that even if the voltage drop period is set to 210, the losses during normal operation do not increase.

[0097] exist Figure 7 The diagram shows the operating waveform of the semiconductor element 10, which is switched on by the drive device 100 of Embodiment 1, during an abnormality. That is, in... Figure 7 In, with Figure 3 Similarly, the waveforms of voltage and current are shown in response to the switching on of semiconductor element 10 starting from time ts, in the case of overcurrent due to the formation of a short circuit path.

[0098] like Figure 7 As shown, with Figure 6 Similarly, the drive signal Sdr is set to "1" during the period from ts to t1, then set to "0" during the period from t1 to t2, and then set to "1" again after t2. Thus, when the semiconductor element 10 is turned on, the drive signal Sdr is set to "1". Figure 6 The same voltage drop period 210. That is, the drive device 100 of Embodiment 1 in normal operation ( Figure 6 ) and abnormal situations ( Figure 7 During the period, the drive signal Sdr is set together.

[0099] exist Figure 7 During the period from ts to t1, that is, from the start of the turn-on until the start of the voltage drop period 210, the waveforms of the gate voltage Vg, drain voltage Vds, and drain current Id are similar to those of the gate voltage Vg, drain voltage Vds, and drain current Id. Figure 3 same.

[0100] However, in Figure 7In this process, by setting a voltage reduction period 210, during the period from time t1 to t2, the gate 15 is discharged through the drive circuit 150, and the gate voltage Vg decreases. Furthermore, in... Figure 7 In the event of an anomaly, the mirroring period 200 (as is normal) does not occur. Figure 2 as well as Figure 6 Therefore, the charging charge of gate 15 at time t1 is greater than that at normal time ( Figure 2 as well as Figure 6 The time t1 is shorter. Therefore, if the voltage drop period 210 is set with the same period length, the amount of reduction in the gate voltage Vg during this voltage drop period 210 will become greater than in normal conditions. As a result, in Figure 8 In the action waveform example, with Figure 6 Unlike the voltage drop phase 210, the gate voltage Vg decreases compared to the mirror voltage Vp.

[0101] During the voltage reduction period 210, in response to the aforementioned decrease in gate voltage Vg, the drain voltage Vds and drain current Id behave as follows: Figure 3 Compared to this, changes occur. Specifically, it is understandable that the drain current Id changes according to... Figure 4 The characteristic relationship shown is reduced. As a result, during the voltage reduction period 210, the increase in losses is significantly suppressed. In addition, with the decrease in drain current Id, the drain voltage Vds increases instantaneously due to the surge voltage caused by the parasitic inductance in the current path including semiconductor element 10 (typically the parasitic inductance of wiring).

[0102] Here, as according to Figure 3 as well as Figure 7 As can be understood from the differences in the progression of losses, when the semiconductor element 10 is turned on by the drive device 100 of Embodiment 1, by setting a voltage drop period 210, the time required until the losses exceed the breakdown energy of the semiconductor element 10 can be extended. Therefore, the possibility of the semiconductor element 10 breaking down before the aforementioned protection circuit effectively operates can be reduced.

[0103] Thus, according to the drive device 100 of embodiment 1, by setting a timing voltage drop period 210 corresponding to the period after the mirroring period 200 during the turn-on operation of the semiconductor element 10, the switching of the semiconductor element can be controlled in a way that reduces the possibility of breakdown during overcurrent abnormalities while suppressing the impact on switching losses during normal operation.

[0104] As can be understood from the above explanation, by extending the voltage drop period 210, the reduction effect of losses during abnormal conditions is improved. On the other hand, the upper limit of the duration of the voltage drop period 210 is limited to ensure that the gate voltage Vg does not drop to the value of the mirror voltage Vp during normal operation. In addition, the start timing of the voltage drop period 210 during the turn-on operation should be set after the mirror period 200 ends, and on the other hand, in order to suppress the rise of the drain current Id during abnormal conditions, it is best not to set it to be too delayed.

[0105] However, the action during switching on varies depending on the characteristics of the semiconductor element 10. Therefore, it is conceivable that the optimal values ​​for the start timing and end timing (i.e., start timing and duration) of the voltage drop period 210 will differ depending on the characteristics of the semiconductor element 10. Therefore, it is preferable to determine the aforementioned optimal values ​​suitable for the characteristics of the semiconductor element 10 in advance through actual testing or simulation, using the semiconductor element 10 as the object of switch control executed by the drive device 100 in such actual testing or simulation. By setting the time lengths Ta and Tb pre-stored in the memory 135 corresponding to the pre-determined optimal values, at least one of the start timing and duration of the voltage drop period 210 can be appropriately set to achieve the effects of Embodiment 1 described above.

[0106] A variation of implementation method 1.

[0107] exist Figure 8 The diagram shows the operation waveform of a semiconductor element that is switched on by the drive device of the modified embodiment 1 when there is an abnormality.

[0108] according to Figure 8 as well as Figure 7 As can be understood by comparison, in a variation of Embodiment 1, the point in which the voltage reduction period 210 includes multiple segmented reduction periods 211, 212 is different from that in Embodiment 1.

[0109] exist Figure 8 In the example, the start and end timings of the segment reduction period 211 are determined by the time lengths Ta1 and Tb1 elapsed from the start turn-on time (time ts). Similarly, the start and end timings of the segment reduction period 212, set after the segment reduction period 211, are determined by the time lengths Ta2 and Tb2 elapsed from the start turn-on time (time ts). <Tb1<Ta2<Tb2)。

[0110] The result includes the setting of the reduction periods 211 and 212 from time t1 to the end of the period. Figure 6 as well as Figure 7The same time t2 is the period after time t2#. In this way, by setting the voltage drop period 210 to include multiple segmented drop periods 211, 212, the period of drain current Id decrease and the period of surge voltage occurrence are also segmented. As a result, the amount of change (rise) of drain voltage Vds in the voltage drop period 210 can be suppressed.

[0111] Furthermore, in a variation of Implementation 1, the voltage reduction period 210 also occurs during the mirroring period 200. Figure 2 as well as Figure 6 After completion, it also needs to be configured so that the gate voltage Vg does not drop to the mirror voltage Vp under normal conditions. Therefore, although omitted in the illustration, semiconductor element 10 follows... Figure 8 The waveforms of the drain voltage Vds and drain current Id when the drive signal Sdr is normally turned on can be compared with... Figure 6 (Implementation Method 1) is the same.

[0112] The driving device of the modified embodiment 1, for example, can be driven by making Figure 5 The structure shown is implemented as follows. First, the time lengths Ta1, Tb1, Ta2, and Tb2 are pre-stored in the memory 135. The delay circuit 130 operates in response to the time lengths Ta1, Tb1, Ta2, and Tb2 elapsed from time ts, inputting a total of four pulses to the insertion pulse generation unit 140. Then, the insertion pulse generation unit 140 generates a pulse based on these four pulses. Figure 8 The timing of the segmentation reduction periods 211 and 212 is set to "0" respectively, while the cutoff pulse signal Pof is set to "1" during other periods. This allows the signal synthesis unit 145 to generate a signal. Figure 8 The driving signal Sdr is shown.

[0113] In addition, Figure 8 The example given is that voltage reduction period 210 includes two segmented reduction periods 211 and 212, but it is also possible to set the number of segments to more than three.

[0114] As explained above, the drive device according to the modified example of Embodiment 1, in addition to the effects described in Embodiment 1, can also suppress the surge voltage during the voltage drop period 210 in the switching operation when an overcurrent abnormality occurs.

[0115] Implementation method 2.

[0116] As can be understood from the description in Embodiment 1 and its variations, the setting of the start timing and duration of the voltage drop period 210 is important in the driving device of this embodiment. In Embodiment 2, a technique for variably adjusting the voltage drop period 210 using information related to the operating state of the semiconductor element 10 (at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj) will be described.

[0117] exist Figure 9 The diagram shows a block diagram illustrating a structural example of the drive device 101 in Embodiment 2.

[0118] like Figure 9 As shown, the drive device 101 of Embodiment 2 is different from the drive device 100 of Embodiment 1. Figure 5 The structure of the drive adjustment unit 111 differs from that of the drive adjustment unit 110 in that it is replaced by the drive adjustment unit 111. The drive adjustment unit 111 differs from the drive adjustment unit 110 in that the external interface circuit 170 is added to it.

[0119] The external interface circuit 170 inputs the detection value detected by the detector 18 disposed on the semiconductor element 10. The detector 18 detects at least one of the following: gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj, which are information quantities ST related to the operating state of the semiconductor element 10 described above. The functions of the edge detection unit 120, the insertion pulse generation unit 140, and the signal synthesis unit 145 in the drive adjustment unit 110 are the same as in Embodiment 1, so they will not be described in detail again.

[0120] In the driving device 101 of Embodiment 2, the driving adjustment unit 110 replaces the delay circuit 130 in Embodiment 1. Figure 5 The circuit includes a delay circuit 131. The delay circuit 131 obtains the value of the aforementioned information quantity ST via an external interface circuit 170. Furthermore, the delay circuit 131 has the function of variably adjusting at least one of the start timing and duration of the voltage drop period 210 based on the information quantity ST. For example, the delay circuit 131 is configured to generate a first pulse P1 and a second pulse P2 according to a scheme that corrects at least one of the durations Ta and Tb of the voltage drop period 210 based on the information quantity ST.

[0121] The insertion pulse generation unit 140 uses the first pulse P1 and the second pulse P2 from the delay circuit 131 to generate a cutoff pulse signal Pof, thereby enabling the drive device 101 to variably adjust at least one of the start timing and duration of the voltage drop period 210 of the drive signal Sdr according to the information amount ST.

[0122] The switching operation of semiconductor element 10 varies with the characteristic deviations of semiconductor element 10 and changes in the operating environment such as temperature. Therefore, when the start and end timings of the voltage drop period 210 are fixed, a margin is required that includes an estimate of the changes in the switching operation of semiconductor element 10 caused by the aforementioned characteristic deviations and operating environment.

[0123] Therefore, in Embodiment 2, information related to the operating state of the semiconductor element 10 is fed back to the drive device 101 via the external interface circuit 170, and at least one of the start timing and end timing of the voltage drop period 210 is variably adjusted in accordance with the changes in the switching operation, thereby achieving optimal switching operation.

[0124] Next, specific examples of the variable adjustment of 210 during the voltage reduction period of the information quantity ST will be explained in turn.

[0125] As the first example, the information quantity ST can be obtained by using the drain voltage Vds of semiconductor element 10.

[0126] exist Figure 10 The diagram shows a typical drain voltage-drain current characteristic of semiconductor element 10.

[0127] like Figure 10 As shown, the semiconductor element 10 has a gate voltage Vg ( Figure 10 The drain voltage-drain current characteristics vary depending on the gate voltage (Vg1 to Vg5). However, regardless of the gate voltage Vg, the drain voltage Vds increases as the drain current Id increases.

[0128] exist Figure 11 The diagram shows the variable adjustment waveform used to illustrate the decrease of drain voltage Vds as information quantity ST. Figure 11 In the image, the dashed line represents the effect on the switching action of semiconductor element 10 when the drain voltage Vds becomes high before the start of the mirroring period 200.

[0129] like Figure 11 As shown, the higher the drain voltage Vds, the faster the drain current Id changes, so the mirror period 200 becomes shorter as the timing advance occurs. Consequently, the higher the drain voltage Vds, the higher the gate voltage Vg at time t1 corresponding to the pre-stored time length Ta.

[0130] Therefore, regarding the voltage drop period 210, by adjusting the time lengths Ta and Tb in a way that the higher the drain voltage Vds, the earlier the start timing (making the time length Ta smaller) and / or the longer the period (making Tb-Ta larger), at least one of the start timing and time length of the voltage drop period 210 can be made more appropriate to adapt to the actual switching operation of the semiconductor element 10. This improves the effect of extending the time required until the semiconductor element 10 experiences an overcurrent anomaly before its breakdown energy exceeds the breakdown energy of the semiconductor element 10, further reducing the likelihood of semiconductor element 10 breakdown.

[0131] exist Figure 12 The diagram shows a first flowchart illustrating the control process for variable adjustment during the reduction period in the drive device 101 of Embodiment 2. Furthermore, with... Figure 12 The process shown in the flowchart is independent. The drive device 101 can obtain the detection value detected by the detector 18, i.e., the amount of information related to the operating state of the semiconductor element, through the external interface circuit 170 at a certain period.

[0132] Reference Figure 12 The drive device 101 detects the transition of the drive control signal Ssw from "0" to "1" through step (hereinafter simply referred to as "S") 110, which is the turn-on command for the semiconductor element 10. The processing of S110 is equivalent to the function of the edge detection unit 120.

[0133] When the drive unit 101 detects an activation command (when "yes" is determined in S110), it executes the processing in S120 and S130. On the other hand, even if the activation action is temporarily completed and the processing returns to "start", the processing after S120 is not executed until an activation command is detected (when "no" is determined in S110).

[0134] In S120, the drive unit 101 determines the value of the information quantity ST used in the variable adjustment during the voltage drop period 210 based on the information quantity ST acquired at regular intervals. For example, when ST is used as information quantity... Figure 11 In the case of the drain voltage Vds before the start of the mirror period 200 as described in the text, the value of the information quantity ST used in the adjustment can be determined by extracting the detection value obtained at a predetermined timing before time ts (before the turn-on operation) or within the period from time ts to tb (after the start of the turn-on operation and before the start of the mirror period 200).

[0135] The drive unit 101 adjusts at least one of the time length Ta of a predetermined time t1 (the start timing of the voltage drop period 210) and the time length Tb of a predetermined time t2 (the end timing of the voltage drop period 210) based on the value of the information quantity ST (here, the drain voltage Vds) determined in S120. For example, when the drain voltage Vds is used as the information quantity ST, at least one of the time lengths Ta and Tb can be adjusted in such a way that the higher the drain voltage Vds, the earlier the start timing of the voltage drop period 210 and / or the longer the time length, and conversely, the lower the drain voltage Vds, the later the start timing of the voltage drop period 210 and / or the shorter the time length.

[0136] Typically, the processing in S130 can be achieved by pre-storing a lookup table or function in the memory 135 to determine the optimal values ​​of the time lengths Ta and Tb for the information quantity ST (drain voltage Vds). Furthermore, the optimal values ​​can be pre-determined through actual experiments or simulations of the switching operation of the semiconductor element 10 under varying information quantity ST (drain voltage Vds). Alternatively, if the memory 135 is configured with the aforementioned analog circuit, a variable mechanism for switching circuit constants or inverter stages for the information quantity ST (drain voltage Vds) can also be provided within this analog circuit.

[0137] In this way, by performing the processing of S120 and S130 for each turn-on command of semiconductor element 10, at least one of the start timing and duration of the voltage drop period 210 can be appropriately and variably adjusted by feeding back information related to the operating state of semiconductor element 10 (here, drain voltage Vds).

[0138] As a second example, ST, as information, can also feed back the drain current Id of semiconductor element 10.

[0139] exist Figure 13 The diagram shows the action waveform used to illustrate the variable adjustment during the decrease of drain current Id as information quantity ST. Figure 13 In the diagram, the dashed line represents the effect of the decrease in drain current Id after switching on on on the switching action of semiconductor element 10.

[0140] like Figure 13 As shown, when the drain current Id is small, the mirror voltage Vp decreases during mirroring period 200. Consequently, the timing of mirroring period 200 is advanced, and the allowable decrease in gate voltage Vg during voltage reduction period 210 becomes larger.

[0141] Therefore, regarding the voltage drop period 210, by correcting the time lengths Ta and Tb in such a way that a smaller drain current Id results in an earlier start timing (making the time length Ta smaller) and / or a longer period length (making Tb-Ta larger), at least one of the start timing and time length of the voltage drop period 210 can be made more appropriate in accordance with the actual switching operation of the semiconductor element 10.

[0142] When using the drain current Id of semiconductor element 10 as information ST, it can also be applied to Figure 12 The control processing applied in the flowchart. At this time, the drive device 101 can extract the drain current Id from the last turn-on operation of the semiconductor element 10 (after time tb) in S120, and determine the amount of information ST used in the variable adjustment during the voltage drop period 210.

[0143] Alternatively, in S120, the drain current Id can be predicted by using the current value of a load (not shown) prior to the current turn-on operation, and the amount of information ST used in the variable adjustment of 210 during the voltage drop period can be determined. In this case, the detector 18 needs to be configured corresponding to the load (not shown).

[0144] In this way, by feeding back the drain current Id of the semiconductor element 10, the position and duration of the voltage drop period 210 can be appropriately and variably adjusted.

[0145] As a third example, the information ST can also provide feedback on the temperature (element temperature) Tj of the semiconductor element 10.

[0146] exist Figure 14 In the middle, it is shown that is used for illustration Figure 4 The graph shown illustrates the temperature dependence of the gate voltage Vg versus the drain current Id when a short-circuit current flows through semiconductor element 10.

[0147] like Figure 14 As shown, when the element temperature Tj of semiconductor element 10 increases, the threshold voltage Vth of semiconductor element 10 decreases. Consequently, the characteristic line of gate voltage Vg versus drain current Id (when short-circuited) shifts to the left in the figure. That is, the drain current Id increases for the same gate voltage Vg.

[0148] exist Figure 15 The diagram shows the action waveform used to illustrate the variable adjustment during the decrease of the component temperature Tj as information quantity ST. Figure 15 In the diagram, dashed lines represent the effect of rising component temperature Tj on the switching action of semiconductor component 10.

[0149] like Figure 15As shown, the threshold voltage Vth of semiconductor device 10 decreases as the device temperature Tj increases. Furthermore, the mirror voltage Vp also changes in conjunction with the threshold voltage Vth, so the mirror voltage Vp also decreases as the device temperature rises.

[0150] As a result, the higher the component temperature Tj rises, the more... Figure 15 The earlier the timing of Vg = Vth, the earlier the timing of the start of mirror period 200, and the earlier the timing of the end of mirror period 200, the more likely it is to occur. As a result, it can be understood that as the device temperature Tj rises, the timing of the occurrence of mirror period 200 is advanced, and the allowable decrease in gate voltage Vg during voltage reduction period 210 becomes larger.

[0151] Therefore, regarding the voltage drop period 210, by adjusting the time lengths Ta and Tb in a way that advances the start timing (making the time length Ta smaller) and / or lengthens the period (making Tb-Ta larger) when the element temperature Tj rises, at least one of the start timing and time length of the voltage drop period 210 can be made more appropriate in accordance with the actual switching operation of the semiconductor element 10.

[0152] When using the element temperature Tj of semiconductor element 10 as information ST, it can also be applied to Figure 12 The control processing applied in the flowchart. At this time, in S120, for example, the drive device 101 can extract the element temperature Tj when the semiconductor element 10 is turned on (time ts), and determine the amount of information ST used in the variable adjustment during the voltage reduction period 210.

[0153] In this way, by feeding back the element temperature Tj of the semiconductor element 10, at least one of the start timing and duration of the voltage drop period 210 can be appropriately and variably adjusted.

[0154] As a fourth example, the information ST can also feed back the gate voltage Vg of the semiconductor element 10 to adjust the voltage drop period 210.

[0155] exist Figure 16 The diagram shows the action waveform used to illustrate the variable adjustment during the decrease of the gate voltage Vg as information quantity ST.

[0156] When the gate voltage Vg is used as the information quantity ST feedback, the mirror voltage Vp can be directly detected. Furthermore, by detecting the gate voltage Vg for a certain period, the start timing (time tb) and end timing (time tc) of the mirror period 200 can also be detected. Thus, the start timing of the voltage drop period 210 can be appropriately set in correspondence with the detection of the end timing of the mirror period 200.

[0157] Furthermore, by feeding back the gate voltage Vg during the voltage reduction period 210, it is possible to reliably prevent the gate voltage Vg from dropping to the mirror voltage Vp and thus ending the voltage reduction period 210.

[0158] exist Figure 17 The diagram shows a second flowchart illustrating the control process for variable adjustment during the reduction period in the drive device 101 of Embodiment 2. Figure 17 As described above, the control process when the gate voltage Vg is used as information quantity ST feedback is shown.

[0159] Reference Figure 17 The drive unit 101 communicates with Figure 5 S110 is the same as S210, which detects the drive control signal Ssw from "0" to "1", that is, the turn-on command to semiconductor element 10.

[0160] When the drive unit 101 detects an on command (when "yes" is determined in S210), it executes the processes in S220 and S230. In S220, the drive unit 101 reads the gate voltage Vg by acquiring the detection value detected by the detector 18 at regular intervals. In S230, it determines the start timing of the voltage drop period 210 by monitoring the shift of the read gate voltage Vg. For example, the start timing (time t1) of the voltage drop period 210 can be determined based on a preset optimal value of the time length (time tc to t1) from the end of the mirror period 200 to the start of the voltage drop period 210, and the start timing (time tc) of the mirror period 200 detected based on the shift of the gate voltage Vg. At the start timing of the voltage drop period 210, the drive signal Sdr in the drive unit 101 changes from "1" to "0".

[0161] Until the voltage drop period 210 begins (when S240 is determined to be "No"), the processes of S220 and S230 are repeatedly executed. After the voltage drop period 210 begins (when S240 is determined to be "Yes"), the drive device 101 executes the processes of S240 to S280 for determining the end timing of the voltage drop period 210.

[0162] In S250, the drive device 101 reads the gate voltage Vg in the same way as in S220, and in S260, compares the gate voltage Vg read in S250 with the sum of the mirror voltage Vp and the margin value ε. Based on the shift of the gate voltage Vg monitored in S230, the mirror voltage Vp can be calculated in advance before determining "yes" in S240.

[0163] Until the gate voltage Vg becomes below Vp+ε (when S260 determines "No"), the drive signal Sdr is maintained at "0" through S270, and the processes of S250 and S260 are repeatedly executed.

[0164] On the other hand, when the gate voltage Vg drops below Vp+ε (when "yes" is determined in S260), the drive device 101 changes the drive signal Sdr from "0" to "1" in S280. As a result, the voltage reduction period 210 ends.

[0165] In this way, by setting the start and end timing of the voltage drop period 210 according to the shift of the gate voltage Vg of the feedback semiconductor element 10, the start timing and duration of the voltage drop period 210 can be optimally and variably adjusted.

[0166] As explained above, according to the drive device of Embodiment 2, by feeding back information related to the operating state of the semiconductor element 10, at least one of the start timing and duration of the voltage drop period 210 can be appropriately set in accordance with the actual switching operation, which depends on the characteristic deviation of the semiconductor element 10 and changes in the operating environment such as temperature. This improves the effect described in Embodiment 1, extending the time required until the semiconductor element 10 experiences losses exceeding its breakdown energy in case of an abnormality, further reducing the possibility of semiconductor element 10 breakdown.

[0167] Furthermore, the feedback information ST can utilize at least one of the aforementioned gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj, and can also feed back multiple information quantities ST. For example, by pre-determining the optimal values ​​of the time lengths Ta and Tb for the combination of multiple information quantities ST and storing them in memory 135, it is possible to... Figure 12 The control process shown in the flowchart performs variable adjustments during the voltage reduction period 210.

[0168] Alternatively, the voltage drop period 210 can also be variably adjusted through the following combination: regarding the start timing of the voltage drop period 210, by... Figure 12 The control processing decision, on the other hand, regarding the timing of the end of the voltage drop period 210, is made through... Figure 17 The processing decisions for S250 to S280.

[0169] Furthermore, in Embodiment 2, similar to the variation of Embodiment 1, the voltage reduction period 210 can be configured using two or more segmented reduction periods. In this case, the start and end timings of each segmented reduction period can be adjusted by feeding back information related to the operating state of the semiconductor element 10.

[0170] Embodiment 3.

[0171] In Embodiment 3, switch control during the turn-off operation is described. When a semiconductor element is turned off in the event of an abnormality such as an overcurrent caused by a load short circuit, an excessive surge voltage may occur, leading to breakdown of the semiconductor element.

[0172] In Figure 18 , a general operation waveform diagram during the turn-on operation of the semiconductor element at the time of abnormality is shown. Furthermore, in the example of Figure 18 , as a scenario where the surge voltage becomes maximum, the operation waveform when the semiconductor element 10 (in the on state) included in the short-circuit path is turned off is also shown.

[0173] Referring to Figure 18 , before time te, the semiconductor element 10 is in a conductive state in which the main electrodes (drain-source) are conductive, but when the short-circuit current as described above flows, the drain current Id before the turn-off operation is a finite value corresponding to the gate voltage Vg (i.e., the on-voltage VH) according to the characteristic relationship shown in Figure 4 . Regarding the drain voltage Vds as well, while the turn-off operation starts from Vds=0 in normal conditions, the turn-off operation starts from Vds=(Vdd-Vss) when the short-circuit current flows.

[0174] At time te, in response to the drive control signal Ssw changing from "1" to "0", the drive device 100 starts discharging the gate 15. That is, the turn-off operation starts from time te. For example, while Ssw="0", the gate 15 is connected to a power supply node that supplies the off-voltage VL (here, a negative voltage). As a result, the gate voltage starts to decrease from time te. Then, at time tf, the gate voltage Vg decreases to the threshold voltage Vth, and after time tf, Vg<Vth is established.

[0175] In the short-circuit state shown in Figure 18 , similar to the turn-on operation described in Figure 3 , a mirror period in which the gate voltage Vg is maintained at a constant value does not occur. On the other hand, although illustration is omitted, during a normal turn-off operation, along with the occurrence of a mirror period similar to that in the turn-on operation shown in Figure 2 , the gate voltage Vg decreases from the on-voltage VH to the off-voltage VL. During the turn-off operation, the gate voltage Vg in the mirror period is also maintained at the mirror voltage Vp common to that during the turn-on operation.

[0176] After time te, the drain current Id decreases as the gate voltage Vg decreases. Then, after time tf when Vg<Vth is established, the drain current Id becomes 0 (Id=0), and the semiconductor element 10 enters the off state.

[0177] At this time, a surge voltage proportional to the rate of decrease of the drain current Id (dId / dt) is superimposed on the drain voltage Vds. If the drain voltage Vds exceeds the withstand voltage due to the effect of this surge voltage, the semiconductor device 10 will break down. Therefore, in order to reduce the possibility of breakdown of the semiconductor device 10 under abnormal conditions, during the disconnection operation starting from the short-circuit state, it is required that the drain voltage Vds with the surge voltage superimposed be suppressed to below the aforementioned withstand voltage.

[0178] To suppress surge voltage and reduce the rate of decrease in drain current Id, a slower switching speed, i.e., a slower decrease in gate voltage, is more advantageous. On the other hand, similar to the turn-on operation, reducing the switching speed of semiconductor element 10 increases losses during normal turn-off operations. Thus, while increasing the switching speed of semiconductor element 10 during turn-off operations reduces losses during normal operation, it increases the likelihood of semiconductor element 10 breakdown in the event of an overcurrent-related anomaly. In Embodiment 3, a switch control during turn-off to improve this trade-off will be described.

[0179] exist Figure 19 The diagram shows a block diagram illustrating a structural example of the drive device 102 in Embodiment 3. Figure 20 The diagram shows the waveform of the turn-on operation during an abnormality (short circuit state) of the semiconductor element controlled by the drive device 102 of Embodiment 3.

[0180] Reference Figure 19 The drive unit 102 has a drive adjustment section 112 and a drive circuit 150.

[0181] According to Figure 20 and Figure 18 As can be understood by comparison, the driving device 102 of Embodiment 3 drives the semiconductor element 10 in a manner that sets a voltage rise period 410. During the voltage rise period 410, when the driving control signal Ssw transitions from "1" to "0" and is disconnected, the driving control signal Ssw is maintained at "0", while the driving signal Sdr is set to "1". Figure 20 As shown, the semiconductor element 10 is driven in such a way that the gate voltage Vg turns upward during the voltage rise period 410.

[0182] like Figure 19 As shown, the drive adjustment unit 112 generates a voltage rise period 410 as described above based on the drive control signal Ssw. Figure 20The drive signal Sdr is the driving signal. The drive adjustment unit 112 includes an edge detection unit 122, a delay circuit 132, a memory 135, an insertion pulse generation unit 142, and a signal synthesis unit 146. The functions of each element of the drive adjustment unit 112 can be implemented either by dedicated electronic circuits (hardware) or by program processing (software).

[0183] The memory 135 is configured to store separately specified... Figure 20 The time lengths Tc and Td of the start and end timings of the voltage rise period 410 are specified. That is, the relationship Td > Tc holds true between Tc and Td. The memory 135 can be configured to store the time lengths Tc and Td together with the start and end timings of the voltage drop period 210 during the specified turn-on operation in Embodiment 1 and its variations.

[0184] When the drive control signal Ssw changes from "1" to "0" at time te, the edge detection unit 122 detects the disconnect command and generates a single trigger pulse. That is, time te corresponds to the disconnect start timing. The single trigger pulse from the edge detection unit 122 is input to the delay circuit 132. Then, the edge detection unit 122 transmits the drive control signal Ssw to the signal synthesis unit 146.

[0185] The delay circuit 132 generates a third pulse P3 that delays the single trigger pulse from the edge detection unit 120 by Tc and a fourth pulse P4 that delays the single trigger pulse from the edge detection unit 120 by Td, and inputs them to the insertion pulse generation unit 142.

[0186] The insertion pulse generation unit 142 can use the third pulse P3 and the fourth pulse P4 to detect the start and end timing of the voltage rise period 410, respectively. For example, during the disconnection operation, the insertion pulse generation unit 142 generates a conduction pulse signal Pon, which is set to "1" during the period from the receipt of the third pulse P3 to the receipt of the fourth pulse P4, and set to "0" during other periods.

[0187] The signal synthesis unit 146 generates a drive signal Sdr by performing a logical OR operation on the drive control signal Ssw and the turn-on pulse signal Pon from the insertion pulse generation unit 142. The result is as follows: Figure 20 As shown, during the period when the drive control signal Ssw is set to "0", the drive signal Sdr is set to "1" during the period from time t3 to time t4, and is set to "0" during other periods. Thus, a voltage rise period 410 is set for the drive signal Sdr. The drive circuit 150 has the same characteristics as in Embodiment 1 (…). Figure 5The same structure described in the diagram discharges the gate 15 during the period when the drive signal Sdr is "0", and charges the gate 15 during the period when the drive signal Sdr is "1".

[0188] The duration of the voltage rise period 410 is set to (Td-Tc) in such a way that the gate voltage Vg transitions to the rising period. Furthermore, time t3 corresponds to the time length Tc elapsed from the time te at the start of the disconnection operation, and time t4 corresponds to the time length Td elapsed from the time te.

[0189] According to Figure 20 and Figure 18 As can be understood from the comparison, during the voltage rise period 410 set at times t3 to t4, the gate voltage Vg temporarily switches to rising. As mentioned above, the drain current Id in the short-circuit state depends on the gate voltage Vg, so during the voltage rise period 410, the gate voltage Vg rises, thus the rate of decrease of the drain current Id is moderated. Accompanying this, the surge voltage decreases, so the drain voltage Vds... Figure 18 The upward trend temporarily turns into a downward trend midway through.

[0190] As a result, the maximum value of the drain voltage Vds can be suppressed. As a result, during the disconnection operation starting from the short-circuit state, the possibility of the semiconductor device 10 breaking down due to the drain voltage Vds, which is superimposed with a surge voltage, exceeding the withstand voltage can be reduced.

[0191] According to Figure 18 as well as Figure 20 As can be understood from the behavior of the drain voltage Vds shown, the voltage rise period 410 needs to be set in the middle of the surge voltage rise period, that is, during the period when the drain current Id decreases (until it decreases to 0), preferably at an earlier timing in the disconnection operation. Therefore, it is envisioned that the voltage rise period 410 during the disconnection operation is different from the voltage drop period 210 during the turn-on operation, and is set at a timing earlier than the mirror period 200 in the normal disconnection operation, starting from time te.

[0192] exist Figure 20 In the process, by setting the voltage rise period 410, the timing of the gate voltage Vg decreasing to the threshold voltage Vth becomes more precise than... Figure 18 The time tf is the same as the time tf' delayed from time tf. The increase in the delay time from time tf to time tf', i.e. the time required until the disconnection action is completed, depends on the length of the voltage rise period 410.

[0193] Therefore, including the normal disconnection operation, the losses during the disconnection operation may increase due to the aforementioned delay time. However, the duration of the voltage rise period 410 can be set as short as possible within a range that allows the rise of the drain voltage Vds to be temporarily stopped by the rise of the gate voltage Vg. Therefore, by minimizing the aforementioned delay time, the increase in losses caused by the application of the voltage rise period 410 can be suppressed. It is understood that, at least compared to the case where the switching speed is reduced overall during the disconnection operation to reduce the rate of decrease of the drain current Id, i.e., the discharge speed of the gate 15 performed by the drive circuit 150 is reduced, the increase in losses due to the surge voltage suppression effect is significantly suppressed.

[0194] Thus, according to the drive device 102 of embodiment 3, by providing a short pulse-shaped voltage rise period 410 during the disconnection operation of the semiconductor element 10, the increase in losses during normal operation can be suppressed, and at the same time, the possibility of semiconductor element 10 breakdown is reduced by suppressing the surge voltage during abnormal overcurrent. Therefore, during the disconnection operation, the switching of the semiconductor element can be controlled in a way that reduces the possibility of breakdown during abnormal overcurrent while suppressing the impact on switching losses during normal operation.

[0195] Furthermore, the disconnection action of the semiconductor element 10 varies depending on the characteristics of the semiconductor element 10. Therefore, the optimal values ​​for the position and duration of the voltage rise period 410 (i.e., the start timing and end timing) are preferably determined in advance through actual testing or simulation, using the semiconductor element 10 as the object of switch control executed by the drive device 102. By setting the time lengths Tb and Tc pre-stored in the memory 135 corresponding to the pre-determined optimal values, the voltage rise period 410 can be set at an appropriate position and duration to achieve the effects of Embodiment 3 described above.

[0196] Furthermore, in Embodiment 3, the voltage drop period 210 segmentation setting in the variation of Embodiment 1 can also be applied to the voltage rise period 410. That is, the voltage rise period 410 can be segmented into any number of segments.

[0197] Implementation method 4.

[0198] In Embodiment 4, a technique is described that uses information related to the operating state of the semiconductor element 10 (at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj) to variably set the voltage rise period 410, similar to Embodiment 2.

[0199] exist Figure 21The diagram shows a block diagram illustrating a structural example of the drive device 103 in Embodiment 4.

[0200] like Figure 21 As shown, the drive device 103 of Embodiment 4 is different from the drive device 102 of Embodiment 3. Figure 19 The structure of the drive adjustment unit 113 differs from that of the drive adjustment unit 112 in that it is replaced by the drive adjustment unit 113. The drive adjustment unit 113 differs from the drive adjustment unit 112 in that it has an external interface circuit 170 added to it.

[0201] and Figure 9 Similarly, the external interface circuit 170 inputs a detection value (detector 18) of at least one of the following: gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj, which are information quantities ST related to the operating state of the semiconductor element 10. The functions of the edge detection unit 122, the insertion pulse generation unit 142, and the signal synthesis unit 146 in the drive adjustment unit 112 are the same as in Embodiment 3, so they will not be described in detail again.

[0202] In the drive device 103 of Embodiment 4, the drive adjustment unit 112 replaces the delay circuit 132 in Embodiment 3. Figure 5 The circuit includes a delay circuit 133. The delay circuit 133 obtains the value of the aforementioned information quantity ST via an external interface circuit 170. Furthermore, the delay circuit 133 has the function of variably adjusting at least one of the start timing and duration of the voltage rise period 410 based on the information quantity ST. For example, the delay circuit 133 is configured to generate a third pulse P3 and a fourth pulse P4 according to a scheme that corrects at least one of the duration Tc and Td of the predetermined voltage rise period 410 based on the information quantity ST.

[0203] By generating a turn-on pulse signal Pon using the third pulse P3 and the fourth pulse P4 from the delay circuit 133 by the insertion pulse generation unit 142, at least one of the start timing and duration of the voltage rise period 410 set during the turn-on operation can be variably adjusted in the drive device 103 according to the amount of information ST, similar to the voltage drop period 210 during the turn-on operation (Embodiment 2).

[0204] In semiconductor device 10, the higher the drain voltage Vds before the disconnection begins (before time te), the better. Figure 20 The longer the time from time te to tf′ increases, the longer the time required for the disconnection operation becomes. Similarly, for the drain current Id, the larger the drain current Id before the disconnection begins (before time te), the longer the time required for the semiconductor element 10 to disconnect (the time from time te to tf′) becomes.

[0205] Therefore, when the drain voltage Vds and drain current Id before the disconnection starts (before time te) are used as information ST, at least one of the time lengths Tc and Td can be adjusted in such a way that the higher the drain voltage Vds or the larger the drain current Id, the earlier the start timing of the voltage rise period 410 is set and / or the longer the duration of the voltage rise period 410 is.

[0206] Additionally, as in Figure 4 As explained in [reference needed], there is a correlation between the gate voltage Vg and the drain current Id under short-circuit conditions, so the gate voltage Vg before the start of disconnection (before time te) can also be used as information ST. For example... Figure 4 As shown, the higher the gate voltage Vg, the larger the drain current Id becomes. Therefore, at least one of the time lengths Tc and Td can be adjusted in such a way that the higher the gate voltage Vg at the start of disconnection (time te), the earlier the start timing of the voltage rise period 410 is set and / or the longer the duration of the voltage rise period 410 is.

[0207] As described in Embodiment 2, as the element temperature Tj increases, the threshold voltage Vth of the semiconductor element 10 decreases. Therefore, the lower the element temperature Tj, the shorter the time required for the semiconductor element 10 to disconnect. Figure 20 The longer the time length (te~tf′) becomes, the earlier the start timing of the voltage rise period 410 can be set and / or the duration of the voltage rise period 410 can be increased. Therefore, at least one of the time lengths Tc and Td can be adjusted in such a way that the lower the component temperature Tj at the start of disconnection (time te), the earlier the start timing of the voltage rise period 410 is set and / or the longer the duration of the voltage rise period 410 is increased.

[0208] exist Figure 22 The diagram shows a flowchart illustrating the control process of variable adjustment during the rise of information about the operating state of a semiconductor element in the drive device of Embodiment 4. Furthermore, with... Figure 22 The process shown in the flowchart is independent, in which the drive device 101 can obtain the detection value obtained by the detector 18, i.e. the amount of information related to the operating state of the semiconductor element, through the external interface circuit 170 at certain intervals.

[0209] Reference Figure 22 In S150, the drive device 103 detects the drive control signal Ssw transitioning from "1" to "0", which is a disconnect command for the semiconductor element 10. The processing in S150 is equivalent to the function of the edge detection unit 122.

[0210] When the drive unit 103 detects a disconnect command (when "yes" is determined in S150), it executes the processes in S160 and S170. On the other hand, even if the disconnection action is temporarily completed and the process returns to "start", the process after S160 is not executed until a disconnect command is detected (when "no" is determined in S150).

[0211] In S160, the drive unit 103 extracts the value of the information quantity ST used in the variable adjustment during the voltage rise period 410 from the information quantity ST acquired at a certain period. For example, as described above, the value of the information quantity ST used in the adjustment can be determined by extracting the detection value acquired at the start timing (time te) of the disconnection command or at a predetermined timing included before the start of disconnection.

[0212] In S170, the drive unit 103 adjusts at least one of the time length Ta of the predetermined time t3 (the start timing of the voltage rise period 410) and the time length Tb of the predetermined time t4 (the end timing of the voltage rise period 410) according to the value of the information amount ST determined in S160.

[0213] The processing in S170 is compatible with implementation method 2 ( Figure 12 S130 is executed in the same way. That is, typically, it can be achieved by pre-storing a lookup table or function in memory 135 for determining the optimal values ​​of the time lengths Tc and Td for the information quantity ST. The optimal values ​​of the time lengths Tc and Td in the disconnection operation can also be pre-determined through actual experiments or simulations of the switching operation of the semiconductor element 10 under the condition that each information quantity ST changes.

[0214] In S170, by feeding back multiple information quantities ST, at least one of the time lengths Tc and Td can be adjusted. In this case, it is necessary to predetermine the optimal values ​​of the time lengths Tc and Td for the combination of multiple information quantities ST.

[0215] In this way, by performing the processing of S160 and S170 for each disconnect command of semiconductor element 10, at least one of the start timing and duration of voltage rise period 410 can be appropriately and variably adjusted by feeding back information related to the operating state of semiconductor element 10 (at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj).

[0216] Therefore, according to the drive device of embodiment 4, by feeding back information related to the operating state of the semiconductor element 10, at least one of the start timing and duration of the voltage rise period 410 can be appropriately set in accordance with the actual switching operation that varies depending on the characteristic deviation of the semiconductor element 10 and the operating environment such as temperature. This improves the surge voltage suppression effect and further reduces the possibility of semiconductor element 10 breakdown.

[0217] Here, in the disconnection operation, unlike the connection operation, it is possible to distinguish between the start of a normal disconnection operation and a disconnection operation during an overcurrent anomaly at the detection time of the disconnection command, based on the amount of information ST of the semiconductor element 10 before the disconnection operation begins (in the on state). Furthermore, as mentioned above, the voltage rise period 410 may not necessarily occur after the mirror period 200 ends, which may slightly affect the switching losses (occurrence losses) during normal operation.

[0218] exist Figure 23 The diagram shows a flowchart illustrating the control process of the configuration during the voltage rise period when the drive device 103 selects the disconnection operation in Embodiment 4.

[0219] Reference Figure 23 The drive unit 103 communicates with Figure 22 S160 is the same as S250, which detects the drive control signal Ssw transitioning from "1" to "0", i.e., a disconnect command for semiconductor element 10. Furthermore, as described above, with... Figure 23 The process shown in the flowchart is independent. During the conduction state of the semiconductor element 10, the drive device 103 also acquires information related to the operating state of the semiconductor element 10 at regular intervals via the external interface circuit 170.

[0220] When the drive unit 103 detects a disconnect command (when "yes" is determined in S250), it executes the processes in S260 and S270. In S260, the drive unit 103 extracts the information ST used in the overcurrent state detection determination in S270 from the detection value of the detector 18 read from the on state of the semiconductor element 10. For example, in S260, the instantaneous value of current or voltage such as drain current Id and drain voltage Vds, or the average or maximum value over a certain period, is extracted from the detection time point (time te) of the disconnect command or prior to it.

[0221] In S270, the drive device 103 determines whether the semiconductor element 10 was in an overcurrent state before being disconnected by comparing the information amount ST extracted in S170 with a predetermined judgment value. Typically, an overcurrent state can be detected when the drain current Id is greater than the judgment value.

[0222] When the drive device 103 detects an overcurrent condition (when "yes" is determined in S270), it configures a voltage rise period 410 for the disconnection operation in S280. In S280, as in Embodiment 3, the voltage rise period 410 can be fixedly set using predetermined time lengths Tc and Td. Alternatively, in S280, by further executing... Figure 22 S160 and S170 can variably set the time lengths Tc and Td by means of feedback information ST (at least one of gate voltage Vg, gate current, drain voltage Vds, drain current Id, and device temperature Tj).

[0223] In contrast, when no overcurrent condition is detected (when "No" is determined in S270), the drive unit 103 performs a disconnection operation by not configuring the voltage rise period 410 in S290. In this case, Figure 20 In the process, the drive signal Sdr remains "0" after time te until the next turn-on command is generated.

[0224] In the driving device 103 of embodiment 4, by applying Figure 23 The control shown does not increase losses during normal disconnection when no overcurrent occurs, but can suppress surge voltage during abnormal disconnection when an overcurrent condition occurs. In particular, the timing and duration of the start point of the voltage rise period 410 can be specifically set to suppress surge voltage during abnormal conditions without worrying about increased stability losses during normal conditions, thus improving the surge voltage suppression effect. As a result, the possibility of semiconductor element 10 breakdown can be further reduced.

[0225] Furthermore, even in Embodiment 4, the voltage rise period 410 can be divided into any number of intervals. Therefore, it is expected that the surge voltage suppression effect during abnormal situations can be further improved.

[0226] In the drive devices 100-103 described in embodiments 1-4, such as in Figure 5 as well as Figure 19 As explained in the previous section, the voltage applied to the gate 15 during the voltage drop period 210 is made common to the cutoff voltage VL of the semiconductor element 10, and the voltage applied to the gate 15 during the voltage rise period 410 is made common to the on-state voltage VH of the semiconductor element 10. Therefore, it is possible to set the voltage drop period 210 and / or the voltage rise period 410 without increasing the number of stages of the voltage level applied to the gate 15 using the drive devices 100 to 103. As a result, circuit structure complexity can be avoided.

[0227] Conversely, even if a voltage different from the on-state voltage VH and the off-state voltage VL is applied to the gate 15 during each of the voltage drop period 210 and the voltage rise period 410, as long as a decrease in the gate voltage Vg occurs during the voltage drop period 210 and / or an increase in the gate voltage Vg occurs during the voltage rise period 410, the same effect as described in this embodiment can be obtained. However, when configured in this way to increase the number of voltage level stages, the structure of the drive devices 100-103, including the drive circuit 150, may become more complex.

[0228] Furthermore, as described above, in the drive devices 101-103 described in Embodiments 1-4, the functions of the drive adjustment units 110-113 can be configured using either hardware or software. In particular, when all the functions of the drive adjustment units 110-113 are implemented using software, it is also possible to use… Figure 1 The control circuit 20 shown is used as part of the function of the drive adjustment unit.

[0229] In this case, a drive signal Sdr can be configured to be directly input from the control circuit 20 to the drive circuit 150 forming the drive device 100, including a cutoff pulse corresponding to the voltage drop period 210 and / or a turn-on pulse corresponding to the voltage rise period 410. In this case, as explained in this embodiment, the drive signal Sdr and the drive control signal Ssw can be identified by comparing the number of signal level changes with the actual number of turn-on and cut-off times of the semiconductor element 10.

[0230] Furthermore, when all of the drive adjustment units 110 to 113 are implemented via software, the start timing and duration of the voltage drop period 210 and / or voltage rise period 410 can be easily adjusted. In this case, regarding the hardware, the drive circuit 150 can be specifically designed to enable the semiconductor element 10 to be turned on and off at high speed, so detailed adjustments such as gate resistor adjustment are not required, reducing the design burden. That is, by utilizing software adjustments based on simplified hardware design, the switching of the semiconductor element can be controlled in a way that simultaneously reduces switching losses during normal operation and reduces the possibility of breakdown during overcurrent abnormalities.

[0231] Furthermore, the switching of the semiconductor element 10 can be controlled by combining the drive devices 100 or 101 of embodiments 1 and 2, and the drive devices 103 or 104 of embodiments 3 and 4, by setting both the voltage drop period 210 during the turn-on operation and the voltage rise period 410 during the turn-off operation. For example, by using a selector or the like that operates according to the drive control signal Ssw, the drive signal Sdr from the drive adjustment unit 110 or 111 of the drive device 100 or 101 and the drive signal Sdr from the drive adjustment unit 112 or 113 of the drive device 102 or 103 can be selectively transmitted to the drive circuit 150, thereby achieving such switching control.

[0232] Implementation method 5.

[0233] In Embodiment 5, a structural example of a power conversion device that uses a driving device for semiconductor elements described in Embodiments 1 to 4 will be described.

[0234] Figure 24 This is a block diagram illustrating the structure of a power conversion system using a power conversion device in Embodiment 5.

[0235] Reference Figure 24 The power conversion system includes a power supply 190, a power conversion device 250, and a load 300. The power supply 190 is a DC power supply that supplies DC power to the power conversion device 250. The power supply 190 can include various structures, such as a DC system, solar cells, or a battery. Alternatively, the power supply 190 can also include a rectifier circuit connected to an AC system, or an AC / DC converter. Furthermore, the power supply 190 can also include a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0236] Load 300 is typically a three-phase electric motor driven by AC power supplied from power conversion device 250. Furthermore, load 300 is not limited to a specific application and can be an electric motor mounted on various electrical devices. For example, electric motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment are used as load 300.

[0237] The power conversion device 250 is, for example, a three-phase inverter connected between the power source 190 and the load 300, which converts the DC power supplied from the power source 190 into AC power and supplies AC power to the load 300.

[0238] The power conversion device 250 includes: a main conversion circuit 251 that converts DC power into AC power for output; and a control circuit 255 that outputs a control signal 256 to the main conversion circuit 251 to control the main conversion circuit 251.

[0239] The main conversion circuit 251 includes at least one semiconductor element 10 and a drive device 100X configured corresponding to each semiconductor element 10. The drive device 100X is a device that generally describes the drive devices 101 to 103 and combinations thereof as described in this embodiment.

[0240] The control signal 256 from the control circuit 255 includes a drive control signal Ssw for controlling the on / off state of the semiconductor element 10. By turning each semiconductor element 10 on and off according to the respective drive control signal Ssw, the main conversion circuit 251 converts the DC power supplied from the power supply 190 into AC power and supplies it to the load 300.

[0241] There are various examples of specific circuit structures for the main converter circuit 251. For instance, the main converter circuit 251 can be a 2-level three-phase full-bridge circuit, which may include six semiconductor elements 10 and six return diodes connected in anti-parallel to the semiconductor elements 10. Regarding the six semiconductor elements 10, every two semiconductor elements 10 are connected in series to form upper and lower branches, and each upper and lower branch constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower branch, i.e., the three output terminals of the main converter circuit 251, are connected to the load 300.

[0242] The control circuit 255 controls the on / off state of the semiconductor elements 10 of the main converter circuit 251 in a manner that supplies the desired power to the load 300. Specifically, the control circuit 255 calculates the on-state time (on-time) of each semiconductor element 10 of the main converter circuit 251 based on the power to be supplied to the load 300. For example, the main converter circuit 251 can be controlled according to PWM control that modulates the on-time of each semiconductor element 10 according to the output voltage.

[0243] Furthermore, at each time point, the control circuit 255 sets the drive control signal Ssw of the semiconductor element 10 that should be in the on state to "1", and on the other hand, sets the drive control signal Ssw of the semiconductor element 10 that should be in the off state to "0".

[0244] The drive unit 100X controls the gate voltage of the corresponding semiconductor element 10 according to the drive control signal Ssw from the control circuit 255. This allows for control of the switching of each semiconductor element 10 while suppressing the impact on normal switching losses, thereby reducing the possibility of breakdown during overcurrent abnormalities. Consequently, the power conversion device 250 can also achieve high power conversion efficiency through low switching losses and reduce the possibility of breakdown during short circuits in the load 300, etc.

[0245] Furthermore, the drive unit 100X can be integrated into a semiconductor module (not shown) containing a semiconductor element 10, or it can be connected to the semiconductor module from the outside.

[0246] Furthermore, while this embodiment describes a two-level three-phase inverter as an example of a power conversion device 250, the drive device 100 described in this embodiment can also be applied to various other power conversion devices. For example, the power conversion device 250 can also be a three-level or multi-level power conversion device. When the load 300 is a single-phase AC load, the power conversion device 250 can be constructed using a single-phase inverter. Additionally, when the load 300 is a DC load, the power conversion device 250 can be constructed using a DC / DC converter or an AC / DC converter.

[0247] Thus, any power conversion device that performs power conversion by controlling the on / off state of the semiconductor element can use the drive device of Embodiments 1 to 4 or a combination thereof to drive device 100X to turn the semiconductor element 10 on / off.

[0248] Furthermore, in Embodiment 5, all the functions of the drive adjustment units 110-113 in the drive device 100X can be implemented by software. In this case, the drive signal Sdr can be configured to include a cutoff pulse corresponding to the voltage drop period 210 and / or a turn-on pulse corresponding to the voltage rise period 410 in the control signal 256 from the control circuit 255. In this case, the drive signal Sdr and the drive control signal Ssw can be identified by comparing the number of signal level changes with the actual number of turn-on and cut-off cycles of the semiconductor element 10.

[0249] Furthermore, the power conversion device of this embodiment is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker, or contactless power supply system. Moreover, it can also be used as a power regulator for solar power generation system, energy storage system, etc.

[0250] The embodiments disclosed herein are merely illustrative at all points and should not be considered as limiting. The scope of the technology disclosed herein is defined not by the foregoing description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A method for driving a semiconductor element, wherein the semiconductor element is turned on and off according to a driving control signal, wherein, The method for driving the semiconductor element includes the following steps: In response to the turn-on command of the drive control signal shifting from the first level to the second level, the turn-on operation of charging the gate of the semiconductor element in the off state is initiated. In response to a disconnection command that shifts the drive control signal from the second level to the first level, a disconnection operation is initiated to discharge the gate of the semiconductor element in the on state; as well as The configuration includes at least one of a gate voltage decrease period and a gate voltage rise period, wherein the gate voltage decrease period is set during the period when the drive control signal is maintained at the second level after the start of the turn-on operation, and the gate voltage rise period is set during the period when the drive control signal is maintained at the first level after the start of the turn-off operation. The gate voltage reduction period is configured to temporarily reduce the gate voltage by discharging the gate after the mirroring period ends. The gate voltage rise period is configured such that during a period when the current of the semiconductor element decreases, the voltage of the gate is temporarily increased by charging the gate.

2. The driving method for a semiconductor element according to claim 1, wherein, The configuration steps include: Based on the amount of information about the operating state of the semiconductor element, at least one of the steps of starting timing and duration configured during the gate voltage reduction period of the turn-on operation can be variably adjusted.

3. The driving method for a semiconductor element according to claim 1, wherein, The configuration steps include: Based on the amount of information about the operating state of the semiconductor element, at least one of the steps configured during the rise of the gate voltage during the disconnection operation can be variably adjusted, including the start timing and the duration.

4. The driving method for a semiconductor element according to claim 2 or 3, wherein, The information about the operating state includes at least one of the following: the voltage between the main electrodes of the semiconductor element, the current between the main electrodes, the gate voltage, and the element temperature.

5. The driving method for a semiconductor element according to any one of claims 1 to 3, wherein, The gate voltage decrease period and the gate voltage rise period are divided into multiple segments.

6. The driving method for a semiconductor element according to any one of claims 1 to 3, wherein, It also includes the following steps: In response to the disconnect command, the overcurrent state of the semiconductor element is detected based on the current or voltage of the semiconductor element in the on state prior to the disconnect command. as well as In the disconnection operation corresponding to the disconnection command, the gate voltage rise period is configured when the overcurrent state is detected, but not when the overcurrent state is not detected.

7. The driving method for a semiconductor element according to any one of claims 1 to 3, wherein, During the periods of the gate voltage reduction and the gate discharge during the disconnection operation, a common first voltage is applied to the gate. During the period of the gate voltage rise and the period of the gate charging during the turn-on operation, a common second voltage is applied to the gate.

8. A driving device for a semiconductor element, wherein the semiconductor element is turned on and off according to a driving control signal, wherein, The driving device for the semiconductor element includes: The drive adjustment unit generates a drive signal in response to an on command that the drive control signal shifts from a first level to a second level and an off command that the drive control signal shifts from the second level to the first level. The drive signal is used to control the on operation of charging the gate of the semiconductor element in the off state and the off operation of discharging the gate of the semiconductor element in the on state. as well as The driving circuit charges or discharges the gate according to the driving signal. The drive adjustment unit: The drive signal is generated in a manner that configures at least one of a gate voltage decrease period and a gate voltage rise period, wherein the gate voltage decrease period is set during the period when the drive control signal is maintained at the second level after the start of the turn-on operation, and the gate voltage rise period is set during the period when the drive control signal is maintained at the first level after the start of the turn-off operation. The gate voltage reduction period is configured to temporarily reduce the gate voltage by discharging the gate after the mirroring period ends. The gate voltage rise period is configured such that during a period when the current of the semiconductor element decreases, the voltage of the gate is temporarily increased by charging the gate.

9. The driving device for a semiconductor element according to claim 8, wherein, The driving device for the semiconductor element also includes an interface circuit that receives a detection value of information about the operating state of the semiconductor element from a detector disposed on the semiconductor element. The drive adjustment unit uses the value of the information input to the interface circuit to variably adjust at least one of the start timing and duration configured during the gate voltage reduction period of the turn-on operation.

10. The driving device for a semiconductor element according to claim 8, wherein, The driving device for the semiconductor element also includes an interface circuit, which receives a detection value of the amount of information about the operating state of the semiconductor element obtained by a detector disposed on the semiconductor element. The drive adjustment unit uses the value of the information input to the interface circuit to make at least one of the start timing and duration configured during the gate voltage rise period of the disconnection operation variable.

11. The driving device for a semiconductor element according to claim 9 or 10, wherein, The information about the operating state includes at least one of the following: the voltage between the main electrodes of the semiconductor element, the current between the main electrodes, the gate voltage, and the element temperature.

12. The driving device for a semiconductor element according to any one of claims 8 to 10, wherein, The drive adjustment unit is configured to divide the period of gate voltage decrease and the period of gate voltage rise into multiple segments.

13. The driving device for a semiconductor element according to any one of claims 8 to 10, wherein, In response to the disconnect command, the drive adjustment unit detects the overcurrent state of the semiconductor element based on the current or voltage of the semiconductor element in the on state prior to the disconnect command. In the disconnect operation corresponding to the disconnect command, the gate voltage rise period is configured when the overcurrent state is detected, but the gate voltage rise period is not configured when the overcurrent state is not detected.

14. The driving device for a semiconductor element according to any one of claims 8 to 10, wherein, When the driving signal is at the first level, the driving circuit electrically connects the gate and the first voltage terminal; conversely, when the driving signal is at the second level, the driving circuit electrically connects the second voltage terminal and the gate. The drive adjustment unit sets the drive signal to the second level during the gate voltage rise period when the drive control signal is at the first level, and sets the drive signal to the first level during periods other than the gate voltage rise period. The drive adjustment unit sets the drive signal to the first level during the period when the drive control signal is at the second level, and sets the drive signal to the second level during the period when the gate voltage decreases.

15. A power conversion device, comprising: A main converter circuit, configured to include at least one of the semiconductor elements, converts the input power and outputs it; and The control circuit outputs control signals to the main conversion circuit. The control signals include the drive control signals for each of the semiconductor elements. The main conversion circuit further includes a driving device according to any one of claims 8 to 14, configured corresponding to each of the semiconductor elements. The driving device controls the switching on and off of each semiconductor element according to the driving control signal.

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