Information bit string allocation device, information bit string conversion circuit, information bit string allocation method, information bit string decoding device, information bit string inverse conversion circuit, and optical communication system

Abstract

The information bit string distribution device (1) is configured to include: a first bit string output unit (11), which acquires an information bit string having a valid bit string containing transmitted data and an invalid bit string containing virtual data, extracts a portion of transmitted data from the transmitted data contained in the valid bit string of the information bit string as first transmitted data, and outputs an information bit string having a valid bit string containing the first transmitted data and an invalid bit string containing virtual data as a first information bit string for transmitting the first transmitted data at a first speed; and a second bit string output unit (12), which extracts transmitted data other than the first transmitted data from the transmitted data contained in the valid bit string of the information bit string acquired by the first bit string output unit (11) as second transmitted data, and outputs an information bit string having a valid bit string containing the second transmitted data and an invalid bit string containing virtual data as a second information bit string for transmitting the second transmitted data at a second speed.

Description

Technical Field

[0001] This invention relates to an information bit string allocation device, an information bit string conversion circuit, an information bit string allocation method, an information bit string decoding device, an information bit string inverse conversion circuit, and an optical communication system. Background Technology

[0002] In optical communication systems that use optical fibers to transmit information bit strings, there exists an optical communication system (hereinafter referred to as "existing optical communication system") that divides the information bit string into multiple parts and transmits each part through distinct subcarriers. Existing optical communication systems use probability distributions to implement probabilistic shaping of the signal point configurations for the transmitted data contained in the information bit strings transmitted by each subcarrier.

[0003] Furthermore, as a technique for generating multiple probability distributions, a distributed matching circuit is disclosed in Non-Patent Document 1.

[0004] Existing technical documents

[0005] Non-patent literature

[0006] Non-patent literature 1: Q.Yu et al., “FPGA Implementation of Rate-Adaptable Prefix-FreeCode Distribution Matching for Probabilistic Constellation Shaping”, Journal of Lightwave Technology, DOI: 10.1109 / JLT.2020.3035039, 2020. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In existing optical communication systems, there is a problem that the transmission speed of the transmitted data contained in the information bit string carried by each subcarrier cannot be changed.

[0009] For existing optical communication systems, assuming the distributed matching circuit disclosed in Non-Patent Document 1 can be applied, it is possible to use different probability distributions to probabilistically shape the signal point configuration of the transmitted data contained in the information bit string transmitted by each subcarrier. However, even if the existing optical communication system performs such probabilistic shaping, it cannot change the transmission speed of the transmitted data contained in the information bit string transmitted by each subcarrier.

[0010] The present invention was made to solve the problems mentioned above, and its purpose is to provide an information bit string allocation device and an information bit string allocation method that can change the transmission speed of the transmitted data contained in the information bit string transmitted by each subcarrier.

[0011] means for solving problems

[0012] The information bit string allocation apparatus of the present invention comprises: a first bit string output unit that acquires an information bit string having a valid bit string containing transmitted data and an invalid bit string containing virtual data, extracts transmitted data of length sb from the transmitted data contained in the valid bit string of the information bit string as first transmitted data, and outputs an information bit string having a valid bit string containing the first transmitted data and an invalid bit string containing virtual data as a first information bit string for transmitting the first transmitted data at a first speed; and a second bit string output unit that receives the valid bit string from the information bit string acquired by the first bit string output unit. The transmitted data, excluding the first transmitted data, is extracted to form the second transmitted data, which is a length of st. An information bit string containing valid bits of the second transmitted data and invalid bits containing virtual data is output as the second information bit string transmitted at a second speed. The st is determined by the first speed at which the first transmitted data is transmitted, and the first speed is determined by the second speed at which the second transmitted data is transmitted. The faster the first speed, the more bits (sb) are in the first transmitted data; the faster the second speed, the more bits (st) are in the second transmitted data.

[0013] Invention Effects

[0014] According to the present invention, it is possible to change the transmission speed of the transmitted data contained in the information bit string transmitted by each subcarrier. Attached Figure Description

[0015] Figure 1 This is a structural diagram showing the information bit string allocation device 1 of Embodiment 1.

[0016] Figure 2 This is a hardware structure diagram showing the hardware of the information bit string allocation device 1 of Embodiment 1.

[0017] Figure 3 This is a hardware structure diagram of a computer when the information bit string allocation device 1 is implemented by software or firmware.

[0018] Figure 4 This is an explanatory diagram showing an example of an information bit string, a first information bit string, and a second information bit string.

[0019] Figure 5This is a flowchart illustrating the information bit string allocation method as a processing step of the information bit string allocation device 1.

[0020] Figure 6 This is a structural diagram showing the second bit string output section 12 implemented by the channel shift selector.

[0021] Figure 7 This is a structural diagram showing the information bit string allocation device 3 of Embodiment 2.

[0022] Figure 8 This is an explanatory diagram showing an example of an information bit string, a first information bit string, a second information bit string, a third information bit string, a fourth information bit string, a fifth information bit string, and a sixth information bit string.

[0023] Figure 9 This is a structural diagram showing the information bit string allocation device 4 of Embodiment 3.

[0024] Figure 10 This is an explanatory diagram showing an example of an information bit string, the first information bit string, the second information bit string, the seventh information bit string, the eighth information bit string, the ninth information bit string, and the tenth information bit string.

[0025] Figure 11 This is a structural diagram showing the information bit string conversion circuit 30 of embodiment 4.

[0026] Figure 12 This is a structural diagram showing the information bit string decoding device 50 of Embodiment 5.

[0027] Figure 13 This is a hardware structure diagram showing the hardware of the information bit string decoding device 50 in Embodiment 5.

[0028] Figure 14 This is a hardware structure diagram of a computer when the information bit string decoding device 50 is implemented by software or firmware.

[0029] Figure 15 This is an explanatory diagram showing an example of an information bit string, a first information bit string, and a second information bit string.

[0030] Figure 16 This is a flowchart illustrating an information bit string decoding method as a processing step of the information bit string decoding device 50.

[0031] Figure 17 This is a structural diagram showing the information bit string decoding device 53 of Embodiment 6.

[0032] Figure 18 This is a structural diagram showing the information bit string decoding device 54 of Embodiment 7.

[0033] Figure 19 This is a structural diagram showing the information bit string inverse conversion circuit 60 of embodiment 8.

[0034] Figure 20 This is a structural diagram showing the optical communication system of Embodiment 9.

[0035] Figure 21 This is a structural diagram showing the internal structure of the signal processing circuit 71.

[0036] Figure 22 This is a structural diagram showing the internal structure of the receiving signal processing circuit 94. Detailed Implementation

[0037] Hereinafter, in order to illustrate the present invention in more detail, the embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

[0038] Implementation Method 1

[0039] Figure 1 This is a structural diagram showing the information bit string allocation device 1 of Embodiment 1.

[0040] Figure 2 This is a hardware structure diagram showing the hardware of the information bit string allocation device 1 of Embodiment 1.

[0041] Figure 1 The information bit string distribution device 1 shown includes a first bit string output unit 11 and a second bit string output unit 12.

[0042] The first bit string output section 11, for example, is... Figure 2 The first bit string output circuit 11a shown is implemented.

[0043] The first bit string output unit 11 acquires an information bit string provided from an external source. The information bit string contains a valid bit string containing transmitted data and an invalid bit string containing dummy data. The dummy data includes one or more invalid bits, each of which can be fixed to 0 or 1. Furthermore, each invalid bit can be ignored.

[0044] The first bit string output unit 11 extracts a portion of the transmission data contained in the valid bit string of the information bit string as the first transmission data.

[0045] The first bit string output unit 11 outputs an information bit string containing a valid bit string containing the first transmitted data and an invalid bit string containing virtual data to the outside as a first information bit string that transmits the first transmitted data at a first speed.

[0046] The first bit string output unit 11 outputs the acquired information bit string to the second bit string output unit 12.

[0047] For example, the output part 12 of the second bit string is... Figure 2 The second bit string output circuit 12a shown is implemented.

[0048] The second bit string output unit 12 extracts the transmission data other than the first transmission data from the transmission data contained in the valid bit string of the information bit string obtained by the first bit string output unit 11 as the second transmission data.

[0049] The second bit string output unit 12 outputs an information bit string containing a valid bit string containing the second transmitted data and an invalid bit string containing virtual data to the outside as a second information bit string that transmits the second transmitted data at a second speed.

[0050] exist Figure 1 In this context, it is assumed that the first bit string output unit 11 and the second bit string output unit 12, which are structural elements of the information bit string distribution device 1, are respectively composed of... Figure 2 The dedicated hardware implementation shown is as follows. That is, it is assumed that the information bit string distribution device 1 is implemented by the first bit string output circuit 11a and the second bit string output circuit 12a.

[0051] The first bit string output circuit 11a and the second bit string output circuit 12a correspond, for example, to a single circuit, a composite circuit, a programmable processor, a parallel programmable processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0052] The structural elements of the information bit string allocation device 1 are not limited to being implemented by dedicated hardware; the information bit string allocation device 1 can also be implemented by software, firmware, or a combination of software and firmware.

[0053] Software or firmware is stored in the computer's memory in the form of a program. A computer refers to the hardware that executes programs, such as CPU (Central Processing Unit), central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor).

[0054] Figure 3 This is a hardware structure diagram of a computer when the information bit string allocation device 1 is implemented by software or firmware.

[0055] When the information bit string distribution device 1 is implemented by software, firmware, etc., a program for causing a computer to execute each processing step in the first bit string output unit 11 and the second bit string output unit 12 is stored in the memory 41. Then, the processor 42 of the computer executes the program stored in the memory 41.

[0056] In addition, in Figure 2 an example is shown in which the structural elements of the information bit string distribution device 1 are implemented by dedicated hardware, and in Figure 3 an example is shown in which the information bit string distribution device 1 is implemented by software, firmware, etc. However, this is merely an example, and it is also possible that a part of the structural elements in the information bit string distribution device 1 are implemented by dedicated hardware and the remaining structural elements are implemented by software, firmware, etc.

[0057] Next, the operation of the information bit string distribution device 1 shown in Figure 1 will be described.

[0058] Figure 4 is an explanatory diagram showing an example of an information bit string, a first information bit string, and a second information bit string.

[0059] Figure 5 is a flowchart showing an information bit string distribution method as a processing step of the information bit string distribution device 1.

[0060] As shown in Figure 4 the information bit string provided to the information bit string distribution device 1 is represented by Bi[u - 1:0]. In Figure 4 "data" represents transmission data, and "virtual" represents virtual data. The same applies in Figure 8 described later.

[0061] The number of bits of the information bit string Bi[u - 1:0] is u. u is a natural number.

[0062] The information bit string Bi[u - 1:0] has a valid bit string Bi[sb + st - 1:0] and an invalid bit string Bi[u - 1:sb + st]. The number of bits of the valid bit string Bi[sb + st - 1:0] is sb + st, and the number of bits of the invalid bit string Bi[u - 1:sb + st] is u - (st + sb). 0 ≤ sb + st ≤ u. sb and st are non - negative integers.

[0063] The transmission data is included in the valid bit string Bi[sb + st - 1:0]. A part of the transmission data is the first transmission data, and in the transmission data, the transmission data other than the first transmission data is the second transmission data. The number of bits of the first transmission data is sb, and the number of bits of the second transmission data is st.

[0064] The number of bits (sb) of the first transmitted data is determined by the transmission speed of the first transmitted data. The faster the transmission speed, the more bits (sb) are transmitted.

[0065] The number of bits *st* in the second transmitted data is determined by the second transmission speed. The faster the second transmission speed, the more bits *st*.

[0066] like Figure 4 As shown, the first information bit string is represented by Bb[vb-1:0].

[0067] The number of bits in the first information bit string is vb. vb is a natural number.

[0068] The first information bit string Bb[vb-1:0] has a valid bit string Bb[sb-1:0] and an invalid bit string Bb[vb-1:sb]. The valid bit string Bb[sb-1:0] contains the first transmitted data, and the number of bits in the valid bit string Bb[sb-1:0] is sb. The invalid bit string Bb[vb-1:sb] contains dummy data, and the number of bits in the invalid bit string Bb[vb-1:sb] is vb-sb.

[0069] like Figure 4 As shown, the second information bit string is represented by Bt[vt-1:0].

[0070] The number of bits in the second information bit string is vt. vt is a natural number.

[0071] The second information bit string Bt[vt-1:0] has a valid bit string Bt[st-1:0] and an invalid bit string Bt[vt-1:st]. The valid bit string Bt[st-1:0] contains the second transmitted data, and the number of bits in the valid bit string Bt[st-1:0] is st. The invalid bit string Bt[vt-1:st] contains dummy data, and the number of bits in the invalid bit string Bt[vt-1:st] is vt-st.

[0072] exist Figure 4 In the example, in the effective bit string Bi[sb+st-1:0] of the information bit string Bi[u-1:0], the first transmitted data is configured on the lower bit side, and the second transmitted data is configured on the upper bit side. However, this is just one example; it is also possible that in the effective bit string Bi[sb+st-1:0], the first transmitted data is configured on the upper bit side, and the second transmitted data is configured on the lower bit side.

[0073] In addition, Figure 4In the example, in the information bit string Bi[u-1:0], the valid bit string Bi[sb+st-1:0] is configured on the lower bit side, and the invalid bit string Bi[u-1:sb+st] is configured on the upper bit side. However, this is just one example; it is also possible that in the information bit string Bi[u-1:0], the valid bit string is configured on the upper bit side, and the invalid bit string is configured on the lower bit side.

[0074] The first bit string output unit 11 obtains the information bit string Bi[u-1:0] provided from the outside. Figure 5 Step ST1).

[0075] The first bit string output unit 11 extracts a portion of the transmission data contained in the valid bit string Bi[sb+st-1:0] of the information bit string Bi[u-1:0] as the first transmission data.

[0076] That is, the first bit string output unit 11 extracts the bit string of Bi[sb-1:0] contained in the transmitted data in the effective bit string Bi[sb+st-1:0] as the first transmitted data.

[0077] The number of bits sb of the first transmitted data can be stored in the internal memory of the first bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1.

[0078] The first bit string output unit 11 extracts a portion of virtual data from the virtual data contained in the invalid bit string Bi[u-1: sb+st] of the information bit string Bi[u-1: 0] as the first virtual data.

[0079] That is, the first bit string output unit 11 extracts the bit string of Bi[sb+st+(vb-sb)-1:sb+st] from the virtual data contained in the invalid bit string Bi[u-1:sb+st] as the first virtual data.

[0080] The number of bits st of the second transmitted data and the number of bits vb of the first information bit string can be stored in the internal memory of the first bit string output unit 11, or they can be provided from outside the information bit string distribution device 1.

[0081] The first bit string output unit 11 generates the first information bit string Bb[vb-1:0] which transmits the first transmitted data at the first speed.

[0082] That is, the first bit string output unit 11 generates a first information bit string Bb[vb-1:0] containing a valid bit string Bb[sb-1:0] containing the extracted first transmitted data and an invalid bit string Bb[vb-1:sb] containing the extracted first virtual data.

[0083] The first transmission speed of the first data transmission is represented by sb / vb. The larger the ratio of the number of bits sb of the first data transmission to the number of bits vb of the first information bit string, the faster the first transmission speed.

[0084] The first bit string output unit 11 outputs the first information bit string Bb[vb-1:0], which transmits the first data at the first speed, to the outside. Figure 5 Step ST2).

[0085] In addition, the first bit string output unit 11 outputs the acquired information bit string Bi[u-1:0] to the second bit string output unit 12.

[0086] The second bit string output unit 12 obtains the information bit string Bi[u-1:0] from the first bit string output unit 11.

[0087] The second bit string output unit 12 extracts the transmission data other than the first transmission data from the transmission data contained in the effective bit string Bi[sb+st-1:0] of the information bit string Bi[u-1:0] as the second transmission data.

[0088] That is, the second bit string output unit 12 extracts the bit string of Bi[sb+st-1:sb] contained in the transmitted data in the effective bit string Bi[sb+st-1:0] as the second transmitted data.

[0089] The number of bits sb of the first transmitted data and the number of bits st of the second transmitted data can be stored in the internal memory of the second bit string output unit 12, or they can be provided from outside the information bit string allocation device 1.

[0090] The second bit string output unit 12 extracts virtual data other than the first virtual data from the virtual data contained in the invalid bit string Bi[u-1: sb+st] of the information bit string Bi[u-1: 0] as the second virtual data.

[0091] That is, the second bit string output unit 12 extracts the bit string of Bi[u-1:sb+st+(vb-sb)] from the virtual data contained in the invalid bit string Bi[u-1:sb+st] as the second virtual data.

[0092] The number of bits vb in the first information bit string can be stored in the internal memory of the second bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1.

[0093] The second bit string output section 12 generates the second information bit string Bt[vt-1:0] which transmits the second data at the second speed.

[0094] That is, the second bit string output unit 12 generates a second information bit string Bt[vt-1:0] containing the extracted second transmitted data and an invalid bit string Bt[vt-1:st] containing the extracted second virtual data.

[0095] The second speed of transmitting the second data is represented by st / vt. The larger the ratio of the number of bits st of the second data to the number of bits vt of the second information bit string, the faster the second speed.

[0096] The second bit string output unit 12 outputs the second information bit string Bt[vt-1:0], which transmits the second data at the second speed, to the outside. Figure 5 Step ST3).

[0097] exist Figure 1 In the information bit string allocation device 1 shown, for example, if vb = vt = v, then for two subcarriers, the transmitted data contained in the effective bit string of the information bit string can be allocated as first transmitted data having a number of bits proportional to the first speed sb / v and second transmitted data having a number of bits proportional to the second speed st / v. However, it is not limited to vb = vt, and vb ≠ vt is also possible.

[0098] exist Figure 1 In the information bit string distribution device 1 shown, the second bit string output unit 12 is shown to be composed of... Figure 2 The example shown is the implementation of the second bit string output circuit 12a. However, this is just one example; the second bit string output section 12 can also be implemented by... Figure 6 The channel shift selector shown is implemented.

[0099] Figure 6 This is a structural diagram showing the second bit string output section 12 implemented by the channel shift selector.

[0100] Figure 6 The second bit string output section 12 shown includes branch sections 21-1, 21-2, 21-3, a 4-channel shifter 22, a 2-channel shifter 23, a 1-channel shifter 24, and selectors 25-1, 25-2, and 25-3.

[0101] Branch 21-1 outputs the information bit string Bi[u-1:0] from the first bit string output section 11 to the 4-channel shifter 22 and selector 25-1 respectively.

[0102] The 4-channel shifter 22 shifts the information bit string Bi[u-1:0] output from the branch 21-1 to the low-order side of the 4-channel.

[0103] The 4-channel shifter 22 outputs the shifted information bit string to the selector 25-1.

[0104] Selector 25-1 selects, for example, any information bit string from the information bit string output from branch 21-1 or the shifted information bit string output from 4-channel shifter 22, based on a control signal provided externally from the information bit string distribution device 1.

[0105] Selector 25-1 outputs the selected information bit string to branch 21-2.

[0106] Branch 21-2 outputs the information bit string from selector 25-1 to 2-channel shifter 23 and selector 25-2 respectively.

[0107] The 2-channel shifter 23 shifts the information bit string output from the branch 21-2 to the low-order side of the 2-channel.

[0108] The 2-channel shifter 23 outputs the shifted information bit string to the selector 25-2.

[0109] Selector 25-2 selects, for example, any information bit string from the information bit string output from branch 21-2 or the shifted information bit string output from 2-channel shifter 23, based on a control signal provided externally from the information bit string distribution device 1.

[0110] Selector 25-2 outputs the selected information bit string to branch 21-3.

[0111] Branch 21-3 outputs the information bit string from selector 25-2 to channel 1 shifter 24 and selector 25-3 respectively.

[0112] The 1-channel shifter 24 shifts the information bit string output from the branch 21-3 to the low-order side of the 1-channel.

[0113] The 1-channel shifter 24 outputs the shifted information bit string to the selector 25-3.

[0114] Selector 25-3 selects, for example, any information bit string from the information bit string output from branch 21-3 or the shifted information bit string output from channel 1 shifter 24, based on a control signal provided externally from the information bit string distribution device 1.

[0115] Selector 25-3 outputs the selected information bit string as the second information bit string Bt[vt-1:0] to the outside.

[0116] Figure 6 The second bit string output section 12 shown can perform shifting of any number of bits from 0 to 7 bits.

[0117] For example, in the case of implementing a 5-bit shift of the information bit string Bi[u-1:0], the control signal shown below is provided from outside the information bit string distribution device 1 to the second bit string output unit 12.

[0118] The second bit string output section 12 is provided with control signals indicating selector 25-1 to select the shifted information bit string output from the 4-channel shifter 22, selector 25-2 to select the information bit string output from the branch section 21-2, and selector 25-3 to select the shifted information bit string output from the 1-channel shifter 24.

[0119] For example, in the case of implementing a 3-bit shift of the information bit string Bi[u-1:0], the control signal shown below is provided from outside the information bit string distribution device 1 to the second bit string output unit 12.

[0120] The second bit string output section 12 is provided with control signals indicating selector 25-1 to select the information bit string output from branch section 21-1, selector 25-2 to select the shifted information bit string output from channel 23, and selector 25-3 to select the shifted information bit string output from channel 14.

[0121] In Embodiment 1 described above, the information bit string allocation device 1 is configured to include: a first bit string output unit 11, which acquires an information bit string having a valid bit string containing transmitted data and an invalid bit string containing virtual data, extracts a portion of transmitted data from the transmitted data included in the valid bit string of the information bit string as first transmitted data, and outputs an information bit string having a valid bit string containing the first transmitted data and an invalid bit string containing virtual data as a first information bit string transmitting the first transmitted data at a first speed; and a second bit string output unit 12, which extracts transmitted data other than the first transmitted data from the transmitted data included in the valid bit string of the information bit string acquired by the first bit string output unit 11 as second transmitted data, and outputs an information bit string having a valid bit string containing the second transmitted data and an invalid bit string containing virtual data as a second information bit string transmitting the second transmitted data at a second speed. Therefore, the information bit string allocation device 1 can change the transmission speed of the transmitted data included in the information bit string transmitted by each subcarrier.

[0122] Implementation Method 2

[0123] In implementation method 2, for those having 3 Figure 1 The information bit string allocation device 1 shown in the figure will be described in terms of information bit string allocation device 3.

[0124] Figure 7 This is a structural diagram showing the information bit string allocation device 3 of Embodiment 2.

[0125] Figure 7 The information bit string allocation device 3 shown includes information bit string allocation devices 1-1, 1-2, and 1-3.

[0126] Information bit string allocation devices 1-1, 1-2, and 1-3 are related to Figure 1 The information bit string allocation device shown is the same as the information bit string allocation device 1.

[0127] The first information bit string allocation device 1-1 among the three information bit string allocation devices obtains the information bit string.

[0128] The first information bit string distribution device 1-1 outputs the first information bit string to the second information bit string distribution device 1-2, and outputs the second information bit string to the third information bit string distribution device 1-3.

[0129] The second information bit string distribution device 1-2 obtains the first information bit string output from the information bit string distribution device 1-1.

[0130] The information bit string allocation device 1-2 extracts a portion of the transmission data from the first transmission data contained in the valid bit string of the first information bit string as the third transmission data.

[0131] The information bit string distribution device 1-2 outputs an information bit string containing a valid bit string of the third transmitted data and an invalid bit string containing virtual data as a third information bit string to the outside, transmitting the third transmitted data at a third speed.

[0132] In addition, the information bit string allocation device 1-2 extracts the transmission data other than the third transmission data from the first transmission data contained in the valid bit string of the first information bit string as the fourth transmission data.

[0133] The information bit string distribution device 1-2 outputs an information bit string containing a valid bit string of the fourth transmission data and an invalid bit string containing virtual data as a fourth information bit string to the outside, transmitting the fourth transmission data at the fourth speed.

[0134] The third information bit string distribution device 1-3 obtains the second information bit string output from the information bit string distribution device 1-1.

[0135] Information bit string allocation device 1-3 extracts a portion of the transmission data from the second transmission data contained in the valid bit string of the second information bit string as the fifth transmission data.

[0136] The information bit string distribution device 1-3 outputs the information bit string containing the valid bit string of the 5th transmitted data and the invalid bit string containing the virtual data as the 5th information bit string to the outside.

[0137] In addition, the information bit string allocation device 1-3 extracts the transmission data other than the fifth transmission data from the second transmission data contained in the valid bit string of the second information bit string as the sixth transmission data.

[0138] The information bit string distribution device 1-3 outputs the information bit string containing the valid bit string of the 6th transmitted data and the invalid bit string containing the virtual data as the 6th information bit string to the outside.

[0139] Next, regarding Figure 7 The operation of the information bit string allocation device 3 shown will be explained.

[0140] Figure 8 This is an explanatory diagram showing an example of an information bit string, a first information bit string, a second information bit string, a third information bit string, a fourth information bit string, a fifth information bit string, and a sixth information bit string.

[0141] like Figure 8 As shown, the first bit string output unit 11 of the information bit string allocation device 1-1 obtains the information bit string Bsrc[w-1:0] from the outside. The number of bits in the information bit string Bsrc[w-1:0] is w. w is a natural number.

[0142] The first bit string output unit 11 of the information bit string allocation device 1-1 extracts a portion of the transmission data contained in the effective bit string Bsrc[s1b+s1t-1:0] of the information bit string Bsrc[w-1:0] as the first transmission data. s1b and s1t are non-negative integers.

[0143] That is, the first bit string output unit 11 extracts the bit string of Bsrc[s1b-1:0] contained in the valid bit string Bsrc[s1b+s1t-1:0] as the first transmitted data.

[0144] The number of bits s1b of the first transmitted data can be stored in the internal memory of the first bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1-1.

[0145] The first bit string output unit 11 of the information bit string allocation device 1-1 extracts a portion of virtual data from the virtual data contained in the invalid bit string Bsrc[w-1:s1b+s1t] of the information bit string Bsrc[w-1:0] as the first virtual data.

[0146] That is, the first bit string output unit 11 extracts the bit string of Bsrc[s1b+s1t+(v1b-s1b)-1:s1b+s1t] from the virtual data contained in the invalid bit string Bsrc[w-1:s1b+s1t] as the first virtual data.

[0147] The number of bits s1t of the second transmitted data and the number of bits v1b of the first information bit string B1b[v1b-1:0] can be stored in the internal memory of the first bit string output unit 11, or they can be provided from the outside of the information bit string allocation device 1-1.

[0148] The first bit string output unit 11 of the information bit string distribution device 1-1 generates the first information bit string B1b[v1b-1:0] which transmits the first transmitted data at the first speed.

[0149] That is, the first bit string output unit 11 generates a first information bit string B1b[v1b-1:0] containing a valid bit string B1b[s1b-1:0] containing the extracted first transmitted data and an invalid bit string B1b[v1b-1:s1b] containing the extracted first virtual data.

[0150] The first speed of transmitting the first data is represented by s1b / v1b. The larger the ratio of the number of bits s1b of the first data to the number of bits v1b of the first information bit string, the faster the first speed.

[0151] The first bit string output unit 11 of the information bit string distribution device 1-1 outputs the first information bit string B1b[v1b-1:0], which transmits the first data at the first speed, to the information bit string distribution device 1-2.

[0152] The first bit string output unit 11 of the information bit string distribution device 1-1 outputs the acquired information bit string Bsrc[w-1:0] to the second bit string output unit 12.

[0153] The second bit string output unit 12 of the information bit string distribution device 1-1 obtains the information bit string Bsrc[w-1:0] from the first bit string output unit 11.

[0154] The second bit string output unit 12 extracts the transmission data other than the first transmission data from the transmission data contained in the valid bit string Bsrc[s1b+s1t-1:0] of the information bit string Bsrc[w-1:0] as the second transmission data.

[0155] That is, the second bit string output unit 12 extracts the bit string of Bsrc[s1b+s1t-1:s1b] contained in the effective bit string Bsrc[s1b+s1t-1:0] as the second transmitted data.

[0156] The number of bits s1b of the first transmitted data and the number of bits s1t of the second transmitted data can be stored in the internal memory of the second bit string output unit 12, or they can be provided from the outside of the information bit string allocation device 1-1.

[0157] The second bit string output unit 12 of the information bit string allocation device 1-1 extracts virtual data other than the first virtual data from the virtual data contained in the invalid bit string Bsrc[w-1:s1b+s1t] of the information bit string Bsrc[w-1:0] as the second virtual data.

[0158] That is, the second bit string output unit 12 extracts the bit string of Bsrc[w-1:s1b+s1t+(v1b-s1b)] from the virtual data contained in the invalid bit string Bsrc[w-1:s1b+s1t] as the second virtual data.

[0159] The number of bits v1b of the first information bit string can be stored in the internal memory of the second bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1-1.

[0160] The second bit string output unit 12 of the information bit string distribution device 1-1 generates a second information bit string B1t[v1t-1:0] that transmits the second data at a second speed.

[0161] That is, the second bit string output unit 12 generates a second information bit string B1t[v1t-1:0] containing a valid bit string B1t[s1t-1:0] containing the extracted second transmitted data and an invalid bit string B1t[v1t-1:s1t] containing the extracted second virtual data.

[0162] The second speed of transmitting the second data is represented by s1t / v1t. The larger the ratio of the number of bits s1t of the second data to the number of bits v1t of the second information bit string, the faster the second speed.

[0163] The second bit string output unit 12 of the information bit string distribution device 1-1 outputs the second information bit string B1t[v1t-1:0], which transmits the second data at the second speed, to the information bit string distribution device 1-3.

[0164] The first bit string output unit 11 of the information bit string distribution device 1-2 obtains the first information bit string B1b[v1b-1:0] from the information bit string distribution device 1-1.

[0165] The first bit string output unit 11 of the information bit string allocation device 1-2 extracts a portion of the transmission data contained in the first transmission data in the effective bit string B1b[s1b-1:0] of the first information bit string B1b[v1b-1:0] as the third transmission data. s1b = s2bb + s2bt, where s2bb and s2bt are non-negative integers.

[0166] That is, the first bit string output unit 11 extracts the bit string of B1b[s2bb-1:0] contained in the first transmitted data in the effective bit string B1b[s1b-1:0] as the third transmitted data.

[0167] The number of bits s2bb of the third transmitted data can be stored in the internal memory of the first bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1-2.

[0168] The first bit string output unit 11 of the information bit string allocation device 1-2 extracts a portion of virtual data from the first virtual data contained in the invalid bit string B1b[v1b-1:s1b] of the first information bit string B1b[v1b-1:0] as the third virtual data.

[0169] That is, the first bit string output unit 11 extracts the bit string of B1b[s1b+(v2bb-s2bb)-1:s1b] from the first virtual data contained in the invalid bit string B1b[v1b-1:s1b] as the third virtual data.

[0170] The number of bits s1b of the first transmitted data and the number of bits v2bb of the third information bit string B2bb[v2bb-1:0] can be stored in the internal memory of the first bit string output unit 11, or they can be provided from the outside of the information bit string distribution device 1-2.

[0171] The first bit string output unit 11 of the information bit string distribution device 1-2 generates the third information bit string B2bb[v2bb-1:0] which transmits the third data at the third speed.

[0172] That is, the first bit string output unit 11 generates a third information bit string B2bb[v2bb-1:0] containing the extracted third transmitted data valid bit string B2bb[s2bb-1:0] and the extracted third virtual data invalid bit string B2bb[v2bb-1:s2bb].

[0173] The third speed of transmitting the third data is represented by s2bb / v2bb. The larger the ratio of the number of bits of the third data transmission s2bb to the number of bits of the third information bit string v2bb, the faster the third speed.

[0174] The first bit string output unit 11 of the information bit string distribution device 1-2 outputs the third information bit string B2bb[v2bb-1:0], which transmits the third data at the third speed, to the outside.

[0175] The first bit string output unit 11 of the information bit string distribution device 1-2 outputs the acquired first information bit string B1b[v1b-1:0] to the second bit string output unit 12.

[0176] The second bit string output unit 12 of the information bit string distribution device 1-2 obtains the first information bit string B1b[v1b-1:0] from the first bit string output unit 11.

[0177] The second bit string output unit 12 extracts the transmission data other than the first transmission data from the first transmission data contained in the valid bit string B1b[s1b-1:0] of the first information bit string B1b[v1b-1:0] as the fourth transmission data.

[0178] That is, the first bit string output unit 11 extracts the bit string of B1b[s1b-1:s2bb] contained in the first transmitted data in the effective bit string B1b[s1b-1:0] as the fourth transmitted data.

[0179] The number of bits s1b of the first transmitted data and the number of bits s2bb of the third transmitted data can be stored in the internal memory of the second bit string output unit 12, or they can be provided from the outside of the information bit string distribution device 1-2.

[0180] The second bit string output unit 12 of the information bit string allocation device 1-2 extracts virtual data other than the third virtual data from the first virtual data contained in the invalid bit string B1b[v1b-1:s1b] of the first information bit string B1b[v1b-1:0] as the fourth virtual data.

[0181] That is, the second bit string output unit 12 extracts the bit string of B1b[v1b-1:s1b+(v2bb-s2bb)] from the first virtual data contained in the invalid bit string B1b[v1b-1:s1b] as the fourth virtual data.

[0182] The number of bits v2bb in the third information bit string B2bb[v2bb-1:0] can be stored in the internal memory of the second bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1-2.

[0183] The second bit string output unit 12 of the information bit string distribution device 1-2 generates the fourth information bit string B2bt[v2bt-1:0] which transmits the fourth data at the fourth speed.

[0184] That is, the second bit string output unit 12 generates a fourth information bit string B2bt[v2bt-1:0] containing the extracted fourth transmitted data and the invalid bit string B2bt[v2bt-1:s2bt] containing the extracted fourth virtual data.

[0185] The fourth speed of transmitting the fourth data is represented by s2bt / v2bt. The larger the ratio of the number of bits s2bt of the fourth data to the number of bits v2bt of the fourth information bit string, the faster the fourth speed.

[0186] The second bit string output unit 12 of the information bit string distribution device 1-2 outputs the fourth information bit string B2bt[v2bt-1:0], which transmits the fourth data at the fourth speed, to the outside.

[0187] The first bit string output unit 11 of the information bit string distribution device 1-3 obtains the second information bit string B1t[v1t-1:0] from the information bit string distribution device 1-1.

[0188] The first bit string output unit 11 of the information bit string allocation device 1-3 extracts a portion of the second transmitted data contained in the effective bit string B1t[s1t-1:0] of the second information bit string B1t[v1t-1:0] as the fifth transmitted data. s1t = s2tb + s2tt, where s2tb and s2tt are non-negative integers.

[0189] That is, the first bit string output unit 11 extracts the bit string of B1t[s2tb-1:0] contained in the second transmitted data in the effective bit string B1t[s1t-1:0] as the fifth transmitted data.

[0190] The number of bits s2tb of the fifth transmitted data can be stored in the internal memory of the first bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1-3.

[0191] The first bit string output unit 11 of the information bit string distribution device 1-3 extracts a portion of virtual data from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] of the second information bit string B1t[v1t-1:0] as the fifth virtual data.

[0192] That is, the first bit string output unit 11 extracts the bit string of B1t[s1t+(v2tb-s2tb)-1:s1t] from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] as the fifth virtual data.

[0193] The number of bits s1t of the second transmitted data and the number of bits v2tb of the fifth information bit string B2tb[v2tb-1:0] can be stored in the internal memory of the first bit string output unit 11, or they can be provided from the outside of the information bit string allocation device 1-3.

[0194] The first bit string output unit 11 of the information bit string distribution device 1-3 generates the fifth information bit string B2tb[v2tb-1:0] which transmits the fifth data at the fifth speed.

[0195] That is, the first bit string output unit 11 generates a fifth information bit string B2tb[v2tb-1:0] containing the extracted fifth transmitted data and the invalid bit string B2tb[v2tb-1:s2tb] containing the extracted fifth virtual data.

[0196] The fifth transmission speed of the fifth data transmission is represented by s2tb / v2tb. The larger the ratio of the number of bits of the fifth data transmission s2tb to the number of bits of the fifth information bit string v2tb, the faster the fifth transmission speed.

[0197] The first bit string output unit 11 of the information bit string distribution device 1-3 outputs the fifth information bit string B2tb[v2tb-1:0], which transmits the fifth data at the fifth speed, to the outside.

[0198] The first bit string output unit 11 of the information bit string distribution device 1-3 outputs the acquired second information bit string B1t[v1t-1:0] to the second bit string output unit 12.

[0199] The second bit string output unit 12 of the information bit string distribution device 1-3 obtains the second information bit string B1t[v1t-1:0] from the first bit string output unit 11.

[0200] The second bit string output unit 12 extracts the transmission data other than the fifth transmission data from the second transmission data contained in the second transmission data contained in the valid bit string B1t[s1t-1:0] of the second information bit string B1t[v1t-1:0] as the sixth transmission data.

[0201] That is, the first bit string output unit 11 extracts the bit string of B1t[s1t-1:s2tb] in the second transmitted data contained in the effective bit string B1t[s1t-1:0] as the sixth transmitted data.

[0202] The number of bits s1t for the second transmitted data and the number of bits s2tb for the fifth transmitted data can be stored in the internal memory of the second bit string output unit 12, or they can be provided from the outside of the information bit string allocation device 1-3.

[0203] The second bit string output unit 12 of the information bit string allocation device 1-3 extracts virtual data other than the fifth virtual data from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] of the second information bit string B1t[v1t-1:0] as the sixth virtual data.

[0204] That is, the second bit string output unit 12 extracts the bit string of B1t[v1t-1:s1t+(v2tb-s2tb)] from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] as the sixth virtual data.

[0205] The number of bits v2tb in the fifth information bit string B2tb[v2tb-1:0] can be stored in the internal memory of the second bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1-3.

[0206] The second bit string output unit 12 of the information bit string distribution device 1-3 generates the sixth information bit string B2tt[v2tt-1:0] which transmits the sixth data at the sixth speed.

[0207] That is, the second bit string output unit 12 generates a sixth information bit string B2tt[v2tt-1:0] containing the extracted sixth transmitted data and the invalid bit string B2tt[v2tt-1:s2tt] containing the extracted sixth virtual data.

[0208] The sixth speed of transmitting the sixth data is represented by s2tt / v2tt. The larger the ratio of the number of bits of the sixth data transmission s2tt to the number of bits of the sixth information bit string v2tt, the faster the sixth speed.

[0209] The second bit string output unit 12 of the information bit string distribution device 1-3 outputs the sixth information bit string B2tt[v2tt-1:0], which transmits the sixth data at the sixth speed, to the outside.

[0210] Figure 7The information bit string allocation device 3 shown is, for example, v1b = v1t = w / 2, v2bb = v2bt = v2tb = v2tt = w / 4. In this case, for the four subcarriers, the transmission data contained in the effective bit string of the information bit string Bsrc[w-1:0] can be allocated as the third transmission data having a number of bits proportional to the third speed s2bb / (w / 4), the fourth transmission data having a number of bits proportional to the fourth speed s2bt / (w / 4), the fifth transmission data having a number of bits proportional to the fifth speed s2tb / (w / 4), and the sixth transmission data having a number of bits proportional to the sixth speed s2tt / (w / 4). However, it is not limited to v1b=v1t=w / 2, v2bb=v2bt=v2tb=v2tt=w / 4, it can also be vb≠vt, or v2bb≠v2bt≠v2tb≠v2tt.

[0211] exist Figure 7 In the illustrated information bit string allocation device 3, the three information bit string allocation devices 1-1, 1-2, and 1-3 are arranged in a tree structure, and the number of levels in the information bit string allocation device 3 is 2. However, this is just one example. For instance, it could also be that seven information bit string allocation devices 1 are arranged in a tree structure, and the number of levels in the information bit string allocation device 3 is 3. Furthermore, it could also be that fifteen information bit string allocation devices 1 are arranged in a tree structure, and the number of levels in the information bit string allocation device 3 is 4.

[0212] In the 3-level structure, the information bit string allocation device 3 can allocate the information bit string Bsrc[w-1:0] into 8 bits and provide the allocated information bit string to each of the 8 subcarriers.

[0213] In the 4-level structure, the information bit string allocation device 3 can allocate the information bit string Bsrc[w-1:0] into 16 bits and provide the allocated information bit string to each of the 16 subcarriers.

[0214] The information bit string allocation device 3 can increase the number of information bit strings allocated by powers of 2 by increasing the number of stages.

[0215] Implementation Method 3

[0216] In implementation method 3, for those having 3 Figure 1 The information bit string allocation device 1 shown in the figure will be described in terms of information bit string allocation device 3.

[0217] Figure 9 This is a structural diagram showing the information bit string allocation device 4 of Embodiment 3. Figure 9 In, with Figure 1 The same labels indicate the same or equivalent parts, so the description is omitted.

[0218] Figure 9 The information bit string allocation device 4 shown includes information bit string allocation devices 1-1, 1-2, and 1-3.

[0219] Information bit string allocation devices 1-1, 1-2, and 1-3 are related to Figure 1 The information bit string allocation device shown is the same as the information bit string allocation device 1.

[0220] The first information bit string allocation device 1-1 among the three information bit string allocation devices obtains the information bit string.

[0221] The first information bit string distribution device 1-1 outputs the first information bit string to the outside and outputs the second information bit string to the second information bit string distribution device 1-2.

[0222] The second information bit string distribution device 1-2 obtains the second information bit string output from the information bit string distribution device 1-1.

[0223] The information bit string allocation device 1-2 extracts a portion of the transmission data from the second transmission data contained in the valid bit string of the second information bit string as the seventh transmission data.

[0224] The information bit string distribution device 1-2 outputs an information bit string containing a valid bit string of the 7th transmitted data and an invalid bit string containing virtual data as a 7th information bit string to the outside, transmitting the 7th transmitted data at the 7th speed.

[0225] In addition, the information bit string allocation device 1-2 extracts the transmission data other than the 7th transmission data from the 2nd transmission data contained in the valid bit string of the 2nd information bit string as the 8th transmission data.

[0226] Information bit string distribution device 1-2 outputs the 8th information bit string, which contains the valid bit string of the 8th transmitted data and the invalid bit string containing the virtual data, to the 3rd information bit string distribution device 1-3.

[0227] The third information bit string distribution device 1-3 obtains the eighth information bit string output from the information bit string distribution device 1-2.

[0228] Information bit string allocation device 1-3 extracts a portion of the transmission data from the 8th transmission data contained in the valid bit string of the 8th information bit string as the 9th transmission data.

[0229] The information bit string distribution device 1-3 outputs an information bit string containing a valid bit string of the 9th transmitted data and an invalid bit string containing virtual data to the outside as the 9th information bit string for transmitting the 9th transmitted data at the 9th speed.

[0230] In addition, the information bit string allocation device 1-3 extracts the transmission data other than the 9th transmission data from the 8th transmission data contained in the valid bit string of the 9th information bit string as the 10th transmission data.

[0231] The information bit string distribution device 1-3 outputs the information bit string containing the valid bit string of the 10th transmitted data and the invalid bit string containing the virtual data as the 10th information bit string to the outside.

[0232] Next, regarding Figure 9 The operation of the information bit string allocation device 4 shown will be explained.

[0233] Figure 10 This is an explanatory diagram showing an example of an information bit string, the first information bit string, the second information bit string, the seventh information bit string, the eighth information bit string, the ninth information bit string, and the tenth information bit string.

[0234] like Figure 10 As shown, the information bit string allocation device 1-1 obtains the information bit string Bsrc[w-1:0] from the outside.

[0235] The operation of information bit string distribution device 1-1 and Figure 7 The information bit string allocation device 1-1 shown operates identically, therefore detailed explanations are omitted.

[0236] Information bit string distribution device 1-1 outputs the first information bit string B1b[v1b-1:0] to the outside and outputs the second information bit string B1t[v1t-1:0] to information bit string distribution device 1-2.

[0237] The first bit string output unit 11 of the information bit string distribution device 1-2 obtains the second information bit string B1t[v1t-1:0] from the information bit string distribution device 1-1.

[0238] The first bit string output unit 11 of the information bit string allocation device 1-2 extracts a portion of the second transmitted data contained in the effective bit string B1t[s1t-1:0] of the second information bit string B1t[v1t-1:0] as the seventh transmitted data. s1t = s2b + s2t, where s2b and s2t are non-negative integers.

[0239] That is, the first bit string output unit 11 extracts the bit string of B1t[s2b-1:0] contained in the second transmitted data in the effective bit string B1t[s1t-1:0] as the seventh transmitted data.

[0240] The number of bits s2b of the 7th transmitted data can be stored in the internal memory of the 1st bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1-2.

[0241] The first bit string output unit 11 of the information bit string distribution device 1-2 extracts a portion of virtual data from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] of the second information bit string B1t[v1t-1:0] as the seventh virtual data.

[0242] That is, the first bit string output unit 11 extracts the bit string of B1t[s1t+(v2b-s2b)-1:s1t] from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] as the seventh virtual data.

[0243] The number of bits s1t of the second transmitted data and the number of bits v2b of the seventh information bit string B2b[v2b-1:0] can be stored in the internal memory of the first bit string output unit 11, or they can be provided from the outside of the information bit string distribution device 1-2.

[0244] The first bit string output unit 11 of the information bit string distribution device 1-2 generates the seventh information bit string B2b[v2b-1:0] which transmits the seventh data at the seventh speed.

[0245] That is, the first bit string output unit 11 generates a seventh information bit string B2b[v2b-1:0] containing the extracted seventh transmitted data valid bit string B2b[s2b-1:0] and the extracted seventh virtual data invalid bit string B2b[v2b-1:s2b].

[0246] The seventh transmission speed of the seventh data transmission is represented by s2b / v2b. The larger the ratio of the number of bits s2b of the seventh data transmission to the number of bits v2b of the seventh information bit string, the faster the seventh speed.

[0247] The first bit string output unit 11 of the information bit string distribution device 1-2 outputs the seventh information bit string B2b[v2b-1:0], which transmits the seventh data at the seventh speed, to the outside.

[0248] The first bit string output unit 11 of the information bit string distribution device 1-2 outputs the acquired second information bit string B1t[v1t-1:0] to the second bit string output unit 12.

[0249] The second bit string output unit 12 of the information bit string distribution device 1-2 obtains the second information bit string B1t[v1t-1:0] from the first bit string output unit 11.

[0250] The second bit string output unit 12 extracts the transmission data other than the seventh transmission data from the second transmission data contained in the second transmission data of the second information bit string B1t[s1t-1:0], which is included in the effective bit string B1t[s1t-1:0], and uses it as the eighth transmission data.

[0251] That is, the first bit string output unit 11 extracts the bit string of B1t[s1t-1:s2b] in the second transmitted data contained in the effective bit string B1t[s1t-1:0] as the eighth transmitted data.

[0252] The number of bits s1t for the second transmitted data and the number of bits s2b for the seventh transmitted data can be stored in the internal memory of the second bit string output unit 12, or they can be provided from outside the information bit string distribution device 1-2.

[0253] The second bit string output unit 12 of the information bit string allocation device 1-2 extracts virtual data other than the seventh virtual data from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] of the second information bit string B1t[v1t-1:0] as the eighth virtual data.

[0254] That is, the second bit string output unit 12 extracts the bit string of B1t[v1t-1:s1t+(v2b-s2b)] from the second virtual data contained in the invalid bit string B1t[v1t-1:s1t] as the eighth virtual data.

[0255] The number of bits v2b in the 7th information bit string B2b[v2b-1:0] can be stored in the internal memory of the 2nd bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1-2.

[0256] The second bit string output unit 12 of the information bit string distribution device 1-2 generates the eighth information bit string B2t[v2t-1:0] which transmits the eighth data at the eighth speed.

[0257] That is, the second bit string output unit 12 generates the eighth information bit string B2t[v2t-1:0] containing the extracted eighth transmitted data valid bit string B2t[s2t-1:0] and the extracted eighth virtual data invalid bit string B2t[v2t-1:s2t].

[0258] The second bit string output unit 12 of the information bit string distribution device 1-2 outputs the eighth information bit string B2t[v2t-1:0] to the information bit string distribution device 1-3.

[0259] The first bit string output unit 11 of the information bit string distribution device 1-3 obtains the eighth information bit string B2t[v2t-1:0] from the information bit string distribution device 1-2.

[0260] The first bit string output unit 11 of the information bit string distribution device 1-3 extracts a portion of the transmission data contained in the effective bit string B2t[s2t-1:0] of the eighth information bit string B2t[v2t-1:0] as the ninth transmission data.

[0261] That is, the first bit string output unit 11 extracts the bit string of B2t[s3b-1:0] contained in the effective bit string B2t[s2t-1:0] as the 9th transmitted data.

[0262] The number of bits s3b of the 9th transmitted data can be stored in the internal memory of the 1st bit string output unit 11, or it can be provided from the outside of the information bit string allocation device 1-3.

[0263] The first bit string output unit 11 of the information bit string distribution device 1-3 extracts a portion of virtual data from the 8th virtual data contained in the invalid bit string B2t[v2t-1:s2t] of the 8th information bit string B2t[v2t-1:0] as the 9th virtual data.

[0264] That is, the first bit string output unit 11 extracts the bit string of B2t[s2t+(v3b-s3b)-1:s2t] from the 8th virtual data contained in the invalid bit string B2t[v2t-1:s2t] as the 9th virtual data.

[0265] The number of bits s2t of the 8th transmitted data and the number of bits v3b of the 9th information bit string B3b[v3b-1:0] can be stored in the internal memory of the 1st bit string output unit 11, or they can be provided from the outside of the information bit string allocation device 1-3.

[0266] The first bit string output unit 11 of the information bit string distribution device 1-3 generates the ninth information bit string B3b[v3b-1:0] which transmits the ninth data at the ninth speed.

[0267] That is, the first bit string output unit 11 generates a ninth information bit string B3b[v3b-1:0] containing the extracted ninth transmitted data valid bit string B3b[s3b-1:0] and the extracted ninth virtual data invalid bit string B3b[v3b-1:s3b].

[0268] The 9th transmission speed of the 9th data is represented by s3b / v3b. The larger the ratio of the number of bits s3b of the 9th data to the number of bits v3b of the 9th information bit string, the faster the 9th transmission speed.

[0269] The first bit string output unit 11 of the information bit string distribution device 1-3 outputs the ninth information bit string B3b[v3b-1:0], which transmits the ninth data at the ninth speed, to the outside.

[0270] The first bit string output unit 11 of the information bit string distribution device 1-3 outputs the acquired eighth information bit string B2t[v2t-1:0] to the second bit string output unit 12.

[0271] The second bit string output unit 12 of the information bit string distribution device 1-3 obtains the eighth information bit string B2t[v2t-1:0] from the first bit string output unit 11.

[0272] The second bit string output unit 12 extracts the transmission data other than the ninth transmission data from the eighth transmission data contained in the effective bit string B2t[s2t-1:0] of the eighth information bit string B2t[v2t-1:0] as the tenth transmission data.

[0273] That is, the first bit string output unit 11 extracts the bit string of B2t[s2t-1:s3b] contained in the eighth transmitted data in the effective bit string B2t[s2t-1:0] as the tenth transmitted data.

[0274] The number of bits s2t for the 8th transmitted data and the number of bits s3b for the 9th transmitted data can be stored in the internal memory of the 2nd bit string output unit 12, or they can be provided from the outside of the information bit string allocation device 1-3.

[0275] The second bit string output unit 12 of the information bit string allocation device 1-3 extracts virtual data other than the ninth virtual data from the eighth virtual data contained in the invalid bit string B2t[v2t-1:s2t] of the eighth information bit string B2t[v2t-1:0] as the tenth virtual data.

[0276] That is, the second bit string output unit 12 extracts the bit string of B2t[v2t-1:s2t+(v3b-s3b)] from the eighth virtual data contained in the invalid bit string B2t[v2t-1:s2t] as the tenth virtual data.

[0277] The number of bits v3b in the 9th information bit string B3b[v3b-1:0] can be stored in the internal memory of the 2nd bit string output unit 12, or it can be provided from the outside of the information bit string allocation device 1-3.

[0278] The second bit string output unit 12 of the information bit string distribution device 1-3 generates the 10th information bit string B3t[v3t-1:0] which transmits the 10th data at the 10th speed.

[0279] That is, the second bit string output unit 12 generates a 10th information bit string B3t[v3t-1:0] containing the extracted 10th transmitted data valid bit string B3t[s3t-1:0] and the extracted 10th virtual data invalid bit string B3t[v3t-1:s3t].

[0280] The 10th speed of transmitting the 10th data is represented by s3t / v3t. The larger the ratio of the number of bits s3t of the 10th data to the number of bits v3t of the 10th information bit string, the faster the 10th speed.

[0281] The second bit string output unit 12 of the information bit string distribution device 1-2 outputs the 10th information bit string B3t[v3t-1:0] which transmits the 10th data at the 10th speed to the outside.

[0282] For example, let w0 be a natural number that is a multiple of 4, and v1b = w0, v1t = w0, v2b = v2t = w0 / 2, v3b = v3t = w0 / 4. In this case, Figure 9 The information bit string allocation device 4 shown can allocate the information bit string Bsrc[w-1:0] in such a way that the maximum value of the branched speed is v1b=w0, v2b=w0 / 2, v3b=w0 / 4, v3t=w0 / 4.

[0283] exist Figure 9 In the information bit string allocation device 4 shown, the number of stages is 3. However, this is just one example; for instance, four information bit string allocation devices 1 can also be configured, and the number of stages in the information bit string allocation device 4 is 4. Furthermore, five information bit string allocation devices 1 can also be configured, and the number of stages in the information bit string allocation device 4 is 5.

[0284] Implementation Method 4

[0285] In Embodiment 4, the information bit string conversion circuit 30, which includes the information bit string allocation device 3 and the information bit string allocation devices 4-1 to 4-4, will be described.

[0286] Figure 11 This is a structural diagram showing the information bit string conversion circuit 30 of embodiment 4.

[0287] Figure 11 The information bit string conversion circuit 30 shown has Figure 7 The diagram shows information bit string allocation device 3, information bit string allocation devices 4-1 to 4-4, distribution matching circuits 5-1 to 5-4, and encoding adjustment circuits 6-1 to 6-4. Information bit string allocation devices 4-1 to 4-4 are respectively connected to… Figure 9 The information bit string allocation device shown is the same as the information bit string allocation device 4.

[0288] Information bit string allocation device 3 is the first information bit string allocation device, and information bit string allocation devices 4-1 to 4-4 are the second information bit string allocation devices.

[0289] Figure 11 The information bit string conversion circuit 30 shown has four second information bit string distribution devices. However, this is just one example, and it may also have five or more second information bit string distribution devices. When the information bit string conversion circuit 30 has five or more second information bit string distribution devices, the distribution matching circuit and the encoding adjustment circuit also each have five or more.

[0290] Information bit string distribution device 3 obtains information bit string BE[w-1:0], outputs the third information bit string BSC[1] to information bit string distribution device 4-1, and outputs the fourth information bit string BSC[2] to information bit string distribution device 4-2.

[0291] In addition, the information bit string distribution device 3 outputs the 5th information bit string BSC[3] to the information bit string distribution device 4-3 and the 6th information bit string BSC[4] to the information bit string distribution device 4-4.

[0292] The third information bit string BSC[1] is equivalent to Figure 8 The third information bit string B2bb[v2bb-1:0] shown, and the fourth information bit string BSC[2] are equivalent to Figure 8 The fourth information bit string shown is B2bt[v2bt-1:0].

[0293] The fifth information bit string BSC[3] is equivalent to Figure 8 The fifth information bit string B2tb[v2tb-1:0] shown, and the sixth information bit string BSC[4] are equivalent to Figure 8 The 6th information bit string shown is B2tt[v2tt-1:0].

[0294] The information bit string allocation device 4-1 obtains the third information bit string BSC[1] and outputs the first information bit string C0[1] to the encoding adjustment circuit 6-1.

[0295] In addition, the information bit string distribution device 4-1 outputs the 7th information bit string C1[1], the 9th information bit string C2[1] and the 10th information bit string C3[1] to the distribution matching circuit 5-1 respectively.

[0296] The first information bit string C0[1] is equivalent to Figure 10 The first information bit string B1b[v1b-1:0] shown, and the seventh information bit string C1[1] are equivalent to Figure 10The 7th information bit string shown is B2b[v2b-1:0].

[0297] The 9th information bit string C2[1] is equivalent to Figure 10 The 9th information bit string B3b[v3b-1:0] shown, and the 10th information bit string C3[1] are equivalent to Figure 10 The 10th information bit string shown is B3t[v3t-1:0].

[0298] The information bit string allocation device 4-2 obtains the fourth information bit string BSC[2] and outputs the first information bit string C0[2] to the encoding adjustment circuit 6-2.

[0299] In addition, the information bit string distribution device 4-2 outputs the 7th information bit string C1[2], the 9th information bit string C2[2], and the 10th information bit string C3[2] to the distribution matching circuit 5-2 respectively.

[0300] The first information bit string C0[2] is equivalent to Figure 10 The first information bit string B1b[v1b-1:0] shown, and the seventh information bit string C1[2] are equivalent to Figure 10 The 7th information bit string shown is B2b[v2b-1:0].

[0301] The 9th information bit string C2[2] is equivalent to Figure 10 The 9th information bit string B3b[v3b-1:0] shown, and the 10th information bit string C3[2] are equivalent to Figure 10 The 10th information bit string shown is B3t[v3t-1:0].

[0302] The information bit string allocation device 4-3 obtains the 5th information bit string BSC[3] and outputs the 1st information bit string C0[3] to the encoding adjustment circuit 6-3.

[0303] In addition, the information bit string distribution device 4-3 outputs the 7th information bit string C1[3], the 9th information bit string C2[3], and the 10th information bit string C3[3] to the distribution matching circuit 5-3 respectively.

[0304] The first information bit string C0[3] is equivalent to Figure 10 The first information bit string B1b[v1b-1:0] shown, and the seventh information bit string C1[3] are equivalent to Figure 10 The 7th information bit string shown is B2b[v2b-1:0].

[0305] The 9th information bit string C2[3] is equivalent to Figure 10 The 9th information bit string B3b[v3b-1:0] shown, and the 10th information bit string C3[3] are equivalent to Figure 10The 10th information bit string shown is B3t[v3t-1:0].

[0306] The information bit string allocation device 4-4 obtains the 6th information bit string BSC[4] and outputs the 1st information bit string C0[4] to the encoding adjustment circuit 6-4.

[0307] In addition, the information bit string distribution device 4-4 outputs the 7th information bit string C1[4], the 9th information bit string C2[4], and the 10th information bit string C3[4] to the distribution matching circuit 5-4 respectively.

[0308] The first information bit string C0[4] is equivalent to Figure 10 The first information bit string B1b[v1b-1:0] shown, and the seventh information bit string C1[4] are equivalent to Figure 10 The 7th information bit string shown is B2b[v2b-1:0].

[0309] The 9th information bit string C2[4] is equivalent to Figure 10 The 9th information bit string B3b[v3b-1:0] shown, and the 10th information bit string C3[4] are equivalent to Figure 10 The 10th information bit string shown is B3t[v3t-1:0].

[0310] The distributed matching circuit 5-k (k = 1, 2, 3, 4) obtains the 7th information bit string C1[k], the 9th information bit string C2[k], and the 10th information bit string C3[k] output from the information bit string distribution device 4-k, respectively.

[0311] The distribution matching circuit 5-k performs probabilistic shaping of the signal point configuration for communication based on the 7th information bit string C1[k], the 9th information bit string C2[k], and the 10th information bit string C3[k], and outputs the bit string D[k] after probability distribution shaping to the encoding adjustment circuit 6-k.

[0312] The distributed matching circuit 5-k is, for example, the same circuit as the distributed matching circuit disclosed in Patent Document 1, and a detailed description of the distributed matching circuit 5-k is omitted.

[0313] Patent Document 1: International Publication No. 2020 / 031257

[0314] The encoding adjustment circuit 6-k (k = 1, 2, 3, 4) obtains the first information bit string C0[k] output from the information bit string distribution device 4-k and the probability distribution shaped bit string D[k] output from the distribution matching circuit 5-k.

[0315] The encoding adjustment circuit 6-k generates a partially probability-distribution-shaped bit string, namely the shaped bit string BS[k], based on the first information bit string C0[k] and the probability distribution-shaped bit string D[k], and outputs the shaped bit string BS[k] to the outside.

[0316] For ease of explanation, the bit string D[k] after probability distribution shaping is the bit string obtained by probability distribution shaping of the 8-value amplitude shift keying (ASK) symbol. The 8-value amplitude shift keying takes 8 values ​​of 1, 3, 5, 7, 9, 11, 13 or 15 as the amplitude value.

[0317] 3 bits are required to represent 8 ASK symbols. Therefore, when the output block of the distributed matching circuit 5-k consists of 128 ASK symbols, at least 384 bits are required as the number of bits in the bit string D[k].

[0318] Furthermore, if the bit string D[k] after probability distribution shaping is a 16ASK symbol with 16 values ​​of 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29 or 31 as the amplitude value, then the number of bits in the bit string D[k] needs to be at least 512 bits.

[0319] The greater the multivaluedness of a symbol, the more bits are calculated as the number of bits in the bit string D[k]. The more bits in the bit string D[k], the greater the power consumption of the distributed matching circuit 5-k, in addition to the increased circuit size. Therefore, the desired number of bits in the bit string D[k] is relatively small.

[0320] To reduce the number of bits in bit string D[k], encoding adjustment circuit 6-k combines bit string D[k] corresponding to symbol string with first information bit string C0[k], thereby generating integer bit string BS[k] corresponding to symbol string with multiple values ​​compared to symbol string represented by bit string D[k].

[0321] The encoding adjustment circuit 6-k outputs the generated integer bit string BS[k] to the outside.

[0322] For example, let bit string D[k] be a 3-bit × 128 bit string representing an 8ASK symbol string of 128 symbols, and the first information bit string C0[k] be a 1-bit × 128 bit string that expands to an 8ASK symbol.

[0323] By combining a 3-bit × 128 bit string with a 1-bit × 128 bit string, a 4-bit × 128 bit string E[k] of 16ASK symbol strings that represents the probability distribution of 128 symbols is obtained.

[0324] In addition, the first information bit string C0[k] can expand the 1 of the 8ASK symbol of bit string D[k] into the 1 or 3 of the 16ASK symbol, expand the 3 of the 8ASK symbol of bit string D[k] into the 5 or 7 of the 16ASK symbol, and expand the 15 of the 8ASK symbol of bit string D[k] into the 29 or 31 of the 16ASK symbol.

[0325] For example, let bit string D[k] be a 3-bit × 128 bit string representing an 8-valued complex number ASK symbol string with 128 symbols, and the first information bit string C0[k] be a 1-bit × 128 bit string that expands to 8ASK symbols.

[0326] By combining a 3-bit × 128 bit string with a 1-bit × 128 bit string, a 4-bit × 128 bit string E[k] is obtained, which represents the probability distribution of the 128 symbols and is a 16-valued complex number ASK symbol string.

[0327] Furthermore, as an 8-valued complex ASK symbol, it is possible to choose any one of (real part, imaginary part) = (1, 1), (3, 1), (5, 1), (5, 3), (5, 5), (7, 1), (7, 3), (7, 5). The first information bit string C0[k] expands (1, 1) of the 8-valued complex ASK symbol of bit string D[k] into (1, 1) or (3, 3), expands (3, 1) of the 8-valued complex ASK symbol into (3, 1) or (1, 3), and expands (5, 1) of the 8-valued complex ASK symbol into (5, 1) or (1, 5). Furthermore, the first information bit string C0[k] can expand the (5, 3) of the 8-valued complex ASK symbol of bit string D[k] into (5, 3) or (3, 5), expand the (5, 5) of the 8-valued complex ASK symbol into (5, 5) or (7, 7), expand the (7, 1) of the 8-valued complex ASK symbol into (7, 1) or (1, 7), expand the (7, 3) of the 8-valued complex ASK symbol into (7, 3) or (3, 7), and expand the (7, 5) of the 8-valued complex ASK symbol into (7, 5) or (5, 7).

[0328] exist Figure 11 In the information bit string conversion circuit 30 shown, the encoding adjustment circuit 6-k (k = 1, 2, 3, 4) generates an integer bit string BS[k] based on the probability distribution-shaped bit string D[k] output from the distribution matching circuit 5-k, and outputs the integer bit string BS[k] to the outside. However, it is not limited to this. Alternatively, the information bit string conversion circuit 30 may not have an encoding adjustment circuit 6-k (k = 1, 2, 3, 4), and the distribution matching circuit 5-k (k = 1, 2, 3, 4) may output the probability distribution-shaped bit string D[k] as BS[k] to the outside.

[0329] Figure 11 The information bit string conversion circuit 30 shown can change the transmission speed of the transmitted data contained in the information bit string transmitted by each subcarrier.

[0330] Implementation Method 5

[0331] In Embodiment 5, an information bit string decoding apparatus 50 having a data extraction unit 51 and a multiplexing unit 52 will be described.

[0332] Figure 12 This is a structural diagram showing the information bit string decoding device 50 of Embodiment 5.

[0333] Figure 13 This is a hardware structure diagram showing the hardware of the information bit string decoding device 50 in Embodiment 5.

[0334] Figure 12 The information bit string decoding device 50 shown includes a data extraction unit 51 and a multiplexing unit 52.

[0335] Data extraction unit 51, for example, is composed of Figure 13 The data extraction circuit 51a shown is implemented.

[0336] The data extraction unit 51 extracts the second transmission data from the second information bit string, which contains a valid bit string containing the second transmission data and an invalid bit string containing virtual data.

[0337] Reuse section 52, for example, is composed of Figure 13 The multiplexing circuit 52a shown is used to implement this.

[0338] The multiplexing unit 52 extracts the first transmission data from the first information bit string, which contains a valid bit string containing the first transmission data and an invalid bit string containing virtual data.

[0339] The multiplexing unit 52 generates an information bit string containing a valid bit string that includes the extracted first transmission data and the second transmission data extracted by the data extraction unit 51, as well as an invalid bit string that includes virtual data.

[0340] exist Figure 12 In this context, it is assumed that the data extraction unit 51 and the multiplexing unit 52, which are structural elements of the information bit string decoding device 50, are respectively composed of... Figure 13 The dedicated hardware implementation shown is assumed to be implemented by data extraction circuit 51a and multiplexing circuit 52a.

[0341] The data extraction circuit 51a and the multiplexing circuit 52a correspond, for example, to a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0342] The structural elements of the information bit string decoding device 50 are not limited to being implemented by dedicated hardware; the information bit string decoding device 50 can also be implemented by software, firmware, or a combination of software and firmware.

[0343] Figure 14 This is a hardware structure diagram of a computer when the information bit string decoding device 50 is implemented by software or firmware.

[0344] When the information bit string decoding device 50 is implemented by software or firmware, a program for causing the computer to execute each processing step in the data extraction unit 51 and the multiplexing unit 52 is stored in the memory 43. Then, the computer's processor 44 executes the program stored in the memory 43.

[0345] In addition, Figure 13 The diagram illustrates an example where the structural elements of the information bit string decoding device 50 are implemented using dedicated hardware. Figure 14 The diagram shows an example of the information bit string decoding device 50 being implemented by software or firmware. However, this is just one example; it is also possible that some structural elements of the information bit string decoding device 50 are implemented by dedicated hardware, while the remaining structural elements are implemented by software or firmware.

[0346] Next, regarding Figure 12 The operation of the information bit string decoding device 50 shown will be explained.

[0347] Figure 15 This is an explanatory diagram showing an example of an information bit string, a first information bit string, and a second information bit string.

[0348] Figure 16 This is a flowchart illustrating an information bit string decoding method as a processing step of the information bit string decoding device 50.

[0349] Provide to Data Extraction Department 51 Figure 15 The second information bit string Ht[vb-1:0] is shown. The second information bit string Ht[vb-1:0] has a valid bit string Ht[st-1:0] containing the second transmitted data and an invalid bit string Ht[vt-1:st] containing the second virtual data.

[0350] The second information bit string Ht[vb-1:0] is equivalent to Figure 4 The second information bit string shown is Bt[vb-1:0].

[0351] Provide to Reuse Department 52 Figure 15The first information bit string Hb[vb-1:0] is shown. The first information bit string Hb[vb-1:0] has a valid bit string Hb[sb-1:0] containing the first transmitted data and an invalid bit string Hb[vb-1:sb] containing the first virtual data.

[0352] The first information bit string Hb[vb-1:0] is equivalent to Figure 4 The first information bit string shown is Bb[vb-1:0].

[0353] When the data extraction unit 51 is provided with the second information bit string Ht[vb-1:0], it extracts the second transmitted data contained in the valid bit string Ht[st-1:0] of the second information bit string Ht[vb-1:0]. Figure 16 Step ST11).

[0354] In addition, the data extraction unit 51 extracts the second virtual data contained in the invalid bit string Ht[vt-1:st] of the second information bit string Ht[vb-1:0].

[0355] The data extraction unit 51 outputs the second transmitted data and the second virtual data to the multiplexing unit 52 respectively.

[0356] The multiplexing unit 52 obtains the second transmission data and the second virtual data from the data extraction unit 51, respectively.

[0357] When the first information bit string Hb[vb-1:0] is provided, the multiplexing unit 52 extracts the first transmission data contained in the effective bit string Hb[sb-1:0] of the first information bit string Hb[vb-1:0].

[0358] In addition, the multiplexing unit 52 extracts the first virtual data contained in the invalid bit string Hb[vb-1:sb] of the first information bit string Hb[vb-1:0].

[0359] The multiplexing unit 52 generates an information bit string Hi[u-1:0] containing a valid bit string Hi[sb+st-1:0] containing the first transmitted data and the second transmitted data, and an invalid bit string Hi[u-1:sb+st] containing the first virtual data and the second virtual data. Figure 16 Step ST12).

[0360] Figure 12 The information bit string decoding device 50 shown is capable of decoding information bit strings equivalent to... Figure 4 The information bit string Bi[u-1:0] shown is decoded from the information bit string Hi[u-1:0].

[0361] Implementation Method 6

[0362] In implementation method 6, for those having 3 Figure 12 The information bit string decoding device 53 of the information bit string decoding device 50 shown will be described.

[0363] Figure 17 This is a structural diagram showing the information bit string decoding device 53 of Embodiment 6.

[0364] Figure 17 The information bit string decoding device 53 shown includes information bit string decoding devices 50-1, 50-2, and 50-3.

[0365] Information bit string decoding devices 50-1, 50-2, and 50-3 are related to Figure 12 The information bit string decoding device 50 shown is the same as the information bit string decoding device.

[0366] The first information bit string decoding device 50-1 of the three information bit string decoding devices 50 obtains... Figure 8 The third information bit string shown is B2bb[v2bb-1:0] and Figure 8 The fourth information bit string B2bt[v2bt-1:0] shown will... Figure 8 The first information bit string B1b[v1b-1:0] shown is output to the third information bit string decoding device 50-3.

[0367] The third information bit string B2bb[v2bb-1:0] is equivalent to Figure 15 The first information bit string Hb[vb-1:0] and the fourth information bit string B2bt[v2bt-1:0] shown are equivalent to Figure 15 The second information bit string shown is Ht[vb-1:0].

[0368] The first information bit string B1b[v1b-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0369] The second information bit string decoding device 50-2 in the three information bit string decoding devices 50 obtains Figure 8 The fifth information bit string shown is B2tb[v2tb-1:0] and Figure 8 The 6th information bit string B2tt[v2tt-1:0] shown will... Figure 8 The second information bit string B1t[v1t-1:0] shown is output to the third information bit string decoding device 50-3.

[0370] The fifth information bit string B2tb[v2tb-1:0] is equivalent to Figure 15The first information bit string Hb[vb-1:0] and the sixth information bit string B2tt[v2tt-1:0] shown are equivalent to Figure 15 The second information bit string shown is Ht[vb-1:0].

[0371] The second information bit string B1t[v1t-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0372] The third information bit string decoding device 50-3 in the three information bit string decoding devices 50 obtains Figure 8 The first information bit string B1b[v1b-1:0] shown is... Figure 8 The second information bit string B1t[v1t-1:0] shown will... Figure 8 The information bit string Bsrc[w-1:0] shown is output to the outside.

[0373] The information bit string Bsrc[w-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0374] Figure 17 The information bit string decoding device 53 shown is related to Figure 7 The information bit string allocation device 3 shown is a pair of devices. Figure 17 The operation of the information bit string decoding device 53 shown is input-output and... Figure 7 The operation of the information bit string allocation device 3 shown is the opposite of the operation of the device.

[0375] exist Figure 17 In the information bit string decoding device 53 shown, the three information bit string decoding devices 50-1, 50-2, and 50-3 are arranged in a tree structure, and the number of levels in the information bit string decoding device 53 is 2. However, this is just one example. For instance, it is also possible to have seven information bit string decoding devices 50 arranged in a tree structure, and the number of levels in the information bit string decoding device 53 is 3. Furthermore, it is also possible to have 15 information bit string decoding devices 50 arranged in a tree structure, and the number of levels in the information bit string decoding device 53 is 4.

[0376] Implementation Method 7

[0377] In implementation method 7, for those having 3 Figure 12 The information bit string decoding device 54 of the information bit string decoding device 50 shown will be described.

[0378] Figure 18 This is a structural diagram showing the information bit string decoding device 54 of Embodiment 7.

[0379] Figure 18The information bit string decoding device 54 shown includes information bit string decoding devices 50-1, 50-2, and 50-3.

[0380] Information bit string decoding devices 50-1, 50-2, and 50-3 are related to Figure 12 The information bit string decoding device 50 shown is the same as the information bit string decoding device.

[0381] The first information bit string decoding device 50-1 of the three information bit string decoding devices 50 obtains... Figure 10 The 9th information bit string B3b[v3b-1:0] shown is... Figure 10 The 10th information bit string B3t[v3t-1:0] shown will... Figure 10 The 8th information bit string B2t[v2t-1:0] shown is output to the 2nd information bit string decoding device 50-2.

[0382] The 9th information bit string B3b[v3b-1:0] is equivalent to Figure 15 The first information bit string Hb[vb-1:0] and the tenth information bit string B3t[v3t-1:0] shown are equivalent to Figure 15 The second information bit string shown is Ht[vb-1:0].

[0383] The 8th information bit string B2t[v2t-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0384] The second information bit string decoding device 50-2 in the three information bit string decoding devices 50 obtains Figure 10 The 7th information bit string B2b[v2b-1:0] shown is... Figure 10 The 8th information bit string B2t[v2t-1:0] shown will... Figure 10 The second information bit string B1t[v1t-1:0] shown is output to the third information bit string decoding device 50-3.

[0385] The 7th information bit string B2b[v2b-1:0] is equivalent to Figure 15 The first information bit string Hb[vb-1:0] and the eighth information bit string B2t[v2t-1:0] shown are equivalent to Figure 15 The second information bit string shown is Ht[vb-1:0].

[0386] The second information bit string B1t[v1t-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0387] The third information bit string decoding device 50-3 in the three information bit string decoding devices 50 obtains Figure 10 The first information bit string B1b[v1b-1:0] shown is... Figure 10 The second information bit string B1t[v1t-1:0] shown will... Figure 10 The information bit string Bsrc[w-1:0] shown is output to the outside.

[0388] The information bit string Bsrc[w-1:0] is equivalent to Figure 15 The information bit string Hi[u-1:0] is shown.

[0389] Figure 18 The information bit string decoding device 54 shown is related to Figure 9 The information bit string allocation device 4 shown is a pair of devices. Figure 18 The operation of the information bit string decoding device 54 shown is input-output and... Figure 9 The operation of the information bit string allocation device 4 shown is the opposite of the operation of the device.

[0390] Figure 18 The information bit string decoding device 54 shown has 3 stages. However, this is just one example; for instance, four information bit string decoding devices 50 can also be configured, resulting in 4 stages for the information bit string decoding device 54. Furthermore, five information bit string decoding devices 50 can also be configured, resulting in 5 stages for the information bit string decoding device 54.

[0391] Implementation Method 8

[0392] In embodiment 8, the information bit string inverse conversion circuit 60, which includes information bit string decoding device 53 and information bit string decoding devices 54-1 to 54-4, will be described.

[0393] Figure 19 This is a structural diagram showing the information bit string inverse conversion circuit 60 of embodiment 8.

[0394] Figure 19 The information bit string inverse conversion circuit 60 shown has Figure 17 The information bit string decoding devices 53, 54-1 to 54-4, decoding adjustment circuits 61-1 to 61-4, and distributed matching terminal circuits 62-1 to 62-4 are shown. The information bit string decoding devices 54-1 to 54-4 are respectively connected to… Figure 18 The information bit string decoding device 54 shown is the same as the information bit string decoding device.

[0395] Information bit string decoding device 53 is the first information bit string decoding device, and information bit string decoding devices 54-1 to 54-4 are the second information bit string decoding devices.

[0396] Figure 19The information bit string inversion circuit 60 shown has four second information bit string decoding devices. However, this is just one example; the information bit string inversion circuit 60 can also have five or more second information bit string decoding devices. When the information bit string inversion circuit 60 has five or more second information bit string decoding devices, the decoding adjustment circuit and the distributed matching terminal circuit also each have five or more.

[0397] The decoding adjustment circuit 61-k (k = 1, 2, 3, 4) is related to... Figure 11 The circuit shown is a pair of encoding adjustment circuits 6-k. The operation of the decoding adjustment circuit 61-k is the opposite of the operation of the encoding adjustment circuit 6-k.

[0398] The bit string HS[k] provided from the outside to the decoding adjustment circuit 61-k is equivalent to the shaped bit string BS[k] output from the encoding adjustment circuit 6-k to the outside.

[0399] The bit string HD[k] output from the decoding adjustment circuit 61-k to the distributed matching terminal circuit 62-k is equivalent to the bit string D[k] output from the distributed matching circuit 5-k to the encoding adjustment circuit 6-k.

[0400] The distributed matching terminal circuit 62-k (k = 1, 2, 3, 4) is related to... Figure 11 The distributed matching circuit 5-k shown is a pair of circuits. The operation of the distributed matching terminal circuit 62-k is the opposite of the operation of the distributed matching circuit 5-k.

[0401] The 7th information bit string HC1[k], the 9th information bit string HC2[k], and the 10th information bit string HC3[k] output from the distributed matching terminal circuit 62-k to the information bit string decoding device 54-k are respectively equivalent to the 7th information bit string C1[k], the 9th information bit string C2[k], and the 10th information bit string C3[k] output from the information bit string distribution device 4-k to the distributed matching circuit 5-k.

[0402] The first information bit string HC0[k] output from the decoding adjustment circuit 61-k to the information bit string decoding device 54-k is equivalent to the first information bit string C0[k] output from the information bit string distribution device 4-k to the encoding adjustment circuit 6-k.

[0403] The information bit string decoding device 54-k (k = 1, 2, 3, 4) is related to... Figure 11 The circuit shown is a pair of information bit string distribution devices 4-k. The operation of the information bit string decoding device 54-k is the opposite of the operation of the information bit string distribution device 4-k.

[0404] The information bit string decoding device 54-1 generates the third information bit string HSC[1] based on the first information bit string HC0[1], the seventh information bit string HC1[1], the ninth information bit string HC2[1], and the tenth information bit string HC3[1].

[0405] The information bit string decoding device 54-2 generates the fourth information bit string HSC[2] based on the first information bit string HC0[2], the seventh information bit string HC1[2], the ninth information bit string HC2[2], and the tenth information bit string HC3[2].

[0406] The information bit string decoding device 54-3 generates the 5th information bit string HSC[3] based on the 1st information bit string HC0[3], the 7th information bit string HC1[3], the 9th information bit string HC2[3] and the 10th information bit string HC3[3].

[0407] The information bit string decoding device 54-4 generates the 6th information bit string HSC[4] based on the 1st information bit string HC0[4], the 7th information bit string HC1[4], the 9th information bit string HC2[4] and the 10th information bit string HC3[4].

[0408] The third information bit string HSC[1] is equivalent to the third information bit string BSC[1] output from the information bit string distribution device 3 to the information bit string distribution device 4-1, and the fourth information bit string HSC[2] is equivalent to the fourth information bit string BSC[2] output from the information bit string distribution device 3 to the information bit string distribution device 4-2.

[0409] The 5th information bit string HSC[3] is equivalent to the 5th information bit string BSC[3] output from the information bit string distribution device 3 to the information bit string distribution device 4-3, and the 6th information bit string HSC[4] is equivalent to the 6th information bit string BSC[4] output from the information bit string distribution device 3 to the information bit string distribution device 4-4.

[0410] The information bit string decoding device 53 is with Figure 11 The circuits of the information bit string distribution device 3 shown are paired, and the operation of the information bit string decoding device 53 is the opposite of the operation of the information bit string distribution device 3.

[0411] The information bit string HE[w-1:0] output from the information bit string decoding device 53 to the outside is equivalent to the information bit string BE[w-1:0] provided from the outside to the information bit string distribution device 3.

[0412] Figure 19 The information bit string inverse conversion circuit 60 shown is related to... Figure 11The information bit string conversion circuit shown is a pair of devices. Figure 19 The operation of the information bit string inverse conversion circuit 60 shown is input-output and... Figure 11 The information bit string conversion circuit 30 shown operates in the opposite manner.

[0413] Implementation Method 9

[0414] In implementation method 9, for those having Figure 11 The optical transmitter 70 of the information bit string conversion circuit 30 shown has an optical transmitter 70 and a digital transmitter 70 with a digital transmitter 70. Figure 19 The optical communication system to which the optical receiver 90 of the information bit string inversion circuit 60 shown is connected via the optical transmission path 80 will be described.

[0415] Figure 20 This is a structural diagram showing the optical communication system of Embodiment 9.

[0416] Figure 20 The optical communication system shown includes an optical transmitter 70, an optical transmission path 80, and an optical receiver 90.

[0417] The optical transmitter 70 includes a signal processing circuit 71, a digital-to-analog converter 72, a light source 73, and an optical modulator 74.

[0418] The optical receiver 90 includes a light source 91, a photodetector 92, an analog-to-digital converter 93, and a signal processing circuit 94.

[0419] like Figure 21 As shown, the transmitting signal processing circuit 71 includes a transmitting code processing circuit 75 and a transmitting waveform processing circuit 78.

[0420] Figure 21 This is a structural diagram showing the internal structure of the signal processing circuit 71.

[0421] The transmitting code processing circuit 75 has Figure 11 The information bit string conversion circuit 30, the error correction coding circuit 76, and the symbol mapping circuit 77 are shown.

[0422] The information bit string conversion circuit 30 obtains the information bit string BE[w-1:0] from the outside and outputs the third information bit string BSC[1], the fourth information bit string BSC[2], the fifth information bit string BSC[3] and the sixth information bit string BSC[4] to the error correction coding circuit 76 respectively.

[0423] Error correction coding circuit 76 performs error correction coding processing on the third information bit string BSC[1], the fourth information bit string BSC[2], the fifth information bit string BSC[3], and the sixth information bit string BSC[4] respectively. Error correction coding processing itself is a well-known technology, so detailed description is omitted.

[0424] The error correction coding circuit 76 outputs the error-corrected 3rd information bit string BSC'[1], the error-corrected 4th information bit string BSC'[2], the error-corrected 5th information bit string BSC'[3], and the error-corrected 6th information bit string BSC'[4] to the symbol mapping circuit 77.

[0425] In addition, the error correction coding circuit 76 outputs the parity check bit string BP[k] (k = 1, 2, 3, 4) generated during the error correction coding process to the symbol mapping circuit 77.

[0426] The symbol mapping circuit 77 generates a transmit modulation symbol string X[k] based on the error-corrected 3rd information bit string BSC'[1], the error-corrected 4th information bit string BSC'[2], the error-corrected 5th information bit string BSC'[3], the error-corrected 6th information bit string BSC'[4], and the parity check bit string BP[k] (k = 1, 2, 3, 4). The generation process of the transmit modulation symbol string X[k] by the symbol mapping circuit 77 is a well-known technique, so detailed description is omitted.

[0427] The symbol mapping circuit 77 outputs the transmitted modulation symbol string X[k] to the transmitted waveform processing circuit 78.

[0428] The transmitting waveform processing circuit 78 generates a digital baseband signal by multiplexing the transmitting modulation symbol strings X[1] to X[4] output from the symbol mapping circuit 77. The generation and processing of the digital baseband signal by the transmitting waveform processing circuit 78 is a well-known technique, so detailed description is omitted.

[0429] The waveform processing circuit 78 outputs the digital baseband signal to the digital-to-analog converter 72.

[0430] The digital-to-analog converter 72 converts the digital baseband signal output from the transmitting waveform processing circuit 78 into an analog electrical signal, and outputs the analog electrical signal to the optical modulator 74. The baud rate of the analog electrical signal is, for example, several Gbaud to hundreds of Gbaud.

[0431] The light source 73 is implemented, for example, by an external resonator-type wavelength-variable light source.

[0432] The light source 73 generates, for example, unmodulated light with a center wavelength of around 1550 nm, and outputs the unmodulated light to the optical modulator 74.

[0433] The optical modulator 74 is implemented, for example, by a polarization multiplexing quadrature phase modulator.

[0434] The optical modulator 74 modulates the unmodulated light output from the light source 73 using the analog electrical signal output from the digital-to-analog converter 72, thereby generating a transmitted optical signal.

[0435] The optical modulator 74 transmits the optical signal to the optical receiver 90 via the optical transmission path 80.

[0436] The optical transmission path 80 is implemented, for example, by optical fiber, optical amplifier, optical combiner / demultiplexer, and wavelength selective switch.

[0437] The light source 91 is implemented, for example, by an external resonator type wavelength-variable light source.

[0438] For example, light source 91 generates unmodulated light with a center wavelength of around 1550nm and outputs the unmodulated light to photodetector 92.

[0439] The photodetector 92 receives the transmitted optical signal output from the optical modulator 74 as the received optical signal.

[0440] The photodetector 92 generates an analog electrical signal by mixing the received optical signal with the unmodulated light output from the light source 91, and outputs the analog electrical signal to the analog-to-digital converter 93.

[0441] The analog-to-digital converter 93 converts the analog electrical signal output from the photodetector 92 into a digital baseband signal, and outputs the digital baseband signal to the receiving signal processing circuit 94.

[0442] like Figure 22 As shown, the receiving signal processing circuit 94 includes a receiving waveform processing circuit 95 and a receiving code processing circuit 96.

[0443] Figure 22 This is a structural diagram showing the internal structure of the receiving signal processing circuit 94.

[0444] The receiving waveform processing circuit 95 separates the digital baseband signal output from the analog-to-digital converter 93 into each subcarrier, generating receiving modulation symbol strings Y[1] to Y[4] that correspond to the transmitting modulation symbol strings X[1] to X[4]. The generation process of the receiving modulation symbol string Y[k] performed by the receiving waveform processing circuit 95 is a well-known technique, so detailed explanation is omitted.

[0445] The receiving waveform processing circuit 95 outputs the received modulation symbol string Y[k] to the receiving code processing circuit 96.

[0446] The receiving code processing circuit 96 includes a symbol demapping circuit 97, an error correction decoding circuit 98, and... Figure 19 The information bit string inverse conversion circuit 60 shown is illustrated.

[0447] The operation of the receive code processing circuit 96 is input, output and... Figure 21The operation of the transmission code processing circuit 75 shown is the opposite of the operation of the transmission code processing circuit.

[0448] The symbol demapping circuit 97 generates information bit strings LS(k) (k=1、2、3、4) that are respectively equivalent to the third information bit string BSC'[1], the fourth information bit string BSC'[2], the fifth information bit string BSC'[3], and the sixth information bit string BSC'[4] after error correction coding, based on the received modulated symbol string Y[k].

[0449] In addition, the symbol demapping circuit 97 generates a bit string LP[k] that is equivalent to the parity check bit string BP[k] (k = 1, 2, 3, 4).

[0450] The symbol demapping circuit 97 outputs the information bit string LS(k) and the bit string LP[k] to the error correction decoding circuit 98, respectively.

[0451] The error correction decoding circuit 98 obtains the information bit string LS(k) and the bit string LP[k] from the symbol demapping circuit 97, respectively.

[0452] The error correction decoding circuit 98 generates information bit strings HSC[k] (k=1, 2, 3, 4) that are equivalent to the 3rd information bit string BSC[1], the 4th information bit string BSC[2], the 5th information bit string BSC[3] and the 6th information bit string BSC[4], respectively, based on the information bit string LS(k) and the bit string LP[k].

[0453] The error correction decoding circuit 98 outputs the information bit string HSC[k] to the information bit string inverse conversion circuit 60.

[0454] The information bit string inverse conversion circuit 60 obtains the information bit string HSC[k] from the error correction decoding circuit 98.

[0455] Figure 20 The optical communication system shown can vary the transmission speed and probability distribution of data transmission for each subcarrier. Therefore, this optical communication system can adjust the trade-off between data transmission distance or data communication quality and frequency utilization efficiency.

[0456] Furthermore, the present invention allows for free combination of various embodiments or arbitrary modification of structural elements in various embodiments, or allows for the omission of arbitrary structural elements in various embodiments.

[0457] Industrial availability

[0458] This invention is applicable to information bit string allocation devices, information bit string conversion circuits, information bit string allocation methods, information bit string decoding devices, information bit string inverse conversion circuits, and optical communication systems.

[0459] Label Explanation

[0460] 1, 1-1, 1-2, 1-3: Information bit string distribution device; 3, 4: Information bit string distribution device; 5-1~5-4: Distribution matching circuit; 6-1~6-4: Encoding adjustment circuit; 11: First bit string output section; 11a: First bit string output circuit; 12: Second bit string output section; 12a: Second bit string output circuit; 21-1, 21-2, 21-3: Branch section; 22: 4-channel shifter; 23: 2-channel shifter; 24: 1-channel shifter; 25-1, 25-2, 25-3: Selector; 30: Information bit string conversion circuit; 41, 43: Memory; 42, 44: Processor; 51: Data extraction section; 51a: Data extraction circuit; 52: Multiplexing section; 52a: Multiplexing circuit; 50, 50-1, 50-2, 50-3 53, 54, 54-1, 54-2, 54-3: Information bit string decoding device; 60: Information bit string inverse conversion circuit; 61-1~61-4: Decoding adjustment circuit; 62-1~62-4: Distributed matching terminal circuit; 70: Optical transmitter; 71: Transmit signal processing circuit; 72: Digital-to-analog converter; 73: Light source; 74: Optical modulator; 75: Transmit code processing circuit; 76: Error correction coding circuit; 77: Symbol mapping circuit; 78: Transmit waveform processing circuit; 80: Optical transmission path; 90: Optical receiver; 91: Light source; 92: Photodetector; 93: Analog-to-digital converter; 94: Receive signal processing circuit; 95: Receive waveform processing circuit; 96: Receive code processing circuit; 97: Symbol demapping circuit; 98: Error correction decoding circuit.

Claims

1. An information bit string conversion circuit, wherein, This information bit string conversion circuit is used in optical communication systems, and it possesses the following features: One primary information bit string allocation device; as well as At least four secondary information bit string allocation devices, The primary information bit string allocation device includes three information bit string allocation devices, namely the first, second, and third information bit string allocation devices. Each of the secondary information bit string allocation devices comprises three information bit string allocation devices, namely the first, second, and third information bit string allocation devices of each of the secondary information bit string allocation devices. The first information bit string allocation device of the primary information bit string allocation device includes: The first bit string output unit acquires an information bit string containing a valid bit string containing transmitted data and an invalid bit string containing virtual data. It extracts transmitted data of length sb from the transmitted data contained in the valid bit string of the information bit string as the first transmitted data and outputs an information bit string containing the valid bit string containing the first transmitted data and the invalid bit string containing virtual data as the first information bit string for transmitting the first transmitted data at the first speed. as well as The second bit string output section extracts a length of transmission data of length st, excluding the first transmission data, from the transmission data contained in the valid bit string of the information bit string obtained from the first bit string output section, and outputs an information bit string containing the valid bit string of the second transmission data and an invalid bit string containing virtual data, as the second information bit string for transmitting the second transmission data at the second speed. The sb is determined based on the first speed at which the first transmitted data is sent. The st is determined based on the second speed at which the second transmitted data is sent. The faster the first speed, the more bits (sb) of the first transmitted data. The faster the second speed, the more bits (st) of the second transmitted data. The first, second, and third information bit string allocation devices of the primary information bit string allocation device, as well as the first, second, and third information bit string allocation devices of the secondary information bit string allocation device, perform information bit string allocation in the same way. In the primary information bit string allocation device: The first information bit string allocation device acquires an information bit string containing a valid bit string of transmitted data and an invalid bit string containing virtual data, outputs the first information bit string to the second information bit string allocation device, and outputs the second information bit string to the third information bit string allocation device. The second information bit string allocation device extracts a portion of the first transmitted data from the first transmitted data contained in the valid bit string of the first information bit string as the third transmitted data, and outputs an information bit string containing the valid bit string of the third transmitted data and an invalid bit string containing virtual data, as the third information bit string for transmitting the third transmitted data at the third speed. It then extracts the transmitted data other than the third transmitted data from the first transmitted data as the fourth transmitted data, and outputs an information bit string containing the valid bit string of the fourth transmitted data and an invalid bit string containing virtual data, as the fourth information bit string for transmitting the fourth transmitted data at the fourth speed. The third information bit string allocation device extracts a portion of the second transmitted data from the valid bit string of the second information bit string as the fifth transmitted data, and outputs an information bit string containing the valid bit string of the fifth transmitted data and an invalid bit string containing virtual data, as the fifth information bit string for transmitting the fifth transmitted data at the fifth speed. It then extracts the transmitted data other than the fifth transmitted data from the second transmitted data as the sixth transmitted data, and outputs an information bit string containing the valid bit string of the sixth transmitted data and an invalid bit string containing virtual data, as the sixth information bit string for transmitting the sixth transmitted data at the sixth speed. In each of the secondary information bit string allocation devices: The first information bit string allocation device obtains an information bit string containing valid bit strings of transmitted data and invalid bit strings of virtual data. It extracts a portion of the transmitted data contained in the valid bit strings of the information bit string as the 11th transmitted data. The information bit string containing the valid bit strings of the 11th transmitted data and the invalid bit strings of virtual data is output as the 11th information bit string, transmitting the 11th transmitted data at the 11th speed. It then extracts the transmitted data other than the 11th transmitted data as the 12th transmitted data. The 12th information bit string, containing the valid bit strings of the 12th transmitted data and the invalid bit strings of virtual data, is output to the second information bit string allocation device. The second information bit string allocation device extracts a portion of the 12th transmitted data contained in the valid bit string of the 12th information bit string as the 7th transmitted data. It outputs the information bit string containing the valid bit string of the 7th transmitted data and the invalid bit string containing virtual data as the 7th information bit string, transmitting the 7th transmitted data at the 7th speed. It then extracts the transmitted data other than the 7th transmitted data from the 12th transmitted data as the 8th transmitted data. Finally, it outputs the 8th information bit string containing the valid bit string of the 8th transmitted data and the invalid bit string containing virtual data to the third information bit string allocation device. The third information bit string allocation device extracts a portion of the transmitted data from the 8th transmitted data contained in the valid bit string of the 8th information bit string as the 9th transmitted data. It outputs an information bit string containing the valid bit string of the 9th transmitted data and an invalid bit string containing virtual data as the 9th information bit string, transmitting the 9th transmitted data at the 9th speed. It also extracts transmitted data other than the 9th transmitted data from the 8th transmitted data as the 10th transmitted data. It outputs an information bit string containing the valid bit string of the 10th transmitted data and an invalid bit string containing virtual data as the 10th information bit string, transmitting the 10th transmitted data at the 10th speed. Each of the secondary information bit string distribution devices acquires any one of the third, fourth, fifth, and sixth information bit strings output from the primary information bit string distribution device, and outputs the seventh, ninth, and tenth information bit strings as output information bit strings to the distributed matching circuit. The distributed matching circuit performs probabilistic shaping of the signal point configuration on the output information bit string and outputs the probabilistically shaped output information bit string.

2. A method for allocating information bit strings, wherein, This information bit string allocation method is applied to an optical communication system, which includes: A primary information bit string allocation device; and At least four secondary information bit string allocation devices, The primary information bit string allocation device includes three information bit string allocation devices, namely the first, second, and third information bit string allocation devices. Each of the secondary information bit string allocation devices comprises three information bit string allocation devices, namely the first, second, and third information bit string allocation devices of each of the secondary information bit string allocation devices. The first information bit string allocation device of the primary information bit string allocation device includes: The first bit string output unit acquires an information bit string containing a valid bit string of transmitted data and an invalid bit string containing dummy data. It extracts transmitted data of length sb from the transmitted data contained in the valid bit string of the information bit string as first transmitted data. It then outputs an information bit string containing the valid bit string of the first transmitted data and the invalid bit string containing dummy data, as the first information bit string for transmitting the first transmitted data at a first speed. The second bit string output section extracts a length of transmission data of length st, excluding the first transmission data, from the transmission data contained in the valid bit string of the information bit string obtained from the first bit string output section, and outputs an information bit string containing the valid bit string of the second transmission data and an invalid bit string containing virtual data, as the second information bit string for transmitting the second transmission data at the second speed. The sb is determined based on the first speed at which the first transmitted data is sent. The st is determined based on the second speed at which the second transmitted data is sent. The faster the first speed, the more bits (sb) of the first transmitted data. The faster the second speed, the more bits (st) of the second transmitted data. The first, second, and third information bit string allocation devices of the primary information bit string allocation device, as well as the first, second, and third information bit string allocation devices of the secondary information bit string allocation device, perform information bit string allocation in the same way. The method includes: The primary information bit string allocation device performs the following operations: The first information bit string allocation device obtains an information bit string containing a valid bit string containing transmitted data and an invalid bit string containing virtual data. The first information bit string is then output to the second information bit string allocation device, and the second information bit string is output to the third information bit string allocation device. The second information bit string allocation device extracts a portion of the first transmitted data from the valid bit string of the first information bit string as the third transmitted data, and outputs an information bit string containing the valid bit string of the third transmitted data and an invalid bit string containing virtual data, which serves as the third information bit string for transmitting the third transmitted data at the third speed. Then, it extracts the transmitted data other than the third transmitted data from the first transmitted data as the fourth transmitted data, and outputs an information bit string containing the valid bit string of the fourth transmitted data and an invalid bit string containing virtual data, which serves as the fourth information bit string for transmitting the fourth transmitted data at the fourth speed. The third information bit string allocation device extracts a portion of the second transmitted data from the valid bit string of the second information bit string as the fifth transmitted data, and outputs an information bit string containing the valid bit string of the fifth transmitted data and an invalid bit string containing virtual data, which serves as the fifth information bit string for transmitting the fifth transmitted data at the fifth speed. Then, it extracts the transmitted data other than the fifth transmitted data from the second transmitted data as the sixth transmitted data, and outputs an information bit string containing the valid bit string of the sixth transmitted data and an invalid bit string containing virtual data, which serves as the sixth information bit string for transmitting the sixth transmitted data at the sixth speed. The following operations are performed by each of the secondary information bit string allocation devices: The first information bit string allocation device obtains an information bit string containing valid bit strings of transmitted data and invalid bit strings containing virtual data. A portion of the transmitted data contained in the valid bit strings of the information bit string is extracted as the 11th transmitted data. This information bit string, containing the valid bit strings of the 11th transmitted data and the invalid bit strings containing virtual data, is output as the 11th information bit string, transmitting the 11th transmitted data at the 11th speed. Transmitted data other than the 11th transmitted data is extracted from the transmitted data as the 12th transmitted data. This 12th information bit string, containing the valid bit strings of the 12th transmitted data and the invalid bit strings containing virtual data, is output to the second information bit string allocation device. The second information bit string allocation device extracts a portion of the 12th transmitted data from the valid bit string of the 12th information bit string as the 7th transmitted data. The information bit string containing the valid bit string of the 7th transmitted data and the invalid bit string containing virtual data is output as the 7th information bit string, transmitting the 7th transmitted data at the 7th speed. The transmission data other than the 7th transmitted data is extracted from the 12th transmitted data as the 8th transmitted data. The 8th information bit string containing the valid bit string of the 8th transmitted data and the invalid bit string containing virtual data is output to the third information bit string allocation device. The third information bit string allocation device extracts a portion of the 8th transmitted data from the valid bit string of the 8th information bit string as the 9th transmitted data. An information bit string containing the valid bit string of the 9th transmitted data and an invalid bit string containing virtual data is output as the 9th information bit string, transmitting the 9th transmitted data at the 9th speed. Similarly, the third information bit string extraction device extracts transmitted data other than the 9th transmitted data from the 8th transmitted data as the 10th transmitted data. An information bit string containing the valid bit string of the 10th transmitted data and an invalid bit string containing virtual data is output as the 10th information bit string, transmitting the 10th transmitted data at the 10th speed. The secondary information bit string allocation devices further perform the following operations: They acquire any one of the third, fourth, fifth, and sixth information bit strings output from the primary information bit string allocation device, and output the seventh, ninth, and tenth information bit strings as output information bit strings to the distributed matching circuit. The distributed matching circuit performs probabilistic shaping of the output information bit string by configuring signal points, and outputs the probabilistically shaped output information bit string.

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