Enhanced cryptographic system and method

Abstract

Methods and systems for extending white-box cryptography are provided. A computing device can retain one or more cryptographic keys encrypted using a white-box cryptographic solution in memory. The one or more cryptographic keys encrypt or decrypt data using cryptographic algorithms not supported by the white-box cryptographic solution. The computing device can perform one or more tamper-proof verifications to detect tampering events intended to tamper with the computing device or applications installed on it. If no tampering event is detected, the computing device can decrypt one or more cryptographic keys using the white-box cryptographic solution and provide one or more cryptographic keys to encrypt or decrypt data using cryptographic algorithms not supported by the white-box cryptographic solution.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 195080, entitled “ENHANCED CRYPTOGRAPHY SYSTEMS AND METHODS,” filed May 31, 2021, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to enhancements or extensions of cryptographic systems and methods. More specifically, this disclosure relates to (i) systems and methods for extending the benefits of white-box cryptography protection to unsupported algorithms, and (ii) systems and methods for extending secure storage in secure cryptographic processors.

[0004] background

[0005] Systems employing cryptography to protect secret data are still vulnerable to attacks from intruders or hackers. Specifically, attackers can access the source code of an application using cryptography, the application's runtime target code, and / or the application's internal workings to obtain or reconstruct the decryption key. The attacker can then use the decryption key to decrypt the secret data. White-box cryptographic systems or solutions obfuscate and embed the secret (or decryption) key within the application code, ensuring that the secret key is neither represented in the source code nor generated during the execution of the corresponding binary code. Therefore, even if an attacker accesses the application's source code or the corresponding binary code, they cannot obtain or reconstruct the secret key. Due to the obfuscation and mixing of the secret key with the application code, applications employing white-box mechanisms or techniques can operate securely even in insecure environments.

[0006] Furthermore, cryptographic processors implementing encryption solutions typically store or retain the secret key in the processor's secure memory. The secret key is used only within the cryptographic processor and is not provided to or released outside of it. Restricting the secret key to the cryptographic processor eliminates or reduces the possibility of external access to it.

[0007] Overview

[0008] Various aspects of this disclosure may be implemented in one or more of the following embodiments:

[0009] Project 1): A method comprising:

[0010] A computing device holds one or more cryptographic keys encrypted using a white-box cryptographic solution in memory, the one or more cryptographic keys using cryptographic algorithms not supported by the white-box cryptographic solution to encrypt or decrypt data;

[0011] The computing device performs one or more tamper-proof verifications to detect tampering events that could be used to tamper with the computing device or applications installed on the computing device; and

[0012] When it is determined that no tampering event has been detected

[0013] Decrypt the one or more cryptographic keys using the white-box cryptographic solution; and

[0014] Provide one or more cryptographic keys to encrypt or decrypt data using cryptographic algorithms that are not supported by the white-box cryptographic solution.

[0015] Project 2): The method described in Project 1 includes:

[0016] Use the described white-box cryptography solution to encrypt one or more decryption keys.

[0017] Project 3): According to the method described in Project 1, wherein the one or more anti-tampering verifications include anti-debugging verifications.

[0018] Project 4): According to the method described in Project 1, wherein the one or more anti-tampering verifications include anti-root verification.

[0019] Project 5): According to the method of Project 1, wherein the one or more anti-tampering verifications include at least one of anti-jailbreak verification or anti-hook verification.

[0020] Project 6): According to the method described in Project 1, wherein the one or more tamper-proof verifications include build time integrity verification.

[0021] Project 7): According to the method of Project 1, wherein performing the one or more anti-tamper verifications includes performing the one or more anti-tamper verifications periodically.

[0022] Item 8): The method described in Item 1 includes:

[0023] Upon detecting a tampering event, the computing device stops the execution of applications installed on the computing device.

[0024] Project 9): The method according to Project 1 further includes encrypting or decrypting the data using the one or more cryptographic keys.

[0025] Item 10): An apparatus comprising:

[0026] Processing circuitry, having a processor and a memory storing executable instructions, which, when executed by the processor, cause the processing circuitry to:

[0027] The memory stores one or more decryption keys encrypted using a white-box cryptography mechanism, the one or more decryption keys being used to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism;

[0028] Perform one or more tamper-proof verifications to detect tampering events that could be used to tamper with the device or an application installed on the device; and

[0029] When it is determined that no tampering event has been detected

[0030] Decrypt the one or more decryption keys using the aforementioned white-box cryptography mechanism; and

[0031] Provide one or more decryption keys to decrypt the data encrypted using the encryption algorithm that is not supported by the white-box cryptography mechanism.

[0032] Item 11): The apparatus according to Item 10, wherein, when executed by the processor, the executable instructions further cause the processing circuitry to:

[0033] The one or more decryption keys are encrypted using the white-box cryptography mechanism described above.

[0034] Item 12): The apparatus according to Item 10, wherein the one or more tamper-proof verifications include debug-proof verifications.

[0035] Item 13): The apparatus according to Item 10, wherein the one or more tamper-proof verifications include root-proof verification.

[0036] Item 14): The apparatus according to Item 10, wherein the one or more tamper-proof verifications include at least one of jailbreak-proof verification or hook-proof verification.

[0037] Item 15): The apparatus according to Item 10, wherein the one or more tamper-proof verifications include build-time integrity verification.

[0038] Item 16): The apparatus according to Item 10, wherein, when the one or more tamper-proof verifications are performed, the executable instructions, when executed by the processor, further cause the processing circuitry to periodically perform the one or more tamper-proof verifications.

[0039] Item 17): The apparatus according to Item 10, wherein, when executed by the processor, the executable instructions further cause the processing circuitry to stop the execution of the application installed on the apparatus upon detecting a tampering event.

[0040] Item 18): The apparatus according to Item 10, wherein, when executed by the processor, the executable instructions further cause the processing circuitry to use the one or more decryption keys to decrypt the data.

[0041] Item 19): The apparatus according to Item 10 includes at least one of the following:

[0042] mobile device;

[0043] Laptop computers;

[0044] Desktop computer; or

[0045] Engine control unit.

[0046] Item 20): A computer-readable medium comprising computer code instructions stored thereon, which, when executed by a processor, cause the processor to:

[0047] One or more decryption keys encrypted using a white-box cryptography mechanism are stored in the memory of a computing device, the one or more decryption keys being used to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism;

[0048] Perform one or more tamper-proof verifications to detect tampering events that could be used to tamper with the computing device or applications installed on the computing device; and

[0049] When it is determined that no tampering event has been detected

[0050] Decrypt the one or more decryption keys using the aforementioned white-box cryptography mechanism; and

[0051] Provide one or more decryption keys to decrypt the data encrypted using the encryption algorithm that is not supported by the white-box cryptography mechanism.

[0052] One embodiment relates to a method. The method includes: storing in memory by a computing device one or more cryptographic keys encrypted using a white-box cryptographic solution, the one or more cryptographic keys being used to encrypt or decrypt data using a cryptographic algorithm not supported by the white-box cryptographic solution; performing one or more tamper-proof verifications by the computing device to detect tampering events intended to tamper with the computing device or applications installed on the computing device; and, upon determining that no tampering event has been detected, decrypting one or more cryptographic keys using the white-box cryptographic solution, and providing one or more cryptographic keys to encrypt or decrypt data using a cryptographic algorithm not supported by the white-box cryptographic solution.

[0053] Another embodiment relates to an apparatus. The apparatus includes processing circuitry having a processor and a memory storing executable instructions, which, when executed by the processor, cause the processing circuitry to: retain in the memory one or more decryption keys encrypted using a white-box cryptography mechanism, the one or more decryption keys decrypting data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism; perform one or more tamper-proof verifications to detect tampering events for tampering with the apparatus or applications installed on the apparatus; and, when it is determined that no tampering event has been detected, decrypt one or more decryption keys using a white-box cryptography mechanism, and provide one or more decryption keys to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism.

[0054] Another embodiment relates to a computer-readable medium including computer code instructions stored thereon. When executed by a processor, the computer code instructions cause the processor to: maintain in the memory of a computing device one or more decryption keys encrypted using a white-box cryptography mechanism, the one or more decryption keys being used to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism; perform one or more tamper-proof verifications to detect tampering events for tampering with the computing device or applications installed on the computing device; and, when it is determined that no tampering event has been detected, decrypt the one or more decryption keys using the white-box cryptography mechanism, providing the one or more decryption keys to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism.

[0055] Another embodiment relates to a method. The method includes: processing circuitry holding a first set of cryptographic resources in a secure memory of a cryptographic processor integrated within the processing circuitry, and holding an encrypted second set of cryptographic resources in a second memory of the processing circuitry. The method includes the processing circuitry or cryptographic processor decrypting the second set of cryptographic resources using at least one cryptographic key from the first set of cryptographic resources, and providing the decrypted second set of cryptographic resources for encrypting or decrypting data. The method also includes the processing circuitry disabling debugging within the processing circuitry.

[0056] In some embodiments, the processing circuitry includes an electronic control unit (ECU). In some embodiments, disabling debugging in the processing circuitry includes disabling the debugging port of the processing circuitry. In some embodiments, disabling debugging in the processing circuitry includes turning off the debugger of the processing circuitry in the production state of the processing circuitry.

[0057] Another embodiment relates to an apparatus including processing circuitry. The processing circuitry may include a cryptographic processor integrated within the processing circuitry. The cryptographic processor may include secure memory. The processing circuitry or cryptographic processor may hold a first set of cryptographic resources in the secure memory of the cryptographic processor integrated within the processing circuitry, and may hold a second set of encrypted cryptographic resources in a second memory of the processing circuitry. The cryptographic processor may use at least one cryptographic key from the first set of cryptographic resources to decrypt the second set of cryptographic resources, and provide the decrypted second set of cryptographic resources to encrypt or decrypt data. The processing circuitry or cryptographic processor may disable debugging within the processing circuitry.

[0058] In some embodiments, the processing circuitry may include an electronic control unit (ECU). In some embodiments, disabling debugging in the processing circuitry may include disabling the debugging port of the processing circuitry. In some embodiments, disabling debugging in the processing circuitry may include turning off the debugger of the processing circuitry in its production state.

[0059] Numerous specific details are provided to impart a thorough understanding of embodiments of the subject matter of this disclosure. In one or more embodiments and / or implementations, the features described in this disclosure may be combined in any suitable manner. In this regard, one or more features of one aspect of the invention may be combined with one or more features of different aspects of the invention. Furthermore, additional features that may not be present in all embodiments or implementations may be identified in some embodiments and / or implementations. Brief description of the attached diagram

[0061] Figure 1 This is a block diagram of a computing device according to an example embodiment, which implements a proposed method for extending the benefits of white-box cryptography protection to unsupported algorithms.

[0062] Figure 2 This is a flowchart illustrating a method for extending the benefits of white-box cryptography protection to unsupported algorithms, based on an example embodiment.

[0063] Figure 3 This is a block diagram of a cryptographic system according to an example embodiment, which extends the secure storage in a secure cryptographic processor.

[0064] Figure 4This is a flowchart of a method for extending secure storage in a secure cryptographic processor according to an example embodiment.

[0065] Detailed description

[0066] Existing data security and / or cryptographic systems are subject to various limitations. The embodiments in this disclosure address at least two technical problems arising in cryptographic systems and methods. The first technical problem relates to white-box cryptography. Specifically, while white-box cryptographic mechanisms or solutions provide enhanced security for secret keys, not all encryption algorithms are supported by white-box cryptography. Some embodiments described herein allow the benefits of white-box cryptography protection to be extended to encryption / decryption algorithms not supported by white-box cryptography. The second technical problem concerns limited secure storage in a cryptographic processor. Specifically, the secure memory or storage in a cryptographic processor used to store secret keys or other secret information is typically very limited and can only store a predefined number of keys or a predefined amount of information, which may be insufficient to store all secret keys or secret information in some practical situations. Some embodiments described herein allow the expansion of secure storage in a secure cryptographic processor.

[0067] Extending the benefits of white-box cryptography protection to algorithms that are not supported.

[0068] When cryptographic algorithms are implemented as source code (e.g., as part of an application), the corresponding cryptographic key (or secret key) is typically retrieved from memory at runtime and passed to the encryption or decryption algorithm. At such a point in time, if a hacker gains access to the executable code or related data at runtime, the hacker can obtain the cryptographic key. The cryptographic key can be stored in memory at runtime or it can be stored as part of the binary code.

[0069] White-box cryptography addresses the weaknesses or vulnerabilities discussed above and enhances the security of cryptographic keys. White-box cryptography never exposes the cryptographic key in memory or binary code. Instead, white-box cryptographic solutions obfuscate, fuzz, and / or mix the key with the encryption or decryption algorithm, making it impossible to reconstruct the cryptographic key even if one accesses the execution code or related execution data associated with the encryption or decryption event. White-box cryptographic solutions can preserve derivatives (or transformations) of the cryptographic key for use in encrypting or decrypting data. Even if a hacker attaches a debugger to a device executing a white-box cryptographic algorithm, the hacker cannot recover the cryptographic key.

[0070] One limitation of white-box cryptography is that no white-box cryptography solution supports all encryption or decryption algorithms. A white-box cryptography solution (or its corresponding library) supports a limited set of cryptographic algorithms and their corresponding obfuscated cryptographic keys. Many companies or entities have legacy or proprietary systems (or applications) that use cryptographic algorithms not supported by any existing white-box cryptography solution.

[0071] The systems and methods described herein allow the benefits of white-box protection (e.g., enhanced security of the secret key) to be extended to cryptographic algorithms not supported by the white-box cryptographic solution. Specifically, the cryptographic algorithms supported by white-box cryptography can be used as intended, and secret keys for unsupported cryptographic algorithms can also be encrypted and / or decrypted. Furthermore, when decrypted by a white-box cryptographic algorithm, tamper-proofing techniques can be used to prevent or mitigate potential access to the secret keys of unsupported cryptographic algorithms. In other words, the systems and methods described herein can be viewed as comprising two main components: a cryptographic component or module for encrypting and / or decrypting secret keys associated with unsupported algorithms using white-box cryptography, and a tamper-proofing module or component for checking or detecting tampering with a computing device or any application installed thereon, thus realizing the proposed method for extending the benefits of white-box protection to unsupported cryptographic algorithms.

[0072] refer to Figure 1 This diagram illustrates a block diagram of a computing device 100 according to an example embodiment, which implements a method for extending the benefits of white-box cryptography protection to unsupported algorithms. In short, the computing device 100 may include an application 102 installed thereon. The application 102 may include or have access to (e.g., via one or more application programming interfaces (APIs)) a white-box solution (or library) 104, a cryptographic component 106, and a tamper-proof component 108. The application 102 may access, or store data in, the random access memory (or other memory) 110 of the computing device 100. The white-box solution 104 may include one or more white-box cryptographic key derivatives 112 (denoted as key derivative 1, ..., key derivative N). The cryptographic component 106 may include an encrypted key blob (or an encrypted set of keys) 114 (e.g., an encrypted set of legacy keys). The encrypted set of keys 114 may represent cryptographic keys associated with cryptographic algorithms not supported by the white-box solution 104 or its corresponding library. The encrypted key set 114 can be encrypted using a white-box solution 104 or an encryption algorithm supported by the corresponding library. Once the encrypted key set 114 is decrypted, the corresponding decryption key 116 (e.g., a legacy key) (referred to herein as key 1, ..., key M) can be provided to RAM 110 for storage.

[0073] refer to Figure 2 According to an example embodiment, a flowchart of illustrated method 200 is shown, which extends the benefits of white-box cryptography protection to unsupported algorithms. In short, method 200 may include maintaining one or more cryptographic keys encrypted using a white-box cryptographic solution in memory (step 202), and checking for tampering events (determination block 204). Method 200 may include decrypting one or more cryptographic keys using a white-box cryptographic solution (step 206), and, if it is determined that no tampering event has been detected, providing one or more cryptographic keys to decrypt data encrypted with an encryption algorithm not supported by the white-box cryptographic solution (step 208). Method 200 may include stopping the application of software integrating the steps of method 200 when a tampering event is detected (step 210).

[0074] Now for reference Figure 1 and Figure 2 The computing device 100 may include a software application 102 that integrates a cryptographic component 106 and a tamper-proof component 108. Both component 106 and component 108 can be implemented as single software modules that can be integrated into various software applications or programs. The software application 102 may integrate a white-box solution 104, or may access the white-box solution 104 via one or more APIs. The white-box solution 104, cryptographic component 106, and tamper-proof component 108 can be controlled by the processor of the computing device 100. Figure 1 (Not shown in the text) Execution.

[0075] The computing device 100 or its processor may maintain a set of encrypted cryptographic keys 114 encrypted using the white-box solution 104 in memory (step 202). When executing the cryptographic component 106, the computing device 100 or processor may encrypt a set of cryptographic (or secret) keys 116 using encryption algorithms supported by the white-box solution 104, and store the corresponding encryption keys 114 in the memory of the computing device 100. The processor may store or maintain the encrypted keys 114 in the processor's flash memory, for example, using the source code or binary code of the cryptographic component 106. The processor may store or maintain the encrypted cryptographic keys in RAM 110. The cryptographic keys 116 may be associated with (or used together with) one or more cryptographic algorithms not supported by the white-box solution 104. In other words, the cryptographic keys 116 may be encryption keys or decryption keys used to encrypt or decrypt data using encryption / decryption algorithms not supported by the white-box solution 104.

[0076] The processor (or computing device 100) may execute anti-tampering component 108 to perform one or more anti-tampering verifications to detect tampering events (decision block 204) for tampering with computing device 100 or application 102 installed on computing device. One or more anti-tampering verifications may include at least one of anti-debugging verification (or inspection), anti-root verification, anti-jailbreak verification, anti-hook verification, or build-time integrity verification.

[0077] When performing anti-debugging verification, the processor or computing device 100 checks whether a debugger is attached to computing device 100, application 102, or any of its components. Once decrypted by cryptography component 106, an attacker could attach a debugger to determine or access cryptography key 116. To avoid this possibility, if a debugger is detected, anti-tampering component 108 can stop the execution of application 102 (or prevent application 102 from starting) upon execution (step 210).

[0078] In the case where computing device 100 is a Linux device (e.g., an Android device), root is a special account that provides system administrator privileges across the entire system or the entire computing device 100. Root protection verification includes the processor checking whether computing device 100 has been tampered with to allow the operating system to run as root and grant users of computing device 100 privileges for process elevation. Under root privileges, a user will have more privileges than the device was originally intended to have. Root privileges grant a user full access to the entire operating system, allowing the user to make changes and access various processes. When a tampering event is detected that causes the operating system of computing device 100 to run as root, the tamper protection component 108, upon execution, can cause the processor to stop the execution of application 102 (or prevent application 102 from starting) (step 210).

[0079] Anti-jailbreak verification is conceptually equivalent to anti-root verification, but it applies to Apple computing devices. In other words, a hacker can root a Linux device but jailbreak an Apple device. The technologies used to implement each of these tampering events are different, and therefore the technologies used to check or detect each of these tampering events are also different. When executed, anti-tampering component 108 can cause the processor to check for tampering events on jailbroken computing device 100 (for Apple devices) and, upon detecting such an event, stop the execution of application 102 (or prevent application 102 from starting) (step 210).

[0080] For build-time integrity verification, when executed, the anti-tampering component 108 can enable the processor to check whether application 102 has been tampered with after build. The processor can check the application's signature at runtime to determine whether the application has been modified after compilation. The processor can stop the execution of application 102 (or prevent application 102 from starting) when a build-time integrity failure is detected (step 210).

[0081] For anti-hook verification, the anti-tampering component 108, when executed, can cause the processor to check whether the computing device 100 or application 102 has been tampered with to include hook code for intercepting function calls, events, and / or messages between different software components. The processor can stop the execution of application 102 (or prevent application 102 from starting) when a hook event is detected (step 210).

[0082] When executed, the anti-tampering component 108 enables the processor to periodically perform one or more anti-tampering verifications during the execution of application 102. For example, the processor may perform anti-tampering verifications before, during, and after the decryption of the encrypted key blob 114. If a tampering event is detected at any point in time, the processor may automatically stop the execution (or startup) of application 102 on computing device 100 (step 210).

[0083] If no tampering event is detected, the processor can decrypt one or more encrypted cryptographic keys 114 using a white-box cryptographic solution (steps 206 and arrow 118), and provide the decrypted cryptographic key for use with cryptographic algorithms not supported by the white-box solution 104 to encrypt or decrypt data (steps 208 and arrow 120). The processor can use a decryption algorithm (and corresponding key derivatives) supported by the white-box solution 104 to decrypt the encrypted cryptographic key 114 associated with an unsupported cryptographic algorithm. When the encrypted cryptographic key 114 is decrypted, the processor can pass the corresponding decryption key 116 to RAM 110 or other memory of the computing device 100. The processor can further use the decrypted key 116 and the corresponding unsupported cryptographic algorithm to encrypt or decrypt data. Note that the cryptographic key 116 can be either an encryption key or a decryption key.

[0084] Considering the aforementioned method involving encrypting non-white-box cryptographic keys using a white-box solution and applying anti-tampering procedures, unsupported cryptographic algorithms and their corresponding cryptographic keys 116 can enjoy similar protection or security as provided by the white-box solution 104. Specifically, when application 102 is not executed, the encryption key is maintained in encrypted form 114 using white-box supported encryption. Since the white-box cryptographic key is never exposed, if a hacker accesses the source code or binary code of application 102, they will not be able to decrypt the encrypted key 114. At runtime, when the cryptographic key 116 associated with an unsupported cryptographic algorithm can be stored in decrypted form, if any tampering event is detected, the anti-tampering component 108 prevents application execution, thus preventing access to the decrypted cryptographic key 116.

[0085] Although with Figure 1 and Figure 2 The associated embodiments are described based on encrypting the cryptographic key blob 114 using the white-box solution 104; however, the same method can be used for other secret information, such as secret information other than the cryptographic key. For example, secret information that can be encrypted using the white-box solution 104 may include digital or security certificates, signatures, or other secret information or data.

[0086] Computing device 100 may include mobile devices, smartphones, tablets, smartwatches, desktop computers, laptops, computer servers, or electronic control units (ECUs) of vehicles. Computing device 100 may have a Linux or Android operating system, iOS, Windows, or another operating system. Application 102 can be downloaded from an online app store and installed on computing device 100.

[0087] Secure storage on extended secure cryptographic processor

[0088] Secure built-in cryptographic processors, such as but not limited to Hardware Security Modules (HSMs), units based on the Secure Hardware Extensions (SHE) specification, or Cryptographic Service Engines (CSE) units, typically have secure memory for storing cryptographic keys or other secret information. However, this secure memory is usually limited and can only store a limited amount of secure data. For example, some secure cryptographic processors can only store 25 or 30 cryptographic keys. This secure memory limitation restricts the number of protection or cryptographic mechanisms that can be used. For example, such cryptographic processors are used in some ECUs, thus limiting the number of protection or cryptographic mechanisms (such as legacy mechanisms) that can be used in the ECU. For digital signature processing and other encryption or decryption needs, the ECU requires more keys than can be stored in the secure memory of the secure cryptographic processor.

[0089] To overcome the aforementioned technical problems, the embodiments described herein allow for the expansion of secure storage within the secure cryptographic processor, thereby increasing the number of protection or cryptographic mechanisms that can be used. Specifically, in addition to the cryptographic keys stored in the secure cryptographic processor, additional cryptographic or secret information can be stored in encrypted form in another memory. The additional cryptographic or secret information can be decrypted using one or more cryptographic keys stored in the secure cryptographic processor. Furthermore, debugging can be disabled to prevent access to the additional cryptographic or secret information during decryption.

[0090] refer to Figure 3 A block diagram is shown of a processing circuit (or microprocessor) 300 configured to be securely stored in a secure cryptographic processor according to an example embodiment. The processing circuit 300 may include a cryptographic processor secure memory 302, flash memory 304, and RAM 306. The cryptographic processor secure memory 302 may store a first set of cryptographic resources 308, such as cryptographic keys Key_1-1, ..., Key_1-N. The flash memory 304 may store additional cryptographic resources 310, such as a second set of cryptographic keys (denoted as Key_2-1, ..., Key_2-M) stored in encrypted form. The cryptographic processor may use one or more encryption algorithms to encrypt the second set of cryptographic keys Key_2-1, ..., Key_2-M, which are associated with one or more cryptographic keys stored in the first set of cryptographic resources 308 in the cryptographic processor secure memory 302. The processing circuit (or microprocessor) 300 may be configured or constructed to disable debugging 314.

[0091] refer to Figure 4 A flowchart of a method 400 for extending secure storage in a secure cryptographic processor according to an example embodiment is shown. In short, method 400 may include holding a first set of cryptographic keys in a first secure memory (e.g., the memory of a secure cryptographic processor) (step 402), and holding a second set of encrypted cryptographic keys in a second memory (step 404). Method 400 may include decrypting the encrypted second set of cryptographic keys using one or more of the first set of cryptographic keys (step 406), and providing the decrypted second set of cryptographic keys for encrypting or decrypting data (step 408). Method 400 may include disabling debugging of processing circuitry, which includes a cryptographic processor or memory storing the decrypted second set of cryptographic keys (step 410). An apparatus (e.g., a computing device) may include processing circuitry (or a microprocessor) 300, or processing circuitry 300 may perform... Figure 4 Method 400 is described in the text.

[0092] Now for reference Figure 3 and Figure 4 The cryptographic processor can use one or more encryption algorithms associated with one or more first cryptographic keys held in the cryptographic processor to encrypt a second set of cryptographic keys (or more generally, a second set of secret information). The processing circuitry 300 or the cryptographic processor can hold the encrypted second set of cryptographic keys or the encrypted second set of secret information in flash memory 304 (step 404). The first set of cryptographic keys or the first set of cryptographic resources 308 is not available to anyone and therefore cannot be disclosed by anyone. As a result, any request from any organization for the first set of cryptographic keys or any key (or any information) of the first set of cryptographic resources 308 can be rejected on the grounds of, for example, unavailability.

[0093] The cryptographic processor can use one or more of the first cryptographic keys held by the cryptographic processor to decrypt the encrypted second cryptographic key or the encrypted second set of secret information (step 406). For example, the cryptographic processor can use the first cryptographic key K_1-x to decrypt the encrypted second cryptographic key or the encrypted second set of secret information. Decryption is performed within the cryptographic processor, such that the first cryptographic key K_1-x (or any cryptographic key in the first cryptographic key set) is always held within the cryptographic processor. The decrypted second cryptographic key or the decrypted second set of secret information can be stored in RAM 306 (or other memory) for encrypting or decrypting data.

[0094] Disabling debugging of the processing circuitry (or microprocessor) 300 or RAM 306 may include disabling debug ports (e.g., JTAG ports, NEXUS ports, or other debug ports) of the processing circuitry (or microprocessor) 300 during production to prevent (e.g., by a hacker) external access to RAM 306, and thus prevent access to the decrypted second set of cryptographic keys or the decrypted second set of secret information held in RAM 306. In some implementations, the debugger may be turned off in the processing circuitry (or microprocessor) 300 when transitioning from a pre-production stage / state to a production stage / state. The debugger may be turned on in the processing circuitry (or microprocessor) 300 to transition from a production state to a diagnostic state. However, in this case, the processing circuitry (or microprocessor) 300 can no longer be used for production because the security of the second set of cryptographic keys or the second set of secret information is compromised when the debugger is on.

[0095] The above about Figure 3 and Figure 4The described method allows for the secure use of additional cryptographic information outside the cryptographic processor by encrypting or decrypting it using one or more cryptographic keys held in the cryptographic processor. The encrypted additional cryptographic information can be held in another memory outside the cryptographic processor (e.g., flash memory 304). Disabling the debugger in the processing circuitry (or microprocessor) 300 prevents access to the additional cryptographic information, especially when the additional cryptographic information is in decrypted form. Therefore, the method discussed above can be considered as extending the secure storage of cryptographic (or secret) information associated with the cryptographic processor.

[0096] In some implementations, the processing circuitry (or microprocessor) 300 may include an ECU, and the methods discussed above provide improved network security using the limited existing resources within the ECU. Without storing the first key in the cryptographic processor and disabling debugging, a hacker could reverse engineer (or deobfuscate) a second set of cryptographic information or keys from flash memory 304 at runtime, or access a second set of cryptographic information or keys in memory (e.g., RAM 306).

[0097] As used herein, the terms “approximately,” “about,” “substantially,” and similar terms are intended to have a broad meaning consistent with common and accepted usage by those skilled in the art to which the subject matter of this disclosure relates. Those skilled in the art, upon review of this disclosure, will understand that these terms are intended to allow for the description of certain features described and claimed, without limiting the scope of those features to the precise numerical ranges provided. Therefore, these terms should be interpreted as indicating that non-substantial or irrelevant modifications or alterations to the described and claimed subject matter are considered to be within the scope of the disclosure set forth in the appended claims.

[0098] It should be noted that the term "exemplary" and its variations, as used herein to describe various embodiments, are intended to indicate that these embodiments are possible examples, representations, or illustrations of possible embodiments (and these terms are not intended to imply that these embodiments are necessarily special or superior examples). It is important to note that the construction and arrangement of the apparatuses and systems shown in the various exemplary embodiments are merely illustrative. Furthermore, any element disclosed in one embodiment may be combined with or used in conjunction with any other embodiment disclosed herein. Additionally, although the drawings and description may show a particular order of method steps, the order of these steps may differ from that depicted and described unless otherwise specified above. Furthermore, two or more steps may be performed simultaneously or partially simultaneously unless otherwise specified above. For example, such variations may depend on the chosen software and hardware system and the designer's choices. All these variations are within the scope of this disclosure.

[0099] As used herein, the term "coupled" and its variations refer to two components being directly or indirectly connected to each other. This connection can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such a connection can be achieved by directly coupling two components to each other, by coupling two components to each other using one or more separate intermediate components, or by coupling two components to each other using an intermediate component that forms a single integral body with one of the two components. If "coupled" or its variations are modified by an appended term (e.g., directly coupled), the general definition of "coupled" provided above is modified by the simple linguistic meaning of the appended term (e.g., "directly coupled" means a connection of two components without any separate intermediate component), resulting in a narrower definition than the general definition of "coupled" provided above. This coupling can be mechanical, electrical, or fluid. For example, circuit A communicatively "coupled" to circuit B can mean that circuit A communicates directly with circuit B (i.e., without an intermediary) or indirectly with circuit B (e.g., through one or more intermediaries).

[0100] References to the location of elements herein (e.g., “top,” “bottom,” “above,” “below”) are used only to describe the orientation of the various elements in the accompanying drawings. It should be noted that the orientation of the various elements may differ according to other exemplary embodiments, and such variations are intended to be included in this disclosure.

[0101] Embodiments within the scope of this disclosure include program products comprising computer- or machine-readable media carrying or having computer- or machine-executable instructions or data structures stored thereon. Such machine-readable media can be any available medium accessible to a computer. A computer-readable medium can be a tangible computer-readable storage medium storing computer-readable program code. Computer-readable storage media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing. More specific examples of computer-readable media may include, but are not limited to, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), optical storage devices, magnetic storage devices, holographic storage media, micromechanical storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium can be any tangible medium that may contain and / or store computer-readable program code for use by and / or in conjunction with an instruction execution system, apparatus, or device. Machine-executable instructions include, for example, instructions and data that cause a computer or processing machine to perform a particular function or group of functions.

[0102] Computer-readable media can also be computer-readable signal media. A computer-readable signal medium may include, for example, a propagated data signal in which computer-readable program code is contained (e.g., in baseband or as part of a carrier wave). Such a propagated signal can take any of a wide variety of forms, including, but not limited to, electrical, electromagnetic, magnetic, optical, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium that is not a computer-readable storage medium but can deliver, propagate, or transmit computer-readable program code for use by or in conjunction with an instruction execution system, device, or apparatus. The computer-readable program code contained on the computer-readable signal medium can be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, radio frequency (RF), or any suitable combination thereof.

[0103] In one embodiment, a computer-readable medium may comprise a combination of one or more computer-readable storage media and one or more computer-readable signal media. For example, computer-readable program code may be transmitted as an electromagnetic signal via an optical fiber for processor execution, or it may be stored in a RAM storage device for processor execution.

[0104] Computer-readable program code for performing the operations of aspects of this disclosure can be written in any combination of one or more other programming languages ​​(including object-oriented programming languages ​​such as Java, Smalltalk, C++, or the like) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program code can execute entirely on the device / computing apparatus (e.g., controller 104), partially on the device / computing apparatus (e.g., controller), as a standalone computer-readable package, partially on the device / computing apparatus and partially on a remote computer, or entirely on a remote computer or server. In the latter case, as described above, the remote computer can be connected to the device / computing apparatus (e.g., controller) via any type of network (including local area network (LAN) or wide area network (WAN), or can be connected to an external computer (e.g., via the Internet through an Internet service provider)).

[0105] The program code may also be stored in a computer-readable medium and may direct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture, the article of manufacture including instructions that implement the functions / actions specified in one or more blocks of a schematic flowchart and / or schematic block diagram.

Claims

1. An enhanced cryptographic method, comprising: A computing device holds one or more cryptographic keys encrypted using a white-box cryptographic solution in memory, the one or more cryptographic keys using cryptographic algorithms not supported by the white-box cryptographic solution to encrypt or decrypt data. The computing device performs one or more tamper-proof verifications to detect tampering events that could be used to tamper with the computing device or applications installed on the computing device. as well as When it is determined that no tampering event has been detected Decrypt one or more cryptographic keys using the white-box cryptography solution described above; as well as Provide one or more cryptographic keys to encrypt or decrypt data using cryptographic algorithms that are not supported by the white-box cryptographic solution.

2. The method according to claim 1, comprising: Use the described white-box cryptography solution to encrypt one or more decryption keys.

3. The method according to claim 1 or 2, wherein, The one or more anti-tampering verifications include anti-debugging verifications.

4. The method according to claim 1 or 2, wherein, The one or more anti-tampering verifications include anti-root verification.

5. The method according to claim 1 or 2, wherein, The one or more anti-tampering verifications include at least one of anti-jailbreak verification or anti-hook verification.

6. The method according to claim 1 or 2, wherein, The one or more tamper-proof verifications include build time integrity verification.

7. The method according to claim 1 or 2, wherein, Performing the one or more anti-tamper verifications includes performing the one or more anti-tamper verifications periodically.

8. The method according to claim 1 or 2, comprising: Upon detecting a tampering event, the computing device stops the execution of applications installed on the computing device.

9. The method according to claim 1 or 2, further comprising encrypting or decrypting the data using the one or more cryptographic keys.

10. An enhanced cryptographic device, comprising: Processing circuitry, having a processor and a memory storing executable instructions, which, when executed by the processor, cause the processing circuitry to: The memory stores one or more decryption keys encrypted using a white-box cryptography mechanism, the one or more decryption keys being used to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism; Perform one or more tamper-proof verifications to detect tampering events that could be used to tamper with the device or an application installed on the device; as well as When it is determined that no tampering event has been detected The white-box cryptography mechanism described above is used to decrypt one or more decryption keys; as well as Provide one or more decryption keys to decrypt the data encrypted with the encryption algorithm that is not supported by the white-box cryptography mechanism.

11. The apparatus according to claim 10, wherein, When executed by the processor, the executable instructions also cause the processing circuitry to: The one or more decryption keys are encrypted using the white-box cryptography mechanism described above.

12. The apparatus according to claim 10 or 11, wherein, The one or more anti-tampering verifications include anti-debugging verifications.

13. The apparatus according to claim 10 or 11, wherein, The one or more anti-tampering verifications include anti-root verification.

14. The apparatus according to claim 10 or 11, wherein, The one or more anti-tampering verifications include at least one of anti-jailbreak verification or anti-hook verification.

15. The apparatus according to claim 10 or 11, wherein, The one or more tamper-proof verifications include build time integrity verification.

16. The apparatus according to claim 10 or 11, wherein, When executing the one or more tamper-proof verifications, the executable instructions, when executed by the processor, also cause the processing circuitry to periodically execute the one or more tamper-proof verifications.

17. The apparatus according to claim 10 or 11, wherein, When executed by the processor, the executable instructions also cause the processing circuitry to stop the execution of the application installed on the device upon detecting a tampering event.

18. The apparatus according to claim 10 or 11, wherein, When executed by the processor, the executable instructions also cause the processing circuitry to use the one or more decryption keys to decrypt the data.

19. The apparatus according to claim 10 or 11, comprising at least one of the following: mobile device; Laptop computers; Desktop computer; or Engine control unit.

20. A computer-readable medium comprising computer code instructions stored thereon, which, when executed by a processor, cause the processor to: One or more decryption keys encrypted using a white-box cryptography mechanism are stored in the memory of a computing device, the one or more decryption keys being used to decrypt data encrypted using an encryption algorithm not supported by the white-box cryptography mechanism; Perform one or more tamper-proof verifications to detect tampering events that could be used to tamper with the computing device or applications installed on the computing device; as well as When it is determined that no tampering event has been detected The white-box cryptography mechanism described above is used to decrypt one or more decryption keys; as well as Provide one or more decryption keys to decrypt the data encrypted with the encryption algorithm that is not supported by the white-box cryptography mechanism.

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