A method of extracting parameters of a tunneling field effect transistor

Abstract

The application discloses a method for extracting parameters of a tunneling field effect transistor, and belongs to the technical field of semiconductors. und The gate capacitance of the TFET device is measured by a semiconductor parameter analyzer, and then the N-type or P-type DL und When the channel surface of the TFET device is in a depletion state, the outer edge gate capacitance surface density C OFS0 of the source end of the device and the outer edge gate capacitance surface density C OFD0 of the drain end of the device are obtained; and parameters L und of the tunneling field effect transistor are obtained according to a formula. The method can be completed by means of only a semiconductor analyzer and MATLAB software, and has the advantages of rapidness and low cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for extracting parameters of a tunneling field-effect transistor. Background Technology

[0002] The development of AIoT (Artificial Intelligence of Things) technology has placed higher demands on semiconductor power consumption, and tunneling field-effect transistors (TFETs) are considered one of the most promising low-power devices. Both the source and drain terminals of a TFET contain tunneling junctions. The source junction provides the on-state current for device conduction, while the drain junction increases the off-state current. Generally, methods such as reducing the drain doping concentration or creating an under-covered drain region are used to increase the tunneling width of the drain junction and reduce the band-tunneling current of the drain junction.

[0003] The drain undercover region refers to the electrical length of a tunneling field-effect transistor (TF-FET) from the gate edge near the drain to the drain tunnel junction. Knowing the length of the drain undercover region is necessary for methods of fabricating it, such as isolating fluctuation sources and adjusting electrical performance. However, existing physical characterization methods can only obtain the physical length of the drain undercover region for a single device, and performing physical characterization on each device is costly. Therefore, there is a need to invent a method for extracting the length of the drain undercover region of a TF-FET, which can extract the electrical length of the drain undercover region solely through electrical characterization. Summary of the Invention

[0004] The purpose of this invention is to provide a method for extracting parameters of tunneling field-effect transistors (DLTS), which can extract parameters of DTS with undercovered drain regions solely through electrical characterization. und -TFET) average drain undercover electrical length L und .

[0005] The technical solution provided by this invention is as follows:

[0006] A method for extracting tunneling field-effect transistors (DLs) with undercovered drain regions und -TFET) average drain undercover electrical length L und The method is characterized by:

[0007] Measuring N-type DL with a semiconductor parameter analyzer und - The gate capacitance of a TFET device (or P-type) is used to obtain an N-type DL. und When the channel surface of a -TFET device (or P-type) is in a depletion state, the surface density of the gate capacitance C at the outer edge of the device source terminal is... OFS0 and the surface density C of the gate capacitance at the outer edge of the device drain terminal OFD0Calculate L according to formula (1) und The value, complete L und The extraction process.

[0008]

[0009] ε in formula (1) OFF and ε ON DL und The dielectric constants of the source gate sidewall and the drain gate sidewall of a -TFET device, L G For DL und - Gate length of a TFET device, EOT is DL und - The effective gate oxide thickness of a TFET device, ε0 is the vacuum dielectric constant, and π is pi. Both ε0 and π are constants known to professionals in the field and can be found in textbooks or online. OFF ε ON L G Both EOT and DL are measured. und The material and structural parameters of a TFET device can only be obtained by extracting parameters from the device under test.

[0010] Furthermore, obtain DL und -TFET device ε OFF ε ON L G The method for EOT parameters has the following characteristics:

[0011] Measuring N-type DL with a semiconductor parameter analyzer und - The gate capacitance of a TFET device (or P-type) is used to obtain an N-type DL. und - The surface density C of the outer edge gate capacitance at the source of a TFET device (or P-type) when the channel surface is in an accumulation state (or inversion state). OFS1 N-type DL und - The surface density C of the outer edge gate capacitance at the drain terminal of a TFET device (or P-type) when the channel surface is in an inversion state (or accumulation state) OFD2 and DL und -TFET device equivalent gate oxide capacitance surface density C OX According to the measured DL und - The layout of a TFET device yields its gate length L G The values ​​are calculated using formulas (2), (3), and (4) to determine EOT and ε. OFF and ε ON The value, complete DL und -TFET device ε OFF ε ON L GAnd EOT parameter extraction work.

[0012]

[0013]

[0014]

[0015] In formula (2), ε OX This refers to the dielectric constant of silicon dioxide, a constant known to professionals in the field, which can be found in textbooks or online. H in formula (3) and formula (4) G All are DL und The gate conductivity layer height of a -TFET device can be found in DL. und The fabrication parameters for -TFET devices are obtained by referring to the deposition thickness of the gate conductive layer material, which is H. G .

[0016] Typically, DL obtained through semiconductor analyzer testing und The gate capacitance of a TFET device refers to the gate-source capacitance and the gate-drain capacitance, which vary with the gate voltage. Their physical components include the equivalent gate oxide capacitance, the outer edge gate capacitance at the source, the outer edge gate capacitance at the drain, and the depletion layer capacitance. These physical components need to be obtained through analysis of test data and cannot be directly measured using a semiconductor analyzer.

[0017] Furthermore, a semiconductor parameter analyzer was used to measure different gate voltages V. G Corresponding N-type DL und - Gate-source capacitance and gate-drain capacitance of a TFET device (or P-type), source voltage V S and leakage voltage V D Both are 0V, gate voltage V G The scan range is from -VDD to VDD. VDD is the DL. und - The power supply voltage corresponding to a circuit composed of TFET devices. DL for each gate length und - Test N TFET devices, and test a total of M devices with different gate lengths. The size of N can be a positive integer greater than or equal to 1, and the size of M can be a positive integer greater than or equal to 1.

[0018] For each gate length DL und For a TFET device, calculate the average gate-source capacitance and gate-drain capacitance of N devices, and divide by the gate area of ​​the device to obtain the average gate-source capacitance surface density C. GS and average gate-drain capacitance surface density C GD , will C GS and C GD The summation yields the average gate capacitance surface density C.GG The gate area of ​​a device refers to the measured DL. und -TFET device gate length L G With gate width W G The product can be obtained by measuring the map.

[0019] Plot the average gate-source capacitance surface density C GS Average gate-drain capacitance surface density C GD and average gate capacitance surface density C GG Relative to gate voltage V G The change curve is used to assist in subsequent data processing. It can be observed that DL... und -TFET devices have unique electrical characteristics, namely, their "C GS -V G "and "C GD -V G "The curve exhibits gate length dependence and secondary activation." (C) GG -V G "The curve exhibits grid length dependence and a three-segment saturation region. Define "C" GG -V G "A certain gate voltage V0 is defined in the saturation region of the middle section of the curve. DL is defined as..." und -TFET devices' "C" GS -V G "A certain gate voltage in the saturation region after the curve turns on for the second time is V1, and DL is defined." und -TFET devices' "C" GD -V G "The gate voltage in the saturation region after the curve is turned on for the second time is V2."

[0020] DL of M types of gate lengths und -The average gate capacitance density of the TFET device C GG V is extracted from the middle. G The value C when =V1 GG1 There are a total of M. From the M types of gate lengths in DL... und -The average gate capacitance density of the TFET device C GG V is extracted from the middle. G The value C when =V2 GG2 There are a total of M. From the M types of gate lengths in DL... und -The average gate-source capacitance surface density of the TFET device C GS V is extracted from the middle. G The value C when =V1 GS1 There are a total of M. From the M types of gate lengths in DL... und -The average gate-source capacitance surface density of the TFET device C GS V is extracted from the middle. GThe value C when =V0 GS0 There are a total of M. From the M types of gate lengths in DL... und -The average gate-source capacitance surface density of the TFET device C GD V is extracted from the middle. G The value C when =V0 GD0 There are a total of M.

[0021] Use MATLAB or other data processing software to process the M C values ​​extracted above. GG1 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GG1 =P1+Q1*(1 / L) G ), where P1 refers to C OX That is, the value on the left side of formula (2). Using the same method, the M C values ​​extracted above are... GG2 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GG2 =P2+Q2*(1 / L) G Q2 refers to C OFD2 *L G That is, the value on the left side of formula (4). Using the same method, the M C values ​​extracted above are... GS1 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GS1 =P3+Q3*(1 / L) G Q3 refers to C OFS1 *L G That is, the value on the left side of formula (3). Using the same method, the M C values ​​extracted above are... GS0 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GS0 =P4+Q4*(1 / L) G Q4 refers to C OFS0 *L G This is used to substitute the corresponding part on the left side of formula (1) for calculation. Using the same method, the M C values ​​extracted above are also calculated. GD0 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GD0 =P5 + Q5 * (1 / L) G Q5 refers to C OFD0 *L G , is used to substitute into the corresponding part on the left side of formula (1) for calculation.

[0022] The beneficial effects of this invention are as follows:

[0023] The method proposed in this invention can be achieved solely through DL und Electrical tests and data analysis were performed on the gate capacitance of the -TFET device to extract the DL. und - The electrical length L of the average drain undercover region of a TFET device und All the work can be done using only a semiconductor parameter analyzer and MATLAB, offering advantages such as speed and low cost. Attached Figure Description

[0024] Figure 1 The extraction of DL proposed in this invention und Flowchart of the average drain undercover electrical length of a TFET device;

[0025] Figure 2 illustrates the method proposed in this invention for extracting a certain DL. und -Interim results of the average drain undercover electrical length of the TFET device, specifically

[0026] (a) is the average gate-source capacitance surface density (C GS ) relative to the gate voltage (V G The curve of change;

[0027] (b) is the average gate-drain capacitance surface density (C GD ) relative to the gate voltage (V G The curve of change;

[0028] (c) represents the average gate capacitance surface density (C GG ) relative to the gate voltage (V G The curve of change;

[0029] (d) is C GG1 Compared to 1 / L G The variation curve and its linear fitting results;

[0030] (e) is C GG2 Compared to 1 / L G The variation curve and its linear fitting results;

[0031] (f) is C GS1 Compared to 1 / L G The variation curve and its linear fitting results;

[0032] (g) is C GS0 Compared to 1 / L G The variation curve and its linear fitting results;

[0033] (h) is C GD0 Compared to 1 / L G The variation curve and its linear fitting results;

[0034] Figure 3 The DL studied in Figure 2 und -Schematic diagram of the structure and geometric parameters of the TFET device;

[0035] In the picture:

[0036] 1—High-resistivity silicon substrate; 2—Shallow trench isolation;

[0037] 3—Gate dielectric layer; 4—Gate conductive layer;

[0038] 5—Source end sidewall; 6—Drain end sidewall;

[0039] 7—Source end impurity doping region; 8—Drain end impurity doping region;

[0040] 9—Source metal layer; 10—Drain metal layer; Detailed Implementation

[0041] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0042] Figure 1 This invention demonstrates the extraction of deep learning (DL) proposed in specific embodiments. und - The average drain undercover electrical length L of a TFET device und The flowchart illustrates the proposed method for extracting L. und Methods and extraction of ε OFF ε ON L G The methods for obtaining EOT parameters and the physical components of each gate capacitance have been integrated. Figure 1 The steps in Figure 3 One of the DLs shown und -TFET devices achieve average drain undercoverage electrical length L und Upon extraction, the device was determined to be an N-type TFET device.

[0043] First, the gate-source capacitance and gate-drain capacitance of the device are tested using a semiconductor parameter analyzer, and the gate voltage V is measured. G The scan range is -2.5V to 2.5V, and the source voltage V... S and leakage voltage V DAll were 0V. A total of five devices with different gate lengths were tested, with five devices tested for each gate length. The gate lengths were 60nm, 120nm, 180nm, 240nm, and 300nm.

[0044] Next, for each gate length device, the measured gate-source capacitance and gate-drain capacitance are divided by the gate area of ​​the device to obtain the gate-source capacitance surface density and the gate-drain capacitance surface density.

[0045] Next, the average gate-source capacitance surface density C corresponding to each gate length device is calculated. GS and average gate-drain capacitance surface density C GD ;

[0046] Next, the average gate-source capacitance surface density C GS and average gate-drain capacitance surface density C GD By summing the results, the average gate capacitance surface density C corresponding to each gate length device can be calculated. GG ;

[0047] Next, as shown in Figure 2(a), the average gate-source capacitance surface density C for each gate length device is calculated. GS Relative to gate voltage V G The change curves are plotted on a graph;

[0048] Next, as shown in Figure 2(b), the average gate-drain capacitance surface density C for each gate length device is calculated. GD Relative to gate voltage V G The change curves are plotted on a graph;

[0049] Gate length dependence and secondary turn-on phenomena can be observed in both Figure 2(a) and Figure 2(b). After each turn-on, there is a region where the capacitance hardly changes relative to the gate voltage; this is the capacitance saturation region, and the corresponding capacitance value is the saturation capacitance. Let V1 = -2.5V and V2 = 1V.

[0050] Next, as shown in Figure 2(c), the average gate capacitance surface density C of each gate length device is calculated. GG Relative to gate voltage V G The change curves are plotted on a graph;

[0051] In Figure 2(c), the gate length dependence and three saturation regions can be observed. The gate voltage of the middle saturation region, -0.7V, is selected as V0.

[0052] Next, for each gate length device, extract V G = Average gate-source capacitance surface density at V1 (C GS As C GS1 ;

[0053] Next, for each gate length device, extract VG = Average gate-source capacitance surface density at V0 (C GS As C GS0 ;

[0054] Next, for each gate length device, extract V G = Average gate-drain capacitance surface density at V0 (C GD As C GD0 ;

[0055] Next, for each gate length device, extract V G = Average gate capacitance surface density (C) at V1 GG As C GG1 ;

[0056] Next, for each gate length device, extract V G = Average gate capacitance surface density (C) at V2 GG As C GG2 ;

[0057] Next, as shown in Figure 2(d), C GG1 Compared to 1 / L G The variation curves and their linear fitting results are plotted on a single graph, and the fitting result is...

[0058] Next, as shown in Figure 2(e), C GG2 Compared to 1 / L G The variation curves and their linear fitting results are plotted on a single graph, and the fitting result is...

[0059] Next, as shown in Figure 2(f), C GS1 Compared to 1 / L G The variation curves and their linear fitting results are plotted on a single graph, and the fitting result is...

[0060] Next, as shown in Figure 2(g), C GS0 Compared to 1 / L G The variation curves and their linear fitting results are plotted on a single graph, and the fitting result is...

[0061] Next, as shown in Figure 2(h), C GD0 Compared to 1 / L G The variation curves and their linear fitting results are plotted on a single graph, and the fitting result is...

[0062] Next, according to formula (2), Substituting the parameter ε0 = 8.85 × 10 -14F / cm and ε ox =3.9, and the extracted EOT = 2.3nm;

[0063] Next, according to formula (4), Substituting the parameters EOT = 2.3 nm and ε0 = 8.85 × 10⁻⁶, we get... -14 F / cm and H G =89nm, ε was extracted ON =7.6;

[0064] Next, according to formula (3), Substituting the parameters EOT = 2.3 nm and ε0 = 8.85 × 10⁻⁶, we get... -14 F / cm and H G =89nm, ε was extracted OFF =6.9;

[0065] Next, according to formula (1), Substituting the parameters EOT = 2.3 nm and ε0 = 8.85 × 10⁻⁶, we get... -14 F / cm, ε OFF =6.9 and ε ON =7.6, extracting L und =19nm;

[0066] L und The length refers to the electrical length from the gate boundary near the drain end to the drain tunnel junction, which is approximately equal to the length L from the gate boundary near the drain end to the drain metal layer boundary. m Subtract the width L of the peak doping concentration region of the drain impurity doping region 8 of the drain metal layer 10. d A certain characterization is obtained through TEM. Figure 3 The L of the device shown m The value is 30nm, and L is obtained through Sentaurus Sprocess simulation. d The width is 10 nm. This verifies that the proposed method extracts DL. und - The reasonableness and accuracy of the length of the average drain undercover region of a TFET device.

[0067] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for extracting parameters of a tunneling field-effect transistor, comprising the following steps: 1) Measure N-type or P-type DL using a semiconductor parameter analyzer und - The gate capacitance of the TFET device, thus obtaining N-type or P-type DL und When the channel surface of a -TFET device is in a depletion state, the surface density of the gate capacitance C at the outer edge of the source terminal of the device is... OFS0 and the surface density C of the gate capacitance at the outer edge of the device drain terminal OFD0 ;Measure N-type or P-type DL using a semiconductor parameter analyzer und - The gate capacitance of the TFET device, thus obtaining N-type or P-type DL und - The surface density C of the outer edge gate capacitance at the source terminal of a TFET device when the channel surface is in an accumulation state or an inversion state. OFS1 N-type or P-type DL und - The surface density C of the outer edge gate capacitance at the drain terminal of a TFET device when the channel surface is in an inversion or accumulation state. OFD2 and DL und -TFET device equivalent gate oxide capacitance surface density C OX ; 2) Calculate L according to formula (1) und The value, （1） According to the measured DL und - The layout of a TFET device yields its gate length L G The values ​​are calculated using formulas (2), (3), and (4) to determine EOT and ε. OFF and ε ON The value; （2） （3） （4） In the above formula (1), ε OFF and ε ON DL und The dielectric constants of the source gate sidewall and the drain gate sidewall of a -TFET device, L G For DL und - Gate length of a TFET device, EOT is DL und - The effective gate oxide thickness of the TFET device, where ε0 is the vacuum dielectric constant. Let π be the mathematical constant ε. OFF ε ON L G Both EOT and DL are measured. und - The material and structural parameters of the TFET device, in formula (2), ε OX This refers to the dielectric constant of silicon dioxide, H in formulas (3) and (4). G All are DL und - The gate conductivity layer height of the TFET device; thus obtaining the parameter L of the tunneling field-effect transistor. und .

2. The method for extracting tunneling field-effect transistor parameters as described in claim 1, characterized in that, Measure different gate voltages V using a semiconductor parameter analyzer G Corresponding N-type or P-type DL und -TFET device gate-source capacitance and gate-drain capacitance, source voltage V S and leakage voltage V D Both are 0V, gate voltage V G The scan range is from -VDD to VDD, where VDD is the DL. und The power supply voltage corresponding to the circuit composed of -TFET devices, and the DL for each gate length. und - Test N TFET devices, and test a total of M devices with different gate lengths. N is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 1.

3. The method for extracting tunneling field-effect transistor parameters as described in claim 2, characterized in that, For each gate length DL und For a TFET device, calculate the average gate-source capacitance and gate-drain capacitance of N devices, and divide by the gate area of ​​the device to obtain the average gate-source capacitance surface density C. GS and average gate-drain capacitance surface density C GD , will C GS and C GD The summation yields the average gate capacitance surface density C. GG And the average gate-source capacitance surface density C is obtained. GS Average gate-drain capacitance surface density C GD and average gate capacitance surface density C GG Relative to gate voltage V G The curve of change, defined as "C" GG -V G "A certain gate voltage V0 is defined in the saturation region of the middle section of the curve. DL is defined as..." und -TFET devices' "C" GS -V G "A certain gate voltage in the saturation region after the curve turns on for the second time is V1, and DL is defined." und -TFET devices' "C" GD -V G "A certain gate voltage in the saturation region after the curve is turned on for the second time is V2; from M gate lengths DL..." und -The average gate capacitance density of the TFET device C GG V is extracted from the middle. G The value C when =V1 GG1 There are a total of M; from M types of grid length DL und -The average gate capacitance density of the TFET device C GG V is extracted from the middle. G The value C when =V2 GG2 There are a total of M; from M types of grid length DL und -The average gate-source capacitance surface density of the TFET device C GS V is extracted from the middle. G The value C when =V1 GS1 There are a total of M; from M types of grid length DL und -The average gate-source capacitance surface density of the TFET device C GS V is extracted from the middle. G The value C when =V0 GS0 There are a total of M; from M types of grid lengths DL und -The average gate-source capacitance surface density of the TFET device C GD V is extracted from the middle. G The value C when =V0 GD0 There are a total of M C's; use MATLAB or other data processing software to process the M C's extracted above. GG1 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GG1 = P1+Q1*(1 / L G ), where P1 refers to C OX Using the same method, process the M C values ​​extracted above. GG2 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GG2 = P2+Q2*(1 / L G Q2 refers to C OFD2 *L G Using the same method, process the M C values ​​obtained above. GS1 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GS1 = P3+Q3*(1 / L G Q3 refers to C OFS1 *L G Using the same method, process the M C values ​​obtained above. GS0 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GS0 = P4 + Q4 * (1 / L) G Q4 refers to C OFS0 *L G Using the same method, process the M C values ​​obtained above. GD0 and its corresponding M 1 / L G Perform a linear fit to obtain the fitting formula C. GD0 = P5 + Q5 * (1 / L) G Q5 refers to C OFD0 *L G .

4. The method for extracting tunneling field-effect transistor parameters as described in claim 3, characterized in that, The gate area A of a DLund-TFET device is equal to the gate length L. G *Gate width W G .

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