Dual channel data deletion and insertion circuit, data deletion method, and data insertion method

Abstract

The application discloses a double-channel data deletion and insertion circuit, a data deletion method and a data insertion method. The circuit comprises an input end, an enable signal register, a selector, a first register, a shift state register, a combination logic block, a second register, a shift cache register and an output end. The input end comprises an enable signal input end and a double-channel data input end. The enable signal input end is connected to the combination logic block through the enable signal register. The double-channel data input end is connected to the combination logic block through the selector and the first register. The output end of the shift state register is connected to the combination logic block. The input end of the shift cache register is connected to the output end of the combination logic block. The output end of the shift cache register is connected to the input end of the combination logic block. The output end of the combination logic block is connected to the output end through the second register. The application realizes data operation only by adding two-stage registers and a small amount of control logic, and greatly reduces resource consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a dual-channel data deletion and insertion circuit, a data deletion method, and a data insertion method. Background Technology

[0002] With the development of integrated circuits and the explosive growth of data volume, designs need to process more data. To reduce design complexity and process requirements, the data bit width is generally expanded in designs, and dual-channel is the most common approach for processing high-speed data.

[0003] In integrated circuit design, data deletion and insertion are common requirements. For example, data can be expanded and compressed on the data bus; data can be controlled in memory according to the memory capacity, deleting invalid data when space is tight and adding blank data when space is free.

[0004] Compared to single-channel serial data transmission, inserting and deleting data in multi-channel data transmission is more complex because the two channels transmit data in parallel and the data order is related. Current methods perform corresponding deletions and insertions on two channels, thus not affecting the data order. Data insertion is shown in Figures 1 and 2. Deletion operations can be performed by directly pulling the valid data bit low.

[0005] However, the insertion method shown in Figure 1-2 is relatively limited and cannot handle the case of inserting a single data. A more common approach is to use two storage devices to buffer the two data channels. However, the control logic during reading is cumbersome. It is necessary to make a judgment based on the data read last time. If the data includes an insertion control signal, the read enable is paused and data insertion is performed in the next clock cycle. The reading of the other channel data is then resumed after one clock cycle.

[0006] The above methods have high resource overhead, and the complex external control logic of storage leads to a decrease in timing performance. Moreover, the process of simply pulling down the valid bit when deleting data is illegal in some application scenarios. For example, if one valid bit is pulled down during data transmission, it will affect the processing speed of the next level. If a subsequent module is designed to process invalid data, it will result in a waste of clock cycles and resources. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a dual-channel data deletion and insertion circuit and method for digital integrated circuits.

[0008] In a first aspect, the present invention provides a dual-channel data deletion and insertion circuit, comprising: an input terminal, an enable signal register ena_d1, a selector, a first register, a shift state register shift_state, a combinational logic block, a second register, a shift buffer register shift data_tmp, and an output terminal;

[0009] The input terminals include an enable signal input terminal ena_in and a dual-channel data input terminal. The enable signal input terminal ena_in is connected to the combinational logic block via an enable signal register ena_d1. The dual-channel data input terminal is connected to the combinational logic block via the selector and the first register. The output terminal of the shift state register shift_state is connected to the combinational logic block. The input terminal of the shift buffer register shift data_tmp is connected to the output terminal of the combinational logic block, and the output terminal is connected to the input terminal of the combinational logic block. The output terminal of the combinational logic block is connected to the output terminal via a second register.

[0010] In one embodiment of the present invention, the dual-channel data input terminal includes: a 0-channel data input terminal data0_in and a 1-channel data input terminal data1_in, and the first register includes: a 0-channel data register data0_d1 and a 1-channel data register data1_d1;

[0011] The 0-channel data input terminal data0_in is connected to the input terminal of the selector, the 1-channel data input terminal data1_in is connected to the input terminal of the selector and the 1-channel data register data1_d1, and the output terminal of the selector is connected to the 0-channel data register data0_d1.

[0012] In one embodiment of the present invention, the second register includes: an enable shift register shift_ena, a 0-channel data shift register shift_data0, and a 1-channel data shift register shift_data1, and the output terminal includes: an enable signal output terminal ena_out, a 0-channel data output terminal data0_out, and a 1-channel data output terminal data1_out;

[0013] The outputs of the combinational logic block are connected to the enable signal outputs ena_out, data output data0_out, and data output data1_out via the enable shift register shift_ena, the 0-channel data shift register shift_data0, and the 1-channel data shift register shift_data1, respectively.

[0014] Secondly, the present invention provides a data deletion method applied to a dual-channel data deletion and insertion circuit, comprising:

[0015] The data to be deleted is determined, and the valid data is transmitted to the 0 channel data register data0_d1; wherein, the data to be deleted is input from the 0 channel data input terminal data0_in or the 1 channel data input terminal data1_in, and the valid data is the data corresponding to the data to be deleted in another channel at the same time;

[0016] Based on the transition state of the shift state register shift_state, process the current data in the 0 channel data register data0_d1, where the current data in the 0 channel data register data0_d1 contains the valid data;

[0017] When the next clock arrives, acquire the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1.

[0018] In one embodiment of the present invention, before the step of processing the current data in the 0-channel data register data0_d1 according to the transition state of the shift state register shift_state, the method further includes:

[0019] The transition state of the shift state register shift_state is detected; the transition state of the shift state register shift_state includes a transition from 0 to 1 or a transition from 1 to 0.

[0020] In one embodiment of the present invention, when the shift state register shift_state transitions from 0 to 1, the step of processing the current data in the 0 channel data register data0_d1 according to the transition state of the shift state register shift_state includes:

[0021] The current data in the 0 channel data register data0_d1 is buffered into the shift buffer register shiftdata_tmp, and the shift enable is pulled low;

[0022] In shift mode, the current data in the shift buffer register shift data_tmp is cached to the 0 channel data shift register shift_data0, the current data in the 0 channel data register data0_d1 is cached to the 1 channel data shift register shift_data1, and the current data in the 1 channel data register data1_d1 is cached to the shift buffer register shift data_tmp.

[0023] When the next clock arrives, the steps of obtaining the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1 include:

[0024] When the next clock arrives, both the data register data0_d1 for channel 0 and the data register data1_d1 for channel 1 maintain the output of the current clock.

[0025] In one embodiment of the present invention, when the shift state register shift_state transitions from 1 to 0, the step of processing the current data in the 0 channel data register data0_d1 according to the transition state of the shift state register shift_state includes:

[0026] The current data containing the valid data in the 0 channel data register data0_d1 is cached into the 1 channel data shift register shift_data1, and the shift enable is kept active;

[0027] When the next clock arrives, the steps of obtaining the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1 include:

[0028] When the next clock arrives, output the current data in the 0-channel data shift register shift_data0 and the current data in the 1-channel data shift register shift_data1.

[0029] Thirdly, the present invention provides a data insertion method applied to the aforementioned dual-channel data deletion and insertion circuit, comprising:

[0030] Obtain the data to be inserted and determine the data insertion position in channel 0 or channel 1;

[0031] The first data is determined based on the data insertion position, and the first data is: the data in another channel corresponding to the original data at the data insertion position at the same time;

[0032] The first data and the original data are processed according to the data insertion position, and the data to be inserted is cached in the 0-channel data shift register shift_data0;

[0033] When the next clock arrives, acquire the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1.

[0034] In one embodiment of the present invention, when the data insertion position is channel 0, the step of processing the first data and the original data according to the data insertion position, and buffering the data to be inserted into the channel 0 data shift register shift_data0, includes:

[0035] The original data and the first data are cached in the 0-channel data register data0_d1 and the 1-channel data register data1_d1, respectively.

[0036] The data to be inserted is cached in the 0-channel data shift register shift_data0. The current data containing the original data in the 0-channel data register data0_d1 is cached in the 1-channel data shift register shift_data1. The current data containing the first data in the 1-channel data register data1_d1 is cached in the shift cache register shift_data_tmp.

[0037] In one embodiment of the present invention, when the data insertion position is channel 1, the step of processing the first data and the original data according to the data insertion position, and buffering the data to be inserted into the channel 0 data shift register shift_data0, includes:

[0038] The original data and the first data are cached in channel 1 data register data1_d1 and channel 0 data register data0_d1, respectively.

[0039] The data to be inserted is cached in the 0-channel data shift register shift_data0. The current data containing the original data in the 1-channel data register data1_d1 is cached in the 1-channel data shift register shift_data1. The current data containing the first data in the 0-channel data register data0_d1 is cached in the shift buffer register shift_data_tmp.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] This invention provides a dual-channel data deletion and insertion circuit, a data deletion method, and a data insertion method. The circuit uses a shift state switching mechanism to perform data operations based on the behavior after deleting or inserting individual data. Compared to existing technologies that utilize storage in dual channels for data deletion and insertion, this invention achieves data operations by adding only two levels of registers and a small amount of control logic, significantly reducing resource consumption. Furthermore, the combinational logic chain is short during circuit implementation, and the corresponding operations do not burden high-frequency timing.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0043] Figure 1a This is a schematic diagram of data insertion in related technologies;

[0044] Figure 1b This is another schematic diagram of data insertion in related technologies;

[0045] Figure 2 This is a schematic diagram of the dual-channel data deletion and insertion circuit provided in an embodiment of the present invention;

[0046] Figure 3 This is a flowchart of the data deletion method provided in an embodiment of the present invention;

[0047] Figure 4a This is a schematic diagram of data processing for the shift state provided in an embodiment of the present invention;

[0048] Figure 4b This is a schematic diagram of data processing in a non-shifted state provided in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram illustrating data deletion when the shift state register shift_state changes from 0 to 1 according to an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram illustrating data deletion when the shift state register shift_state changes from 1 to 0 according to an embodiment of the present invention;

[0051] Figure 7 This is a flowchart of the data insertion method provided in an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram illustrating data insertion when the shift state register shift_state changes from 0 to 1 according to an embodiment of the present invention;

[0053] Figure 9 This is a waveform diagram of random deletion stimulus verification provided in an embodiment of the present invention;

[0054] Figure 10 This is a waveform diagram of random deletion and insertion stimulus verification provided in an embodiment of the present invention. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0056] Figure 2 This is a schematic diagram of the dual-channel data deletion and insertion circuit provided in an embodiment of the present invention. Figure 2 As shown, this embodiment of the invention provides a dual-channel data deletion and insertion circuit, including: an input terminal, an enable signal register ena_d1, a selector, a first register, a shift state register shift_state, a combinational logic block, a second register, a shift buffer register shift data_tmp, and an output terminal;

[0057] The input terminals include: an enable signal input terminal ena_in and a dual-channel data input terminal. The enable signal input terminal ena_in is connected to the combinational logic block via the enable signal register ena_d1. The dual-channel data input terminal is connected to the combinational logic block via a selector and a first register. The output terminal of the shift state register shift_state is connected to the combinational logic block. The input terminal of the shift buffer register shift data_tmp is connected to the output terminal of the combinational logic block, and the output terminal is connected to the input terminal of the combinational logic block. The output terminal of the combinational logic block is connected to the output terminal via a second register.

[0058] Optionally, the dual-channel data input terminal includes: a 0-channel data input terminal data0_in and a 1-channel data input terminal data1_in, and the first register includes: a 0-channel data register data0_d1 and a 1-channel data register data1_d1;

[0059] The data input terminal data0_in of channel 0 is connected to the input terminal of the selector, the data input terminal data1_in of channel 1 is connected to the input terminal of the selector and the data register data1_d1 of channel 1 respectively, and the output terminal of the selector is connected to the data register data0_d1 of channel 0.

[0060] Optionally, the second register includes: an enable shift register shift_ena, a 0-channel data shift register shift_data0, and a 1-channel data shift register shift_data1, and the output includes: an enable signal output ena_out, a 0-channel data output data0_out, and a 1-channel data output data1_out;

[0061] The outputs of the combinational logic block are connected to the enable signal outputs ena_out, data output data0_out, and data output data1_out via the enable shift register shift_ena, the 0-channel data shift register shift_data0, and the 1-channel data shift register shift_data1, respectively.

[0062] Figure 3 This is a flowchart of the data deletion method provided in an embodiment of the present invention. Figure 3The embodiment of the present invention shown provides a data deletion method applied to the above-mentioned dual-channel data deletion and insertion circuit, including:

[0063] S31. Determine the data to be deleted and transfer the valid data to the 0 channel data register data0_d1; wherein, the data to be deleted is input from the 0 channel data input terminal data0_in or the 1 channel data input terminal data1_in, and the valid data is the data corresponding to the data to be deleted in another channel at the same time;

[0064] S32. Based on the transition state of the shift state register shift_state, process the current data in the 0 channel data register data0_d1. The current data in the 0 channel data register data0_d1 contains valid data.

[0065] S33. When the next clock arrives, obtain the outputs of data register data0_d1 for channel 0 and data register data1_d1 for channel 1.

[0066] Optionally, before processing the current data in the 0 channel data register data0_d1 based on the transition state of the shift state register shift_state, the method further includes:

[0067] Detect the transition state of the shift state register shift_state; the transition state of the shift state register shift_state includes a transition from 0 to 1 or a transition from 1 to 0.

[0068] The following embodiment describes the data deletion methods for different transition states of the shift state register shift_state.

[0069] For example, when the shift state register shift_state transitions from 0 to 1, the step of processing the current data in the channel 0 data register data0_d1 according to the transition state of the shift state register shift_state includes:

[0070] S221. Buffer the current data in the 0 channel data register data0_d1 into the shift buffer register shiftdata_tmp, and pull the shift enable low;

[0071] S222. In shift mode, cache the current data in shift buffer register shift data_tmp to shift_data0 for channel 0 data shift register, cache the current data in data0_d1 for channel 0 data shift register shift_data1 for channel 1 data shift register, and cache the current data in data1_d1 for channel 1 data shift register shift data_tmp.

[0072] Figure 4a This is a schematic diagram of data processing for the shift state provided in an embodiment of the present invention. Figure 4b This is a schematic diagram of data processing in a non-shifted state provided by an embodiment of the present invention. It should be noted that, please refer to... Figures 4a-4b The biggest difference between the shifted and non-shifted states lies in the data processing from data_d1 (channel 0 data register data0_d1, channel 1 data register data1_d1) to shift_data (channel 0 data shift register shift_data0, channel 1 data shift register shift_data1). For example, in the non-shifted state, data is transmitted directly without processing (data0_d1->shift_data0; data1_d1->shift_data1); while in the shifted state, the data on channel 1 needs to be buffered, resulting in a phase difference between the input and output (data0_d1->shift_data1; data1_d1->shift_data_tmp; shift_data_tmp->shift_data0). The arrow -> indicates the specific data flow direction, and the output is always taken directly from shift_data, consistent with the circuit structure.

[0073] Figure 5 This is a schematic diagram illustrating data deletion when the shift state register shift_state transitions from 0 to 1, as provided in an embodiment of the present invention. Figure 5As shown, when the shift state register shift_state changes from 0 to 1, taking the deletion of channel 0 data data2 as an example, at the same moment, the corresponding data in channel 1 for data2 is data3. Therefore, data3 is the valid data corresponding to data2, and data3 is transferred to the channel 0 data register data0_d1. Then, the current data in the channel 0 data register data0_d1 is buffered into the shift buffer register shift data_tmp. The current data in the channel 0 data register data0_d1 contains the valid data data3. At the same time, the shift enable is pulled low, waiting for the next clock to perform the normal shift state operation (the shift_data operation of clk3). That is to say, shift_ena = 1'b0, the shift_data of the current clock (clk2) is invalid, and the output port does not output.

[0074] Furthermore, while maintaining the shift state, the current data (including valid data data3) in the shift buffer register shift data_tmp is buffered to the 0 channel data shift register shift_data0, the current data in the 0 channel data register data0_d1 is buffered to the 1 channel data shift register shift_data1, and the current data in the 1 channel data register data1_d1 is buffered to the shift buffer register shift data_tmp.

[0075] When the next clock arrives, the steps for obtaining the outputs of channel 0 data register data0_d1 and channel 1 data register data1_d1 include:

[0076] When the next clock arrives, both the data register data0_d1 for channel 0 and the data register data1_d1 for channel 1 will maintain the output of the current clock.

[0077] Please continue reading Figure 5 From the output results (data0_out for channel 0 and data1_out for channel 1), the data output after the above processing is data0, data1, data3, data4, and data2 has been deleted.

[0078] Figure 6 This is a schematic diagram illustrating data deletion when the shift state register shift_state transitions from 1 to 0, as provided in an embodiment of the present invention. On the other hand, as... Figure 6 As shown, when the shift state register shift_state transitions from 1 to 0, the steps for processing the current data in the channel 0 data register data0_d1 according to the transition state of the shift state register shift_state include:

[0079] The current data containing valid data in the channel 0 data register data0_d1 is buffered into the channel 1 data shift register shift_data1, and the shift enable is kept active.

[0080] When the next clock arrives, the steps for obtaining the outputs of channel 0 data register data0_d1 and channel 1 data register data1_d1 include:

[0081] When the next clock arrives, output the current data in the channel 0 data shift register shift_data0 and the current data in the channel 1 data shift register shift_data1.

[0082] Specifically, taking the deletion of channel 0 data data2 as an example, when the shift status register shift_state transitions from 1 to 0, the current data containing valid data data3 in the channel 0 data register data0_d1 is buffered into the channel 1 data shift register shift_data1. At this time, the shift mode is maintained, and the shift enable remains active (the output in the next cycle will retrieve data from shift_data and output normally); the next clock cycle will then perform normal no-shift mode operation (the shift_data operation of clk3). Please continue to see... Figure 6 From the output results, the output data is data0, data1, data2, data3, data5, data6, and the deleted data data2. Among them, data0 is the data of the previous clock corresponding to data1 and data2.

[0083] Figure 7 This is a flowchart of the data insertion method provided in an embodiment of the present invention. Figure 7 As shown, this embodiment of the invention also provides a data insertion method applied to a dual-channel data deletion and insertion circuit, including:

[0084] S71. Obtain the data to be inserted and determine the data insertion position in channel 0 or channel 1;

[0085] S72. Determine the first data based on the data insertion position. The first data is the data in another channel corresponding to the original data at the data insertion position at the same time.

[0086] S73. Process the first data and the original data according to the data insertion position, and cache the data to be inserted into the 0-channel data shift register shift_data0;

[0087] S74. When the next clock arrives, obtain the outputs of data register data0_d1 for channel 0 and data register data1_d1 for channel 1.

[0088] It should be understood that data insertion can also be divided into two cases: the shift state register shift_state transitioning from 1 to 0 and from 0 to 1. However, due to the pipelining process and the existence of only one buffer (shift buffer register shift_data_tmp), the circuit described above is more suitable for insertion in either the case of transitioning from 0 to 1 or from 1 to 0. Furthermore, unrestricted data insertion will lead to the loss of normal data. In other words, if the data insertion is restricted to transitioning from 0 to 1 (or from 1 to 0), corresponding data deletion is required to ensure that normal data is not lost.

[0089] Figure 8 This is a schematic diagram illustrating data insertion when the shift state register shift_state transitions from 0 to 1 according to an embodiment of the present invention. When the data insertion position is channel 0, step S73, which involves processing the first data and the original data according to the data insertion position and buffering the data to be inserted into the channel 0 data shift register shift_data0, includes:

[0090] S731. Buffer the original data and the first data into the 0-channel data register data0_d1 and the 1-channel data register data1_d1 respectively;

[0091] S732. Buffer the data to be inserted into the 0-channel data shift register shift_data0, buffer the current data containing the original data in the 0-channel data register data0_d1 into the 1-channel data shift register shift_data1, and buffer the current data containing the first data in the 1-channel data register data1_d1 into the shift buffer register shift_data_tmp.

[0092] Specifically, such as Figure 8As shown, when the shift state register shift_state changes from 0 to 1, the data to be inserted is IDLE, and the data insertion position is the position where the original data data2 is located. The original data data2 and the first data data3 are cached in the 0-channel data register data0_d1 and the 1-channel data register data1_d1, respectively. The data to be inserted, IDLE, is cached in the 0-channel data shift register shift_data0. Then, the current data containing the original data data2 in the 0-channel data register data0_d1 is cached in the 1-channel data shift register shift_data1, and the current data containing the first data data3 in the 1-channel data register data1_d1 is cached in the shift buffer register shift_data_tmp.

[0093] The output shows that the data is data0, data1, IDLE, data2, data3, data5, and data6, with the data IDLE inserted before data2.

[0094] When the data insertion position is channel 1, the steps of processing the first data and the original data according to the data insertion position, and buffering the data to be inserted into the channel 0 data shift register shift_data0 include:

[0095] The original data and the first data are cached in the 1-channel data register data1_d1 and the 0-channel data register data0_d1, respectively.

[0096] The data to be inserted is cached in the 0-channel data shift register shift_data0. The current data containing the original data in the 1-channel data register data1_d1 is cached in the 1-channel data shift register shift_data1. The current data containing the first data in the 0-channel data register data0_d1 is cached in the shift buffer register shift_data_tmp.

[0097] Since the process of inserting data into channel 1 is similar to that of inserting data into channel 0, it will not be described in detail here.

[0098] To verify the timing accuracy of the data deletion and data insertion methods provided in this invention, a verification environment was built using SystemVerilog, and simulations were performed using Vivado in conjunction with Modelsim. To confirm...

[0099] Simulation 1: Setting up a random deletion stimulus. Set up continuous data input and enable signal, randomly generate a delete flag while keeping the insertion flag always at 0. The actual simulation waveform is as follows: Figure 9As shown, the dual-channel data deletion and insertion circuit for digital integrated circuits provided by this invention can perform continuous data deletion operations.

[0100] Simulation 2: Setting up random deletion and insertion stimuli. It should be noted that insertion and deletion operations cannot be performed simultaneously within the same clock cycle, and the insertion operation can only be performed when there is no shift transfer. If the current mode is shift transfer mode, the insertion signal will be ignored.

[0101] like Figure 10 As shown, to illustrate that insertion can only be performed in the no-shift transmission mode, the internal control signal insert_d1 for insertion is invoked. It can be seen that only two insertions were successful (insertion before 7 and insertion before 29). Combined with the simulation waveforms, it can be concluded that this circuit can perform insertion and deletion operations on dual-channel data.

[0102] The designed circuit was synthesized using Design Compiler, employing a 28nm process library. The final synthesized area was 1615µm. 2 The frequency is 1.2 GHz. The frequency can be further increased by using additional registers to buffer the data to be shifted during the insertion operation. Therefore, the above circuit is feasible and can be used in high-frequency circuit design.

[0103] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0104] This invention provides a dual-channel data deletion and insertion circuit, a data deletion method, and a data insertion method. The circuit uses a shift state switching mechanism to perform data operations based on the behavior after deleting or inserting individual data. Compared to existing technologies that utilize storage in dual channels for data deletion and insertion, this invention achieves data operations by adding only two levels of registers and a small amount of control logic, significantly reducing resource consumption. Furthermore, the combinational logic chain is short during circuit implementation, and the corresponding operations do not burden high-frequency timing.

[0105] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0106] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0107] Although this application has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in carrying out the claimed application by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0108] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A dual channel data delete and insert circuit, characterized by, include: Input terminals, enable signal register ena_d1, selector, first register, shift state register shift_state, combinational logic block, second register, shift buffer register shift_data_tmp, and output terminals; The input terminals include an enable signal input terminal ena_in and a dual-channel data input terminal. The enable signal input terminal ena_in is connected to the combinational logic block via an enable signal register ena_d1. The dual-channel data input terminal is connected to the combinational logic block via the selector and the first register. The output terminal of the shift state register shift_state is connected to the combinational logic block. The input terminal of the shift buffer register shift_data_tmp is connected to the output terminal of the combinational logic block, and the output terminal is connected to the input terminal of the combinational logic block. The output terminal of the combinational logic block is connected to the output terminal via a second register. The circuit is configured as follows: The data to be deleted is determined, and the valid data is transferred to the channel 0 data register data0_d1. The data to be deleted is input from either the channel 0 data input terminal data0_in or the channel 1 data input terminal data1_in, and the valid data is the data corresponding to the data to be deleted in another channel at the same time. Based on the transition state of the shift state register shift_state, the current data in the channel 0 data register data0_d1 is processed, and the current data in the channel 0 data register data0_d1 includes the valid data. When the next clock arrives, the outputs of the channel 0 data register data0_d1 and the channel 1 data register data1_d1 are obtained. or: Obtain the data to be inserted and determine the data insertion position in channel 0 or channel 1; determine the first data based on the data insertion position, the first data being the data corresponding to the original data at the data insertion position in another channel at the same time; process the first data and the original data based on the data insertion position, and buffer the data to be inserted into the channel 0 data shift register shift_data0; when the next clock arrives, obtain the outputs of the channel 0 data register data0_d1 and the channel 1 data register data1_d1.

2. The dual-channel data deletion and insertion circuit according to claim 1, characterized in that, The dual-channel data input terminal includes: a 0-channel data input terminal data0_in and a 1-channel data input terminal data1_in; the first register includes: a 0-channel data register data0_d1 and a 1-channel data register data1_d1. The 0-channel data input terminal data0_in is connected to the input terminal of the selector, the 1-channel data input terminal data1_in is connected to the input terminal of the selector and the 1-channel data register data1_d1, and the output terminal of the selector is connected to the 0-channel data register data0_d1.

3. The dual-channel data deletion and insertion circuit according to claim 2, characterized in that, The second register includes: an enable shift register shift_ena, a 0-channel data shift register shift_data0, and a 1-channel data shift register shift_data1; the output includes: an enable signal output ena_out, a 0-channel data output data0_out, and a 1-channel data output data1_out. The outputs of the combinational logic block are connected to the enable signal outputs ena_out, data output data0_out, and data output data1_out via the enable shift register shift_ena, the 0-channel data shift register shift_data0, and the 1-channel data shift register shift_data1, respectively.

4. A data deletion method, characterized in that, The dual-channel data deletion and insertion circuit described in any one of claims 1 to 3 includes: The data to be deleted is determined, and the valid data is transmitted to the 0 channel data register data0_d1; wherein, the data to be deleted is input from the 0 channel data input terminal data0_in or the 1 channel data input terminal data1_in, and the valid data is the data corresponding to the data to be deleted in another channel at the same time; Based on the transition state of the shift state register shift_state, process the current data in the 0 channel data register data0_d1, where the current data in the 0 channel data register data0_d1 contains the valid data; When the next clock arrives, acquire the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1.

5. The data deletion method according to claim 4, characterized in that, Before processing the current data in the 0-channel data register data0_d1 based on the transition state of the shift state register shift_state, the method further includes: The transition state of the shift state register shift_state is detected; the transition state of the shift state register shift_state includes a transition from 0 to 1 or a transition from 1 to 0.

6. The data deletion method according to claim 5, characterized in that, When the shift state register shift_state transitions from 0 to 1, the steps for processing the current data in the 0 channel data register data0_d1 according to the transition state of the shift state register shift_state include: The current data in the 0 channel data register data0_d1 is buffered into the shift buffer register shift data_tmp, and the shift enable is pulled low; In the shift state, the current data in the shift buffer register shift data_tmp is cached to the 0 channel data shift register shift_data0, the current data in the 0 channel data register data0_d1 is cached to the 1 channel data shift register shift_data1, and the current data in the 1 channel data register data1_d1 is cached to the shift buffer register shift data_tmp; When the next clock arrives, the steps of obtaining the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1 include: When the next clock arrives, both the data register data0_d1 for channel 0 and the data register data1_d1 for channel 1 maintain the output of the current clock.

7. The data deletion method according to claim 5, characterized in that, When the shift state register shift_state transitions from 1 to 0, the steps for processing the current data in the 0 channel data register data0_d1 according to the transition state of the shift state register shift_state include: The current data containing the valid data in the 0 channel data register data0_d1 is cached into the 1 channel data shift register shift_data1, and the shift enable is kept active; When the next clock arrives, the steps of obtaining the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1 include: When the next clock arrives, output the current data in the 0-channel data shift register shift_data0 and the current data in the 1-channel data shift register shift_data1.

8. A data insertion method, characterized in that, The dual-channel data deletion and insertion circuit described in any one of claims 1 to 3 includes: Obtain the data to be inserted and determine the data insertion position in channel 0 or channel 1; The first data is determined based on the data insertion position, and the first data is: the data in another channel corresponding to the original data at the data insertion position at the same time; The first data and the original data are processed according to the data insertion position, and the data to be inserted is cached in the 0-channel data shift register shift_data0; When the next clock arrives, acquire the outputs of the 0-channel data register data0_d1 and the 1-channel data register data1_d1.

9. The data insertion method according to claim 8, characterized in that, When the data insertion position is channel 0, the steps of processing the first data and the original data according to the data insertion position, and buffering the data to be inserted into the channel 0 data shift register shift_data0, include: The original data and the first data are cached in the 0-channel data register data0_d1 and the 1-channel data register data1_d1, respectively. The data to be inserted is cached in the 0-channel data shift register shift_data0. The current data containing the original data in the 0-channel data register data0_d1 is cached in the 1-channel data shift register shift_data1. The current data containing the first data in the 1-channel data register data1_d1 is cached in the shift cache register shiftdata_tmp.

10. The data insertion method according to claim 8, characterized in that, When the data insertion position is channel 1, the steps of processing the first data and the original data according to the data insertion position, and buffering the data to be inserted into the channel 0 data shift register shift_data0, include: The original data and the first data are cached in channel 1 data register data1_d1 and channel 0 data register data0_d1, respectively. The data to be inserted is cached in the 0-channel data shift register shift_data0, the current data containing the original data in the 1-channel data register data1_d1 is cached in the 1-channel data shift register shift_data1, and the current data containing the first data in the 0-channel data register data0_d1 is cached in the shift cache register shiftdata_tmp.

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