A multi-rate 1553b interface circuit

Abstract

The application relates to the field of data buses, in particular to a multi-rate 1553B interface circuit. The multi-rate 1553B interface circuit comprises an interface chip D1, an inverter D2, an inverter D3, an AND gate D4 and an AND gate D5; a 1M / 4M port of the interface chip D1 is connected with a capacitor C1, a capacitor C2 and an isolation transformer T1; an output end of the inverter D2 is connected with a first input end of the AND gate D4, and an output end of the inverter D3 is connected with a first input end of the AND gate D5; an output end of the AND gate D4 is connected with a receiving enable pin of the interface chip D1, and an output end of the AND gate D5 is connected with a transmitting enable pin of the interface chip D1. The multi-rate 1553B interface circuit disclosed by the application can adapt to 1Mbps, 4Mbps and 10Mbps application rates, directly replaces an existing 1553B interface circuit, reduces the development difficulty of the 1553B interface, improves the integration of the interface circuit, saves the development cost of the 1553B interface, and realizes the standard modularization of the 1553B interface circuit.

Description

Technical Field

[0001] This invention relates to the field of data buses, and more specifically to a multi-rate 1553B interface circuit. Background Technology

[0002] The 1553B bus was initially used in aviation buses. The MILSTD-155 standard was first proposed in 1973. After several revisions and improvements, the standard was named "Digital Time Division Command / Response Multiplexed Data Bus". Due to its characteristics such as good real-time performance, strong anti-interference, high reliability, and bidirectional transmission, it is now widely used in electronic systems in many fields such as aircraft, ships, automobiles, missiles, satellites, and even the International Space Station.

[0003] my country adopted the MIL-STD-1553B standard and developed its corresponding standard, GJB289-87, which was proposed in 1987 and revised to GJB289A-97 in 1997. Compared to other high-speed serial buses, the 1553B bus remains the most widely used interconnect bus in the aircraft field due to its significantly high reliability and fault tolerance mechanisms. This is because flight equipment may encounter a series of special or harsh environments during operation, such as severe vibration, high-altitude electromagnetic interference, large-scale temperature changes, and lightning strikes, and the 1553B bus took these potential problems into account during its initial design. With the increasing digitization of equipment such as missiles, the requirements for the speed and accuracy of their electronic systems are growing, and the demand for ground testing technology for missile-borne electronic systems is also increasing. Testing generates a large amount of data; the standard code rate of the 1553B bus protocol is 1Mbps, but 1Mbps is gradually becoming insufficient to meet the increasingly demanding performance requirements of weaponry.

[0004] The high-speed 1553B standard increased its communication rate to 4 Mbps. Subsequently, SAE, in accordance with the requirements of the U.S. Air Force, customized the AS5652 communication protocol standard, namely the EBR-1553B bus protocol, for small suspended interface devices, increasing the bus rate to 10 Mbps. The AS5652 standard is based on the MIL-STD-1553B standard, the difference being that EBR-1553 no longer uses the traditional transformer coupling method in terms of physical medium, but instead uses an RS485 bus as the transmission medium. RS485 operates in half-duplex mode, supports multi-point data communication, and has a maximum transmission rate of up to 20 Mb / s. The RS485 / 422 bus generally supports a maximum of 32 nodes. The RS485 bus is a relatively mature bus method used in industry, and its signal transmission, relay, lightning protection, reliability, and cost are all superior to the existing 1553B bus.

[0005] However, there are significant differences in the hardware of the interface circuits between MIL-1553B and EBR-1553B. The MIL-1553B interface uses a dedicated 1553B transceiver and a dedicated coupling transformer. The interface circuit is as follows: Figure 1 As shown; the EBR-1553B interface circuit uses an RS485 transceiver interface circuit, such as... Figure 2 As shown; the differences between the MIL-1553B interface circuit and the EBR-1553B interface circuit are shown in the figure. Figure 3 .

[0006] A comparison reveals that the MIL-1553B uses a transceiver and coupling transformer for its interface, while the 4Mbps interface uses a high-speed transceiver. The EBR-1553B, on the other hand, uses an RS485 transceiver. Regarding interface signals, the MIL-1553B uses a differential interface, while the EBR-1553B uses a single-ended interface. Furthermore, the transmit disable and receive enable signals of the MIL-1553B and EBR-1553B have opposite polarities. These two interfaces are incompatible, increasing the cost of widespread adoption. Summary of the Invention

[0007] This invention provides a multi-rate 1553B interface circuit, the purpose of which is to realize an interface circuit that can be compatible with two interface methods, so as to reduce costs.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] This invention provides a multi-rate 1553B interface circuit, including an interface chip D1, an inverter D2, an inverter D3, an AND gate D4, and an AND gate D5; the 1M / 4M port of the interface chip D1 is connected to capacitors C1 and C2 and an isolation transformer T1; the output of the inverter D2 is connected to the first input of the AND gate D4, and the output of the inverter D3 is connected to the first input of the AND gate D5; the output of the AND gate D4 is connected to the receive enable pin of the interface chip D1, and the output of the AND gate D5 is connected to the transmit enable pin of the interface chip D1.

[0010] MIL-1553B Operating Mode: The interface circuit is connected to the MIL-1553B controller; the BUSINN pin of the MIL-1553B controller is grounded, the BUSINP pin is connected to the data receive pin of the interface chip D1, the BUSOUTP pin is connected to the data transmit pin of the interface chip D1, the BUSOUTP pin is left floating, the BUSINEN pin is connected to the input of the inverter D2, and the BUSOUTIN pin is connected to the input of the inverter D3; the second inputs of AND gates D4 and D5 are both connected to a high level; the 10M port of the interface chip D1 is not connected to the 1553B bus, and the 1M / 4M port is connected to the external 1553B bus through the positive and negative terminals of the 1553B;

[0011] EBR-1553B Operating Mode: The interface circuit is connected to the EBR-1553B controller; the BUSIN pin of the EBR-1553B controller is connected to the data receive pin of the interface chip D1, the BUSOUT pin is connected to the data transmit pin of the interface chip D1, the BUSINENn pin is connected to the second input terminal of the AND gate D4, and the BUSOUTEN pin is connected to the second input terminal of the AND gate D5; the input terminals of inverters D2 and D3 are both connected to a low level; the 10M port of the interface chip D1 is connected to the external EBR-1553B bus through the positive and negative terminals of the 1553B, the 1M / 4M port is not connected to the 1553B bus, and capacitors C1 and C2 are both floating.

[0012] Furthermore, the interface chip D1 adopts the RS485 interface chip MAX3485ESA.

[0013] Furthermore, both inverters D2 and D3 are SN74LVC1G04DPWR.

[0014] Furthermore, both AND gates D4 and D5 are SN74LVC1G08DPWR.

[0015] Furthermore, the isolation transformer T1 is a DM2755.

[0016] Furthermore, both capacitors C1 and C2 are DC blocking capacitors and are externally mounted.

[0017] The beneficial effects achieved by this invention are as follows:

[0018] The multi-rate 1553B interface circuit disclosed in this invention can adapt to various application rates of 1Mbps, 4Mbps, and 10Mbps, directly replacing the existing 1553B interface circuit, reducing the development difficulty of the 1553B interface, improving the integration of the interface circuit, saving the development cost of the 1553B interface, and realizing the standard modularization of the 1553B interface circuit. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a traditional MIL-1553B interface circuit.

[0021] Figure 2 This is a schematic diagram of the traditional EBR-1553B interface circuit.

[0022] Figure 3 This is a comparison diagram showing the differences between the traditional MIL-1553B interface circuit and the traditional EBR-1553B interface circuit.

[0023] Figure 4 This is a schematic diagram of the overall architecture of the present invention.

[0024] Figure 5 This is the circuit connection diagram of the present invention.

[0025] Figure 6 This is a circuit connection diagram of the present invention when it is operating in 1M / 4MMIL-1553B mode.

[0026] Figure 7 This is a schematic diagram of the circuit connection when the present invention is operating in 10MEBR-1553B mode.

[0027] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0030] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, if the word "and / or" appears throughout the text, it means including three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0031] This invention provides a multi-rate 1553B interface circuit. Since the primary and backup channels have the same interface form, a single channel is used as an example here. This invention uses an RS485 interface chip, a DC blocking capacitor, an isolation transformer, an inverter, and an AND gate to implement a multi-rate, transformer-coupled, and direct-coupled compatible 1553B interface circuit.

[0032] like Figure 4 , 5 As shown, the interface circuit includes an interface chip D1, an inverter D2, an inverter D3, an AND gate D4, and an AND gate D5. The 1M / 4M port of the interface chip D1 is connected to capacitors C1 and C2 and an isolation transformer T1. The output of the inverter D2 is connected to the first input of the AND gate D4, and the output of the inverter D3 is connected to the first input of the AND gate D5. The output of the AND gate D4 is connected to the receive enable pin of the interface chip D1, and the output of the AND gate D5 is connected to the transmit enable pin of the interface chip D1.

[0033] MIL-1553B operating mode, such as Figure 6As shown: The interface circuit is connected to the MIL-1553B controller; the BUSINN pin of the MIL-1553B controller is grounded, the BUSINP pin is connected to the data receive pin of the interface chip D1, the BUSOUTP pin is connected to the data transmit pin of the interface chip D1, the BUSOUTP pin is left floating, the BUSINEN pin is connected to the input of the inverter D2, and the BUSOUTIN pin is connected to the input of the inverter D3; the second inputs of AND gates D4 and D5 are both connected to a high level; the 10M port of the interface chip D1 is not connected to the 1553B bus, and the 1M / 4M port is connected to the external 1553B bus through the positive and negative terminals of the 1553B;

[0034] EBR-1553B operating modes, such as Figure 7 As shown: The interface circuit is connected to the EBR-1553B controller; the BUSIN pin of the EBR-1553B controller is connected to the data receive pin of the interface chip D1, the BUSOUT pin is connected to the data transmit pin of the interface chip D1, the BUSINENn pin is connected to the second input terminal of the AND gate D4, and the BUSOUTEN pin is connected to the second input terminal of the AND gate D5; the input terminals of inverters D2 and D3 are both connected to a low level; the 10M port of the interface chip D1 is connected to the external EBR-1553B bus through the positive and negative terminals of the 1553B, the 1M / 4M port is not connected to the 1553B bus, and the capacitors C1 and C2 are both floating.

[0035] The interface circuit is packaged into a standardized module, compatible with two modes; in actual use, only slight adjustments to the connection method are needed to achieve compatibility with different 1553B buses.

[0036] The interface circuit uses an RS485 interface chip MAX3485ESA for interface chip D1, SN74LVC1G04DPWR for inverters D2 and D3, SN74LVC1G08DPWR for AND gates D4 and D5, and a DM2755 isolation transformer T1 (turns ratio 1:2.7, 1:3.25). The circuit is powered by 3.3V. Capacitors C1 and C2 are both DC blocking capacitors and are externally mounted. In MIL-1553B operating mode, a 0.1uF 100V capacitor needs to be soldered; in 10MEBR-1553B operating mode, C1 and C2 are left floating.

[0037] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A multi-rate 1553B interface circuit, characterized in that: The interface includes an interface chip D1, an inverter D2, an inverter D3, an AND gate D4, and an AND gate D5. The 1M / 4M port of the interface chip D1 is connected to capacitors C1 and C2 and an isolation transformer T1. The output of the inverter D2 is connected to the first input of the AND gate D4, and the output of the inverter D3 is connected to the first input of the AND gate D5. The output of the AND gate D4 is connected to the receive enable pin of the interface chip D1, and the output of the AND gate D5 is connected to the transmit enable pin of the interface chip D1. MIL-1553B Operating Mode: The interface circuit is connected to the MIL-1553B controller; the BUSINN pin of the MIL-1553B controller is grounded, the BUSINP pin is connected to the data receive pin of the interface chip D1, the BUSOUTP pin is connected to the data transmit pin of the interface chip D1, the BUSOUTP pin is left floating, the BUSINEN pin is connected to the input of the inverter D2, and the BUSOUTIN pin is connected to the input of the inverter D3; the second inputs of AND gates D4 and D5 are both connected to a high level; the 10M port of the interface chip D1 is not connected to the 1553B bus, and the 1M / 4M port is connected to the external 1553B bus through the positive and negative terminals of the 1553B; EBR-1553B Operating Mode: The interface circuit is connected to the EBR-1553B controller; the BUSIN pin of the EBR-1553B controller is connected to the data receive pin of the interface chip D1, the BUSOUT pin is connected to the data transmit pin of the interface chip D1, the BUSINENn pin is connected to the second input terminal of the AND gate D4, and the BUSOUTEN pin is connected to the second input terminal of the AND gate D5; the input terminals of inverters D2 and D3 are both connected to a low level; the 10M port of the interface chip D1 is connected to the external EBR-1553B bus through the positive and negative terminals of the 1553B, the 1M / 4M port is not connected to the 1553B bus, and capacitors C1 and C2 are both floating.

2. The multi-rate 1553B interface circuit according to claim 1, characterized in that: The interface chip D1 uses the RS485 interface chip MAX3485ESA.

3. The multi-rate 1553B interface circuit according to claim 1, characterized in that: Both inverters D2 and D3 are SN74LVC1G04DPWR.

4. The multi-rate 1553B interface circuit according to claim 1, characterized in that: Both AND gates D4 and D5 are SN74LVC1G08DPWR.

5. A multi-rate 1553B interface circuit according to claim 1, characterized in that: The isolation transformer T1 is a DM2755.

6. The multi-rate 1553B interface circuit according to claim 1, characterized in that: Both capacitors C1 and C2 are DC blocking capacitors and are externally mounted.

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