Tamper-resistant circuit for debug port of integrated circuit chip

Abstract

This invention provides a tamper-proof circuit for a debug port of an integrated circuit chip, comprising: a debug port including at least one debug signal terminal; an integrated circuit chip including at least one debug signal pin and a first control pin, the debug signal pin being connected to the corresponding debug signal terminal; at least one tamper-proof unit, wherein a first resistor is connected between a power supply voltage and a control terminal of a first switching transistor; one end of a second resistor is connected to the power supply voltage, and the other end is connected to the debug signal pin; a third resistor is connected between the control terminal of the first switching transistor and the first control pin; a first connection terminal of the first switching transistor is connected to the debug signal pin, and the other end is grounded through a fourth resistor; a first connection terminal of a second switching transistor is connected to the control terminal of the first switching transistor, and the control terminal is connected to a second connection terminal of the first switching transistor, the second connection terminal being grounded. Compared with the prior art, this invention has the advantages of high security, flexible control, and low cost.

Description

[Technical Field]

[0001] This invention relates to the field of circuit design technology, and in particular to a circuit for preventing tampering with the debug port of an integrated circuit chip. [Background Technology]

[0002] ASICs (Application-Specific Integrated Circuits) are widely used in the automotive industry. Typically, a debug pin is reserved for software programming and debugging of the chip. During the early stages of development, software engineers can easily update the software version and improve chip functionality using the debug pin. However, when the product is officially released, the debug port needs to be disabled to prevent unauthorized access and modification of the chip's internal code, which could affect product security and functionality.

[0003] Currently, to address this issue, applications typically disable the debug port permanently in the final step of the production process by modifying the OTP fuse, making it difficult to troubleshoot and locate the problem during after-sales service and maintenance. Another approach is to wait a period after the chip is powered on before disabling the debug port. This allows for software modifications and restarting the debug port during the waiting period when debugging is needed later. However, this method is extremely easy to crack and provides opportunities for external intrusion. The attacker can also use this time difference to tamper with the internal software, thus failing to achieve complete protection.

[0004] Therefore, it is necessary to propose a new technical solution to address the above problems. [Summary of the Invention]

[0005] One of the objectives of this invention is to provide a tamper-proof circuit for the debugging port of an integrated circuit chip, which features high security, flexible control, and low cost.

[0006] According to one aspect of the present invention, a tamper-proof circuit for a debug port of an integrated circuit chip is provided, comprising: a debug port including at least one debug signal terminal; an integrated circuit chip including at least one debug signal pin and at least one first control pin, each of the debug signal pins being connected to a corresponding debug signal terminal; and at least one tamper-proof unit, each of the tamper-proof units being connected to a corresponding debug signal pin and a corresponding first control pin, wherein each tamper-proof unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first switching transistor, and a second switching transistor, wherein one end of the first resistor is connected to a power supply voltage VC. The first resistor is connected to the control terminal of the first switch, and the second resistor is connected to the power supply voltage VCC. The third resistor is connected to the control terminal of the first switch, and the third resistor is connected to the first control pin of the anti-tampering unit. The first connection terminal of the first switch is connected to the debugging signal pin of the anti-tampering unit, and the other end is grounded through the fourth resistor. The first connection terminal of the second switch is connected to the control terminal of the first switch, and the control terminal is connected to the second connection terminal of the first switch, and the second connection terminal is grounded.

[0007] Compared with existing technologies, this invention uses a combination of hardware and software to disable the debug port, preventing external parties from tampering with the software code through the debug port. Furthermore, the debug port function can be easily reopened by modifying hardware components during subsequent maintenance and debugging. This circuit features high security, flexible control, and low cost. [Attached Image Description]

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0009] Figure 1 This is a schematic diagram of the functional modules of a debug port anti-tampering circuit for an integrated circuit chip in one embodiment of the present invention;

[0010] Figure 2 As shown in one embodiment of the present invention Figure 1 The circuit diagram of the first anti-tampering unit is shown below;

[0011] Figure 3 As shown in one embodiment of the present invention Figure 1The circuit diagram of the second anti-tampering unit is shown below;

[0012] Figure 4 This is a schematic diagram of the functional modules of a debug port anti-tampering circuit for an integrated circuit chip in another embodiment of the present invention;

[0013] Figure 5 As shown in one embodiment of the present invention Figure 4 The circuit diagram of the first anti-tampering unit is shown below;

[0014] Figure 6 As shown in one embodiment of the present invention Figure 4 The circuit diagram of the second anti-tampering unit is shown.

Detailed Implementation Methods

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms coupling, connection, linking, and interconnection used herein to indicate electrical connection mean direct or indirect connection. For example, A being connected to B includes both a direct electrical connection between A and B and a connection between A and B via electrical components or circuits. In this invention, "greater than" means greater than, and "less than or equal to" means less than or equal to.

[0017] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0018] Please refer to Figure 1 As shown, it is a functional module schematic diagram of a debug port anti-tampering circuit for an integrated circuit chip in one embodiment of the present invention. Figure 1The tamper protection circuit for the debug port of the integrated circuit chip shown includes a debug port 1, a first tamper protection unit 2, a second tamper protection unit 3, and an integrated circuit chip (ASIC) 4. The integrated circuit chip 4 can be debugged by connecting the debug port 1 through an external cable.

[0019] Debug port 1 includes two debug signal terminals: SDA (data debug signal) and SCK (clock debug signal). Integrated circuit chip 4 includes two debug signal pins: Debug_SDA (data debug signal) and Debug_SCK (clock debug signal). Integrated circuit chip 4 also includes two first control pins: GPIO1 (General-purpose input / output) and GPIO2. Specifically, SDA is connected to Debug_SDA; SCK is connected to Debug_SCK; the first anti-tampering unit 2 is connected to GPIO1 and Debug_SDA; and the second anti-tampering unit 3 is connected to GPIO2 and Debug_SCK.

[0020] Please refer to Figure 2 As shown, this is an embodiment of the present invention. Figure 1 The circuit diagram of the first anti-tampering unit is shown. Figure 2 The first anti-tampering unit shown includes a first resistor R1, a second resistor R2, a third resistor R5, a fourth resistor R7, a first switch Q1, and a second switch Q3. One end of the first resistor R1 is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switch Q1. One end of the second resistor R2 is connected to the power supply voltage VCC, and the other end is connected to the data debugging signal pin Debug_SDA. One end of the third resistor R5 is connected to the control terminal of the first switch Q1, and the other end is connected to the first control pin GPIO1. The first connection terminal of the first switch Q1 is connected to the data debugging signal pin Debug_SDA, and the other end is grounded via the fourth resistor R7. The first connection terminal of the second switch Q3 is connected to the control terminal of the first switch Q1, and its control terminal is connected to the second connection terminal of the first switch Q1, which is then grounded.

[0021] exist Figure 2In the specific embodiment shown, the first switching transistor Q1 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor Q1 are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor Q3 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor Q3 are the collector, emitter, and base of the NPN transistor, respectively.

[0022] Please refer to Figure 3 As shown, this is an embodiment of the present invention. Figure 1 The circuit diagram of the second anti-tampering unit is shown. Figure 2 The second anti-tampering unit shown includes a first resistor R3, a second resistor R4, a third resistor R6, a fourth resistor R8, a first switch Q2, and a second switch Q4. One end of the first resistor R3 is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switch Q2. One end of the second resistor R4 is connected to the power supply voltage VCC, and the other end is connected to the clock debugging signal pin Debug_SCK. One end of the third resistor R6 is connected to the control terminal of the first switch Q2, and the other end is connected to the first control pin GPIO2. The first connection terminal of the first switch Q2 is connected to the clock debugging signal pin Debug_SCK, and the other end is grounded through the fourth resistor R8. The first connection terminal of the second switch Q4 is connected to the control terminal of the first switch Q2, and its control terminal is connected to the second connection terminal of the first switch Q2, which is grounded.

[0023] exist Figure 3 In the specific embodiment shown, the first switching transistor Q2 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor Q2 are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor Q4 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor Q4 are the collector, emitter, and base of the NPN transistor, respectively.

[0024] In one specific embodiment, the power supply voltage VCC is the power supply for integrated circuit chip 4.

[0025] The following is based on Figure 2 and Figure 3 introduce Figure 1 The diagram illustrates the specific working principle of the anti-tampering circuit for the debug port of an integrated circuit chip.

[0026] When it is necessary to keep the debug port 1 open, such as during early-stage R&D debugging, the integrated circuit chip 4 can be left unconfigured with the first control pins GPIO1 and GPIO2, maintaining their original high-impedance state, or the first control pins GPIO1 and GPIO2 can be pulled high. In this case, due to the pull-up resistors R1 and R3, the bases of transistors Q1 and Q2 will be at a high level (equal to the power supply voltage VCC). The third resistors R5 and R6 act as current-limiting resistors to prevent excessive current from damaging the first control pins GPIO1 and GPIO2 of the integrated circuit chip 4. At this time, the emitters of transistors Q1 and Q2 are connected through the second resistors R2 and R3 respectively. 4. Connected to the power supply voltage VCC, since the bases and emitters of transistors Q1 and Q2 are both at high level, transistors Q1 and Q2 are both in the off state. Since transistors Q1 and Q2 are off, the bases of transistors Q3 and Q4 are at low level, so transistors Q3 and Q4 are also in the off state. When transistors Q1 and Q2 are off, the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK are in the pull-up state through pull-up resistors R2 and R4 respectively. Due to the communication protocol, the pull-up state does not affect the normal communication function. The integrated circuit chip 4 can be programmed and debugged by the outside world through debugging port 1. In other words, during R&D and debugging, the integrated circuit chip 4 is not configured with the first control pins GPIO1 and GPIO2. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level. The outside world can perform debugging work on the integrated circuit chip 4 through the debugging port 1.

[0027] When debug port 1 needs to be shut down (e.g., when the product is officially released), integrated circuit chip 4 can be configured to pull the first control pins GPIO1 and GPIO2 low (or configure the first control pins GPIO1 and GPIO2 to a low level). At this time, the bases of transistors Q1 and Q2 will be at a low level, while the emitters will be at a high level due to the action of the second resistors R2 and R4, thus turning on transistors Q1 and Q2. The data debug signal pin Debug_SDA and the clock debug signal pin Debug_SCK are connected to GND through the fourth resistors R7 and R8, respectively. Since the upper ends of the fourth resistors R7 and R8 are connected to the bases of transistors Q3 and Q4, respectively, it can be known from the condition that transistors Q3 and Q4 are conducting at this time. The base of Q1 and Q2 is about 0.7V higher than the collector, so transistors Q3 and Q4 are also in the conducting state at this time. Therefore, the collectors of transistors Q3 and Q4 further pull the bases of transistors Q1 and Q2 low, thus keeping them in the conducting state. Since the signal levels of the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK will always be pulled low to about 0.7V at this time, which does not meet the Debug communication protocol, the integrated circuit chip 4 will automatically configure the first control pins GPIO1 and GPIO2 to a low level every time it is powered on again, thereby realizing the anti-tampering function. The outside world cannot communicate normally with the integrated circuit chip 4 through the debugging port 1. In other words, when the product is officially released and debug port 1 needs to be closed, the integrated circuit chip 4 is configured with the first control pins GPIO1 and GPIO2 at a low level. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned on, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a low level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned on, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a low level. The outside world cannot perform debugging work on the integrated circuit chip 4 through debug port 1.

[0028] When debug port 1 is closed and needs to be re-enabled, for example, when a product malfunctions and debug port 1 needs to be re-enabled (or when a product malfunctions and needs maintenance and debugging), the third resistors R5 and R6 can be removed in hardware. At this time, the state is equivalent to not configuring the first control pins GPIO1 and GPIO2 at the beginning, keeping them in their original high impedance state. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level, so debug port 1 is opened. The outside world can re-debug the integrated circuit chip 4 through debug port 1 to troubleshoot the cause of the fault. In other words, when the product malfunctions and requires maintenance and debugging, the third resistors R5 and R6 are removed. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level, so the outside world can perform maintenance and debugging on the integrated circuit chip 4 through the debugging port 1.

[0029] Correspondingly, by restoring the original hardware, that is, by adding the third resistors R5 and R6 in the hardware, and configuring the first control pins GPIO1 and GPIO2 of the integrated circuit chip 4 to pull low (or configure the first control pins GPIO1 and GPIO2 to low level), the debug port 1 can be shut down again.

[0030] It should be noted that this invention is also applicable to debugging ports for other communication types.

[0031] Based on the above Figures 1-3As shown, the present invention provides a tamper-proof circuit for a debug port of an integrated circuit chip, comprising: a debug port including at least one debug signal terminal; an integrated circuit chip including at least one debug signal pin and at least one first control pin, each debug signal pin being connected to a corresponding debug signal terminal; at least one tamper-proof unit, each tamper-proof unit being connected to a corresponding debug signal pin and a corresponding first control pin, the tamper-proof unit including a first resistor, a second resistor, a third resistor, a fourth resistor, a first switch transistor, and a second switch transistor, wherein one end of the first resistor is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switch transistor; one end of the second resistor is connected to the power supply voltage VCC, and the other end is connected to the debug signal pin corresponding to the tamper-proof unit; one end of the third resistor is connected to the control terminal of the first switch transistor, and the other end is connected to the first control pin corresponding to the tamper-proof unit; a first connection terminal of the first switch transistor is connected to the debug signal pin corresponding to the tamper-proof unit, and its other end (i.e., the second connection terminal) is grounded through the fourth resistor; the first connection terminal of the second switch transistor is connected to the control terminal of the first switch transistor, its control terminal is connected to the second connection terminal of the first switch transistor, and its second connection terminal is grounded.

[0032] In one embodiment, the first switching transistor is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor are the collector, emitter, and base of the NPN transistor, respectively.

[0033] In one embodiment, when the debug port 1 needs to be kept open, the integrated circuit chip is not configured with a first control pin, and both the first and second switches in the anti-tampering unit are turned off; the debug signal pin connected to the anti-tampering unit is at a high level, allowing external debugging of the integrated circuit chip through the debug port; when the debug port 1 needs to be closed, the integrated circuit chip is configured with a low first control pin, and both the first and second switches in the anti-tampering unit are turned on; the debug signal pin connected to the anti-tampering unit is at a low level, preventing external debugging of the integrated circuit chip through the debug port; when the debug port 1 is closed and needs to be reactivated, the third resistor is removed, and both the first and second switches in the anti-tampering unit are turned off; the debug signal pin connected to the anti-tampering unit is at a high level, allowing external maintenance and debugging of the integrated circuit chip through the debug port.

[0034] exist Figures 1-3In the specific embodiment shown, there are two debug signal terminals: a data debug signal terminal SDA and a clock debug signal terminal SCK; there are two debug signal pins: a data debug signal pin Debug_SDA and a clock debug signal pin Debug_SCK; there are two first control pins: a first control pin GPIO1 and a first control pin GPIO2; there are two anti-tampering units: a first anti-tampering unit 2 and a second anti-tampering unit 3; the first anti-tampering unit 2 is connected to the first control pin GPIO1 and the data debug signal pin Debug_SDA; the second anti-tampering unit 3 is connected to the first control pin GPIO2 and the clock debug signal pin Debug_SCK.

[0035] Please refer to Figure 4 As shown, it is a functional module schematic diagram of a debug port anti-tampering circuit for an integrated circuit chip in another embodiment of the present invention. Figure 4 and Figure 1 The difference is that, Figure 4 The integrated circuit chip 4 shown also includes two second control pins, namely the second control pin GPIO3 and the second control pin GPIO4; the first anti-tampering unit 2 is also connected to the second control pin GPIO3, and the second anti-tampering unit 3 is also connected to the second control pin GPIO4.

[0036] Figure 4 The tamper protection circuit for the debug port of the integrated circuit chip shown includes a debug port 1, a first tamper protection unit 2, a second tamper protection unit 3, and an integrated circuit chip (ASIC) 4. The integrated circuit chip 4 can be debugged by connecting the debug port 1 through an external cable.

[0037] Debug port 1 includes two debug signal terminals: SDA (data debug signal) and SCK (clock debug signal). Integrated circuit chip 4 includes two debug signal pins: Debug_SDA (data debug signal) and Debug_SCK (clock debug signal). Integrated circuit chip 4 also includes two first control pins: GPIO1 (General-purpose input / output) and GPIO2. Integrated circuit chip 4 also includes two second control pins: GPIO3 and GPIO4. Specifically, the data debug signal terminal SDA is connected to the Debug_SDA pin; the clock debug signal terminal SCK is connected to the Debug_SCK pin; the first anti-tampering unit 2 is connected to the GPIO1, GPIO3, and Debug_SDA pins; and the second anti-tampering unit 3 is connected to the GPIO2, GPIO4, and Debug_SCK pins.

[0038] Please refer to Figure 5 As shown, this is an embodiment of the present invention. Figure 4 The circuit diagram of the first anti-tampering unit is shown. Figure 5 and Figure 2 The difference is that, Figure 5 The first anti-tampering unit shown also includes a fifth resistor R9 and a sixth resistor R11. The fifth resistor R9 and the sixth resistor R11 are connected in series between the power supply voltage VCC and the ground terminal. The connection node between the fifth resistor R9 and the sixth resistor R11 is connected to the second control pin GPIO3.

[0039] Figure 4The first anti-tampering unit shown includes a first resistor R1, a second resistor R2, a third resistor R5, a fourth resistor R7, a fifth resistor R9, a sixth resistor R11, a first switch Q1, and a second switch Q3. One end of the first resistor R1 is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switch Q1. One end of the second resistor R2 is connected to the power supply voltage VCC, and the other end is connected to the data debugging signal pin Debug_SDA. One end of the third resistor R5 is connected to the control terminal of the first switch Q1, and the other end is connected to the first control... Pin GPIO1 is connected; the first connection terminal of the first switch Q1 is connected to the data debugging signal pin Debug_SDA, and its other end (i.e., the second connection terminal) is grounded through the fourth resistor R7; the first connection terminal of the second switch Q3 is connected to the control terminal of the first switch Q1, and its control terminal is connected to the second connection terminal of the first switch Q1, and its second connection terminal is grounded; the fifth resistor R9 and the sixth resistor R11 are connected in series between the power supply voltage VCC and the ground terminal, and the connection node between the fifth resistor R9 and the sixth resistor R11 is connected to the second control pin GPIO3.

[0040] exist Figure 5 In the specific embodiment shown, the first switching transistor Q1 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor Q1 are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor Q3 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor Q3 are the collector, emitter, and base of the NPN transistor, respectively.

[0041] Please refer to Figure 6 As shown, this is an embodiment of the present invention. Figure 4 The circuit diagram of the second anti-tampering unit is shown. Figure 6 and Figure 3 The difference is that, Figure 6 The second anti-tampering unit shown also includes a fifth resistor R10 and a sixth resistor R12. The fifth resistor R10 and the sixth resistor R12 are connected in series between the power supply voltage VCC and the ground terminal. The connection node between the fifth resistor R10 and the sixth resistor R12 is connected to the second control pin GPIO4.

[0042] Figure 6The second anti-tampering unit shown includes a first resistor R3, a second resistor R4, a third resistor R6, a fourth resistor R8, a fifth resistor R10, a sixth resistor R12, a first switch Q2, and a second switch Q4. One end of the first resistor R3 is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switch Q2. One end of the second resistor R4 is connected to the power supply voltage VCC, and the other end is connected to the clock debugging signal pin Debug_SCK. One end of the third resistor R6 is connected to the control terminal of the first switch Q2, and the other end is connected to the first control pin... GPIO2 is connected; the first connection terminal of the first switch Q2 is connected to the clock debugging signal pin Debug_SCK, and its other end (i.e., the second connection terminal) is grounded through the fourth resistor R8; the first connection terminal of the second switch Q4 is connected to the control terminal of the first switch Q2, and its control terminal is connected to the second connection terminal of the first switch Q2, and its second connection terminal is grounded; the fifth resistor R10 and the sixth resistor R12 are connected in series between the power supply voltage VCC and the ground terminal, and the connection node between the fifth resistor R10 and the sixth resistor R12 is connected to the second control pin GPIO4.

[0043] exist Figure 6 In the specific embodiment shown, the first switching transistor Q2 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor Q2 are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor Q4 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor Q4 are the collector, emitter, and base of the NPN transistor, respectively.

[0044] In one specific embodiment, the power supply voltage VCC is the power supply for integrated circuit chip 4.

[0045] The following is based on Figure 5 and Figure 6 introduce Figure 4 The diagram illustrates the specific working principle of the anti-tampering circuit for the debug port of an integrated circuit chip.

[0046] When it is necessary to keep the debug port 1 open, such as during early-stage R&D debugging, the integrated circuit chip 4 can be left unconfigured with the first control pins GPIO1 and GPIO2, maintaining their original high-impedance state, or the first control pins GPIO1 and GPIO2 can be pulled high. In this case, due to the pull-up resistors R1 and R3, the bases of transistors Q1 and Q2 will be at a high level (equal to the power supply voltage VCC). The third resistors R5 and R6 act as current-limiting resistors to prevent excessive current from damaging the first control pins GPIO1 and GPIO2 of the integrated circuit chip 4. At this time, the emitters of transistors Q1 and Q2 are connected through the second resistors R2 and R3 respectively. 4. Connected to the power supply voltage VCC, transistors Q1 and Q2 are both in the off state because their bases and emitters are both high. Since transistors Q1 and Q2 are off, the bases of transistors Q3 and Q4 are low, so they are also in the off state. When transistors Q1 and Q2 are off, the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK are pulled up by resistors R2 and R4 respectively. Due to the communication protocol, this pull-up state does not affect normal communication. External circuitry can program and debug integrated circuit chip 4 through debugging port 1. Furthermore, integrated circuit chip 4 does not need to determine whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within the predetermined voltage range. In other words, during R&D and debugging, integrated circuit chip 4 is not configured with the first control pins GPIO1 and GPIO2. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level; integrated circuit chip 4 does not need to determine whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within the predetermined voltage range, and the outside world can perform debugging work on integrated circuit chip 4 through debugging port 1.

[0047] When debug port 1 needs to be closed (e.g., when the product is officially released), integrated circuit chip 4 can be configured to pull the first control pins GPIO1 and GPIO2 low (or configure the first control pins GPIO1 and GPIO2 to a low level). At this time, the bases of transistors Q1 and Q2 will be at a low level, while the emitters will be at a high level due to the action of the second resistors R2 and R4, thus turning on transistors Q1 and Q2. The data debug signal pin Debug_SDA and the clock debug signal pin Debug_SCK are connected to GND through the fourth resistors R7 and R8, respectively. The upper ends of resistors R7 and R8 are connected to the bases of transistors Q3 and Q4. Since the conditions for transistor conduction are known, the bases of transistors Q1 and Q2 are approximately 0.7V higher than their collectors at this time. Therefore, transistors Q3 and Q4 are also in a conducting state. Furthermore, the collectors of transistors Q3 and Q4 pull the bases of transistors Q1 and Q2 low, thus maintaining their conducting state. However, since the signal levels of the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK will always be pulled low to approximately 0.7V, this does not meet the Debug communication protocol. In addition, integrated circuit chip 4 determines whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within a predetermined voltage range. This can be achieved by adjusting the values ​​of the fifth resistor R9 and / or the sixth resistor R11 to prevent the voltage value of the second control pin GPIO3 from falling outside the predetermined voltage range; similarly, it can be achieved by adjusting the values ​​of the fifth resistor R10 and / or the sixth resistor R12 to prevent the voltage value of the second control pin GPIO4 from falling outside the predetermined voltage range. If either the voltage value of the second control pins GPIO3 or GPIO4 is outside the set predetermined voltage range, debug port 1 remains closed. Each time the circuit is powered on again, integrated circuit chip 4 automatically configures the first control pins GPIO1 and GPIO2 to a low-level state. The circuit remains in a low-level locked state, and even if the levels of the first control pins GPIO1 and GPIO2 are subsequently pulled high, the states of the first anti-tampering unit 2 and the second anti-tampering unit 3 will not change. Even if the first anti-tampering unit 2 and the second anti-tampering unit 3 are compromised and removed, debug port 1 cannot be opened because the voltage values ​​of the second control pins GPIO3 and / or GPIO4 are outside the set predetermined voltage range. By combining the two, the anti-tampering function is achieved, and the outside world cannot communicate normally with the integrated circuit chip 4 through debugging port 1.In other words, when the product is officially released and debug port 1 needs to be closed, the integrated circuit chip 4 configures the first control pins GPIO1 and GPIO2 to a low level. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned on, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a low level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned on, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a low level; the integrated circuit chip 4 determines whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within the predetermined voltage range; by adjusting the resistance values ​​of the fifth resistor R9 and / or the sixth resistor R11 in the first anti-tampering unit 2, and the resistance values ​​of the fifth resistor R10 and / or the sixth resistor R12 in the second anti-tampering unit 3, the voltage value of at least one of the second control pins GPIO3 and GPIO4 is not within the predetermined voltage range. In this way, the outside world cannot perform debugging work on the integrated circuit chip 4 through debug port 1.

[0048] When debug port 1 is closed and needs to be re-enabled, for example, when a product malfunctions and debug port 1 needs to be re-enabled (or when a product malfunctions and needs maintenance and debugging), the third resistors R5 and R6 can be removed in hardware. At this time, the state is equivalent to not configuring the first control pins GPIO1 and GPIO2 at the beginning, keeping them in their original high impedance state. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level, thereby canceling the pull-down state of debug port 1. In addition, integrated circuit chip 4 determines whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within a predetermined voltage range. The voltage value of the second control pin GPIO3 can be made within the predetermined voltage range by adjusting the resistance values ​​of the fifth resistor R9 and / or the sixth resistor R11. The voltage value of the second control pin GPIO4 can be made within the predetermined voltage range by adjusting the resistance values ​​of the fifth resistor R10 and / or the sixth resistor R12. When the voltage values ​​of the second control pins GPIO3 and GPIO4 are both within the set predetermined voltage range, the debug port 1 is opened, and the outside world can re-debug the software of integrated circuit chip 4 through debug port 1 to troubleshoot the cause of the fault. In other words, when a product malfunctions and requires maintenance and debugging, the third resistors R5 and R6 are removed. At this time, the first switch Q1 and the second switch Q3 in the first anti-tampering unit 2 are both turned off, and the data debugging signal pin Debug_SDA connected to the first anti-tampering unit 2 is at a high level; the first switch Q2 and the second switch Q4 in the second anti-tampering unit 3 are both turned off, and the clock debugging signal pin Debug_SCK connected to the second anti-tampering unit 3 is at a high level; the integrated circuit chip 4 determines whether the voltage values ​​of the second control pins GPIO3 and GPIO4 are within the predetermined voltage range; by adjusting the resistance values ​​of the fifth resistor R9 and / or the sixth resistor R11 in the first anti-tampering unit 2, and the resistance values ​​of the fifth resistor R10 and / or the sixth resistor R12 in the second anti-tampering unit 3, the voltage values ​​of the second control pins GPIO3 and GPIO4 are made to be within the predetermined voltage range. In this way, the external system can perform debugging work on the integrated circuit chip 4 through the debugging port 1.

[0049] Correspondingly, by restoring the original hardware, that is, by adding the third resistor R5 / R6 in the hardware, and restoring the fifth resistor R9 / R10 and / or the sixth resistor R11 / R12, and configuring the first control pins GPIO1 and GPIO2 of the integrated circuit chip 4 to pull low (or configure the first control pins GPIO1 and GPIO2 to low level), the debug port 1 can be shut down again.

[0050] In a preferred embodiment, when the integrated circuit chip 4 can be debugged by the outside world through the debugging port 1, the resistance values ​​of the fifth resistor R9 and R11 are different; and / or the resistance values ​​of the sixth resistor R10 and R12 are different, thereby further increasing the difficulty of cracking.

[0051] It should be noted that this invention is also applicable to debugging ports for other communication types.

[0052] Based on the above Figures 4-6 As shown, the present invention provides a tamper-proof circuit for a debug port of an integrated circuit chip, comprising: a debug port including at least one debug signal terminal; an integrated circuit chip including at least one debug signal pin, at least one first control pin, and at least one second control pin, each debug signal pin being connected to a corresponding debug signal terminal; and at least one tamper-proof unit, each tamper-proof unit being connected to a corresponding debug signal pin, a corresponding first control pin, and a corresponding second control pin, the tamper-proof unit including a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first switching transistor, and a second switching transistor, wherein one end of the first resistor is connected to the power supply voltage VCC, and the other end is connected to the control pin of the first switching transistor. The first resistor is connected to the control terminal of the first switch, and the other end is connected to the first control pin of the anti-tampering unit. The first connection terminal of the first switch is connected to the debugging signal pin of the anti-tampering unit, and the other end (i.e., the second connection terminal) is grounded through the fourth resistor. The first connection terminal of the second switch is connected to the control terminal of the first switch, and its control terminal is connected to the second connection terminal of the first switch, and its second connection terminal is grounded. The fifth and sixth resistors are connected in series between the power supply voltage VCC and the ground terminal, and the connection node between the fifth and sixth resistors is connected to the second control pin GPIO of the anti-tampering unit.

[0053] In one embodiment, the first switching transistor is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor are the emitter, collector, and base of the PNP transistor, respectively; the second switching transistor is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor are the collector, emitter, and base of the NPN transistor, respectively.

[0054] In one embodiment, when the debug port 1 needs to be kept open, the integrated circuit chip does not have a first control pin configured. At this time, both the first and second switches in the anti-tampering unit are turned off, and the debug signal pin connected to the anti-tampering unit is at a high level. The integrated circuit chip does not need to determine whether the voltage value of the second control pin is within a predetermined voltage range, and external systems can debug the integrated circuit chip through the debug port. When the debug port 1 needs to be closed, the integrated circuit chip configures the first control pin to a low level. At this time, both the first and second switches in the anti-tampering unit are turned on; the debug signal pin connected to the anti-tampering unit is at a low level; the integrated circuit chip determines whether the voltage value of the second control pin is within a predetermined voltage range; and through adjustment... The fifth and / or sixth resistor values ​​in the anti-tamper unit are adjusted so that the voltage value of at least one second control pin is not within a predetermined voltage range, preventing external debugging of the integrated circuit chip through the debugging port. When debugging port 1 is closed and needs to be reactivated, the third resistor is removed. At this time, both the first and second switching transistors in the anti-tamper unit are turned off, and the debugging signal pin connected to the anti-tamper unit is at a high level. The integrated circuit chip determines whether the voltage value of the second control pin is within a predetermined voltage range. By adjusting the fifth and / or sixth resistor values ​​in the anti-tamper unit, the voltage value of each second control pin is made within the predetermined voltage range, allowing external debugging of the integrated circuit chip through the debugging port.

[0055] exist Figures 4-6 In the specific embodiment shown, there are two debug signal terminals: a data debug signal terminal SDA and a clock debug signal terminal SCK; there are two debug signal pins: a data debug signal pin Debug_SDA and a clock debug signal pin Debug_SCK; there are two first control pins: a first control pin GPIO1 and a first control pin GPIO2; there are two second control pins: a second control pin GPIO3 and a second control pin GPIO4; there are two anti-tampering units: a first anti-tampering unit 2 and a second anti-tampering unit 3; the first anti-tampering unit 2 is connected to the first control pin GPIO1, the second control pin GPIO3, and the data debug signal pin Debug_SDA; the second anti-tampering unit 3 is connected to the first control pin GPIO2, the second control pin GPIO4, and the clock debug signal pin Debug_SCK.

[0056] In summary, the tamper-proof circuit for the debug port of an integrated circuit chip provided by this invention has the following beneficial effects:

[0057] 1. This invention uses a combination of hardware and software to disable the Debug port, preventing external parties from tampering with the software code through the Debug port; and allows for easy modification of hardware components to reopen the Debug port during subsequent maintenance and debugging.

[0058] 2. This invention requires only a few transistors and resistors, saving software development costs through hardware implementation. Furthermore, while providing secure anti-tampering functionality, the debug function can be easily reactivated through simple circuit modifications, facilitating later maintenance.

[0059] 3. The software implementation of this invention is simple; it can be easily restored without damaging the chip structure; it has good protection and is difficult to crack.

[0060] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the foregoing specific embodiments.

Claims

1. A tamper-proof circuit for the debug port of an integrated circuit chip, characterized in that, It includes: A debug port, which includes at least one debug signal terminal; An integrated circuit chip includes at least one debug signal pin and at least one first control pin, wherein each debug signal pin is connected to a corresponding debug signal terminal; At least one anti-tampering unit is provided, each of which is connected to a corresponding debug signal pin and a corresponding first control pin. Each anti-tampering unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first switching transistor, and a second switching transistor. One end of the first resistor is connected to the power supply voltage VCC, and the other end is connected to the control terminal of the first switching transistor. One end of the second resistor is connected to the power supply voltage VCC, and the other end is connected to the debug signal pin corresponding to the anti-tampering unit. One end of the third resistor is connected to the control terminal of the first switching transistor, and the other end is connected to the first control pin corresponding to the anti-tampering unit. A first connection terminal of the first switching transistor is connected to the debug signal pin corresponding to the anti-tampering unit, and its other end is grounded through the fourth resistor. A first connection terminal of the second switching transistor is connected to the control terminal of the first switching transistor, and its control terminal is connected to a second connection terminal of the first switching transistor, which is then grounded.

2. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 1, characterized in that, The first switching transistor is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor are the emitter, collector, and base of the PNP transistor, respectively. The second switching transistor is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor are the collector, emitter, and base of the NPN transistor, respectively.

3. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 2, characterized in that, When the debug port needs to be kept open, the integrated circuit chip is not configured with the first control pin. At this time, the first and second switching transistors in the anti-tampering unit are both turned off. The debug signal pin connected to the anti-tampering unit is at a high level, and the outside world can perform debugging work on the integrated circuit chip through the debug port. When the debug port needs to be closed, the integrated circuit chip configures the first control pin to a low level. At this time, both the first and second switching transistors in the anti-tampering unit are turned on; the debug signal pin connected to the anti-tampering unit is at a low level, and the integrated circuit chip cannot be debugged by the outside through the debug port. When the debug port is closed and needs to be reactivated, the third resistor is removed. At this time, the first and second switching transistors in the anti-tampering unit are both turned off. The debug signal pin connected to the anti-tampering unit is at a high level, and the integrated circuit chip can be maintained and debugged by the outside world through the debug port.

4. The anti-tampering circuit for the debug port of an integrated circuit chip according to any one of claims 1-3, characterized in that, The debugging signal terminals are two, namely the data debugging signal terminal SDA and the clock debugging signal terminal SCK; The debugging signal pins are two: the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK. The first control pin consists of two pins, namely the first control pin GPIO1 and the first control pin GPIO2. The anti-tampering unit consists of two units, namely a first anti-tampering unit and a second anti-tampering unit; The first anti-tampering unit is connected to the first control pin GPIO1 and the data debugging signal pin Debug_SDA; The second anti-tampering unit is connected to the first control pin GPIO2 and the clock debugging signal pin Debug_SCK.

5. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 1, characterized in that, The integrated circuit chip also includes at least one second control pin; Each of the anti-tampering units is connected to a corresponding second control pin; The anti-tampering unit further includes a fifth resistor and a sixth resistor, which are connected in series between the power supply voltage VCC and the ground terminal. The connection node between the fifth resistor and the sixth resistor is connected to the second control pin corresponding to the anti-tampering unit.

6. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 5, characterized in that, The first switching transistor is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the first switching transistor are the emitter, collector, and base of the PNP transistor, respectively. The second switching transistor is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the second switching transistor are the collector, emitter, and base of the NPN transistor, respectively.

7. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 6, characterized in that, When the debug port needs to be kept open, the integrated circuit chip does not have the first control pin configured. At this time, the first and second switching transistors in the anti-tampering unit are both turned off, and the debug signal pin connected to the anti-tampering unit is at a high level. The integrated circuit chip does not need to determine whether the voltage value of the second control pin is within a predetermined voltage range, and the outside world can perform debugging work on the integrated circuit chip through the debug port. When the debug port needs to be closed, the integrated circuit chip configures the first control pin to a low level. At this time, both the first and second switching transistors in the anti-tampering unit are turned on; the debug signal pin connected to the anti-tampering unit is at a low level; the integrated circuit chip determines whether the voltage value of the second control pin is within a predetermined voltage range; by adjusting the fifth resistor and / or the sixth resistor in the anti-tampering unit, the voltage value of at least one of the second control pins is not within the predetermined voltage range, and the integrated circuit chip cannot be debugged by the outside through the debug port; When the debug port is closed and needs to be re-enabled, the third resistor is removed. At this time, the first and second switching transistors in the anti-tampering unit are both turned off, and the debug signal pin connected to the anti-tampering unit is at a high level. The integrated circuit chip determines whether the voltage value of the second control pin is within a predetermined voltage range. By adjusting the fifth and / or sixth resistors in the anti-tampering unit, the voltage value of each second control pin is made to be within the predetermined voltage range, and the integrated circuit chip can be debugged by the outside world through the debug port.

8. The anti-tampering circuit for the debug port of an integrated circuit chip according to any one of claims 5-7, characterized in that, The debugging signal pins are two: the data debugging signal pin Debug_SDA and the clock debugging signal pin Debug_SCK. The first control pin consists of two pins, namely the first control pin GPIO1 and the first control pin GPIO2. There are two second control pins, namely the second control pin GPIO3 and the second control pin GPIO4. The anti-tampering unit consists of two units, namely a first anti-tampering unit and a second anti-tampering unit; The first anti-tampering unit is connected to the first control pin GPIO1, the second control pin GPIO3, and the data debugging signal pin Debug_SDA; The second anti-tampering unit is connected to the first control pin GPIO2, the second control pin GPIO4, and the clock debug signal pin Debug_SCK.

9. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 5, characterized in that, When external parties can debug the integrated circuit chip through the debugging port. The resistance value of the fifth resistor in each of the aforementioned anti-tampering units is different; and / or The resistance value of the sixth resistor in each of the tamper-proof units is different.

10. The anti-tampering circuit for the debug port of an integrated circuit chip according to claim 1, characterized in that, The power supply voltage VCC is the power supply for the integrated circuit chip.

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