A signal and power integrity co-analysis method for high-speed core particle serial channel

Abstract

The application discloses a signal and power integrity co-analysis method for a high-speed core particle serial channel, constructs an equivalent circuit of a sending end, models nonlinear characteristics of the sending end based on a neural network sending end model, extracts S parameters of a propagation medium and a receiving end and converts the S parameters into impulse responses, and obtains signal and power integrity analysis results based on signal and power integrity co-analysis based on impulse response superposition. The neural network sending end model can accurately model nonlinear behaviors of the sending end under different input and output loads; the propagation medium and the receiving end model effectively extracts system impulse responses of insertion loss and far-end crosstalk of the channel from the S parameters, accurately models complex crosstalk effects in a high-density channel; and the signal and power integrity co-analysis framework further improves the analysis speed based on the impulse response superposition mode, and can effectively improve the simulation verification efficiency in the circuit design process.

Description

Technical Field

[0001] This invention belongs to the field of chip simulation verification, specifically involving a method for collaborative analysis of signal and power integrity for high-speed chip serial channels. Background Technology

[0002] With the development of high-performance computing and high-bandwidth communication, the integration density of integrated circuits is constantly increasing to achieve better performance. However, in recent years, with the gradual evolution of advanced processes, the improvement of transistor density in two-dimensional planar structures has encountered physical bottlenecks, Moore's Law has gradually slowed down, and chip R&D costs have increased significantly. To overcome the current predicament of chip design and manufacturing, high-density heterogeneous integrated chips based on chips have emerged. A chip refers to a pre-manufactured, functional, and combinable die, and each chip can be implemented using the optimal process node during the design phase. Several individually manufactured chips are integrated together through 2.5D / 3D packaging to form a larger-scale chip and build a complex heterogeneous integrated system. Chip technology has the characteristics of modularity, scalability, and process partitioning, which can reduce the cost and cycle of large-scale chip design and manufacturing, and has outstanding advantages in domain-specific processing architectures.

[0003] Inter-chip communication occurs via interconnects in the interposer layer. As circuit operating frequencies and data rates increase, high-density communication between chips is required. The complex coupling effects between these high-density, high-speed channels lead to more severe signal distortion and inter-symbol interference, deteriorating the signal integrity of the high-speed channels between chips. On the other hand, the demand for low-power design results in continuously decreasing chip operating voltages, which in turn reduces signal and power supply noise margins. Even slight noise can cause circuit malfunctions. Therefore, during the design of chip-level integrated circuits, it is necessary to perform co-analysis of signal and power integrity for the chip's serial channels to ensure normal circuit operation.

[0004] Existing signal and power integrity co-analysis techniques mainly suffer from the following problems:

[0005] (1) High-speed channels contain nonlinear transmitters, which are usually buffers. Accurate modeling of these transmitters is required. While commonly used transistor-level models such as SPICE have high accuracy, their simulation efficiency is low. Behavioral-level models such as IBIS improve simulation speed by using lookup tables, but at the expense of accuracy. Currently, many works have proposed using neural networks to model nonlinear buffers. However, most of these works only consider isolated nonlinear buffers and do not take into account the impact of the overall circuit on the transmitter. This makes the models unsuitable for simulating high-speed channels. Therefore, it is urgent to propose a nonlinear circuit modeling method that balances accuracy and efficiency.

[0006] (2) There is complex crosstalk between high-speed channels, which is difficult to model, and the coupling between power supply noise and signal further exacerbates the modeling difficulty. Existing technologies usually directly simulate S-parameters to analyze the signal integrity of high-speed channels, which is very inefficient in complex systems and makes it difficult to model the coupling between power supply noise and signal.

[0007] (3) In the process of circuit design, it is necessary to verify the high-speed channel. Usually, a large number of pseudo-random sequences are generated as inputs for transient simulation, and the bit error rate and eye diagram of the output signal are observed. Traditional simulation software takes a lot of time and is inefficient.

[0008] To achieve efficient and accurate modeling and analysis of high-speed chip serial channels, this invention proposes a collaborative analysis method for signal and power integrity of high-speed chip serial channels. Summary of the Invention

[0009] To overcome the shortcomings of existing technologies, this invention provides a method for co-analysis of signal and power integrity in high-speed chip serial channels.

[0010] A method for co-analysis of signal and power integrity for high-speed chip serial channels includes the following steps:

[0011] S1. Transmitter Modeling: Based on neural networks, the inherent characteristics of the transmitter, de-emphasis, and the nonlinear characteristics of noise coupling are modeled.

[0012] S2. Modeling of the transmission medium and receiver: The transmission medium and receiver are a multi-port network containing several input ports and output ports. The S-parameters of the multi-port network are extracted, and the impulse response between any two input and output ports is obtained through transformation to obtain the model of the transmission medium and receiver.

[0013] S3. Signal and Power Integrity Co-analysis: For a given input sequence, it is decomposed into time-shifted superposition of square wave pulses. The square wave pulses and power supply voltage sequence are then input into the transmitter model, propagation medium, and receiver model to obtain the pulse response and coupling noise under ideal conditions. The pulse response is then time-shifted according to the input to obtain the output signal under ideal conditions. Finally, the coupling noise is superimposed on the ideal output signal to obtain the signal and power integrity analysis results.

[0014] Specifically, the serial channel includes a transmitter, a propagation medium, and a receiver. The transmitter can be equipped with a de-emphasis module as needed. The de-emphasis module is a two-tap coefficient finite impulse response filter, i.e.

[0015]

[0016] Where, x iand x i-1 Let be the input voltages at time i and time i-1, respectively. Let i be the input voltage after de-emphasis, and the sum of C0 and C1 is 1; communication between chips involves several serial channels, and there is a coupling effect between multiple serial channels.

[0017] Furthermore, in step S1, the nonlinear characteristics of the transmitting end are modeled using a neural network, including the following steps:

[0018] S1.1 Establish the equivalent circuit of the transmitter, and the influence of the propagation medium and the receiver on the transmitter is equivalent to a load consisting of an ideal transmission line and a pull-up matching resistor connected in series, and connected in parallel with the original load capacitor of the transmitter. Input a square wave to the equivalent circuit of the transmitter and perform transient simulation to obtain the output waveform of the transmitter. By changing the load, input square wave and power supply noise of the transmitter, generate several sets of data.

[0019] S1.2 Design three neural networks to model the inherent characteristics of the transmitter, the deemphasis, and the nonlinear characteristics of noise coupling, respectively. Train the three neural networks with the generated data to obtain the ideal model of the transmitter, the deemphasis model, and the noise coupling model.

[0020] Furthermore, the specific method for generating data by the sending end in step S1.1 is as follows:

[0021] For the ideal model of the transmitter, the equivalent circuit of the transmitter is connected to an ideal power supply. By changing the load capacitance, characteristic impedance of the transmission line, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, several sets of output waveforms of the transmitter are obtained through transient simulation.

[0022] For the deemphasis model of the transmitter, the equivalent circuit of the transmitter is connected to an ideal power supply. The transmitter input square wave deemphasis and re-input circuit is changed. By changing the load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, amplitude and rise / fall time of the input square wave and the deemphasis coefficient of the transmitter, several sets of transmitter output waveforms are obtained through transient simulation.

[0023] For the noise coupling model at the transmitter, the load capacitance, transmission line characteristic impedance, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, and amplitude and frequency of the power supply noise at the transmitter are changed. Transient simulations are performed on the equivalent circuits of the transmitter with ideal power supply and noisy power supply respectively. Several sets of transmitter output signals under noise coupling and ideal transmitter output signals are obtained. Subtracting the latter from the former yields several sets of transmitter output coupling noise.

[0024] Furthermore, in step S1.2, the inputs to the ideal model of the transmitting end are the load capacitance of the transmitting end, the characteristic impedance of the transmission line, the pull-up voltage value of the matching resistor, and the input voltage sequence from t-α to t, and the output is the output voltage of the transmitting end at time t.

[0025] The inputs to the transmitter deemphasis model are the transmitter's load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, deemphasis coefficient C0, and the input voltage sequence from t-β to t. The output is the transmitter's output voltage at time t.

[0026] The inputs to the transmitter noise coupling model are the transmitter's load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, input voltage sequence from t-γ to t, and power supply voltage sequence from t-γ to t. The output is the transmitter's output coupling noise at time t.

[0027] To obtain the output signal corresponding to an input signal of length L, it is necessary to perform L calculations of the neural network model.

[0028] Furthermore, the size of the S-parameters in step S2 depends on the frequency sampling points specified by the user and the number of serial channels in the chip system. For a system with n serial channels, let the input and output ports of the i-th channel be ports 2i-1 and 2i, respectively, and the S-parameters be a matrix of f×2n×2n, where f is the number of frequency sampling points.

[0029] Furthermore, in step S2, the impulse response h ji The steps to obtain it are as follows:

[0030] S21. Convert the S-parameters into the frequency domain transfer function H using the following method. ji :

[0031]

[0032]

[0033] Where i and j are the numbers of the input and output ports, respectively;

[0034] S22, H ji The interpolation is a function that is uniformly sampled with frequency, and then the inverse Fourier transform is used to convert the interpolated transfer function into an impulse response h in the time domain. ji .

[0035] Furthermore, in step S3, the length of the square wave pulse is two unit intervals UI, and a trapezoidal wave is used to replace the equivalent square wave pulse, for a rise / fall time of T. rf The pulse shape, before (UI-T) rf ) / 2 is low level, after T rfIt then rises to a high level, and the high level lasts for UI-T. rf It then began to descend, passing through T rf Then it drops to a low level, remaining (UI-T) rf ) / 2 remains low.

[0036] Furthermore, in step S3,

[0037] The impulse response is obtained as follows: as needed, the square wave pulse or the de-emphasized square wave pulse and the corresponding input features are input into the ideal model of the transmitter or the de-emphasized model of the transmitter to obtain the output signal of the transmitter. Then, the output signal of the transmitter is convolved with the corresponding impulse response to obtain the impulse response between each pair of input and output ports.

[0038] The coupling noise is obtained by inputting the input signal, power supply voltage sequence, load capacitance of the transmitter, characteristic impedance of the transmission line, pull-up voltage value of the matching resistor, input voltage sequence from t-γ to t, and power supply voltage sequence from t-γ to t into the noise coupling model of the transmitter to obtain the output coupling noise of the transmitter. Then, the output coupling noise of the transmitter is convolved with the corresponding impulse response to obtain the coupling noise between each pair of input and output ports.

[0039] Furthermore, in step S3, for a system with n serial channels, the ideal output signal z of output port k is... k The calculation method for (t) is as follows:

[0040]

[0041] Where m is the number of bits in the input sequence, r k,2i-1 (t) represents the impulse response between input port 2i-1 and output port k, x τ,2i-1 The τth bit input to port 2i-1 takes the value 0 or 1.

[0042] Compared with existing technologies, this invention has the following advantages: the neural network-based transmitter model can accurately model the nonlinear behavior of the transmitter under different input and output loads, and has a faster simulation speed than traditional transistor model simulation; the propagation medium and receiver model effectively extracts the system impulse response of the channel insertion loss and far-end crosstalk from the S-parameters, and accurately models the complex crosstalk effects in high-density channels; the signal and power integrity co-analysis framework further improves the analysis speed based on the impulse response superposition method, while having high accuracy, and can effectively improve the efficiency of simulation verification in the circuit design process. Attached Figure Description

[0043] Figure 1 This invention provides a collaborative analysis framework for signal and power integrity.

[0044] Figure 2 This invention relates to a high-speed chip serial channel structure;

[0045] Figure 3 This is the structure of the transmitting neural network model of the present invention;

[0046] Figure 4 This invention relates to the structure of a multi-port network for both the transmission medium and the receiving end.

[0047] Figure 5 This is an example diagram illustrating the calculation of the output signal in a two-channel design according to the present invention;

[0048] Figure 6 This is a comparison of the eye diagrams obtained by the present invention and simulation software;

[0049] Figure 7 This is a comparison of the analysis time between the present invention and simulation software. Detailed Implementation

[0050] The invention will now be further described with reference to the accompanying drawings.

[0051] like Figure 1 As shown, a signal and power integrity co-analysis method for high-speed chip serial channels is described, with the following specific implementation steps:

[0052] Step 1: Modeling the sending end.

[0053] like Figure 2 The diagram shows a high-speed chip serial channel structure. Inter-chip communication utilizes several single-ended, unidirectional, full-duplex serial channels. The standard package and advanced package systems have 16 and 64 serial channels, respectively. Each serial channel includes a transmitter, a propagation medium, and a receiver. The transmitter can be equipped with a de-emphasis module, especially at higher data rates, to obtain a higher quality output signal. Input data can be represented as x1x2...x m , where x i The value can be either 0 or 1. During simulation, the input data is typically converted into a square wave with a certain rise / fall time. For chip-level integrated circuits, the deemphasis module is a two-tap coefficient finite impulse response (FIR) filter, and the deemphasis process for the input data can be expressed as:

[0054]

[0055] Where, x i and x i-1 Let be the input voltages at time i and time i-1, respectively. Let C0 be the deemphasized input voltage at time i, and the sum of C0 and C1 is 1. Power supply noise will couple to the transmitter output through the transmitter, and then to the serial channel output. Therefore, it is necessary to model the inherent characteristics of the transmitter, the deemphasis, and the nonlinear characteristics of noise coupling. This invention uses a neural network to model these three characteristics, specifically including the following two steps:

[0056] 1.1) Establish the equivalent circuit of the transmitter and construct the dataset.

[0057] First, establish the equivalent circuit of the transmitter. The influence of the propagation medium and the receiver on the transmitter is equivalent to a load consisting of an ideal transmission line and a pull-up matching resistor connected in series, and connected in parallel with the original load capacitance of the transmitter. The characteristic impedance of the ideal transmission line is the same as the characteristic impedance of the propagation medium, and the pull-up voltage of the matching resistor is the equivalent open-circuit voltage of the receiver.

[0058] To construct the dataset, a square wave was input to the equivalent circuit of the transmitter and transient simulation was performed to obtain the output waveform of the transmitter. Several sets of data were generated by changing the load, input square wave, and power supply noise of the transmitter. Specifically, for the ideal transmitter model, the equivalent circuit of the transmitter is connected to an ideal power supply. By changing the load capacitance, transmission line characteristic impedance, pull-up voltage of the matching resistor, and the amplitude and rise / fall time of the input square wave, several sets of transmitter output waveforms are obtained through transient simulation. For the de-emphasis model of the transmitter, the equivalent circuit of the transmitter is connected to an ideal power supply, and the input square wave is de-emphasized and then re-inputted into the circuit. By changing the load capacitance, transmission line characteristic impedance, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, and de-emphasis coefficient, several sets of transmitter output waveforms are obtained through transient simulation. For the noise coupling model of the transmitter, by changing the load capacitance, transmission line characteristic impedance, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, and amplitude and frequency of the power supply noise, transient simulations are performed on the equivalent circuits of the transmitter connected to the ideal power supply and the noise-enhanced power supply, respectively, to obtain several sets of transmitter output signals under noise coupling and the ideal transmitter output signal. Subtracting the latter from the former yields several sets of transmitter output coupled noise.

[0059] 1.2) Design three neural networks to model the inherent characteristics of the transmitter, the de-emphasis, and the nonlinear characteristics of noise coupling, respectively. The structure of the neural networks is as follows: Figure 3 As shown, where Figure 3 (a) shows the structures of the ideal model and the de-emphasis model at the transmitter. Figure 3 (b) shows the structure of the noise coupling model at the transmitter.

[0060] The input to the ideal model of the transmitter is the load capacitance C of the transmitter. L Transmission line characteristic impedance Z0, matching resistor pull-up voltage Vp The input voltage sequence [u(t-α), u(t-α+1), ..., u(t)] from time t-α to time t is given, and the output is the transmitter output voltage y(t) at time t. The input of the transmitter deemphasis model is the transmitter load capacitance C. L Transmission line characteristic impedance Z0, matching resistor pull-up voltage V p The de-emphasis coefficient C0 and the input voltage sequence from t-β to t [u] d (t-β),u d (t-β+1),...,u d [(t)], the output is the transmitting voltage y at time t. d (t); The input to the transmitter noise coupling model is the load capacitance C of the transmitter. L Transmission line characteristic impedance Z0, matching resistor pull-up voltage V p The input voltage sequence [u(t-γ), u(t-γ+1), ..., u(t)] from time t-γ to time t, the power supply voltage sequence [v(t-γ), v(t-γ+1), ..., v(t)] from time t-γ to time t, and the output is the coupled noise d(t) at time t. The outputs of the three models can be expressed as:

[0061] y(t)=f i [u(t-α),...,u(t),C L ,Z0,V p ],

[0062] y d (t)=f d [u d (t-β),...,u d (t),C L ,Z0,V p [,C0],

[0063] d(t)=f p [u(t-γ),...,u(t),v(t-γ),...,v(t),C L ,Z0,V p ],

[0064] Among them, f i [·],f d [·] and f p[·] represents the ideal transmitter model, the de-emphasis model, and the noise coupling model, respectively. The values ​​of α, β, and γ depend on the transmitter design. In this invention, the values ​​of α, β, and γ are all 45. The ideal transmitter model and the de-emphasis model consist of one input layer, three hidden layers, and one output layer, with the hidden layer having 18 nodes. The noise coupling model employs an innovative network design: the input voltage sequence and the power supply voltage sequence are first input into a hidden layer with γ nodes, and then the intermediate features obtained are input together with the remaining three features into the three hidden layers and the one output layer. To obtain the output signal corresponding to an input signal of length L, L neural network model calculations are required. The generated data is used to train the three neural networks respectively to obtain the ideal transmitter model, the de-emphasis model, and the noise coupling model.

[0065] Step 2: Modeling the transmission medium and the receiving end.

[0066] Communication between chips involves several serial channels, and coupling effects exist between these channels. The propagation medium and receiver can be viewed as a multi-port network containing several input and output ports, such as... Figure 4 As shown, let the input and output ports of the i-th channel be ports 2i-1 and 2i, respectively. Extract the S-parameters of the multi-port network. The size of the S-parameters depends on the user-specified frequency sampling points and the number of serial channels in the chip system. For a system with n serial channels, the S-parameters are an f×2n×2n matrix, where f is the number of frequency sampling points. The S-parameters are first converted into the frequency domain transfer function H in the following way. ji :

[0067]

[0068]

[0069] Where i and j are the numbers of the input and output ports, respectively; then H... ji The interpolation is a function uniformly sampled with frequency, and then the inverse Fourier transform (IFFT) is used to convert the interpolated transfer function into an impulse response h in the time domain. ji Thus, the models of the transmission medium and the receiving end were obtained.

[0070] The propagation medium and receiver model describes the insertion loss and far-end crosstalk response of the channel. Based on the derived model, for a system with n serial channels, the output of receiver port k... It can be calculated using the following formula:

[0071]

[0072] in, This represents the input signal at port 2i-1, h.k,2i-1 This represents the impulse response between port 2i-1 and port k, and the symbol * indicates the convolution operation.

[0073] Step 3: Co-analysis of signal and power integrity.

[0074] Since the inference and propagation media of the transmitting neural network model and the convolution of the receiving model still suffer from high computational cost and long processing time when dealing with long input sequences, this invention proposes an analysis method based on impulse response. For a given input sequence, it is decomposed into a time-shifted superposition of square wave pulses, where the length of the square wave pulse is two unit intervals (UI). Since real-world square waves always have a certain rise / fall time, a trapezoidal wave is used to represent the square wave pulse. For rise / fall times of T... rf The pulse shape is as follows: (UI-T) rf ) / 2 is low level, after T rf It then rises to a high level, and the high level lasts for UI-T. rf It then began to descend, passing through T rf Then it drops to a low level, remaining (UI-T) rf ) / 2 is kept low. Then, the square wave pulse and power supply voltage sequence are input into the transmitter model, propagation medium, and receiver model to obtain the ideal impulse response and coupling noise. The impulse response is obtained by first inputting the square wave pulse (or a de-emphasized square wave pulse) and other features into the transmitter ideal model or transmitter de-emphasized model as needed to obtain the transmitter output signal. Then, the transmitter output signal is convolved with the corresponding impulse response to obtain the impulse response between each pair of input and output ports. The coupling noise is obtained by inputting the input signal, power supply voltage sequence, and other features into the transmitter noise coupling model to obtain the transmitter output coupling noise. Then, the transmitter output coupling noise is convolved with the corresponding impulse response to obtain the coupling noise between each pair of input and output ports. The impulse response is time-shifted and superimposed according to the input to obtain the ideal output signal. The coupling noise is then superimposed onto the ideal output signal to obtain the signal and power integrity analysis results. For a system with n serial channels, the ideal output signal z of output port k... k The calculation method for (t) is as follows:

[0075]

[0076] Where m is the number of bits in the input sequence, r k,2i-1 (t) represents the impulse response between input port 2i-1 and output port k, x τ,2i-1 The τth bit input to port 2i-1 takes the value 0 or 1. Figure 5This diagram illustrates the output signal of port 2 in a two-channel system. First, a square wave pulse is input into the transmitter models of both the first and second channels to obtain the transmitter output signal. Then, the transmitter output signal of the first channel is compared with h... 21 Convolution is performed to obtain the impulse response between port 1 and port 2. The output signal from the transmitter of the second channel is then compared with h. 23 Convolution is performed to obtain the impulse response between port 3 and port 2. When calculating the output of port 2 given the input data, the previously obtained impulse responses are time-shifted and superimposed according to the input data to obtain the final output signal.

[0077] like Figure 6 As shown, the eye diagram obtained by this invention in a single-channel design is compared with the simulation results of simulation software. Figure 6 (a) and Figure 6 (b) Eye diagrams obtained by the present invention and simulation software under noise-free conditions, respectively. Figure 6 (c) and Figure 6 (d) The eye diagrams obtained by the present invention and simulation software under power supply noise coupling are shown respectively. It can be seen that the results of the two are very similar, and the average relative error of the key parameters of the eye diagram is 0.82-1.85%. Figure 7 The comparison of analysis time between the present invention and simulation software on two designs is shown. It can be seen that, with the signal sampling step size and UI remaining constant, the analysis time of the simulation software varies with the circuit complexity, while the simulation time of the present invention remains almost constant, achieving an efficiency improvement of 18-44 times compared to the simulation software. In summary, the method of the present invention can effectively improve the efficiency of signal and power integrity co-analysis in high-speed chip serial channels, while also possessing high accuracy.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for co-analyzing signal and power integrity in high-speed chip serial channels, characterized in that, The method includes the following steps: S1. Transmitter Modeling: Modeling the inherent characteristics, de-emphasis, and nonlinear characteristics of noise coupling at the transmitter based on neural networks; Modeling the nonlinear characteristics of the transmitter using neural networks includes the following steps: S1.1 Establish the equivalent circuit of the transmitter, and the influence of the propagation medium and the receiver on the transmitter is equivalent to a load consisting of an ideal transmission line and a pull-up matching resistor connected in series, and connected in parallel with the original load capacitor of the transmitter. Input a square wave to the equivalent circuit of the transmitter and perform transient simulation to obtain the output waveform of the transmitter. By changing the load, input square wave and power supply noise of the transmitter, generate several sets of data. S1.2 Design three neural networks to model the inherent characteristics of the transmitter, the deemphasis, and the nonlinear characteristics of noise coupling, respectively. Train the three neural networks with the generated data to obtain the ideal model of the transmitter, the deemphasis model, and the noise coupling model. S2. Modeling of the Propagation Medium and Receiver: The propagation medium and receiver are represented as a multi-port network with several input and output ports. The S-parameters of the multi-port network are extracted, and then the impulse response between any two input and output ports is obtained through transformation, thus deriving the model of the propagation medium and receiver; Impulse Response. The steps to obtain it are as follows: S21. Convert the S-parameters into a frequency domain transfer function using the following method. : ， ， Where i and j are the numbers of the input and output ports, respectively; S22, will The interpolation is a function that is uniformly sampled with frequency, and then the inverse Fourier transform is used to convert the interpolated transfer function into an impulse response in the time domain. ; S3. Signal and Power Integrity Co-analysis: For a given input sequence, it is decomposed into time-shifted superposition of square wave pulses. The square wave pulses and power supply voltage sequence are then input into the transmitter model, propagation medium, and receiver model to obtain the pulse response and coupling noise under ideal conditions. The pulse response is then time-shifted according to the input to obtain the output signal under ideal conditions. Finally, the coupling noise is superimposed on the ideal output signal to obtain the signal and power integrity analysis results.

2. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 1, characterized in that, The serial channel includes a transmitter, a propagation medium, and a receiver. The transmitter can be equipped with a de-emphasis module, which is a two-tap coefficient finite impulse response filter. ， in, and Let be the input voltages at time i and time i-1, respectively. Let i be the input voltage after de-emphasis. and The sum is 1; communication between cores involves several serial channels, and there is a coupling effect between multiple serial channels.

3. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 1, characterized in that, The specific method for generating data at the sending end in step S1.1 is as follows: For the ideal model of the transmitter, the equivalent circuit of the transmitter is connected to an ideal power supply. By changing the load capacitance, characteristic impedance of the transmission line, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, several sets of output waveforms of the transmitter are obtained through transient simulation. For the deemphasis model of the transmitter, the equivalent circuit of the transmitter is connected to an ideal power supply. The transmitter input square wave deemphasis and re-input circuit is changed. By changing the load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, amplitude and rise / fall time of the input square wave and the deemphasis coefficient of the transmitter, several sets of transmitter output waveforms are obtained through transient simulation. For the noise coupling model at the transmitter, the load capacitance, transmission line characteristic impedance, pull-up voltage of the matching resistor, amplitude and rise / fall time of the input square wave, and amplitude and frequency of the power supply noise at the transmitter are changed. Transient simulations are performed on the equivalent circuits of the transmitter with ideal power supply and noisy power supply respectively. Several sets of transmitter output signals under noise coupling and ideal transmitter output signals are obtained. Subtracting the latter from the former yields several sets of transmitter output coupling noise.

4. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 1, characterized in that, In step S1.2, the inputs to the ideal model of the transmitting end are the load capacitance of the transmitting end, the characteristic impedance of the transmission line, the pull-up voltage value of the matching resistor, and the input voltage sequence from t-α to t. The output is the output voltage of the transmitting end at time t. The inputs to the transmitter deemphasis model are the transmitter's load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, and deemphasis coefficient. The input voltage sequence from t-β to t is given, and the output is the output voltage of the transmitting end at time t. The inputs to the transmitter noise coupling model are the transmitter's load capacitance, transmission line characteristic impedance, matching resistor pull-up voltage, input voltage sequence from t-γ to t, and power supply voltage sequence from t-γ to t. The output is the transmitter's output coupling noise at time t. To obtain the output signal corresponding to an input signal of length L, it is necessary to perform L-fold calculations of the neural network model.

5. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 1, characterized in that, In step S2, the size of the S-parameters depends on the frequency sampling points specified by the user and the number of serial channels in the chip system. For a system with n serial channels, let the input and output ports of the i-th channel be ports 2i-1 and 2i, respectively. The S-parameters are a matrix of f×2n×2n, where f is the number of frequency sampling points.

6. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 1, characterized in that, In step S3, the length of the square wave pulse is two unit intervals UI. A trapezoidal wave is used to derive the equivalent square wave pulse. For rise / fall times of... The pulse shape, before It is a low level, after It then rises to a high level and remains at a high level. It then began to descend, passing through Then it drops to a low level, remaining Keep it low.

7. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 6, characterized in that, In step S3 The impulse response is obtained as follows: as needed, the square wave pulse or the de-emphasized square wave pulse and the corresponding input features are input into the ideal model of the transmitter or the de-emphasized model of the transmitter to obtain the output signal of the transmitter. Then, the output signal of the transmitter is convolved with the corresponding impulse response to obtain the impulse response between each pair of input and output ports. The coupling noise is obtained by inputting the input signal, power supply voltage sequence, load capacitance of the transmitter, characteristic impedance of the transmission line, pull-up voltage value of the matching resistor, input voltage sequence from t-γ to t, and power supply voltage sequence from t-γ to t into the noise coupling model of the transmitter to obtain the output coupling noise of the transmitter. Then, the output coupling noise of the transmitter is convolved with the corresponding impulse response to obtain the coupling noise between each pair of input and output ports.

8. The signal and power integrity co-analysis method for high-speed chip serial channels according to claim 6, characterized in that, In step S3, for a system with n serial channels, the ideal output signal of output port k is... The calculation method is as follows: ， Where m is the number of bits in the input sequence, The impulse response between input port 2i-1 and output port k. The input to port 2i-1 Each bit has a value of either 0 or 1.

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