A circuit key input vector identification method based on association rule analysis

Abstract

The application relates to a circuit key input vector identification method based on association rule analysis, which comprises the following steps: obtaining a netlist of a circuit to be identified and analyzing and constructing a circuit integrity linked list; judging the circuit type according to the circuit integrity linked list, constructing an initial input vector set according to the circuit type, and generating an initial input vector; calculating the reliable value of the initial input vector based on the initial input vector set, obtaining and returning the initial key input vector based on the reliable value of the initial input vector; analyzing the association rule of the original input end of the circuit to be identified based on the initial key input vector through an association rule analysis model; generating a new input vector sample according to the association rule of the original input end; calculating the reliable value of the new input vector sample, obtaining and returning the key input vector. Compared with the prior art, the analysis method provided by the application can be used for combination circuits and time sequence circuits, and has the advantages of low complexity, fast convergence speed, small test fluctuation, high accuracy and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit reliability assessment, and in particular to a method for identifying critical input vectors of circuits based on association rule analysis. Background Technology

[0002] Currently, tools and algorithms for circuit reliability assessment are mainly categorized into measurement-based methods, sampling-based methods, and model-analytical methods. However, these methods often calculate the average reliability of the circuit based on multiple input vectors (MIVs), neglecting the impact of individual input vectors (IIVs) on the circuit.

[0003] Meanwhile, different input vectors have varying impacts on circuit reliability, sometimes differing by orders of magnitude. Identifying reliability-critical input vectors (RCIVs) provides circuit designers with a quick reference to the circuit reliability boundary, ensuring that the circuit maintains reliability requirements even when RCIVs are applied to the original inputs. Patent CN114024829A uses association rule analysis to locate circuit faults, but existing RCIVs methods are limited by slow convergence speed, resulting in significant fluctuations in reliability analysis and testing. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology, such as slow convergence speed and large test fluctuations, and to provide a method for identifying key input vectors of circuits based on association rule analysis.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A method for identifying key circuit input vectors based on association rule analysis includes the following steps:

[0007] S1: Obtain and parse the netlist of the circuit to be identified, and construct a circuit integrity linked list;

[0008] S2: Determine the circuit type based on the circuit integrity linked list, construct an initial input vector set based on the circuit type and the basic parameters of the circuit integrity linked list, and use each initial input vector in the initial input vector set as the input signal of the circuit;

[0009] S3: Based on the circuit's input signal, calculate the overall reliability value of the circuit under each initial input vector, obtain and return the initial key input vector based on the overall reliability value of the circuit;

[0010] S4: Based on the initial key input vector, the association rules of the original input terminals of the circuit to be identified are analyzed through the association rule analysis model;

[0011] S5: Generate new input vector samples based on the association rules of the original input.

[0012] S6: Calculate the reliable value of the new input vector sample, obtain and return the key input vector.

[0013] Further, step S1 includes:

[0014] S1.1: Read and parse the circuit netlist, extract the basic gate information of the circuit, and construct a circuit integrity linked list to store the basic gate information;

[0015] S1.2: Identify all original input terminals and basic gates in the circuit based on the circuit integrity linked list;

[0016] S1.3: The number of original input terminals and the number of basic gates in the statistical circuit;

[0017] S1.4: Initialize the fault probability of the basic gates and the total number of initial input vectors.

[0018] Further, step S2 includes:

[0019] S2.1: Based on the circuit integrity linked list, determine the circuit type. If it is a combinational logic circuit, proceed to step S2.2; otherwise, skip to step S2.3.

[0020] S2.2: Based on the original number of input terminals and the total number of initial input vectors, randomly generate an initial input vector zero matrix and execute step S2.5;

[0021] S2.3: Based on the integrity linked list, count the number of flip-flops in the sequential circuit;

[0022] S2.4: Based on the number of original input terminals, the number of flip-flops, and the total number of initial input vectors, randomly generate an initial input vector zero matrix;

[0023] S2.5: Randomly generate a Boolean vector whose every bit consists of "0" or "1". The number of Boolean vectors is equal to the number of input vectors, and the size of the Boolean vectors is the same as the number of rows of the initial input vector zero matrix.

[0024] S2.6: Assign the Boolean vector to the zero vector matrix;

[0025] S2.7: Output the set of input vectors obtained by assigning values ​​to the vector zero matrix.

[0026] Further, step S3 includes:

[0027] S3.1: Based on the fault probability of the basic gate and the total number of initial input vectors, perform random fault injection the same number of times as the total number of initial input vectors;

[0028] S3.2: Calculate the overall reliability value of the circuit under each input vector based on the initial input vector set;

[0029] S3.3: Sort the input vector set according to the overall reliability value of the circuit under each input vector, and obtain the initial key input vector based on the sorting result;

[0030] S3.4: Based on the initial key input vector, calculate the probability that each original input signal of the initial key input vector is "1".

[0031] Further, step S4 includes:

[0032] S4.1: Initialize minimum support and minimum confidence;

[0033] S4.2: Initialize the first counting parameter k to 1, and set the first assignment threshold parameter and the second assignment threshold parameter;

[0034] S4.3: Identify candidate k-itemsets based on the initial key input vector;

[0035] S4.4: If the candidate k-item set is empty, proceed to step S4.19; otherwise, proceed to step S4.5.

[0036] S4.5: Initialize the second counter parameter i to 1;

[0037] S4.6: Calculate the support of the i-th array of the candidate k-itemsets;

[0038] S4.7: If the support of the i-th array of the candidate k-items set is greater than or equal to the minimum support, then proceed to step S4.8; otherwise, proceed to step S4.9.

[0039] S4.8: Add the i-th array element of the candidate k-itemsset to the frequent k-itemsset;

[0040] S4.9: Increment the second counting parameter i by 1;

[0041] S4.10: If the i-th array of the candidate k-items set is empty, then execute step S4.7; otherwise, execute step S4.11.

[0042] S4.11: Initialize the third counting parameter j to be 1;

[0043] S4.12: Calculate the confidence score of the j-th array of frequent k-itemsets;

[0044] S4.13: If the confidence of the j-th array of the frequent k-itemset is greater than or equal to the minimum confidence, then proceed to step S4.14; otherwise, proceed to step S4.15.

[0045] S4.14: Add the j-th array of the frequent k-itemsets to the frequent confidence k-itemsets and the association rule set;

[0046] S4.15: Increment the third counting parameter j by 1;

[0047] S4.16: If the j-th array of the frequent k-itemsets is empty, then execute step S4.17; otherwise, return to step S4.12.

[0048] S4.17: Combine any two items from the frequent confidence k-item set to form a candidate k+1 itemset;

[0049] S4.18: Increment the first counting parameter k by 1, and return to step S4.4;

[0050] S4.19: If the association rule set is empty and the minimum confidence level is greater than the first assignment threshold parameter, then execute step S4.20; otherwise, execute step S4.21.

[0051] S4.20: Subtract the second assignment threshold parameter from the minimum support, subtract the second assignment threshold parameter from the minimum confidence, and return to step S4.2;

[0052] S4.21: Returns the set of association rules.

[0053] Further, step S5 includes:

[0054] S5.1: Maximize the integration of all rules in the association rule set and return the original input signal "1" association rule and "0" association rule;

[0055] S5.2: Construct multiple new input vector sets;

[0056] S5.3: Assign values ​​to the new input vector set based on the "1" association rule and the "0" association rule. The values ​​of the random input signals are assigned according to the probability of each original input signal taking "1" in the initial key input vector of S3.4.

[0057] Further, step S6 includes:

[0058] S6.1: Based on the fault probability of the basic gate and the total number of initial input vectors N, perform N random fault injections;

[0059] S6.2: Calculate the overall reliability value of the circuit under each new input vector based on the new input vector set;

[0060] S6.3: Sort the new input vector set according to the overall reliability value of the circuit under each new input vector, and return the key input vector according to the sorting result.

[0061] Furthermore, the initial key input vector includes the input vector with the largest reliability value and the input vector with the smallest reliability value, and the key input vector includes the new input vector with the largest reliability value and the new input vector with the smallest reliability value.

[0062] Further, in step S2.2, the number of rows in the zero matrix of the input vector is the number of original input terminals, and the number of columns is the number of input vectors; in step S2.4, the number of rows in the zero matrix of the input vector is the sum of the number of original input terminals and the number of trigger input terminals, and the number of columns is the number of input vectors.

[0063] Furthermore, the reliability is calculated using a continuous convex approximation algorithm.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] 1) The analysis method based on association rule analysis provided by this invention can be used for combinational circuits and sequential circuits. It uses an association rule analysis model to identify the associated original inputs of the circuit, while reducing the complexity of identifying key reliability input vectors. It has a faster convergence speed, reduces fluctuations during testing, and thus improves accuracy.

[0066] 2) Based on the frequency of the identified associated original inputs and the unidentified inputs, the present invention generates new input vector samples and establishes a feedback mechanism, thereby further accelerating the identification speed of key reliability input vectors.

[0067] 3) This invention can identify the input vector with the highest reliability and the input vector with the lowest reliability in one round of calculation.

[0068] 4) This invention supports the identification of both MIVs and IIVs. Attached Figure Description

[0069] Figure 1 This is a flowchart of the core steps of the present invention;

[0070] Figure 2 This is a detailed flowchart of the present invention;

[0071] Figure 3 This is an example illustration of the present invention on the ISCAS-85 reference circuit C17. Detailed Implementation

[0072] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0073] Example 1

[0074] like Figure 1 As shown, this invention proposes a method for identifying key circuit input vectors based on association rule analysis. The specific process of this embodiment is as follows: Figure 2 As shown, the method includes the following steps:

[0075] S1: Obtain and parse the netlist of the circuit to be identified, and construct a circuit integrity linked list.

[0076] The specific process of step S1 includes:

[0077] S1.1: Read and parse the circuit netlist, extract the basic gate information of the circuit, and construct a circuit integrity linked list Lc to store the basic gate information;

[0078] S1.2: Based on the integrity linked list Lc, identify all original input terminals and basic gates in the circuit;

[0079] S1.3: The number of original input terminals PI and the number of basic gates Ng in the statistical circuit;

[0080] S1.4: Initialize the fault probability pg of the basic gate and the total number N of the initial input vectors according to actual needs.

[0081] S2: Determine the circuit type based on the circuit integrity list, construct an initial input vector set based on the circuit type and the basic parameters of the circuit integrity list, and use each initial input vector in the initial input vector set as the input signal of the circuit.

[0082] The specific process of step S2 includes:

[0083] S2.1: Based on the integrity linked list Lc, determine the circuit type. If it is a combinational logic circuit, proceed to step S2.2; otherwise, skip to step S2.3.

[0084] S2.2: Based on the original number of circuit inputs PI and the total number of initial input vectors N, randomly generate an initial input vector zero matrix Initial_inputs of size PI×N, and execute step S2.5;

[0085] S2.3: Based on the integrity linked list Lc, count the number of flip-flops FI in the sequential circuit;

[0086] S2.4: Based on the original number of circuit inputs PI, the number of flip-flops FI, and the total number of initial input vectors N, randomly generate an initial input vector zero matrix Initial_inputs of size (PI+FI)×N;

[0087] S2.5: Initialize the counting parameter i = 1;

[0088] S2.6: If i≤N, then proceed to step S2.7; otherwise, skip to step S2.10.

[0089] S2.7: Based on the original number of circuit inputs PI, a Boolean vector input of size PI×1 is randomly generated. Each bit of the vector consists of "0" or "1" to represent different input signals.

[0090] S2.8: Let Initial_inputs(i,:)=input;

[0091] S2.9: Execute i = i + 1, then return to step S2.6;

[0092] S2.10: Returns the initial input vector set Initial_inputs.

[0093] S3: Based on the circuit's input signal, calculate the overall reliability value of the circuit under each initial input vector, obtain and return the initial key input vector based on the overall reliability value of the circuit.

[0094] The specific process of step S3 includes:

[0095] S3.1: Based on the fault probability pg of the basic gate and the total number of initial input vectors N, perform N random fault injections;

[0096] S3.2: Based on the initial input vector set Initial_inputs and the failure probability pg of each basic gate, the overall reliability value R of the circuit under each input vector is calculated using a continuous convex approximation method. i , i = 1, 2, ..., N;

[0097] S3.3: Sort Initial_inputs according to the size of R and return the first n initial key input vectors pre_RCIV with the largest and / or smallest reliable values;

[0098] S3.4: Based on pre_RCIV, calculate the probability p of each original input signal taking "1" in the initial key input vector.

[0099] S4: Based on the initial key input vector, the association rules of the original input terminals of the circuit to be identified are analyzed through the association rule analysis model.

[0100] The specific process of step S4 includes:

[0101] S4.1: Initialize the minimum support (MST) and minimum confidence (MCT);

[0102] S4.2: Set the first counting parameter k = 1, and initially assign values ​​to the threshold parameters ε and δ;

[0103] S4.3: Based on pre_RCIV, identify all candidate k-itemsets Cand_top_k;

[0104] S4.4: If Cand_top_k is an empty set, then execute step S4.19; otherwise, execute step S4.5.

[0105] S4.5: Set the second counting parameter i = 1;

[0106] S4.6: Calculate the i-th array Cand_top_k of the candidate k-itemsset. i support level (Cand_top_k) i );

[0107] S4.7: If sup(Cand_top_k i If the value is greater than or equal to MST, then proceed to step S4.8; otherwise, proceed to step S4.9.

[0108] S4.8: Cand_top_k i Add to the frequent k-itemset Fre_top_k;

[0109] S4.9: Let i = i + 1;

[0110] S4.10: If Cand_top_k i If it is an empty set, proceed to step S4.7; otherwise, proceed to step S4.11.

[0111] S4.11: Set the third counting parameter j = 1;

[0112] S4.12: Calculate the j-th array Fre_top_k of frequent k-itemsets j confidence level conf(Fre_top_k) j );

[0113] S4.13: If conf(Fre_top_k j If the value is greater than or equal to MCT, then proceed to step S4.14; otherwise, proceed to step S4.15.

[0114] S4.14: Set Fre_top_k j Add to the frequent confidence k-item set Fre_conf_k and the association rule set Ara_top;

[0115] S4.15: Let j = j + 1;

[0116] S4.16: If Fre_top_k j If it is an empty set, proceed to step S4.17; otherwise, return to step S4.12.

[0117] S4.17: Combine any two items from Fre_conf_k to form a candidate k+1 itemset;

[0118] S4.18: Let k = k + 1, then return to step S4.4;

[0119] S4.19: If Ara_top is an empty set and MCT>ε, then execute step S4.20; otherwise, execute step S4.21.

[0120] S4.20: Let MST = MST - δ, MCT = MCT - δ, and return to step S4.2;

[0121] S4.21: Returns the association rule set Ara_top.

[0122] S5: Generate new input vector samples based on the association rules of the original input.

[0123] The specific process of step S5 includes:

[0124] S5.1: Maximize and integrate all rules in Ara_top, returning the original input signal "1" associated rule input_1 and "0" associated rule input_0;

[0125] S5.2: Construct m new input vector sets new_iv;

[0126] S5.3: Assign values ​​to new_iv based on input_1 and input_0. The values ​​of random input signals are assigned according to p in S3.4.

[0127] S6: Calculate the reliable value of the new input vector sample, obtain and return the key input vector.

[0128] S6.1: Based on the fault probability pg of the basic gate and the total number of initial input vectors N, perform N random fault injections and return the fault probability pg of each basic gate after the fault injection.

[0129] S6.2: Based on the new input vector set new_iv and the failure probabilities pg of each basic gate, the overall reliability value R of the circuit under each input vector is calculated using a continuous convex approximation method. i , i = 1, 2, ..., m;

[0130] S6.3: Sort new_iv according to the size of R and return the first n initial key input vectors RCIV with the largest and / or smallest reliable values.

[0131] To further illustrate the process and identification results of the method proposed in this invention, this invention uses the C17 circuit as an example to identify its RCIVs. For example... Figure 3 As shown, in stages S1 and S2, the present invention initially generates M different input vectors randomly. Then, a continuous convex approximation model is used to calculate the overall reliability of the circuit when applying these input vectors. Next, all input vectors are sorted by reliability value, and 2n pre_RCIVs are selected from the top and bottom. In stage S3, the best and worst pre_RCIV items are first constructed. Then, based on the association rule analysis model, all candidate k-itemsets and frequent k-itemsets satisfying MST and MCT are progressively identified. At the beginning of stage S4, the identified original input association rules are merged; PI1 and PI2 are associated with the input "1" and have the best reliability. No association rules for the input "0" have been found so far. Similarly, for the worst input vector, PI3, PI4, and PI5 are "1", and PI1 is "0". In stages S5 and S6, the present invention regenerates N input vectors using the above criteria. With the input values ​​determined by the present invention, the number of input vector simulations required to identify RCIVs is reduced. For example, the identification of WRIVs in the example only requires simulation of 2 input vectors. Then, by sorting all the input vectors, we can identify n BRIVs and n WRIVs. Finally, we obtain the RCIV and reliability boundary of C17.

[0132] Therefore, compared with traditional methods, this invention provides two RCIV recognition techniques for combinational and sequential circuits, and simultaneously supports the recognition of the most reliable input vector and the least reliable input vector. By adopting an association rule analysis model to identify the associated original inputs of the circuit, the accuracy is improved while reducing the complexity of RCIV recognition. By establishing a feedback mechanism, new input vector samples are generated based on the frequency of the identified associated original inputs and the unidentified inputs, thereby further accelerating the RCIV recognition speed.

[0133] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0135] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0136] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0137] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0138] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0139] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for identifying key circuit input vectors based on association rule analysis, characterized in that, Includes the following steps: S1: Obtain and parse the netlist of the circuit to be identified, and construct a circuit integrity linked list; S2: Determine the circuit type based on the circuit integrity linked list, construct an initial input vector set based on the circuit type and the basic parameters of the circuit integrity linked list, and use each initial input vector in the initial input vector set as the input signal of the circuit; S3: Based on the circuit's input signal, calculate the overall reliability value of the circuit under each initial input vector, obtain and return the initial key input vector based on the overall reliability value of the circuit; S4: Based on the initial key input vector, the association rules of the original input terminals of the circuit to be identified are analyzed through the association rule analysis model; S5: Generate new input vector samples based on the association rules of the original input. S6: Calculate the reliable value of the new input vector sample, obtain and return the key input vector.

2. The method for identifying key circuit input vectors based on association rule analysis according to claim 1, characterized in that, Step S1 includes: S1.1: Read and parse the circuit netlist, extract the basic gate information of the circuit, and construct a circuit integrity linked list to store the basic gate information; S1.2: Identify all original input terminals and basic gates in the circuit based on the circuit integrity linked list; S1.3: The number of original input terminals and the number of basic gates in the statistical circuit; S1.4: Initialize the fault probability of the basic gates and the total number of initial input vectors.

3. The method for identifying key circuit input vectors based on association rule analysis according to claim 2, characterized in that, Step S2 includes: S2.1: Based on the circuit integrity linked list, determine the circuit type. If it is a combinational logic circuit, proceed to step S2.2; otherwise, skip to step S2.

3. S2.2: Based on the original number of input terminals and the total number of initial input vectors, randomly generate an initial input vector zero matrix and execute step S2.5; S2.3: Based on the integrity linked list, count the number of flip-flops in the sequential circuit; S2.4: Based on the number of original input terminals, the number of flip-flops, and the total number of initial input vectors, randomly generate an initial input vector zero matrix; S2.5: Randomly generate a Boolean vector whose every bit consists of "0" or "1". The number of Boolean vectors is equal to the number of input vectors, and the size of the Boolean vectors is the same as the number of rows of the initial input vector zero matrix. S2.6: Assign the Boolean vector to the zero vector matrix; S2.7: Output the set of input vectors obtained by assigning values ​​to the vector zero matrix.

4. The method for identifying key circuit input vectors based on association rule analysis according to claim 3, characterized in that, Step S3 includes: S3.1: Based on the fault probability of the basic gate and the total number of initial input vectors, perform random fault injection the same number of times as the total number of initial input vectors; S3.2: Calculate the overall reliability value of the circuit under each input vector based on the initial input vector set; S3.3: Sort the input vector set according to the overall reliability value of the circuit under each input vector, and obtain the initial key input vector based on the sorting result; S3.4: Based on the initial key input vector, calculate the probability that each original input signal of the initial key input vector is "1".

5. The method for identifying key circuit input vectors based on association rule analysis according to claim 4, characterized in that, Step S4 includes: S4.1: Initialize minimum support and minimum confidence; S4.2: Initialize the first counting parameter k to 1, and set the first assignment threshold parameter and the second assignment threshold parameter; S4.3: Identify candidate k-itemsets based on the initial key input vector; S4.4: If the candidate k-item set is empty, proceed to step S4.19; otherwise, proceed to step S4.

5. S4.5: Initialize the second counter parameter i to 1; S4.6: Calculate the support of the i-th array of the candidate k-itemsets; S4.7: If the support of the i-th array of the candidate k-items set is greater than or equal to the minimum support, then proceed to step S4.8; otherwise, proceed to step S4.

9. S4.8: Add the i-th array element of the candidate k-itemsset to the frequent k-itemsset; S4.9: Increment the second counting parameter i by 1; S4.10: If the i-th array of the candidate k-items set is empty, then execute step S4.7; otherwise, execute step S4.

11. S4.11: Initialize the third counting parameter j to be 1; S4.12: Calculate the confidence score of the j-th array of frequent k-itemsets; S4.13: If the confidence of the j-th array of the frequent k-itemset is greater than or equal to the minimum confidence, then proceed to step S4.14; otherwise, proceed to step S4.

15. S4.14: Add the j-th array of the frequent k-itemsets to the frequent confidence k-itemsets and the association rule set; S4.15: Increment the third counting parameter j by 1; S4.16: If the j-th array of the frequent k-itemsets is empty, then execute step S4.17; otherwise, return to step S4.

12. S4.17: Combine any two items from the frequent confidence k-item set to form a candidate k+1 itemset; S4.18: Increment the first counting parameter k by 1, and return to step S4.4; S4.19: If the association rule set is empty and the minimum confidence level is greater than the first assignment threshold parameter, then execute step S4.20; otherwise, execute step S4.

21. S4.20: Subtract the second assignment threshold parameter from the minimum support, subtract the second assignment threshold parameter from the minimum confidence, and return to step S4.2; S4.21: Returns the set of association rules.

6. The method for identifying key circuit input vectors based on association rule analysis according to claim 5, characterized in that, Step S5 includes: S5.1: Maximize and integrate all rules in the association rule set, returning the original input signal "1" association rule and "0" association rule; S5.2: Construct multiple new input vector sets; S5.3: Assign values ​​to the new input vector set based on the "1" association rule and the "0" association rule. The values ​​of the random input signals are assigned according to the probability of each original input signal taking "1" in the initial key input vector of S3.

4.

7. The method for identifying key circuit input vectors based on association rule analysis according to claim 6, characterized in that, Step S6 includes: S6.1: Based on the fault probability of the basic gate and the total number of initial input vectors, perform the same number of random fault injections; S6.2: Calculate the overall reliability value of the circuit under each new input vector based on the new input vector set; S6.3: Sort the new input vector set according to the overall reliability value of the circuit under each new input vector, and return the key input vector according to the sorting result.

8. The method for identifying key circuit input vectors based on association rule analysis according to claim 1, characterized in that, The initial key input vector includes the input vector with the largest reliability value and the input vector with the smallest reliability value. The key input vector also includes the new input vector with the largest reliability value and the new input vector with the smallest reliability value.

9. The method for identifying key circuit input vectors based on association rule analysis according to claim 3, characterized in that, Step S2.2 The number of rows in the zero matrix of the input vector is the number of original input terminals, and the number of columns is the number of input vectors; Step S2.4 The number of rows in the zero matrix of the input vector is the sum of the number of original input terminals and the number of trigger input terminals, and the number of columns is the number of input vectors.

10. A method for identifying key circuit input vectors based on association rule analysis according to claim 7, characterized in that, The reliability value is calculated using a continuous convex approximation algorithm.

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