A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes: a first driving circuit, which includes a first shift register; the first shift register includes: a first control circuit, a second control circuit, a first output circuit, and a second output circuit; the control terminal of the first control circuit is connected to a first reset terminal, and its input terminal is connected to a first voltage terminal; the first output terminal of the first control circuit and the first output terminal of the second control circuit are both connected to the control terminal of the first output circuit, and the second output terminals of the first control circuit and the second control circuit are both connected to the control terminal of the second output circuit; in the output-off mode, the first control circuit is turned on, and the voltage signal provided by the first voltage terminal controls both the first and second output circuits to turn off. In this invention, the first and second output circuits of the first shift register can be controlled to turn off simultaneously, which can improve the stability of the output signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work.

[0003] The main component of an electronic device that enables display functionality is the display panel. The display panel uses a driving circuit to control the pixel array to display the image. In related technologies, the driving circuit typically includes multiple cascaded shift registers.

[0004] Common display panel manufacturing processes typically involve creating shift registers on both the left and right sides of the display panel, creating a dual-sided drive. However, when single-sided drive is required, the shift register on the stable output side can be interfered with by the shift register on the other side, affecting the stability of the output signal and consequently the display quality. Summary of the Invention

[0005] The present invention provides a display panel and display device to solve the problem of unstable output signal of existing shift registers.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a first driving circuit, the first driving circuit including a first shift register;

[0007] The first shift register includes: a first control circuit, a second control circuit, a first output circuit, and a second output circuit;

[0008] The control terminal of the first control circuit is connected to the first reset terminal, and the input terminal of the first control circuit is connected to the first voltage terminal;

[0009] The first input terminal of the second control circuit is connected to the first clock terminal, the second input terminal of the second control circuit is connected to the second clock terminal, and the third input terminal of the second control circuit is connected to the shift input terminal.

[0010] The first output terminal of the first control circuit and the first output terminal of the second control circuit are both connected to the control terminal of the first output circuit, and the second output terminal of the first control circuit and the second output terminal of the second control circuit are both connected to the control terminal of the second output circuit.

[0011] The output terminals of both the first and second output circuits are connected to the shift output terminal;

[0012] The first shift register includes a normal output mode and an output-off mode;

[0013] In the normal output mode, the first control circuit is turned off, and the second control circuit controls the first output circuit or the second output circuit to output.

[0014] In the output shutdown mode, the first control circuit is turned on, and the voltage signal provided by the first voltage terminal controls both the first output circuit and the second output circuit to be turned off.

[0015] According to another aspect of the present invention, a display device is provided, including the aforementioned display panel.

[0016] In this invention, the first shift register includes a first control circuit, a second control circuit, a first output circuit, and a second output circuit. In normal output mode, the first control circuit is turned off, and the second control circuit controls either the first or second output circuit to output, thus realizing the normal output function of the first shift register. In output-off mode, the first control circuit is turned on, and the voltage signal provided by the first voltage terminal controls both the first and second output circuits to turn off, so the shift output terminal of the first shift register no longer outputs a signal. In this invention, the first shift register can be turned on or off, and the first and second output circuits can be turned off simultaneously. Therefore, while ensuring the normal operation of the display panel, the single-sided and double-sided driving modes of the display panel can be flexibly switched. In single-sided driving, the first shift register on the stable output side will not be interfered with by the first shift register on the other side that has been turned off, thus improving the stability of the output signal. In addition, a damaged first shift register can be turned off, which can avoid the problem of the damaged first shift register affecting the stability of the output signal and improve the display effect.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a first shift register provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of another first shift register provided in an embodiment of the present invention;

[0023] Figure 5 yes Figure 2 A timing diagram of the first shift register shown;

[0024] Figure 6 This is a schematic diagram of yet another first shift register provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a first shift register provided in an embodiment of the present invention. Figure 1 and Figure 2As shown, the display panel includes: a first driving circuit 10, which includes a first shift register 11; the first shift register 11 includes: a first control circuit 12, a second control circuit 13, a first output circuit 14, and a second output circuit 15; the control terminal of the first control circuit 12 is connected to the first reset terminal RST, and the input terminal of the first control circuit 12 is connected to the first voltage terminal Va; the first input terminal of the second control circuit 13 is connected to the first clock terminal CK1, the second input terminal of the second control circuit 13 is connected to the second clock terminal CK2, and the third input terminal of the second control circuit 13 is connected to the shift input terminal IN; the first output terminal of the first control circuit 12 and the first output terminal of the second control circuit 13 are also included. Both the first output circuit 14 and the second output circuit 13 are connected to the control terminal N1 of the first output circuit 14. The second output terminal of the first control circuit 12 and the second output terminal of the second control circuit 13 are both connected to the control terminal N2 of the second output circuit 15. The output terminals of the first output circuit 14 and the second output circuit 15 are both connected to the shift output terminal OUT. The first shift register 11 includes a normal output mode and a shutdown output mode. In the normal output mode, the first control circuit 12 is turned off, and the second control circuit 13 controls the first output circuit 14 or the second output circuit 15 to output. In the shutdown output mode, the first control circuit 12 is turned on, and the voltage signal provided by the first voltage terminal Va controls the first output circuit 14 and the second output circuit 15 to be turned off.

[0029] In this embodiment, the display panel includes a display area 30 and a non-display area 31. The display area 30 is used for display. The display area 30 includes a plurality of pixels 32 arranged in an array, but the pixel arrangement in the display panel is not limited to an array arrangement and can also be other pixel arrangements, which will not be described in detail here.

[0030] The non-display area 31 of the display panel is equipped with peripheral circuitry and other circuit structures to drive the pixels 32 in the display area 30 for display. The non-display area 31 includes a first driving circuit 10, which provides driving signals to multiple rows of pixels 32 in the display area 30 to drive the display area 30 for display. The first driving circuit 10 includes a first shift register 11, wherein the shift output terminal of the first shift register 11 provides a corresponding driving signal to a row of pixels 32 via a signal line.

[0031] In this embodiment, the first shift register 11 includes a first control circuit 12. The control terminal of the first control circuit 12 is connected to the first reset terminal RST, the input terminal of the first control circuit 12 is connected to the first voltage terminal Va, the first output terminal of the first control circuit 12 is connected to the control terminal N1 of the first output circuit 14, and the second output terminal of the first control circuit 12 is connected to the control terminal N2 of the second output circuit 15. The first reset signal provided by the first reset terminal RST is a voltage signal with alternating high and low levels, which can control the on / off state of the first control circuit 12. If the first reset signal provided by the first reset terminal RST turns on the first control circuit 12, the voltage signal provided by the first voltage terminal Va is written to the control terminal N1 of the first output circuit 14 and simultaneously written to the control terminal N2 of the second output circuit 15, controlling the on / off state of both the first and second output circuits.

[0032] The first shift register 11 includes a second control circuit 13. The first input terminal of the second control circuit 13 is connected to the first clock terminal CK1, the second input terminal is connected to the second clock terminal CK2, the third input terminal is connected to the shift input terminal IN, the first output terminal is connected to the control terminal N1 of the first output circuit 14, and the second output terminal is connected to the control terminal N2 of the second output circuit 15. When the first shift register 11 is operating normally, the first clock terminal CK1 provides a first clock signal with alternating high and low levels, and the second clock terminal CK2 provides a second clock signal with alternating high and low levels. The first clock signal is different from the second clock signal. The third input terminal of the second control circuit 13 is connected to the shift input terminal IN. The shift input terminal IN of this stage of the first shift register 11 is connected to the shift output terminal of the previous stage's first shift register. For the first stage of the first shift register 11, the signal at its shift output terminal is transmitted not only to one row of pixels 32 in the display area 30, but also to the shift input terminal IN of the cascaded next-stage first shift register 11. The second control circuit 13 responds to the signals of the first clock terminal CK1, the second clock terminal CK2, and the shift input terminal IN, thereby controlling the on / off state of the first output circuit 14 and the on / off state of the second output circuit 15.

[0033] The first shift register 11 includes a first output circuit 14 and a second output circuit 15. The first output terminal of the first control circuit 12 and the first output terminal of the second control circuit 13 are both connected to the control terminal N1 of the first output circuit 14, and the second output terminals of the first control circuit 12 and the second control circuit 13 are both connected to the control terminal N2 of the second output circuit 15. The output terminals of the first output circuit 14 and the second output circuit 15 are both connected to the shift output terminal OUT. When the first control circuit 12 is off, the second control circuit 13 controls the on / off state of the first output circuit 14 and the second output circuit 15. When the first control circuit 12 is on, the first control circuit 12 controls the on / off state of the first output circuit 14 and the second output circuit 15.

[0034] Specifically, the first output circuit 14 is connected between the first power signal terminal VG1 and the shift output terminal OUT. If the first output circuit 14 is switched to the on state, the voltage signal provided by the first power signal terminal VG1 is written to the shift output terminal OUT; if the first output circuit 14 is switched to the off state, the voltage signal provided by the first power signal terminal VG1 cannot be written to the shift output terminal OUT. The second output circuit 15 is connected between the second power signal terminal VG2 and the shift output terminal OUT. If the second output circuit 15 is switched to the on state, the voltage signal provided by the second power signal terminal VG2 is written to the shift output terminal OUT; if the second output circuit 15 is switched to the off state, the voltage signal provided by the second power signal terminal VG2 cannot be written to the shift output terminal OUT. It can be understood that the voltage signal provided by the first power signal terminal VG1 is different from the voltage signal provided by the second power signal terminal VG2. Normally, of the first power signal terminal VG1 and the second power signal terminal VG2, one provides a stable high voltage, and the other provides a stable low voltage. Based on the circuit structure of the first shift register 11, the magnitude of the voltage signal provided by the first power supply signal terminal VG1 and the magnitude of the voltage signal provided by the second power supply signal terminal VG2 are reasonably designed.

[0035] The first shift register 11 includes a normal output mode and a shutdown output mode.

[0036] In normal output mode, the first reset signal provided by the first reset terminal RST controls the first control circuit 12 to turn off. Then, the second control circuit 13 controls the on / off states of the first output circuit 14 and the second output circuit 15. Specifically, if the second control circuit 13 controls the first output circuit 14 to turn on and the second output circuit 15 to turn off, the signal transmitted by the first output circuit 14 is written to the shift output terminal OUT, achieving normal output of the first shift register 11; or, if the second control circuit 13 controls the first output circuit 14 to turn off and the second output circuit 15 to turn on, the signal transmitted by the second output circuit 15 is written to the shift output terminal OUT, achieving normal output of the first shift register 11. This means that the first shift register 11 is on and performs normal output operation.

[0037] In the output-off mode, the first reset signal provided by the first reset terminal RST controls the first control circuit 12 to turn on. The first control circuit 12 then controls the on / off state of the first output circuit 14 and the second output circuit 15. Specifically, the voltage signal provided by the first voltage terminal Va controls both the first output circuit 14 and the second output circuit 15 to turn off. As a result, the shift output terminal OUT of the first shift register 11 is in a floating state and no longer outputs signals, meaning that the first shift register 11 is turned off and stops working.

[0038] As described above, the first shift register 11 can be turned on or off. When the display panel has a dual-side drive mode, by controlling the first shift register 11 to turn it on or off, the drive mode of the display panel can be flexibly switched between dual-side drive mode and single-side drive mode. Furthermore, in single-side drive mode, the first shift register 11 on the stable output side will not be interfered with by the first shift register 11 on the other side, which is already turned off, thus improving the stability of the output signal. Additionally, when one side of the first shift register 11 is damaged, the damaged first shift register 11 can be turned off. In this way, the damaged first shift register will not affect the stability of the output signal, improving the display effect.

[0039] In this invention, the first shift register includes a first control circuit, a second control circuit, a first output circuit, and a second output circuit. In normal output mode, the first control circuit is turned off, and the second control circuit controls either the first or second output circuit to output, thus realizing the normal output function of the first shift register. In output-off mode, the first control circuit is turned on, and the voltage signal provided by the first voltage terminal controls both the first and second output circuits to turn off, so the shift output terminal of the first shift register no longer outputs a signal. In this invention, the first shift register can be turned on or off, and the first and second output circuits can be turned off simultaneously. Therefore, while ensuring the normal operation of the display panel, the single-sided and double-sided driving modes of the display panel can be flexibly switched. In single-sided driving, the first shift register on the stable output side will not be interfered with by the first shift register on the other side that has been turned off, thus improving the stability of the output signal. In addition, a damaged first shift register can be turned off, which can avoid the problem of the damaged first shift register affecting the stability of the output signal and improve the display effect.

[0040] The above is the core idea of ​​this invention. To make the above-mentioned objectives, features, and advantages of this invention more apparent and understandable, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0041] The optional display panel further includes: multiple first scan lines; a first driving circuit including multiple first driving units and multiple second driving units, wherein the first driving unit is electrically connected to a first end of the first scan line, and the second driving unit is electrically connected to a second end of the first scan line; the first driving unit includes a first shift register, and the second driving unit includes a first shift register. The optional first driving circuit can operate in a single-sided driving mode and a double-sided driving mode; in the single-sided driving mode, the first control circuit in the first driving unit is turned on and the first control circuit in the second driving unit is turned off, or the first control circuit in the first driving unit is turned off and the first control circuit in the second driving unit is turned on; in the double-sided driving mode, the first control circuit in the first driving unit is turned off, and the first control circuit in the second driving unit is turned off.

[0042] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 3As shown, the display panel includes multiple first scan lines 33. The first driving circuit 10 includes multiple first driving units 10a located at the first end (left side of the figure) of the first scan line 33, and the first driving circuit 10 also includes multiple second driving units 10b located at the second end (right side of the figure) of the first scan line 33.

[0043] A first scan line 33 corresponds to a first driving unit 10a and also to a second driving unit 10b. Specifically, the first end of the first scan line 33 is electrically connected to the corresponding first driving unit 10a, and the second end of the first scan line 33 is electrically connected to the corresponding second driving unit 10b. The first scan line 33 connects to at least one row of pixels 32, and the first driving circuit 10 provides the required scanning signal to the pixels 33 through the first scan line 33 to drive the pixels 32 for display.

[0044] The first driving unit 10a includes a first shift register. Multiple first driving units 10a in the first driving circuit 10 are cascaded and electrically connected, that is, the first shift registers in multiple first driving units 10a are cascaded and electrically connected. The second driving unit 10b includes a first shift register. Multiple second driving units 10b in the first driving circuit 10 are cascaded and electrically connected, that is, the first shift registers in multiple second driving units 10b are cascaded and electrically connected.

[0045] The first driving circuit 10 of the display panel operates in a dual-side driving mode. In dual-side driving mode, for the same first scan line 33, the corresponding first driving unit 10a and second driving unit 10b provide the same scan signal to the first scan line 33. Specifically, the first control circuit of the first shift register in the first driving unit 10a can be turned off, and the first control circuit of the first shift register in the second driving unit 10b can also be turned off. Based on this, the second control circuit of the first shift register in the first driving unit 10a controls the first output circuit and the second output circuit to output, and the first shift register in the first driving unit 10a normally provides a scan signal to the first scan line 33. Similarly, the second control circuit of the first shift register in the second driving unit 10b controls the first output circuit and the second output circuit to output, and the first shift register in the second driving unit 10b normally provides a scan signal to the first scan line 33. It can be understood that in dual-side driving mode, the corresponding first driving unit 10a and second driving unit 10b provide the same scan signal to the same first scan line 33.

[0046] The first driving circuit 10 of the display panel also includes a single-sided driving mode. In the first single-sided driving mode, the first driving unit 10a drives the first scan line 33; that is, for any given first scan line 33, the corresponding first driving unit 10a provides a scan signal to that first scan line 33. In the second single-sided driving mode, the second driving unit 10b drives the first scan line 33; that is, for any given first scan line 33, the corresponding second driving unit 10b provides a scan signal to that first scan line 33.

[0047] In the first single-sided driving mode, the first control circuit of the first shift register in the first driving unit 10a can be turned off, and the first control circuit of the first shift register in the second driving unit 10b can be turned on. Based on this, the first shift register in the second driving unit 10b stops working. Meanwhile, the second control circuit of the first shift register in the first driving unit 10a controls the first and second output circuits to output, and the first shift register in the first driving unit 10a normally provides a scanning signal to the first scan line 33. Thus, the first driving unit 10a in the first driving circuit 10 drives the first scan line 33.

[0048] In the second single-sided driving mode, the first control circuit of the first shift register in the first driving unit 10a can be turned on, and the first control circuit of the first shift register in the second driving unit 10b can be turned off. Based on this, the first shift register in the first driving unit 10a stops working. Meanwhile, the second control circuit of the first shift register in the second driving unit 10b controls the first and second output circuits to output, and the first shift register in the second driving unit 10b normally provides a scanning signal to the first scan line 33. Thus, the second driving unit 10b in the first driving circuit 10 drives the first scan line 33.

[0049] As described above, the first shift register can be controlled to operate normally or stop operating, thereby enabling flexible switching between dual-sided and single-sided driving modes of the display panel. Furthermore, when the first shift register is turned off, both the first and second output circuits can be simultaneously shut down by the first control circuit. Therefore, the turned-off first shift register will not interfere with the stable output of the other first shift register. Moreover, if one side of the first shift register is damaged, the signal output of the other first shift register can be maintained by turning off that side's first shift register; the damaged first shift register will not interfere with the operation of the normal first shift register. This improves the stability of the output signal of the first driving circuit, thereby enhancing the display effect.

[0050] It is understood that the display panel also includes a driver chip 40, which provides corresponding clock signals, power signals and reset signals to each of the first shift registers in the first driver circuit 10.

[0051] Specifically, in combination Figure 2 and Figure 3 As shown, for the first shift register 11 located on the side of the first end of the first scan line 33, the driver chip 40 provides a first clock signal to the first clock terminal CK1 of each first shift register 11 through a first clock signal line, and provides a second clock signal to the second clock terminal CK2 of each first shift register 11 through a second clock signal line. The driver chip 40 provides a first power signal (e.g., VGH) to the first power signal terminal VG1 of each first shift register 11 through a first power signal line, and provides a second power signal (e.g., VGL) to the second power signal terminal VG2 of each first shift register 11 through a second power signal line. If the voltage signal of the first voltage terminal Va is the same as the first power signal, the driver chip 40 also provides a first voltage signal (e.g., VGH) to the first voltage terminal Va of each first shift register 11 through the first power signal line. The driver chip 40 also provides a first reset signal to the first reset terminal RST of each first shift register 11 through a first reset signal line RSTa.

[0052] Similarly, for the first shift register 11 located on the side where the second end of the first scan line 33 is located, the driver chip 40 provides corresponding signals to the first clock terminal CK1, the second clock terminal CK2, the first power signal terminal VG1, the second power signal terminal VG2, the first voltage terminal Va and the first reset terminal RST of the first shift register 11 through another set of independent first clock signal lines, second clock signal lines, first power signal lines, second power signal lines and first reset signal lines RSTb.

[0053] Assuming the first reset terminal RST provides a high voltage, it can control the first control circuit 12 to turn off; if the first reset terminal RST provides a low voltage, it can control the first control circuit 12 to turn on.

[0054] Based on this, the driver chip 40 provides high voltage to the first reset signal line RSTa and the first reset signal line RSTb simultaneously, which can turn off the first control circuit 12 of each first shift register in the first driver circuit 10, so that the first driver circuit 10 of the display panel enters the dual-side drive mode.

[0055] The driver chip 40 provides a high voltage to the first reset signal line RSTa and a low voltage to the first reset signal line RSTb, which can control the first control circuit 12 of the first shift register in each first drive unit 10a to turn off and control the first control circuit 12 of the first shift register in each second drive unit 10b to turn on, so that the second drive unit 10b stops working. Then the first drive circuit 10 of the display panel enters the first single-sided drive mode, in which each first drive unit 10a drives the first scan line 33.

[0056] The driver chip 40 provides a low voltage to the first reset signal line RSTa and a high voltage to the first reset signal line RSTb, which can control the first control circuit 12 of the first shift register in each first drive unit 10a to turn on and control the first control circuit 12 of the first shift register in each second drive unit 10b to turn off, so that the first drive unit 10a stops working. Then the first drive circuit 10 of the display panel enters the second single-sided drive mode, in which each second drive unit 10b drives the first scan line 33.

[0057] It should be noted that the first driving circuit 10 can serve as a light-emitting control circuit, used to provide the light-emitting control signal EMIT to the pixel 32 in the display panel. The first driving circuit 10 can also serve as a data writing control circuit, used to control whether the pixel 33 in the display panel performs data signal writing, etc., without specifically limiting the function of the first driving circuit.

[0058] Figure 4 This is a schematic diagram of another first shift register provided in an embodiment of the present invention. For example... Figure 4 As shown, the optional first control circuit 12 includes: a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the first reset terminal RST, and the first transistor M1 is connected between the first voltage terminal Va and the control terminal N1 of the first output circuit 14; the gate of the second transistor M2 is connected to the first reset terminal RST, and the second transistor M2 is connected between the first voltage terminal Va and the control terminal N2 of the second output circuit 15.

[0059] In this embodiment, the gates of the first transistor M1 and the second transistor M2 are connected to the first reset terminal RST. The first reset signal provided by the first reset terminal RST is used to control the first transistor M1 and the second transistor M2 to be turned on or off simultaneously. That is, when the first shift register is turned off, the first output circuit 14 and the second output circuit 15 can be turned off simultaneously, and the turned-off first shift register will not interfere with the first shift register with stable output on the other side.

[0060] The input terminal of the first transistor M1 is connected to the first voltage terminal Va, and the output terminal is connected to the control terminal N1 of the first output circuit 14. If the first transistor M1 is turned on, the voltage signal provided by the first voltage terminal Va is written to the control terminal N1 of the first output circuit 14. If the first transistor M1 is turned off, the voltage signal provided by the first voltage terminal Va cannot be written to the control terminal N1 of the first output circuit 14.

[0061] The input terminal of the second transistor M2 is connected to the first voltage terminal Va, and the output terminal is connected to the control terminal N2 of the second output circuit 15. If the second transistor M2 is turned on, the voltage signal provided by the first voltage terminal Va is written to the control terminal N2 of the second output circuit 15. If the second transistor M2 is turned off, the voltage signal provided by the first voltage terminal Va cannot be written to the control terminal N2 of the second output circuit 15.

[0062] Optionally, both the first transistor M1 and the second transistor M2 are P-type transistors; in normal output mode, the first reset terminal RST provides a high voltage; in output-off mode, the first reset terminal RST provides a low voltage.

[0063] Specifically, in normal output mode, the first reset signal provided by the first reset terminal RST needs to control the first control circuit 12 to turn off. If the first transistor M1 and the second transistor M2 are both P-type transistors, then in normal output mode, the first reset signal provided by the first reset terminal RST is a high voltage that can turn off the P-type transistors, thereby turning off both the first transistor M1 and the second transistor M2. Then the first control circuit 12 switches to the off state, and the second control circuit 13 controls the on / off state of the first output circuit 14 and the second output circuit 15.

[0064] In the off-output mode, the first reset signal provided by the first reset terminal RST needs to control the first control circuit 12 to turn on. If the first transistor M1 and the second transistor M2 are both P-type transistors, then in the off-output mode, the first reset signal provided by the first reset terminal RST is a low voltage that enables the P-type transistors to turn on, thereby turning on both the first transistor M1 and the second transistor M2. Then the first control circuit 12 switches to the on state, and the voltage signal provided by the first voltage terminal Va is written to the control terminal N1 of the first output circuit 14 and the control terminal N2 of the second output circuit 15.

[0065] In other embodiments, both the first transistor and the second transistor may be N-type transistors. In normal output mode, the first reset terminal provides a low voltage; in output-off mode, the first reset terminal provides a high voltage. In normal output mode, the low voltage at the first reset terminal turns off both the first and second transistors, switching the first control circuit to an off state, and the second control circuit controls the on / off states of the first and second output circuits. In output-off mode, the high voltage at the first reset terminal turns on both the first and second transistors, switching the first control circuit to an on state, and the voltage signal provided by the first voltage terminal is written to the control terminals of the first and second output circuits.

[0066] The optional first output circuit 14 includes: a first capacitor C1 and a third transistor M3; the gate of the third transistor M3 is connected to the control terminal N1 of the first output circuit 14, and the third transistor M3 is connected between the first power signal terminal VG1 and the shift output terminal OUT; the first capacitor C1 is coupled between the first power signal terminal VG1 and the gate of the third transistor M3.

[0067] In this embodiment, the gate of the third transistor M3 is connected to the control terminal N1 of the first output circuit 14. The potential change of the control terminal N1 of the first output circuit 14 controls the on / off state of the third transistor M3. Optionally, the third transistor M3 can be a P-type transistor. When the control terminal N1 of the first output circuit 14 is at a high voltage, the third transistor M3 is turned off; when the control terminal N1 of the first output circuit 14 is at a low voltage, the third transistor M3 is turned on. In other embodiments, the third transistor can also be an N-type transistor. If the third transistor M3 is turned on, the voltage signal provided by the first power supply signal terminal VG1 is written to the shift output terminal OUT; if the third transistor M3 is turned off, the transmission path between the first power supply signal terminal VG1 and the shift output terminal OUT is disconnected. The first power supply signal terminal VG1 is also coupled to the potential of the gate of the third transistor M3 through the first capacitor C1.

[0068] The optional second output circuit 15 includes: a second capacitor C2, a fourth transistor M4, and a fifth transistor M5; the gate of the fourth transistor M4 is connected to the second power supply signal terminal VG2, and the fourth transistor M4 is connected between the control terminal N2 of the second output circuit 15 and the gate of the fifth transistor M5; the fifth transistor M5 is connected between the second clock terminal CK2 and the shift output terminal OUT; the second capacitor C2 is coupled between the shift output terminal OUT and the gate of the fifth transistor M5.

[0069] In this embodiment, the gate of the fourth transistor M4 is connected to the second power supply signal terminal VG2, which provides a stable voltage signal. Specifically, the voltage signal provided by the second power supply signal terminal VG2 controls the fourth transistor M4 to turn on. The control terminal N2 of the second output circuit 15 is connected to the gate of the fifth transistor M5, and the potential change of the control terminal N2 of the second output circuit 15 controls the on / off state of the fifth transistor M5. The fifth transistor M5 can be a P-type transistor; in this case, a high voltage at the control terminal N2 of the second output circuit 15 turns the fifth transistor M5 off, and a low voltage at the control terminal N2 turns it on. In other embodiments, the fifth transistor can also be an N-type transistor. If the fifth transistor M5 is on, the second clock signal provided by the second clock terminal CK2 is written to the shift output terminal OUT; if the fifth transistor M5 is off, the transmission path between the second clock terminal CK2 and the shift output terminal OUT is disconnected. The second capacitor C2 couples the potential of the gate of the fifth transistor M5 with the potential of the shift output terminal OUT.

[0070] The optional second control circuit 13 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; the gate of the sixth transistor M6 is connected to the first clock terminal CK1, and the sixth transistor M6 is connected between the shift input terminal IN and the gate of the tenth transistor M10; the gate of the seventh transistor M7 is connected to the first clock terminal CK1, and the seventh transistor M7 is connected between the second power supply signal terminal VG2 and the first node N3; the gate of the eighth transistor M8 is connected to the first node N3, and the eighth transistor M8 is connected between the first power supply signal terminal VG1 and the ninth transistor M9; the gate of the ninth transistor M9 is connected to the second clock terminal CK2, and the ninth transistor M9 is connected between the eighth transistor M8 and the control terminal N2 of the second output circuit 15; the tenth transistor M10 is connected between the first clock terminal CK1 and the first node N3. Optionally, the first node N3 is the control terminal N1 of the first output circuit 14; the gate of the tenth transistor M10 is connected to the control terminal N2 of the second output circuit 15.

[0071] In this embodiment, the first clock signal provided by the first clock terminal CK1 controls the on / off state of the sixth transistor M6. If the sixth transistor M6 is turned on, the signal of the shift input terminal IN is written to the control terminal N2 of the second output circuit 15 to control the on / off state of the second output circuit 15, and the signal of the shift input terminal IN is written to the gate of the tenth transistor M10 to control the on / off state of the tenth transistor M10.

[0072] The first clock signal provided by the first clock terminal CK1 also controls the on / off state of the seventh transistor M7. If the seventh transistor M7 is turned on, the voltage signal provided by the second power supply signal terminal VG2 is written to the first node N3 (i.e., the control terminal N1 of the first output circuit 14) to control the on / off state of the first output circuit 14, and the voltage signal provided by the second power supply signal terminal VG2 is also written to the gate of the eighth transistor M8 to control the on / off state of the eighth transistor M8.

[0073] The potential change of the first node N3 controls the on / off state of the eighth transistor M8. If the eighth transistor M8 is turned on, the voltage signal provided by the first power supply signal terminal VG1 is written to one end of the ninth transistor M9.

[0074] The second clock signal provided by the second clock terminal CK2 controls the on / off state of the ninth transistor M9. If the ninth transistor M9 is turned on, current flows through the ninth transistor M9 and adjusts the potential of the gate of the tenth transistor M10 (i.e., the control terminal N2 of the second output circuit 15), thereby controlling the on / off state of the tenth transistor M10 and the on / off state of the second output circuit 15.

[0075] In this embodiment, the first transistor M1 to the tenth transistor M10 may all be P-type transistors. In other embodiments, the first transistor to the tenth transistor may all be N-type transistors; or, the first transistor to the tenth transistor may include at least one N-type transistor and at least one P-type transistor. Specifically, the P-type transistor may be a low-temperature polycrystalline silicon transistor, such as an LTPS-TFT; and / or, the N-type transistor may be a metal-oxide-semiconductor transistor, such as an IGZO-TFT; but it is not limited thereto.

[0076] Optionally, both the third transistor M3 and the fifth transistor M5 can be P-type transistors, and the voltage signal provided at the first voltage terminal Va is a high voltage. In other embodiments, both the third transistor and the fifth transistor can be N-type transistors, and the voltage signal provided at the first voltage terminal is a low voltage. The first shift register has two operating modes: a normal output mode and a shutdown output mode.

[0077] In this embodiment, in the normal output mode, if the first control circuit 12 needs to be turned off, the first reset terminal RST provides a high voltage to control the first transistor M1 and the second transistor M2 to be turned off simultaneously. Based on this, the second control circuit 13 controls the potential of the control terminal N1 of the first output circuit 14 and the potential of the control terminal N2 of the second output circuit 15, so as to turn on the first output circuit 14 or the second output circuit 15, and the first shift register performs normal output.

[0078] In the output-off mode, the first control circuit 12 needs to be turned on. Therefore, the first reset terminal RST provides a low voltage to control the first transistor M1 and the second transistor M2 to turn on simultaneously. Based on this, the voltage signal at the first voltage terminal Va is written to the control terminal N1 of the first output circuit 14 and the control terminal N2 of the second output circuit 15. In the output-off mode, the first output circuit 14 and the second output circuit 15 are simultaneously turned off to stop the first shift register from working. Based on this, the voltage signal at the first voltage terminal Va needs to control both the first output circuit 14 and the second output circuit 15 to turn off. Correspondingly, the voltage signal at the first voltage terminal Va is a high voltage, used to control the third transistor M3 to turn off and the fifth transistor M5 to turn off.

[0079] Optionally, in normal output mode, the first clock terminal CK1 provides a voltage signal that alternates between high and low levels, and the second clock terminal CK2 provides a voltage signal that alternates between high and low levels; in output-off mode, the first clock terminal CK1 provides a fixed voltage signal, and the second clock terminal CK2 provides a fixed voltage signal. Optionally, in output-off mode, the first clock terminal CK1 and the second clock terminal CK2 provide the same fixed voltage signal.

[0080] In this embodiment, in normal output mode, the first clock terminal CK1 provides a voltage signal with alternating high and low levels, and the second clock terminal CK2 provides a voltage signal with alternating high and low levels to ensure the normal operation of the first shift register, and its shift output terminal OUT outputs a signal. Specifically, in normal output mode, the first clock terminal CK1 and the second clock terminal CK2 can provide opposite clock signals, where the clock signal provided by the first clock terminal CK1 is defined as CK, and the clock signal provided by the second clock terminal CK2 is defined as XCK.

[0081] In the output shutdown mode, the first output circuit 14 and the second output circuit 15 are controlled to be shut down. At this time, the first clock terminal CK1 and the second clock terminal CK2 can provide fixed voltage signals, which can reduce the power consumption caused by signal transitions. Specifically, in the output shutdown mode, the first clock terminal CK1 and the second clock terminal CK2 can provide the same fixed voltage signal.

[0082] Figure 5 yes Figure 2 The diagram shows a timing schematic of the first shift register. (Combined with...) Figure 4 and Figure 5As shown, when the first shift register is working normally, i.e., in normal output mode (Ta), the signal received at the shift input IN is a voltage signal with alternating high and low levels. The first clock terminal CK1 provides a voltage signal with alternating high and low levels, the second clock terminal CK2 provides a voltage signal with alternating high and low levels, and the first reset terminal RST provides a high voltage to turn off the first transistor M1 and the second transistor M2. When the first shift register stops working, i.e., in off output mode (Tb), the signal received at the shift input IN is a fixed voltage signal, such as a high voltage. The first clock terminal CK1 provides a fixed voltage signal, such as a high voltage, the second clock terminal CK2 provides a fixed voltage signal, such as a high voltage, and the first reset terminal RST provides a low voltage to turn on the first transistor M1 and the second transistor M2. Here, the high voltage can both be VGH, and the low voltage can both be VGL.

[0083] based on Figure 4 The structure of the first shift register shown can optionally include a first power supply signal terminal VG1 providing a high voltage VGH, a second power supply signal terminal VG2 providing a low voltage VGL, and a first voltage terminal Va providing a high voltage VGH. The first power supply signal terminal VG1 can be multiplexed as the first voltage terminal Va.

[0084] If the signal provided by the first reset terminal RST is a high voltage VGH, then the first transistor M1 and the second transistor M2 are turned off, and the first shift register switches to normal output mode (Ta). In normal output mode, the signal received by the shift input terminal IN undergoes a high-low level transition, the signal provided by the first clock terminal CK1 undergoes a high-low level transition, and the signal provided by the second clock terminal CK2 undergoes a high-low level transition. This controls the on / off state of the third transistor M3 to the tenth transistor M10, so that the high voltage VGH provided by the first power supply signal terminal VG1 is written to the shift output terminal OUT, or the signal provided by the second clock terminal CK2 is written to the shift output terminal OUT.

[0085] If the signal provided by the first reset terminal RST is a low voltage VGL, it controls the first transistor M1 and the second transistor M2 to turn on. At this time, the first shift register switches to the output-off mode (Tb). In the output-off mode, the high voltage VGH provided by the first voltage terminal Va controls the third transistor M3 and the fifth transistor M5 to turn off simultaneously. Then, the shift output terminal OUT does not output a signal. At this time, the shift output terminal OUT is in a floating state, and the first shift register stops working.

[0086] Figure 6 This is a schematic diagram of another first shift register provided in an embodiment of the present invention. Figure 6 and Figure 4 The difference lies in the fact that the structures of the second output circuit 15 and / or the second control circuit 13 are different.

[0087] For the second output circuit 15, such as Figure 6 The optional second output circuit 15 shown includes: a second capacitor C2, a fourth transistor M4, and a fifth transistor M5; the gate of the fourth transistor M4 is connected to the gate of the fifth transistor M5, and the fourth transistor M4 is connected between the first power supply signal terminal VG1 and the control terminal N1 of the first output circuit 14; the gate of the fifth transistor M5 is connected to the control terminal N2 of the second output circuit 15, and the fifth transistor M5 is connected between the second power supply signal terminal VG2 and the shift output terminal OUT; the second capacitor C2 is coupled between the second clock terminal CK2 and the gate of the fifth transistor M5.

[0088] For the second control circuit 13, such as Figure 6 The optional second control circuit 13 further includes: a third capacitor C3; the gate of the tenth transistor M10 is connected to the first power signal terminal VG1 through the third capacitor C3. Optionally, the tenth transistor M10 is a dual-gate transistor. The optional second control circuit 13 also includes: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourth capacitor C4; the gate of the eleventh transistor M11 is connected to the first clock terminal CK1, and the eleventh transistor M11 is connected between the shift input terminal IN and the control terminal N2 of the second output circuit 15; the gate of the twelfth transistor M12 is connected to the first node N3, and the twelfth transistor M12 is connected between the second clock terminal CK2 and the first terminal N4 of the thirteenth transistor M13; the gate of the thirteenth transistor M13 is connected to the second clock terminal CK2, the first terminal N4 of the thirteenth transistor M13 is connected to the first node N3 through the fourth capacitor C4, and the second terminal of the thirteenth transistor M13 is connected to the control terminal N1 of the first output circuit 14.

[0089] In this embodiment, the gates of the fourth transistor M4 and the fifth transistor M5 are both connected to the control terminal N2 of the second output circuit 15. Optionally, the fourth transistor M4 and the fifth transistor M5 can be turned on or off simultaneously.

[0090] Optionally, all of the first transistors M1 to the thirteenth transistor M13 may be P-type transistors. In other embodiments, all of the first transistors to the thirteenth transistor may be N-type transistors; or, the first transistors to the thirteenth transistor may include at least one N-type transistor and at least one P-type transistor.

[0091] In normal output mode, the first reset terminal RST provides a high voltage to control the first transistor M1 and the second transistor M2 to turn off simultaneously. At this time, the second control circuit 13 controls the potential of the control terminal N1 of the first output circuit 14 and the potential of the control terminal N2 of the second output circuit 15, so as to turn on the first output circuit 14 or the second output circuit 15, and the first shift register performs normal output.

[0092] In the output shutdown mode, the first reset terminal RST provides a low voltage to control the first transistor M1 and the second transistor M2 to be turned on simultaneously. At this time, the high voltage signal of the first voltage terminal Va is written to the control terminal N1 of the first output circuit 14 and the control terminal N2 of the second output circuit 15, so that the first output circuit 14 and the second output circuit 15 are turned off simultaneously, and the first shift register stops working.

[0093] Combination Figure 6 and Figure 5 As shown, if the signal provided by the first reset terminal RST is a high voltage VGH, then the first transistor M1 and the second transistor M2 are turned off, and the first shift register switches to normal output mode (Ta). In normal output mode, the signal received by the shift input terminal IN undergoes a high-low level transition, the signal provided by the first clock terminal CK1 undergoes a high-low level transition, and the signal provided by the second clock terminal CK2 undergoes a high-low level transition. This controls the on / off state of the third transistor M3 to the thirteenth transistor M13, so that the high voltage VGH provided by the first power supply signal terminal VG1 is written to the shift output terminal OUT, or the low voltage VGL provided by the second power supply signal terminal VG2 is written to the shift output terminal OUT.

[0094] If the signal provided by the first reset terminal RST is a low voltage VGL, it controls the first transistor M1 and the second transistor M2 to turn on. At this time, the first shift register switches to the output-off mode (Tb). In the output-off mode, the high voltage VGH provided by the first voltage terminal Va controls the third transistor M3 and the fifth transistor M5 to turn off simultaneously. Then, the shift output terminal OUT does not output a signal. At this time, the shift output terminal OUT is in a floating state, and the first shift register stops working.

[0095] It is understood that the structure of the first shift register in this invention is not limited to... Figure 4 and Figure 6 As shown.

[0096] This invention also provides a display device, which includes a display panel as provided in any of the above embodiments. Figure 7 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 7 As shown, the display device 100 includes, but is not limited to, full-screen mobile phones, tablet computers, and digital cameras. Furthermore, the display device 100 can be a liquid crystal display device, an LED display device, an OLED display device, or a flexible display device, and is not limited thereto.

[0097] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0098] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first driving circuit, the first driving circuit including a first shift register; The first shift register includes: a first control circuit, a second control circuit, a first output circuit, and a second output circuit; The control terminal of the first control circuit is connected to the first reset terminal, and the input terminal of the first control circuit is connected to the first voltage terminal; The first input terminal of the second control circuit is connected to the first clock terminal, the second input terminal of the second control circuit is connected to the second clock terminal, and the third input terminal of the second control circuit is connected to the shift input terminal. The first output terminal of the first control circuit and the first output terminal of the second control circuit are both connected to the control terminal of the first output circuit, and the second output terminal of the first control circuit and the second output terminal of the second control circuit are both connected to the control terminal of the second output circuit. The output terminals of both the first and second output circuits are connected to the shift output terminal; The first shift register includes a double-sided output mode and a single-sided output mode; In the dual-output mode, the first control circuit is turned off, and the second control circuit controls the first output circuit or the second output circuit to output. In the single-sided output mode, the first control circuit is turned on, and the voltage signal provided by the first voltage terminal controls both the first output circuit and the second output circuit to be turned off.

2. The display panel according to claim 1, characterized in that, The first control circuit includes: a first transistor and a second transistor; The gate of the first transistor is connected to the first reset terminal, and the first transistor is connected between the first voltage terminal and the control terminal of the first output circuit; The gate of the second transistor is connected to the first reset terminal, and the second transistor is connected between the first voltage terminal and the control terminal of the second output circuit.

3. The display panel according to claim 2, characterized in that, Both the first transistor and the second transistor are N-type transistors; In the dual-output mode, the first reset terminal provides a low voltage; In the single-sided output mode, the first reset terminal is provided with a high voltage.

4. The display panel according to claim 2, characterized in that, Both the first transistor and the second transistor are P-type transistors; In the dual-output mode, the first reset terminal provides a high voltage; In the single-sided output mode, the first reset terminal provides a low voltage.

5. The display panel according to claim 1, characterized in that, In the dual-output mode, the first clock terminal provides a voltage signal that alternates between high and low levels, and the second clock terminal provides a voltage signal that alternates between high and low levels. In the single-sided output mode, the first clock terminal provides a fixed voltage signal, and the second clock terminal provides a fixed voltage signal.

6. The display panel according to claim 5, characterized in that, In the single-sided output mode, the first clock terminal and the second clock terminal provide the same fixed voltage signal.

7. The display panel according to claim 1, characterized in that, The first output circuit includes: a first capacitor and a third transistor; The gate of the third transistor is connected to the control terminal of the first output circuit, and the third transistor is connected between the first power signal terminal and the shift output terminal. The first capacitor is coupled between the first power signal terminal and the gate of the third transistor.

8. The display panel according to claim 7, characterized in that, The second output circuit includes: a second capacitor, a fourth transistor, and a fifth transistor; The gate of the fourth transistor is connected to the second power signal terminal, and the fourth transistor is connected between the control terminal of the second output circuit and the gate of the fifth transistor. The fifth transistor is connected between the second clock terminal and the shift output terminal; The second capacitor is coupled between the shift output terminal and the gate of the fifth transistor.

9. The display panel according to claim 1, characterized in that, The second control circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The gate of the sixth transistor is connected to the first clock terminal, and the sixth transistor is connected between the shift input terminal and the gate of the tenth transistor. The gate of the seventh transistor is connected to the first clock terminal, and the seventh transistor is connected between the second power signal terminal and the first node; The gate of the eighth transistor is connected to the first node, and the eighth transistor is connected between the first power signal terminal and the ninth transistor. The gate of the ninth transistor is connected to the second clock terminal, and the ninth transistor is connected between the eighth transistor and the control terminal of the second output circuit. The tenth transistor is connected between the first clock terminal and the first node.

10. The display panel according to claim 9, characterized in that, The first node is the control terminal of the first output circuit; The gate of the tenth transistor is connected to the control terminal of the second output circuit.

11. The display panel according to claim 7, characterized in that, The second output circuit includes: a second capacitor, a fourth transistor, and a fifth transistor; The gate of the fourth transistor is connected to the gate of the fifth transistor, and the fourth transistor is connected between the first power signal terminal and the control terminal of the first output circuit. The gate of the fifth transistor is connected to the control terminal of the second output circuit, and the fifth transistor is connected between the second power supply signal terminal and the shift output terminal. The second capacitor is coupled between the second clock terminal and the gate of the fifth transistor.

12. The display panel according to claim 8 or 11, characterized in that, Both the third transistor and the fifth transistor are N-type transistors, and the voltage signal provided by the first voltage terminal is a low voltage. Alternatively, both the third and fifth transistors may be P-type transistors, and the voltage signal provided at the first voltage terminal may be a high voltage.

13. The display panel according to claim 9, characterized in that, The second control circuit also includes: a third capacitor; The gate of the tenth transistor is connected to the first power signal terminal through the third capacitor.

14. The display panel according to claim 9, characterized in that, The tenth transistor is a dual-gate transistor.

15. The display panel according to claim 9, characterized in that, The second control circuit also includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourth capacitor; The gate of the eleventh transistor is connected to the first clock terminal, and the eleventh transistor is connected between the shift input terminal and the control terminal of the second output circuit. The gate of the twelfth transistor is connected to the first node, and the twelfth transistor is connected between the second clock terminal and the first terminal of the thirteenth transistor; The gate of the thirteenth transistor is connected to the second clock terminal, the first terminal of the thirteenth transistor is connected to the first node through the fourth capacitor, and the second terminal of the thirteenth transistor is connected to the control terminal of the first output circuit.

16. The display panel according to claim 1, characterized in that, Also includes: Multiple first scan lines; The first driving circuit includes a plurality of first driving units and a plurality of second driving units, wherein the first driving units are electrically connected to the first end of the first scan line, and the second driving units are electrically connected to the second end of the first scan line. The first driving unit includes the first shift register, and the second driving unit includes the first shift register.

17. The display panel according to claim 16, characterized in that, The first driving circuit has two operating modes: single-sided driving mode and double-sided driving mode. In the single-sided drive mode, the first control circuit in the first drive unit is turned on and the first control circuit in the second drive unit is turned off, or the first control circuit in the first drive unit is turned off and the first control circuit in the second drive unit is turned on. In the dual-drive mode, the first control circuit in the first drive unit is turned off, and the first control circuit in the second drive unit is also turned off.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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