Storage device and method of operating the same

Abstract

A memory device is provided. The memory device includes a plurality of passage layers, a plurality of word lines, a plurality of memory layers disposed between the passage layers and the word lines, and a plurality of memory cells defined at a plurality of intersections of the passage layers and the word lines. The memory device is configured to perform a first operation m times and a second operation n times, m being greater than or equal to n. In the first operation, a first electric field is generated at a portion of the memory layers. The plurality of word lines is configured to generate a second electric field at the portion of the memory layers in the second operation, the second electric field having a different electric field direction than the first electric field.

Description

Technical Field

[0001] This disclosure relates to a storage device and a method of operating the same. Background Technology

[0002] To reduce size and weight, increase power density, and improve portability, three-dimensional (3D) vertical memory structures have been developed. However, because the target memory cell shares a charge trapping layer with adjacent cells, lateral charge migration has been observed during various operations of the memory device. As the number of layers in a 3D vertical memory structure increases, lateral charge migration becomes a significant reliability issue due to the proportional reduction in lateral dimensions. For example, the threshold voltage variation caused by lateral charge migration increases with the number of write / erase cycles. Physical separation of the charge trapping layer has been proposed to improve reliability. However, this solution presents technical challenges in terms of fabrication. Summary of the Invention

[0003] This disclosure provides a storage device and a method of operating thereof for suppressing lateral charge migration in order to improve reliability.

[0004] A storage device according to this disclosure includes a plurality of channel layers, a plurality of word lines, a plurality of storage layers disposed between the channel layers and the word lines, and a plurality of storage cells defined at a plurality of intersections of the channel layers and the word lines. The storage device is configured to perform a first operation m times and a second operation n times, where m is greater than or equal to n. In the first operation, a first electric field is generated in a portion of the storage layers. The plurality of word lines are configured to generate a second electric field in that portion of the storage layers in the second operation, the direction of the second electric field being different from the direction of the first electric field.

[0005] An operating method of a storage device according to this disclosure includes performing a first operation m times and performing a second operation n times, where m is greater than or equal to n. The storage device includes a plurality of channel layers, a plurality of word lines, a plurality of storage layers disposed between the channel layers and the word lines, and a plurality of storage cells defined at a plurality of intersections of the channel layers and the word lines. In the first operation, a first electric field is generated in a portion of the storage layer. Furthermore, performing the second operation includes generating a second electric field in that portion of the storage layer using the word lines, wherein the electric field direction of the second electric field is different from the electric field direction of the first electric field.

[0006] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 An exemplary embodiment of the storage device according to this disclosure is shown;

[0008] Figure 2 A flowchart illustrating the operation method of the storage device according to this disclosure is provided.

[0009] Figures 3A-3B An exemplary embodiment of the method of operating a storage device according to the present disclosure is shown;

[0010] Figures 4A to 4C Another exemplary embodiment of the method of operating a storage device according to the present disclosure is shown;

[0011] Figures 5A to 5C This illustrates yet another exemplary embodiment of the method of operating a storage device according to the present disclosure;

[0012] Figure 6 Further exemplary embodiments of the method of operating the storage device according to the present disclosure are shown;

[0013] Figure 7 A test result is shown using the operating method according to this disclosure. Attached image description:

[0015] 100: Storage device;

[0016] 110: substrate;

[0017] 112: Lower conductive layer;

[0018] 120: Stacked;

[0019] 122: Conductive strip;

[0020] 124: Dielectric strip;

[0021] 126: Mask layer;

[0022] 130: Storage layer;

[0023] 132: Barrier layer;

[0024] 134: Charge trapping layer;

[0025] 136: Tunneling layer;

[0026] 140: Channel layer;

[0027] 150: Dielectric post;

[0028] 152: Conductor;

[0029] 154: Plug;

[0030] A: Partial;

[0031] B: Arrow;

[0032] M: Storage unit;

[0033] S1, S2: Steps;

[0034] V1: First voltage;

[0035] V2: Second voltage;

[0036] WL0: Word line, 0th word line;

[0037] WL m-3 : Word line;

[0038] WL m-2 : Word line;

[0039] WL m-1 : Character line, m-1th character line;

[0040] WL m : character line, m-th character line. Detailed Implementation

[0041] The various embodiments will now be described in more detail with reference to the accompanying drawings. The description and drawings are provided for illustrative purposes only and are not intended to be limiting. For clarity, elements may not be drawn to scale. Furthermore, some elements and / or symbols may be omitted in some drawings. It is contemplated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further explanation.

[0042] This disclosure provides a storage device. The storage device includes a plurality of channel layers, a plurality of word lines, a plurality of storage layers disposed between the channel layers and the word lines, and a plurality of storage cells defined at a plurality of intersections of the channel layers and the word lines. The storage device is configured to perform a first operation m times and a second operation n times, where m is greater than or equal to n. m is, for example, an integer from 1 to 100,000, and n is, for example, an integer from 1 to 1,000, but is not limited thereto. In the first operation, a first electric field is generated in a portion of the storage layers. The plurality of word lines are configured to generate a second electric field in that portion of the storage layers in the second operation, the direction of the second electric field being different from the direction of the first electric field.

[0043] The second electric field generated in the second operation is used as a recovery electric field to provide recovery stress, thereby suppressing the lateral charge migration caused by the stress generated by the first electric field during the first operation. Laterally migrated charges in the continuously arranged storage layers, particularly in their charge trapping layers, can be recovered and returned to their original positions after the application of recovery stress.

[0044] Specifically, in the second operation, the second electric field may be generated by applying a first voltage to one word line corresponding to that portion of the memory layer and a second voltage to another word line corresponding to that portion of the memory layer. The first voltage may be 1V to 3V, and the second voltage may be 7V to 10V. In some embodiments, in the first operation, the first electric field is generated by applying a first voltage to a first word line in a word line pair and a second voltage to a second word line in the word line pair, and in the second operation, the second electric field may be generated by applying a second voltage to the first word line and a first voltage to the second word line. In some embodiments, in the second operation, the second electric field is generated by applying one or more first voltages to word lines located on one side of the portion of the memory layer and one or more second voltages to word lines located on the other side of the portion of the memory layer. In this embodiment, in the second operation, multiple second electric fields may be generated sequentially through a corresponding memory layer including that portion.

[0045] Please refer to Figure 1 This illustrates an exemplary embodiment of a storage device according to the present disclosure. Figure 1 The exemplary storage device 100 shown includes a substrate 110, a plurality of stacked layers 120, a plurality of storage layers 130, and a plurality of channel layers 140. The stacked layers 120 are disposed on the substrate 110 and separated by a plurality of channels. The plurality of stacked layers 120 include a plurality of conductive strips 122 and a plurality of dielectric strips 124 alternately arranged with each other. The conductive strips 122 include word lines, for example shown... Figure 1 More details about part A Figures 3A-3B arrive Figures 5A to 5C The character lines WL0~WL mentioned in the text m Storage layer 130 is disposed on multiple sidewalls of stack 120. Channel layer 140 is disposed on storage layer 130.

[0046] Specifically, as shown Figure 1 As shown in Figures 3A-3B to 5A-5C, which provide further details of part A, the plurality of storage layers 130 may include a plurality of barrier layers 132 disposed on the plurality of sidewalls of the stack 120, a plurality of charge trapping layers 134 disposed on the barrier layers 132, and a plurality of tunneling layers 136 disposed on the charge trapping layers 134. In this embodiment, a channel layer 140 is disposed on the tunneling layers 136. Furthermore, a first electric field and a second electric field are generated in the charge trapping layers 134. The barrier layers 132 may be formed of oxide. The charge trapping layers 134 may be formed of nitride. The tunneling layers 136 may be formed of oxide.

[0047] Channel layer 140 can be formed of polysilicon. In some embodiments, such as Figure 1As shown, the plurality of channel layers 140 can be provided by a polysilicon layer conformally formed on the substrate 110, the stack 120 and the memory layer 130.

[0048] In some embodiments, the storage device 100 further includes a conductive layer 112 disposed in the substrate 110 and located beneath the plurality of stacked layers 120. In some embodiments, the storage device 100 further includes a mask layer 126 disposed on the stacked layers 120. The mask layer 126 may be formed of oxide. In some embodiments, the storage device 100 further includes a plurality of dielectric pillars 150 disposed in the remaining space of the channel. In some embodiments, the storage device 100 further includes a plurality of conductors 152 disposed on the dielectric pillars 150. In some embodiments, the storage device 100 further includes a plurality of plugs 154 disposed beneath the dielectric pillars 150. The plugs 154 may be disposed beneath the channel layer 140. The plugs 154 may be formed from polysilicon using a selective epitaxial growth process.

[0049] Although Figure 1 Taking a 3D vertical channel structure oxide / nitride / oxide (ONO) type memory as an example, it is expected that the memory device according to this disclosure is not limited to this. For example, the memory device according to this disclosure can be a floating gate memory, a silicon / oxide / nitride / oxide / silicon (SONOS) type memory, a floating point memory, or a ferroelectric field-effect transistor (FeFET) memory, etc. In addition, the memory device according to this disclosure can have a two-dimensional (2D) flash structure, a three-dimensional (3D) flash structure, a NOR structure, a NAND gate structure, etc.

[0050] This disclosure also provides a method of operating a storage device. The storage device includes multiple channel layers, multiple word lines, multiple storage layers disposed between the channel layers and the word lines, and multiple storage cells defined at multiple intersections of the channel layers and the word lines. Other details are the same as described above and will not be repeated here.

[0051] Please refer to Figure 2 The diagram illustrates a flowchart of an operation method according to the present disclosure. The operation method according to the present disclosure includes performing a first operation m times in step S1 and performing a second operation n times in step S2, where m is greater than or equal to n. m is, for example, an integer from 1 to 100,000, and n is, for example, an integer from 1 to 1,000, but is not limited thereto. In some embodiments, m is an integer from 1 to 100,000, and n is 1.

[0052] In the first operation, a first electric field is generated in a portion of the memory layer. The first operation can be a read operation, an erase operation, or a write operation, etc.

[0053] Performing the second operation includes generating a second electric field in that portion of the memory layer using word lines, wherein the direction of the second electric field is different from the direction of the first electric field. The direction of the second electric field may be opposite to the direction of the first electric field. Specifically, in the second operation, the second electric field can be generated by applying a first voltage to one word line corresponding to that portion of the memory layer and applying a second voltage to another word line corresponding to that portion of the memory layer. The second voltage may be greater than the first voltage. The first voltage and the second voltage can be determined based on the maximum and minimum values ​​of the voltages applied in the first operation. For example, the first voltage may be the same as the minimum voltage applied in the first operation, and the second voltage may be the same as the maximum voltage applied in the first operation. In some embodiments, the first voltage may be from 1V to 3V, and the second voltage may be from 7V to 10V. In some embodiments, steps S1 and S2 may be repeated.

[0054] The following will refer to Figures 3A-3B arrive Figure 6 Various specific embodiments of the operating method according to this disclosure are provided. For ease of understanding, most of the accompanying drawings will show corresponding... Figure 1 A series of memory cells M in part A is used for illustration. The conductive strip 122 adjacent to memory cells M in the series is used as word lines corresponding to the series. Here, word line WL0 to word line WLm are shown. m For example, in the case where each serial unit comprises 48 memory cells M, m can be 47. Given a second voltage greater than the first voltage, an electric field is generated in the corresponding charge trapping layer 134, having an electric field direction from the word line to which the second voltage is applied. The electric field generated during operation is indicated by arrows, where the electric field direction is the same as the arrow direction. For clarity of the figures, some electric fields generated during operation may be omitted.

[0055] Figures 3A-3B An exemplary embodiment of the method of operation according to this disclosure is shown. For example... Figure 3A As shown, in some operations, word lines corresponding to a serial sequence can be provided in pairs. In this case, in the first operation, the first electric field is applied to a first word line (e.g., WL) in a word line pair. m A first voltage V1 and a second word line (e.g., WL) applied to the word line pair m-1 The second voltage V2 is used to generate it. In the second operation, as... Figure 3B As shown, a second voltage V2 can be applied to the first word line (i.e., WL). m ) and apply the first voltage V1 to the second word line (i.e., WL) m-1A second electric field is generated by a first voltage V1. In some embodiments, the first voltage V1 can be 1V and the second voltage V2 can be 7V.

[0056] In some embodiments, such as Figure 3A As shown, in the first operation, a first voltage V1 and a second voltage V2 are alternately applied to all word lines WL0 to WL corresponding to the serial line. m In this embodiment, in the first operation, the first electric field is applied to a plurality of first word lines (e.g., WL1, ..., WL) in a plurality of word line pairs. m-2 WL m Multiple first voltages V1 and multiple second word lines (e.g., WL0, ..., WL) applied to the multiple word line pairs m-3 WL m-1 This is generated by applying multiple second voltages V2 to the plurality of first word lines (i.e., WL1, ..., WL). In the second operation, this is achieved by applying second voltages V2 to the plurality of first word lines (i.e., WL1, ..., WL2). m-2 WL m and applying a first voltage V1 to the plurality of second word lines (i.e., WL0, ..., WL). m-3 WL m-1 This generates a second electric field.

[0057] In addition, such as Figure 3A As shown, in the first operation, a first electric field with an opposite electric field direction may be generated. In this embodiment, in the second operation, a second electric field with a correspondingly opposite electric field direction, different from the electric field direction at the corresponding location during the first operation, is generated to provide restoring stress. For example, please refer to... Figure 6 In the first operation, an electric field with a first electric field direction (e.g., downward) and a second electric field direction (e.g., upward) are generated. After m first operations, a second operation consisting of two steps can be performed. In the first step, an electric field with a third electric field direction (e.g., upward) opposite to the first electric field direction is generated n times. In the second step, an electric field with a fourth electric field direction (e.g., downward) opposite to the second electric field direction is generated p times. According to some embodiments, m is an integer from 1 to 100000, n is an integer from 1 to 1000, and p is an integer from 1 to 1000. The first and second operations can be repeated.

[0058] Figures 4A to 4CAnother exemplary embodiment of the method of operation according to this disclosure is shown. Various first operations can cause lateral charge migration in the storage device, including but not limited to read operations, erase operations, and write operations. This embodiment can be used to suppress such lateral charge migration without particular limitation. In the second operation, a second electric field is generated by applying one or more first voltages V1 to the plurality of word lines on one side of the portion of the storage layer corresponding to which the first electric field is generated, and by applying one or more second voltages V2 to the plurality of word lines on the other side of the portion of the storage layer. According to some embodiments, the second voltage V2 may be a pass-through voltage (V... pass (), which can be 8V. Correspondingly, the first voltage V1 can be able to be related to V pass Provide a sufficiently strong electric field below V pass The voltage. For example, the first voltage V1 could be 1V.

[0059] More specifically, a series of memory cells M corresponding to this part of the memory layer corresponds to a 0th word line WL0 to a mth word line WL m The i-th word line and the (i+1)-th word line correspond to this portion of the memory layer, where i is an integer greater than or equal to 0 and less than m. In the second operation, multiple first voltages V1 can be applied to the (i+1)-th word line to the m-th word line WL. m A second electric field is generated by applying multiple second voltages V2 to the 0th word line WL0 to the 1st word line. For example, suppose the portion of the storage layer that generates the first electric field is the charge trapping layer 134 corresponding to the (m-1)th word line WL0. m-1 and the m-th line WL m In the part where the i-th word line is the (m-1)-th word line WL m-1 The (i+1)th character line is the mth character line WL m .like Figure 4A As shown, a first voltage V1 can be applied to the m-th word line WL. m And apply a second voltage V2 to word line 0 (WL0) to word line m-1 (WL) m-1 This generates a second electric field in that section.

[0060] In some embodiments, such as Figures 4A to 4C As shown, in the second operation, multiple second electric fields can be generated sequentially through a corresponding storage layer including this portion. In this way, the electric field can be scanned and recovered page by page to fix the laterally migrated charge layer by layer. In this embodiment, the second electric field is at the m-th word line WL. m It is generated sequentially in the direction of the 0th word line WL0.

[0061] Figures 5A to 5CThis illustrates yet another exemplary implementation of the method of operation according to this disclosure. This implementation is related to... Figures 4A to 4C The difference in the implementation scheme lies in that the first voltage V1 and the second voltage V2 are applied to word lines on different sides of this portion of the memory layer. More specifically, in the second operation, multiple first voltages V1 are applied to the 0th word line WL0 to the 1st word line and multiple second voltages V2 are applied to the (i+1)th word line to the mth word line WL0. m This generates the second electric field. For example, suppose the portion of the storage layer that generates the first electric field is the charge trapping layer 134 corresponding to the (m-1)th word line WL. m-1 and the m-th line WL m In the part where the i-th word line is the (m-1)-th word line WL m-1 The (i+1)th character line is the mth character line WL m .like Figure 5C As shown, a first voltage V1 can be applied to word line 0 (WL0) to word line m-1 (WL). m-1 And apply a second voltage V2 to the m-th word line WL m This generates a second electric field in that section. In some embodiments, such as Figures 5A to 5C As shown, in the second operation, multiple second electric fields can be generated sequentially through a corresponding memory layer including this portion. In this embodiment, the second electric field is generated from the 0th word line WL0 to the mth word line WL. m They are generated sequentially in the direction shown. Other details are similar to the implementation schemes in Figures 4A to 4C, and will not be repeated here.

[0062] Figure 7 This illustrates a test result using the operating method according to this disclosure. Example E utilizes... Figures 3A-3B In the proposed implementation, the first operation is a read operation, and the second operation is performed once every 1000 first operations. The first voltage is 1V, and the second voltage is 7V. In contrast, in the comparative example CE, only the first operation is performed. Figure 7 As shown, the operating method according to this disclosure can suppress high threshold voltage tailing caused by lateral charge migration, as indicated by arrow B. Furthermore, the operating method according to this disclosure allows for up to one million read operations without degradation.

[0063] In summary, this disclosure provides a storage device and a method of operating thereof for suppressing lateral charge migration. This solves reliability issues without adding technical challenges to the manufacturing process.

[0064] While this disclosure has been given above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A storage device, comprising: Multiple channel layers; Multiple character lines; Multiple storage layers are disposed between the multiple channel layers and the multiple word lines; as well as Multiple storage cells are defined at multiple intersections of the multiple channel layers and the multiple word lines; The storage device is configured to perform a first operation m times and a second operation n times, where m is greater than or equal to n. In the first operation, a first electric field is generated in a portion of the plurality of memory layers, and the plurality of word lines are configured to generate a second electric field in that portion of the plurality of memory layers in the second operation, the electric field direction of the second electric field being different from that of the first electric field, the stress generated by the first electric field being capable of causing charge migration in the lateral direction of the memory device. In this second operation, the second electric field is generated by applying a first voltage to one word line corresponding to the portion of the plurality of word lines and a second voltage to another word line corresponding to the portion of the plurality of memory layers; the second electric field is used as a recovery electric field to provide recovery stress to suppress charge migration in the lateral direction caused by the stress generated by the first electric field during the first operation.

2. The storage device according to claim 1, comprising: One substrate; Multiple stacks are disposed on the substrate and separated by multiple channels, the multiple stacks including multiple conductive strips and multiple dielectric strips alternately disposed thereon, the multiple conductive strips including the multiple word lines; The plurality of storage layers are disposed on the plurality of sidewalls of the plurality of stacked layers; as well as The plurality of channel layers are disposed on the plurality of storage layers.

3. The storage device according to claim 2, further comprising: A conductive layer is disposed in the substrate and located under the plurality of stacked layers; A mask layer is disposed on the plurality of stacked layers; Multiple dielectric pillars are disposed in the remaining space of the multiple channels; Multiple conductors are disposed on the multiple dielectric pillars; as well as Multiple plugs are disposed under the multiple dielectric pillars.

4. The storage device according to claim 2, wherein the plurality of storage layers comprises: Multiple barrier layers are disposed on the multiple sidewalls of the multiple stacked layers; Multiple charge trapping layers are disposed on the multiple blocking layers; as well as Multiple tunneling layers are disposed on the multiple charge trapping layers; The plurality of channel layers are disposed on the plurality of tunneling layers; and The first electric field and the second electric field are generated in the plurality of charge trapping layers.

5. The storage device according to claim 1, wherein the first voltage is 1V to 3V and the second voltage is 7V to 10V.

6. The storage device of claim 1, wherein in the first operation, the first electric field is generated by a first voltage applied to a first word line of a word line pair and a second voltage applied to a second word line of the word line pair, and wherein in the second operation, the second electric field is generated by the second voltage applied to the first word line and the first voltage applied to the second word line.

7. The storage device of claim 1, wherein in the second operation, the second electric field is generated by applying one or more first voltages to one side of the plurality of word lines corresponding to the portion of the plurality of storage layers and applying one or more second voltages to the plurality of word lines corresponding to the other side of the portion of the plurality of storage layers.

8. The storage device of claim 7, wherein in the second operation, a plurality of second electric fields are generated sequentially through a corresponding storage layer including the portion.

9. A method of operating a storage device, wherein the storage device includes a plurality of channel layers, a plurality of word lines, a plurality of storage layers disposed between the plurality of channel layers and the plurality of word lines, and a plurality of storage cells defined at a plurality of intersections of the plurality of channel layers and the plurality of word lines, and wherein the method of operating the storage device includes: A first operation is performed m times, wherein a first electric field is generated in a portion of the plurality of memory layers during the first operation; as well as Perform the second operation n times, including: A second electric field is generated in the portion of the plurality of memory layers using the plurality of word lines, wherein the direction of the second electric field is different from the direction of the first electric field, and the stress generated by the first electric field can cause charge migration in the lateral direction of the memory device; wherein m is greater than or equal to n; In this second operation, the second electric field is generated by applying a first voltage to one word line of the plurality of word lines corresponding to the portion of the plurality of memory layers and applying a second voltage to another word line of the plurality of word lines corresponding to the portion of the plurality of memory layers. The second electric field is used as a recovery electric field to provide recovery stress in order to suppress charge migration in the lateral direction caused by the stress generated by the first electric field during the first operation.

10. The method of operating the storage device according to claim 9, wherein the electric field direction of the second electric field is opposite to the electric field direction of the first electric field.

11. The method of operating the storage device according to claim 9, wherein the first voltage is 1V to 3V and the second voltage is 7V to 10V.

12. The method of operating the storage device according to claim 9, wherein in the first operation, the first electric field is generated by applying a first voltage to a first word line in a word line pair and a second voltage to a second word line in the word line pair, and wherein in the second operation, the second electric field is generated by applying the second voltage to the first word line and applying the first voltage to the second word line.

13. The method of operating a storage device according to claim 9, wherein in the first operation, the first electric field is generated by applying a plurality of first voltages to a plurality of first word lines in a plurality of word line pairs and a plurality of second voltages to a plurality of second word lines in the plurality of word line pairs, and wherein in the second operation, the second electric field is generated by applying the plurality of second voltages to the plurality of first word lines and applying the plurality of first voltages to the plurality of second word lines.

14. The method of operating a storage device according to claim 9, wherein in the second operation, the second electric field is generated by applying one or more first voltages to the plurality of word lines corresponding to one side of the portion of the plurality of storage layers and applying one or more second voltages to the plurality of word lines corresponding to the other side of the portion of the plurality of storage layers.

15. The method of operating the storage device according to claim 14, wherein in the second operation, a plurality of second electric fields are generated sequentially through a corresponding storage layer including the portion.

16. The method of operating the storage device according to claim 14, wherein the plurality of second voltages are voltages.

17. The method of operating a storage device according to claim 9, wherein a series of the plurality of storage cells corresponding to the portion of the plurality of storage layers corresponds to a 0th word line to a mth word line, an ith word line and an (i+1)th word line corresponding to the portion of the plurality of storage layers, i being an integer greater than or equal to 0 and less than m, and wherein in the second operation, the second electric field is generated by applying a plurality of first voltages to the (i+1)th word line to the mth word line and applying a plurality of second voltages to the 0th word line to the ith word line.

18. The method of operating a storage device according to claim 9, wherein a series of the plurality of storage cells corresponding to the portion of the plurality of storage layers corresponds to a 0th word line to a mth word line, an ith word line and an i+1th word line corresponding to the portion of the plurality of storage layers, i being an integer greater than or equal to 0 and less than m, and wherein in the second operation, the second electric field is generated by applying a plurality of first voltages to the 0th word line to the ith word line and applying a plurality of second voltages to the i+1th word line to the mth word line.

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