Data transmission structure, data transmission method and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a data transmission structure, a data transmission method and a memory. The data transmission structure comprises: a data transmission module configured to generate second data in response to a flip control signal and first data; and a control module configured to generate the flip control signal in response to an enable control signal and the second data. When the second data of a previous bit is the same as the first data of a current bit, the flip control signal and the first data are used to turn off the data transmission module, and the second data of the current bit is generated according to the second data of the previous bit. When the second data of the previous bit is different from the first data of the current bit, the flip control signal and the first data are used to turn on the data transmission module, and the second data of the current bit is generated according to the first data of the current bit. The invalid current consumption in the memory is avoided, and the power consumption of the memory is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a data transmission structure, data transmission method, and memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transfer speed. With the development of semiconductor technology, DRAM technology is becoming increasingly advanced, and the integration of memory cells is becoming higher and higher; at the same time, various applications are placing increasingly higher demands on the performance, power consumption, and reliability of DRAM.

[0003] The memory bus is quite long. To prevent data attenuation during bus transmission, a driver needs to be set up on the bus to compensate for the transmitted data. During the transmission of data on the bus, if the current data state is inconsistent with the previous data state, the bus data will flip. If the current data state is consistent with the previous data state, although the bus data will not flip, the control signal of the control transistor in the driver will flip.

[0004] When bus data does not flip, the control signal flipping of the control transistor in the driver will cause invalid current consumption in the memory, resulting in meaningless power loss. In addition, since the power consumption of the driver is relatively large, the amount of bus data processed by the driver is large, resulting in a large power loss of the memory. Summary of the Invention

[0005] This disclosure provides a data transmission structure, a data transmission method, and a memory. When the bus data does not flip, it avoids invalid flipping of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory.

[0006] One embodiment of this disclosure provides a data transmission structure, including a data transmission module for receiving first data and a flip control signal, configured to generate second data in response to the flip control signal and the first data; and a control module for receiving the second data and an enable control signal, configured to generate a flip control signal in response to the enable control signal and the second data; the enable control signal is used to enable the data transmission module to perform data transmission; in cases where the second data of the current bit is the same as the first data of the current bit, the flip control signal and the first data are used to turn off the data transmission module, and the second data of the current bit is generated based on the second data of the previous bit; and in cases where the second data of the current bit is different from the first data of the current bit, the flip control signal and the first data are used to turn on the data transmission module, and the second data of the current bit is generated based on the first data of the current bit.

[0007] The data transmission structure provided in this embodiment uses a flip control signal generated based on the previous bit of second data. That is, the flip control signal contains information about the previous bit of second data. The data transmission module controls the on / off state based on the flip control signal and the current bit of first data. This is equivalent to adding a process to determine whether the current bit of first data and the previous bit of second data are the same. When the current bit of first data and the previous bit of second data are the same, the data transmission module is directly turned off, that is, the driver in the bus is turned off. This avoids invalid flipping of the control signal of the control transistor in the driver, thereby avoiding unnecessary current consumption in the memory and reducing the power consumption of the memory.

[0008] In addition, the flip control signal includes a first control signal and a second control signal; the control module includes: a first control unit configured to generate the first control signal based on the second data and an enable control signal; and a second control unit configured to generate the second control signal based on the second data and the enable control signal; when the enable control signal is a valid signal, the generated first control signal and the second control signal are inverse signals to each other.

[0009] In addition, the first control unit includes: a first NOR gate, one input terminal for receiving second data, another input terminal for receiving an enable control signal, and an output terminal for outputting a first control signal.

[0010] Additionally, the second control unit includes: a first NAND gate, one input terminal for receiving second data, the other input terminal connected to the output terminal of the first inverter, the output terminal for outputting a second control signal, and the input terminal of the first inverter for receiving an enable control signal.

[0011] In addition, the data transmission module includes: a second NAND gate, one input terminal for receiving first data and the other input terminal for receiving a first control signal; a second NOR gate, one input terminal for receiving the first data and the other input terminal for receiving a second control signal; a P-type transistor, the gate of which is connected to the output terminal of the second NAND gate, the source of which is coupled to the power supply voltage, and the drain of which is used to output the second data; and an N-type transistor, the gate of which is connected to the output terminal of the second NOR gate, the source of which is grounded, and the drain of which is connected to the drain of the P-type transistor.

[0012] Additionally, the control module further includes: an input sampler for receiving second data and an enable control signal, configured to sample the second data and generate third data in response to the effective level of the enable control signal; a first control unit generates a first control signal based on the third data, and a second control unit generates a second control signal based on the third data. By sampling the data, the enable control signal adjusts the value of the second data for the current bit, improving the timing stability of data transfer in the memory.

[0013] Additionally, the input sampler includes a latch, with an input terminal for receiving second data and a clock terminal for receiving an enable control signal.

[0014] In addition, the clock input of the latch includes a positive clock input and a negative clock input. The positive clock input is connected to the output of the second inverter, and the negative clock input and the input of the second inverter are used to receive the enable control signal.

[0015] Another embodiment of this disclosure provides a data transmission method applied to the data transmission method provided in the above embodiment, comprising: generating a flip control signal based on the value of the previous bit of second data and an enable control signal; determining whether it is necessary to transmit the value of the current bit of first data to adjust the value of the second data based on the value of the previous bit of second data and the value of the current bit of first data; and generating the second data in response to the flip control signal and the value of the current bit of first data based on the determination result.

[0016] The toggle control signal is generated based on the previous bit of second data. That is, the toggle control signal contains the information of the previous bit of second data. Based on the toggle control signal and the value of the current bit of first data, that is, according to the value of the previous bit of second data and the value of the current bit of first data, it is determined whether the value of the current bit of first data needs to be transmitted to adjust the value of the second data. Then, the second data is generated based on the result of the determination. By adding a determination process during data transmission, the control signal of the control transistor in the driver is prevented from being ineffectively toggled, thereby avoiding unnecessary current consumption in the memory and reducing the power consumption of the memory.

[0017] In addition, determining whether it is necessary to transmit the value of the first data of the current bit to adjust the value of the second data includes: if the value of the second data of the previous bit is different from the value of the first data of the current bit, the result of the determination is used to indicate that the value of the first data of the current bit is transmitted to generate the value of the second data of the current bit; if the value of the second data of the previous bit is the same as the value of the first data of the current bit, the result of the determination is used to indicate that the value of the second data of the current bit is directly generated based on the value of the second data of the previous bit.

[0018] Additionally, generating a toggle control signal based on the value of the previous bit of second data and an enable control signal includes: sampling the second data in response to the effective level of the enable control signal to generate third data, and generating a toggle control signal based on the value of the third data.

[0019] Additionally, the value of the second data is sampled based on the enable control signal to generate the third data; the flip control signal includes a first control signal and a second control signal, and the flip control signal is generated based on the value of the third data, including: generating the first control signal based on the third data and the enable control signal, and generating the second control signal based on the inverted signal of the third data and the enable control signal.

[0020] Additionally, in response to the flip control signal and the value of the first data of the current bit, generating second data includes: generating a pull-up control signal based on the value of the first data of the current bit and the first control signal, the pull-up control signal being used to pull up the value of the second data; and generating a pull-down control signal based on the value of the second data of the current bit and the second control signal, the pull-down control signal being used to pull down the value of the second data.

[0021] Additionally, if the pull-up control signal is valid and the pull-down control signal is invalid, the value of the second data is pulled up; if the pull-up control signal is invalid and the pull-down control signal is valid, the value of the second data is pulled down; if both the pull-up and pull-down control signals are invalid, the value of the second data of the current bit is directly generated based on the value of the second data of the previous bit.

[0022] Another embodiment of this disclosure also provides a memory that uses the data transmission structure provided in the above embodiments for data transmission, so as to avoid invalid switching of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a data transmission structure provided in an embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of the structure of a control module provided in an embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the structure of a data transmission module provided in an embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of the structure of a control module with a data sampler provided in an embodiment of the present disclosure;

[0028] Figures 5-8 This is a schematic diagram of signal timing changes in a data transmission structure provided in an embodiment of the present disclosure;

[0029] Figure 9 This is a flowchart illustrating the steps of a data transmission method provided in another embodiment of this disclosure. Detailed Implementation

[0030] As the background technology shows, memory buses are relatively long. To prevent data attenuation during bus transmission, a driver is needed to compensate for the transmitted data. During bus transmission, if the current data state differs from the previous data state, the bus data will flip. If the current data state matches the previous data state, although the bus data will not flip, the control signal of the control transistor in the driver will flip. When the bus data does not flip, the flipping of the control signal in the driver leads to unnecessary current consumption in the memory, resulting in meaningless power loss. In addition, because the driver has high power consumption, the amount of bus data processed by the driver is large, leading to significant power loss in the memory.

[0031] One embodiment of this disclosure provides a data transmission structure that avoids invalid switching of control signals of control transistors in the driver when bus data does not flip, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory.

[0032] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0033] Figure 1 This is a schematic diagram of the data transmission structure provided in this embodiment. Figure 2 This is a schematic diagram of the control module provided in this embodiment. Figure 3 This is a schematic diagram of the data transmission module provided in this embodiment. Figure 4 This is a schematic diagram of the control module with a data sampler provided in this embodiment. Figures 5-8 The diagram below illustrates the signal timing changes of the data transmission structure provided in this embodiment. The data transmission structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0034] refer to Figure 1 The data transmission structure includes:

[0035] The data transmission module 100 is used to receive first data D and a flip control signal, and is configured to generate second data Q in response to the flip control signal and the first data D.

[0036] The control module 200 is configured to receive a second data Q and an enable control signal EnB, and to generate a toggle control signal in response to the enable control signal EnB and the second data Q.

[0037] Wherein, the first data D is the data before transmission, the second data Q is the data after transmission, the toggle control signal is the control signal of the control transistor in the driver, and the enable control signal EnB is used to enable the data transmission module 100 to perform data transmission. Specifically, the enable control signal EnB controls the data transmission module 100 to generate the second data Q based on the first data D by generating the toggle control signal.

[0038] The second data Q of the current bit is the same as the first data D of the current bit. The toggle control signal and the first data D are used to turn off the data transmission module 100. The second data Q of the current bit is generated based on the second data of the previous bit. The second data Q of the current bit is different from the first data D of the current bit. The toggle control signal and the first data D are used to turn on the data transmission module 100. The second data Q of the current bit is generated based on the first data of the current bit.

[0039] The data transmission structure provided in this embodiment uses a flip control signal generated based on the previous bit of second data Q. That is, the flip control signal contains information about the previous bit of second data Q. The data transmission module 100 controls the on / off state based on the flip control signal and the current bit of first data D. This is equivalent to adding a process to determine whether the current bit of first data D and the previous bit of second data Q are the same. When the current bit of first data D and the previous bit of second data Q are the same, the data transmission module 100 is directly turned off, that is, the driver in the bus is turned off. This avoids invalid flipping of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory.

[0040] Specifically, refer to Figure 2 In some embodiments, the flip control signal includes a first control signal En2 and a second control signal En2B. The control module 200 includes: a first control unit 301 configured to generate the first control signal En2 based on second data Q and an enable control signal EnB; and a second control unit 302 configured to generate the second control signal En2B based on the second data Q and the enable control signal EnB. When the enable control signal EnB is valid, the generated first control signal En2 and the second control signal En2B are inverse signals. One of the first control signal En2 and the second control signal En2B serves as the control signal for the P-type transistor in the driver, and the other serves as the control signal for the N-type transistor in the driver.

[0041] It should be noted that in this embodiment and the following description, the first control signal En2 is used as the control signal of the P-type transistor in the driver and the second control signal En2B is used as the control signal of the N-type transistor in the driver for detailed description. This does not constitute a limitation on this embodiment. In other embodiments, the first control signal En2 can be used as the control signal of the N-type transistor in the driver and the second control signal En2B can be used as the control signal of the P-type transistor in the driver.

[0042] Continue to refer to Figure 2 In one example, the first control unit 301 includes: a first NOR gate 201, one input terminal for receiving second data Q, another input terminal for receiving an enable control signal EnB, and an output terminal for outputting a first control signal En2.

[0043] Continue to refer to Figure 2 In one example, the second control unit 302 includes: a first NAND gate 210, one input terminal for receiving second data Q, another input terminal for connecting to the output terminal of a first inverter 220, the output terminal for outputting a second control signal En2B, and the input terminal of the first inverter 220 for receiving an enable control signal EnB.

[0044] Since there is a delay between the input and output signals of each component, assuming that the first data D of the previous bit appears at time t1, the second data Q of the previous bit generated by the first data D will appear at time t2 after a certain delay. The first control signal En2 and the second control signal En2B generated based on the second data Q of the previous bit and the enable control signal EnB will appear at time t3 after a certain delay. The second data Q of the current bit generated based on the first control signal En2, the second control signal En2B and the first data D of the current bit will appear at time t4 after a certain delay. Based on the above discussion, it can be seen that the first data D of the previous bit appears at time t1, the second data of the previous bit appears at time t2, the first data D of the current bit appears between time t3 and t4, and the second data of the current bit appears at time t4, which conforms to the data transmission timing of the memory.

[0045] refer to Figure 3 In some embodiments, the data transmission module 100 includes: a second NAND gate 102, one input terminal for receiving first data D and the other input terminal for receiving a first control signal En2; a second NOR gate 120, one input terminal for receiving the first data D and the other input terminal for receiving a second control signal En2B; and a P-type transistor 101, the gate of which is connected to the output terminal of the second NAND gate 102, and the source of which is coupled to the power supply voltage V. DDThe drain is used to output the second data Q; the gate of the N-type transistor 103 is connected to the output terminal of the second NOR gate 102, the source is grounded to GND, and the drain is connected to the drain of the P-type transistor 101.

[0046] Specifically, the second NAND gate 102 generates a P-type transistor control signal Dp based on the first data D and the first control signal En2. The P-type transistor control signal Dp is used to control the conduction or cutoff of the P-type transistor 101. The second NOR gate 120 generates an N-type transistor control signal Dn based on the first data D and the second control signal En2B. The N-type transistor control signal Dn is used to control the conduction or cutoff of the N-type transistor 103.

[0047] based on Figures 1-3 The truth table for the data transmission structure, including the first data D, the second data Q, the enable control signal EnB, the first control signal En2, the second control signal En2B, the P-transistor control signal Dp, and the N-transistor control signal Dn, is as follows:

[0048] Table 1 - Truth table corresponding to each data in the data transmission structure provided in this embodiment.

[0049] 0 0 1 0 1 1 0 Data transmission module 100 is off, Q is held. 0 0 0 1 1 1 0 Data transmission module 100 is off, Q is held. 0 1 1 0 1 1 0 Data transmission module 100 is off, Q is held. 0 1 0 0 0 1 1 Data transmission module 100 is enabled, Q is flipped. 1 0 1 0 1 1 0 Data transmission module 100 is off, Q is held. 1 0 0 1 1 0 0 Data transmission module 100 is enabled, Q is flipped. 1 1 1 0 1 1 0 Data transmission module 100 is off, Q is held. 1 1 0 0 0 1 0 Data transmission module 100 is off, Q is held.

[0050] It should be noted that the design in Table 1, which uses the enable control module 200 when the enable control signal EnB = 0 as an example for detailed explanation, is only for those skilled in the art to understand the implementation of this solution and does not constitute a limitation on this embodiment; in other embodiments, the enable control module when the enable control signal = 1 can also be designed. (Referring to Table 1 and...) Figure 3 As can be seen from the content, the data transmission structure includes four working states, as follows:

[0051] (1) When the second data Q of the current bit is 0 and the first data D of the current bit is 0:

[0052] When the enable control signal EnB is 1, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the third data En1, that is, En2 is the NOR value of 1 and 0, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the second data Q of the previous bit, that is, En2B is the NAND value of 0 and 0, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the first data D of the current bit, that is, Dp is the NAND value of 0 and 0, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the first data D of the current bit, that is, Dn is the NOR value of 1 and 0, which is 0; therefore, it can be seen that when the enable control signal EnB = 1, Dp = 1, Dn = 0, and both the P-type transistor 101 and the N-type transistor are turned off.

[0053] When the enable control signal EnB is 0, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 0 and 0, which is 1; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 1 and 0, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 1 and 0, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 1 and 0, which is 0; therefore, it can be seen that when the enable control signal EnB = 0, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0054] In summary, in working state (1), regardless of whether the enable control signal EnB is 1 or 0, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, and the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0. The data transmission module 100 is turned off, and the current bit, the second data Q, remains unchanged, that is, the second data Q does not flip. By keeping the P-transistor control signal Dp generated by the second NAND gate 102 and the N-transistor control signal Dn generated by the second NOR gate 120 unchanged, the invalid flipping of the control signal of the control transistor in the driver is avoided, which leads to a change in the working state of the control transistor, thereby reducing the power consumption of the memory.

[0055] (2) When the second data Q of the current bit is 1 and the first data D of the current bit is 0:

[0056] When the enable control signal EnB is 1, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 1 and 1, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 0 and 1, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 0 and 0, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 1 and 0, which is 0; therefore, it can be seen that when the enable control signal EnB = 1, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0057] When the enable control signal EnB is 0, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 0 and 1, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 1 and 1, which is 0; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 0 and 0, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 0 and 0, which is 1. Therefore, when the enable control signal EnB = 0, Dp = 1, Dn = 1, P-type transistor 101 is cut off and N-type transistor is turned on.

[0058] In summary, in working state (2), when the enable control signal EnB is 1, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0, the data transmission module 100 is turned off, and the current bit second data Q remains unchanged; when the enable control signal EnB is 0, the P-transistor control signal Dp is 1, the N-transistor control signal Dn is 1, the data transmission module 100 is turned on, and the current bit second data Q is pulled down to 0 based on the conduction of the N-type transistor, which is consistent with the current bit first data D.

[0059] (3) When the second data Q of the current bit is 0 and the first data D of the current bit is 1:

[0060] When the enable control signal EnB is 1, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 1 and 0, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 0 and 0, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 0 and 1, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 1 and 1, which is 0; therefore, it can be seen that when the enable control signal EnB = 1, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0061] When the enable control signal EnB is 0, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 0 and 0, which is 1; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 1 and 0, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 1 and 1, which is 0; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 1 and 1, which is 0; Therefore, when the enable control signal EnB = 0, Dp = 0, Dn = 0, P-type transistor 101 is turned on and N-type transistor is turned off.

[0062] In summary, in working state (3), when the enable control signal EnB is 1, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0, the data transmission module 100 is turned off, and the current bit second data Q remains unchanged; when the enable control signal EnB is 0, the P-transistor control signal Dp is 0, the N-transistor control signal Dn is 0, the data transmission module 100 is turned on, and the current bit second data Q is pulled up to 1 based on the conduction of the P-type transistor, which is consistent with the current bit first data D.

[0063] (4) When the second data Q of the current bit is 1 and the first data D of the current bit is 1:

[0064] When the enable control signal EnB is 1, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 1 and 1, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 0 and 1, which is 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 0 and 1, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 1 and 1, which is 0; Therefore, when the enable control signal EnB = 1, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0065] When the enable control signal EnB is 0, En2 is generated by the first NOR gate 201 based on the enable control signal EnB and the previous bit of second data Q, that is, En2 is the NOR value of 0 and 1, which is 0; En2B is generated by the first NAND gate 210 based on the inverted signal of the enable control signal EnB and the previous bit of second data Q, that is, En2B is the NAND value of 1 and 1, which is 0; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit of first data D, that is, Dp is the NAND value of 0 and 1, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit of first data D, that is, Dn is the NOR value of 0 and 1, which is 0; therefore, it can be seen that when the enable control signal EnB = 0, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0066] In summary, in working state (4), regardless of whether the enable control signal EnB is 1 or 0, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, and the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0. The data transmission module 100 is turned off, and the current bit, the second data Q, remains unchanged, that is, the second data Q does not flip. By keeping the P-transistor control signal Dp generated by the second NAND gate 102 and the N-transistor control signal Dn generated by the second NOR gate 120 unchanged, the control signal of the control transistor in the driver is not invalidally flipped, which leads to a change in the working state of the control transistor, thereby reducing the power consumption of the memory.

[0067] In some embodiments, the control module 200 further includes: an input sampler for receiving second data Q and an enable control signal EnB, configured to generate third data En1 using the second data Q in response to an active level of the enable control signal EnB; correspondingly, a first control unit 301 generates a first control signal En2 based on the third data En1, and a second control unit 302 generates a second control signal En2B based on the third data En1. By sampling the data, the value of the second data Q of the current bit is adjusted by the enable control signal EnB, thereby improving the timing stability of data transfer in the memory.

[0068] Further, refer to Figure 4 The input sampler includes a latch 300, with input terminal d for receiving second data Q and clock terminal for receiving enable control signal EnB. More specifically, in one example, the latch's clock terminal includes a positive clock terminal Lat and a negative clock terminal LatB. The positive clock terminal Lat is connected to the output of the second inverter 320, and the negative clock terminal LatB and the input of the second inverter 320 are used to receive the enable control signal EnB.

[0069] For control module 200 with latch 300, refer to Figures 5-8The third data En1 is generated based on the sampling of the enable control signal EnB. Combined with the discussion in Table 1, the following truth table can be derived:

[0070] Table 2 - Truth Table of Data Corresponding to Each Data in the Data Transmission Structure Provided in This Embodiment

[0071]

[0072]

[0073] It should be noted that the design in Table 2, which uses the enable control module 200 when the enable control signal EnB = 0 as an example for detailed explanation, is only for those skilled in the art to understand the implementation of this solution and does not constitute a limitation on this embodiment; in other embodiments, the enable control module when the enable control signal = 1 can also be designed.

[0074] Combine Table 2 and Figure 3 As can be seen from the content, the data transmission structure includes four working states, as follows:

[0075] (1) When the second data Q of the current bit is 0 and the first data D of the current bit is 0:

[0076] When the enable control signal EnB is 1, the data transmission structure is not started, the enable control signal EnB does not enable latch 300, and the third data En1 remains unchanged. When the third data En1 is 0, the data references the second row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit of the second data Q remains unchanged. When the third data En1 is 1, the data references the fourth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit of the second data Q remains unchanged.

[0077] refer to Figure 5When the enable control signal EnB is 0, the data transmission structure starts. The enable control signal EnB enables latch 300. The third data En1 is generated based on latch 300 and the second data Q sampled from the previous bit of the enable control signal EnB. En2 is generated by the first NOR gate 201 according to the enable control signal EnB and the third data En1, that is, En2 is the NOR value of 0 and 0, which is 1. En2B is generated by the first NAND gate 210 according to the inverted signal of the enable control signal EnB and the third data En1, that is, En... 2B is the NAND value of 1 and 0, which is set to 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit first data D, that is, Dp is the NAND value of 1 and 0, which is set to 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit first data D, that is, Dn is the NOR value of 1 and 0, which is set to 0; it can be seen that when the enable control signal EnB = 0, Dp = 1, Dn = 0, both P-type transistor 101 and N-type transistor are turned off, and the current bit second data Q remains unchanged.

[0078] In summary, in working state (1), regardless of whether the enable control signal EnB is 1 or 0, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, and the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0. The data transmission module 100 is turned off, and the current bit, the second data Q, remains unchanged, that is, the second data Q does not flip. By keeping the P-transistor control signal Dp generated by the second NAND gate 102 and the N-transistor control signal Dn generated by the second NOR gate 120 unchanged, the invalid flipping of the control signal of the control transistor in the driver is avoided, which leads to a change in the working state of the control transistor, thereby reducing the power consumption of the memory.

[0079] (2) When the second data Q of the current bit is 1 and the first data D of the current bit is 0:

[0080] When the enable control signal EnB is 1, the data transmission structure is not started, the enable control signal EnB does not enable latch 300, and the third data En1 remains unchanged. When the third data En1 is 0, the data references the second row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit of the second data Q remains unchanged. When the third data En1 is 1, the data references the fourth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit of the second data Q remains unchanged.

[0081] refer to Figure 6When the enable control signal EnB is 0, the data transmission structure starts. The enable control signal EnB enables latch 300. The third data En1 is generated based on latch 300 and the second data Q sampled from the previous bit of the enable control signal EnB. En2 is generated by the first NOR gate 201 according to the enable control signal EnB and the third data En1, that is, En2 is the NOR value of 0 and 1, which is 0. En2B is generated by the first NAND gate 210 according to the inverted signal of the enable control signal EnB and the third data En1, that is, En2... B is a NAND value of 1 and 1, which is 0; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit first data D, that is, Dp is a NAND value of 0 and 0, which is 1; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit first data D, that is, Dn is a NOR value of 0 and 0, which is 1; it can be seen that when the enable control signal EnB = 0, Dp = 1, Dn = 1, the P-type transistor 101 is cut off, the N-type transistor is turned on, and the current bit second data Q is pulled down to 0.

[0082] In summary, in working state (2), when the enable control signal EnB is 1, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0, the data transmission module 100 is turned off, and the current bit second data Q remains unchanged; when the enable control signal EnB is 0, the P-transistor control signal Dp is 1, the N-transistor control signal Dn is 1, the data transmission module 100 is turned on, and the current bit second data Q is pulled down to 0 based on the conduction of the N-type transistor, which is consistent with the current bit first data D.

[0083] (3) When the second data Q of the current bit is 0 and the first data D of the current bit is 1:

[0084] When the enable control signal EnB is 1, the data transmission structure is not started, the enable control signal EnB does not enable latch 300, and the third data En1 remains unchanged. When the third data En1 is 0, the data references the sixth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit, the second data Q, remains unchanged. When the third data En1 is 1, the data references the eighth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit, the second data Q, remains unchanged.

[0085] refer to Figure 7When the enable control signal EnB is 0, the data transmission structure starts. The enable control signal EnB enables latch 300. The third data En1 is generated based on latch 300 and the second data Q sampled from the previous bit of the enable control signal EnB. En2 is generated by the first NOR gate 201 according to the enable control signal EnB and the third data En1, that is, En2 is the NOR value of 0 and 0, which is 1. En2B is generated by the first NAND gate 210 according to the inverted signal of the enable control signal EnB and the third data En1, that is, En2... B is the NAND value of 1 and 0, which is set to 1; Dp is generated by the second NAND gate 202 based on the first control signal En2 and the current bit first data D, that is, Dp is the NAND value of 1 and 1, which is set to 0; Dn is generated by the second NOR gate 220 based on the second control signal En2B and the current bit first data D, that is, Dn is the NOR value of 1 and 1, which is set to 0; it can be seen that when the enable control signal EnB = 0, Dp = 0, Dn = 0, the P-type transistor 101 is turned on and the N-type transistor is turned off, and the current bit second data Q is pulled up to 1.

[0086] In summary, in working state (3), when the enable control signal EnB is 1, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0, the data transmission module 100 is turned off, and the current bit second data Q remains unchanged; when the enable control signal EnB is 0, the P-transistor control signal Dp is 0, the N-transistor control signal Dn is 0, the data transmission module 100 is turned on, and the current bit second data Q is pulled up to 1 based on the conduction of the P-type transistor, which is consistent with the current bit first data D.

[0087] (4) When the second data Q of the current bit is 1 and the first data D of the current bit is 1:

[0088] When the enable control signal EnB is 1, the data transmission structure is not started, the enable control signal EnB does not enable latch 300, and the third data En1 remains unchanged. When the third data En1 is 0, the data references the sixth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit, the second data Q, remains unchanged. When the third data En1 is 1, the data references the eighth row of Table 2. At this time, Dp=1, Dn=0, both P-type transistor 101 and N-type transistor are turned off, and the current bit, the second data Q, remains unchanged.

[0089] refer to Figure 8When the enable control signal EnB is 0, the data transmission structure starts. The enable control signal EnB enables latch 300. The third data En1 is generated based on latch 300 and the second data Q sampled from the previous bit of the enable control signal EnB. En2 is generated by the first NOR gate 201 according to the enable control signal EnB and the third data En1, that is, En2 is the NOR value of 0 and 1, which is 0. En2B is generated by the first NAND gate 210 according to the inverted signal of the enable control signal EnB and the third data En1. 1 is generated, that is, En2B is the NAND value of 1 and 1, which is 0; Dp is generated by the second NAND gate 202 according to the first control signal En2 and the current bit first data D, that is, Dp is the NAND value of 0 and 1, which is 1; Dn is generated by the second NOR gate 220 according to the second control signal En2B and the current bit first data D, that is, Dn is the NOR value of 0 and 1, which is 0; it can be seen that when the enable control signal EnB = 0, Dp = 1, Dn = 0, and both P-type transistor 101 and N-type transistor are turned off.

[0090] In summary, in working state (4), regardless of whether the enable control signal EnB is 1 or 0, the P-transistor control signal Dp generated by the second NAND gate 102 remains unchanged at 1, and the N-transistor control signal Dn generated by the second NOR gate 120 remains unchanged at 0. The data transmission module 100 is turned off, and the current bit, the second data Q, remains unchanged, that is, the second data Q does not flip. By keeping the P-transistor control signal Dp generated by the second NAND gate 102 and the N-transistor control signal Dn generated by the second NOR gate 120 unchanged, the control signal of the control transistor in the driver is not invalidally flipped, which leads to a change in the working state of the control transistor, thereby reducing the power consumption of the memory.

[0091] The data transmission structure provided in this embodiment uses a flip control signal generated based on the second data Q. That is, the flip control signal contains information about the previous bit of the second data Q. The data transmission module 100 controls the on / off state based on the flip control signal and the current bit of the first data D. This is equivalent to adding a process to determine whether the current bit of the first data D and the previous bit of the second data Q are the same. When the current bit of the first data D and the previous bit of the second data Q are the same, the data transmission module 100 is directly turned off, that is, the driver in the bus is turned off. This avoids invalid flipping of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory.

[0092] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0093] It should be noted that the features disclosed in the data transmission structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new data transmission structure embodiments.

[0094] Another embodiment of this disclosure provides a data transmission method applied to the data transmission structure provided in the above embodiments, so as to avoid invalid switching of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory; Figure 9 The following is a flowchart illustrating each step of the data transmission method provided in this embodiment. The data transmission method provided in this embodiment will be described in detail below with reference to the accompanying drawings. Corresponding parts of the above embodiments will not be repeated here. The details are as follows:

[0095] refer to Figure 9 Data transmission methods include:

[0096] Step 401: Generate a flip control signal based on the value of the previous bit of the second data and the enable control signal.

[0097] Step 402: Determine whether it is necessary to transmit the value of the first data of the current bit in order to adjust the value of the second data.

[0098] Specifically, based on the value of the previous bit of second data and the value of the current bit of first data, it is determined whether it is necessary to transmit the value of the current bit of first data in order to adjust the value of the second data.

[0099] More specifically, if the value of the previous bit of second data is different from the value of the current bit of first data, the result of the judgment indicates that the value of the current bit of first data should be transmitted to generate the value of the current bit of second data; if the value of the previous bit of second data is the same as the value of the current bit of first data, the result of the judgment is used to indicate that the value of the current bit of second data should be generated directly based on the value of the previous bit of second data.

[0100] Step 403: Based on the judgment result, generate second data in response to the flip control signal and the value of the current bit first data.

[0101] The toggle control signal is generated based on the previous bit of second data. That is, the toggle control signal contains the information of the previous bit of second data. Based on the toggle control signal and the value of the current bit of first data, that is, according to the value of the previous bit of second data and the value of the current bit of first data, it is determined whether the value of the current bit of first data needs to be transmitted to adjust the value of the second data. Then, the second data is generated based on the result of the determination. By adding a determination process during data transmission, the control signal of the control transistor in the driver is prevented from being ineffectively toggled, thereby avoiding unnecessary current consumption in the memory and reducing the power consumption of the memory.

[0102] In some embodiments, step 401 further includes: sampling second data to generate third data in response to the effective level of the enable control signal, and generating a flip control signal based on the third data.

[0103] Further, in some embodiments, step 401 includes: sampling the value of the second data based on the enable control signal to generate the third data; the flip control signal includes a first control signal and a second control signal, and generating the flip control signal based on the value of the third data includes: generating the first control signal based on the third data and the enable control signal, and generating the second control signal based on the inverted signal of the third data and the enable control signal.

[0104] In some embodiments, step 403 includes: generating a pull-up control signal based on the value of the first data of the current bit and a first control signal, the pull-up control signal being used to pull up the value of the second data; and generating a pull-down control signal based on the value of the second data of the current bit and a second control signal, the pull-down control signal being used to pull down the value of the second data.

[0105] Specifically, if the pull-up control signal is valid and the pull-down control signal is invalid, the value of the second data is pulled up; if the pull-up control signal is invalid and the pull-down control signal is valid, the value of the second data is pulled down; if both the pull-up control signal and the pull-down control signal are invalid, the value of the second data of the current bit is directly generated based on the value of the second data of the previous bit.

[0106] It should be noted that the features disclosed in the data transmission method provided in the above embodiments can be arbitrarily combined without conflict to obtain new data transmission method embodiments.

[0107] Another embodiment of this disclosure provides a memory that uses the data transmission structure provided in the above embodiments for data transmission, so as to avoid invalid switching of the control signal of the control transistor in the driver, thereby avoiding invalid current consumption in the memory and reducing the power consumption of the memory.

[0108] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0109] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A data transmission structure, characterized in that, include: A data transmission module is configured to receive first data and a flip control signal, and to generate second data in response to the flip control signal and the first data. A control module, configured to receive the second data and an enable control signal, and to generate the flip control signal in response to the enable control signal and the second data; The enable control signal is used to enable the data transmission module to perform data transmission; The second data of the current bit is the same as the first data of the current bit. The flip control signal and the first data are used to turn off the data transmission module. The second data of the current bit is generated based on the second data of the previous bit. The second data of the current bit is different from the first data of the current bit. The flip control signal and the first data are used to turn on the data transmission module. The second data of the current bit is generated based on the first data of the current bit. The flip control signal includes a first control signal and a second control signal; The control module includes: A first control unit is configured to generate the first control signal based on the second data and the enable control signal; The second control unit is configured to generate the second control signal based on the second data and the enable control signal; When the enable control signal is valid, the generated first control signal and the second control signal are inverse signals.

2. The data transmission structure according to claim 1, characterized in that, The first control unit includes: a first NOR gate, one input terminal for receiving the second data, another input terminal for receiving the enable control signal, and an output terminal for outputting the first control signal.

3. The data transmission structure according to claim 1, characterized in that, The second control unit includes: a first NAND gate, one input terminal for receiving the second data, another input terminal connected to the output terminal of a first inverter, the output terminal for outputting the second control signal, and the input terminal of the first inverter for receiving the enable control signal.

4. The data transmission structure according to claim 1, characterized in that, The data transmission module includes: The second NAND gate has one input terminal for receiving the first data and the other input terminal for receiving the first control signal. The second NOR gate has one input terminal for receiving the first data and the other input terminal for receiving the second control signal. The P-type transistor has its gate connected to the output of the second NAND gate, its source coupled to the power supply voltage, and its drain used to output the second data. The N-type transistor has its gate connected to the output of the second NOR gate, its source grounded, and its drain connected to the drain of the P-type transistor.

5. The data transmission structure according to claim 1, characterized in that, The control module further includes: An input sampler, configured to receive the second data and the enable control signal, is configured to sample the second data and generate third data in response to an effective level of the enable control signal; The first control unit generates the first control signal based on the third data, and the second control unit generates the second control signal based on the third data.

6. The data transmission structure according to claim 5, characterized in that, The input sampler includes: a latch, with an input terminal for receiving the second data and a clock terminal for receiving the enable control signal.

7. The data transmission structure according to claim 6, characterized in that, The latch's clock input includes a positive clock input and a negative clock input. The positive clock input is connected to the output of the second inverter, and the negative clock input and the input of the second inverter are used to receive the enable control signal.

8. A data transmission method, applied to the data transmission structure described in any one of claims 1 to 7, characterized in that, include: A toggle control signal is generated based on the value of the second data bit of the previous bit and the enable control signal. Based on the value of the second data in the previous bit and the value of the first data in the current bit, determine whether it is necessary to transmit the value of the first data in the current bit to adjust the value of the second data; Based on the result of the judgment, in response to the flip control signal and the value of the first data of the current bit, the second data is generated.

9. The data transmission method according to claim 8, characterized in that, The step of determining whether it is necessary to transmit the value of the first data for the current bit to adjust the value of the second data includes: If the value of the second data bit in the previous bit is different from the value of the first data bit in the current bit, the result of the judgment is used to indicate the transmission of the value of the first data bit in the current bit to generate the value of the second data bit in the current bit; If the value of the second data in the previous bit is the same as the value of the first data in the current bit, the result of the judgment is used to indicate that the value of the second data in the current bit is directly generated based on the value of the second data in the previous bit.

10. The data transmission method according to claim 8, characterized in that, The step of generating a flip control signal based on the value of the previous bit of second data and an enable control signal includes: sampling the second data in response to the effective level of the enable control signal to generate third data, and generating the flip control signal based on the value of the third data.

11. The data transmission method according to claim 10, characterized in that, include: The third data is generated by sampling the value of the second data based on the enable control signal; The flip control signal includes a first control signal and a second control signal, and generating the flip control signal based on the value of the third data includes: The first control signal is generated based on the third data and the enable control signal, and the second control signal is generated based on the inverted signal of the third data and the enable control signal.

12. The data transmission method according to claim 11, characterized in that, The process of generating the second data in response to the toggle control signal and the value of the first data of the current bit includes: A pull-up control signal is generated based on the value of the first data of the current bit and the first control signal, and the pull-up control signal is used to pull up the value of the second data; A pull-down control signal is generated based on the value of the second data of the current bit and the second control signal, the pull-down control signal being used to pull down the value of the second data.

13. The data transmission method according to claim 12, characterized in that, include: If the pull-up control signal is valid and the pull-down control signal is invalid, pull up the value of the second data. If the pull-up control signal is invalid and the pull-down control signal is valid, pull down the value of the second data. If both the pull-up control signal and the pull-down control signal are invalid, the value of the second data in the current bit is directly generated based on the value of the second data in the previous bit.

14. A memory, characterized in that, Data transmission is performed using the data transmission structure described in any one of claims 1 to 7.

Images