Memory devices, memory systems, and methods of operating the same

Abstract

The present application relates to a memory device, a memory system, and an operating method thereof. The memory device includes a first memory group and a control device. The first memory group includes a first nonvolatile memory cell storing multi-bit data. The control device performs a plurality of programming operations to store the multi-bit data in the first nonvolatile memory cell. In accordance with a program state of the first nonvolatile memory cell while the plurality of programming operations are performed, the control device performs a read operation for acquiring bit data of the multi-bit data that has been programmed in the first nonvolatile memory cell in response to a read command before the most significant bit data of the multi-bit data is programmed in the first nonvolatile memory cell. The control device outputs data obtained in response to the read command.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2022-0084914, filed on July 11, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory system and a method of operating the same, and more specifically, to an apparatus and method for programming or retrieving data in a non-volatile memory device of a memory system. Background Technology

[0004] A data processing system includes a memory system or a data storage device. A data processing system can be evolved to store larger amounts of data in the data storage device, to store data faster in the data storage device, and to retrieve data stored in the data storage device faster. The memory system or data storage device may include non-volatile memory cells and / or volatile memory cells for storing data. Summary of the Invention

[0005] The embodiments in this disclosure can provide a memory system, a data processing system, and an operating process or method that can quickly and reliably process data into a memory device by reducing the operational complexity and performance degradation of the memory system, thereby improving the utilization efficiency of the memory device.

[0006] Embodiments of this disclosure may provide apparatus or methods for improving the input / output performance of a memory system.

[0007] In an embodiment, a memory device may include: a first memory bank including a first non-volatile memory cell configured to store multiple bits of data; and a control device configured to: perform a plurality of programming operations to store the multiple bits of data in the first non-volatile memory cell; and, while performing the plurality of programming operations, according to the programming state of the first non-volatile memory cell, before the most significant bit of the multiple bits of data is programmed into the first non-volatile memory cell, in response to a read command to perform a read operation to obtain the bit data of the multiple bits of data that has been programmed into the first non-volatile memory cell; and output the bit data corresponding to the read command.

[0008] The memory device can be configured to determine the programming state based on the number of bits of data programmed into the first non-volatile memory cell.

[0009] The control device can be further configured to change the level of the read voltage applied to the first non-volatile memory cell during a read operation, based on the programming state of the first non-volatile memory cell.

[0010] The control device is further configured to increase the level of the read voltage applied to the first non-volatile memory cell to read the least significant bit data as the number of bits of data programmed into the first non-volatile memory cell increases.

[0011] The control device can be configured to perform multiple programming operations in a first non-volatile memory cell in the order of least significant bit data to most significant bit data among multiple bits of data.

[0012] The memory device may further include a data buffer configured to temporarily store write data comprising multi-bit data to be stored in the first non-volatile memory cell. The control device may be further configured to remove the portion of the write data corresponding to the bit data from the data buffer after the bit data has been programmed into the first non-volatile memory cell and before all data in the multi-bit data has been programmed into the first non-volatile memory cell.

[0013] The memory system may further include a second memory bank comprising second non-volatile memory cells that store flags corresponding to the programming state of the first non-volatile memory cell. The control device may be further configured to read the flags stored in the second non-volatile memory cell before performing a read operation on the first non-volatile memory cell to identify the programming state of the first non-volatile memory cell.

[0014] The control device can be further configured to perform error correction operations on data obtained from the first memory group while skipping the error correction operation on the flags obtained from the second memory group.

[0015] The memory device may further include a register configured to record information indicating whether a programming operation performed on bit data that was most recently programmed into a first non-volatile memory cell has been completed.

[0016] The control device can be further configured to perform a programming status check operation on the first non-volatile memory cell to identify the programming status based on the information recorded in the register.

[0017] In another embodiment, a method of operating a memory system may include: programming least significant bit data of a plurality of bits into a first non-volatile memory cell configured to store the plurality of bits; performing a read operation on the least significant bit data programmed into the first non-volatile memory cell in response to a read command before programming the most significant bit data of the plurality of bits into the first non-volatile memory cell; and outputting the least significant bit data to an external device in response to the read command.

[0018] The method may further include programming a flag into a second non-volatile memory cell, the flag indicating whether programming of the least significant bit data in the first non-volatile memory cell is complete; programming the bits of the multi-bit data other than the least significant bit data in the first non-volatile memory cell; and updating the flag in response to whether programming of the bits of the multi-bit data other than the least significant bit data is complete.

[0019] The method may further include: when the bit data other than the least significant bit data is the most significant bit data, terminating the programming operation in the first non-volatile memory cell after completing the programming of the bit data; when the bit data other than the least significant bit data is not the most significant bit data, programming another bit data other than the least significant bit data in the first non-volatile memory cell; and updating the flag according to whether the programming of the other bit data other than the least significant bit data is completed.

[0020] The method may further include: after programming of the least significant bit data is completed, storing an indicator indicating whether programming of the least significant bit data is completed in a register; programming the bit data other than the least significant bit data in a first non-volatile memory cell; and updating the indicator stored in the register according to the completion of programming of the bit data other than the least significant bit data.

[0021] Performing a read operation may include: determining the level of a read voltage based on the programming state of a first non-volatile memory cell; and reading the least significant bit data by applying a read voltage with the determined level to the first non-volatile memory cell.

[0022] The method may further include determining the programming state based on the number of bits of data programmed into the first non-volatile memory cell from among the multiple bits of data.

[0023] Multiple bits of data can be programmed into the first non-volatile memory cell in order from least significant bit to most significant bit. As the number of bits of data programmed into the first non-volatile memory cell increases, the read voltage level increases.

[0024] In another embodiment, a memory system may include: a memory die including a first non-volatile memory cell configured to store multiple bits of data; and a controller configured to, in response to a read command, read bit data that has been programmed into the first non-volatile memory cell according to the state of the first non-volatile memory cell before the most significant bit of the multiple bits of data is programmed into the first non-volatile memory cell, wherein the bit data is part of the multiple bits of data.

[0025] The memory system may further include a data buffer configured to temporarily store write data comprising multi-bit data to be stored in the first non-volatile memory cell. The controller may be further configured to remove the portion of the write data corresponding to the bit data from the data buffer after the bit data has been programmed into the first non-volatile memory cell and before all the data in the multi-bit data has been programmed into the first non-volatile memory cell.

[0026] The controller can be configured to determine the programming state based on the number of bits of data programmed into the first non-volatile memory cell from among multiple bits of data. The controller is configured to determine the level of the read voltage based on the programming state, and to perform a read operation to obtain the bit data by applying the read voltage to the first non-volatile memory cell.

[0027] In one embodiment, a method of operating a controller may include: controlling a memory device to sequentially program a sequence of data bits of a multi-bit data, while recording information indicating that programming is completed sequentially each time each data bit of the sequence is programmed; and controlling the memory device to read the programmed data bits in the sequence before completing the programming of the multi-bit data by determining a read voltage for reading based on information recorded at the read time point. Attached Figure Description

[0028] The description herein refers to the accompanying drawings, in which the same reference numerals refer to the same parts throughout the drawings.

[0029] Figure 1 A memory system according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A data processing system according to an embodiment of the present disclosure is shown.

[0031] Figure 3 A memory system according to another embodiment of the present disclosure is shown.

[0032] Figure 4 References to embodiments of the present disclosure are shown. Figures 1 to 3 The inner layer of the controller described.

[0033] Figure 5 A memory device according to an embodiment of the present disclosure is shown.

[0034] Figure 6 A first example of programming multi-bit data into a non-volatile memory cell is shown according to an embodiment of the present disclosure.

[0035] Figure 7 A second example of programming multi-bit data into a non-volatile memory cell is shown according to an embodiment of the present disclosure.

[0036] Figure 8 A third example of programming multi-bit data into a non-volatile memory cell is shown according to embodiments of the present disclosure.

[0037] Figure 9 A first example of programming operations performed within a memory system according to another embodiment of the present disclosure is shown.

[0038] Figure 10 The diagram illustrates the level variation of the read voltage for LSB data based on the programming state of a non-volatile memory cell, according to an embodiment of the present disclosure.

[0039] Figure 11 A first example of a read operation performed within a memory system according to another embodiment of the present disclosure is shown.

[0040] Figure 12 Embodiments according to this disclosure are shown Figure 11 The operation margin for the read operation is shown.

[0041] Figure 13 The illustration shows a read voltage having a level determined in response to a flag, according to an embodiment of the present disclosure.

[0042] Figure 14 A second example of a read operation performed within a memory system according to another embodiment of the present disclosure is shown.

[0043] Figure 15 Embodiments according to this disclosure are shown Figure 14 The operation margin for the read operation is shown.

[0044] Figure 16 The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a first programming method is shown in an embodiment of the present disclosure.

[0045] Figure 17 The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a second programming method is shown in an embodiment of the present disclosure.

[0046] Figure 18The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a third programming method is shown in an embodiment of the present disclosure. Detailed Implementation

[0047] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. The elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0048] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0049] In this disclosure, the terms “comprising,” “including,” “including,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. Furthermore, the terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0050] In this disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when a specified block / unit / circuit / component is not currently operational, e.g., not switched on or activated, it may be said that the block / unit / circuit / component is configured to perform a task. Blocks / units / circuits / components used with "configured to" include hardware, such as circuits, memory storing program instructions operable to perform the operation, etc. Furthermore, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors running software) in a manner capable of performing a task to be solved. "Configured to" may also include means (e.g., integrated circuits) that adapt a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means suitable for implementing or performing one or more tasks.

[0051] As used in this disclosure, the term "circuit" or "logic" means all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only) and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors, or (ii) a portion of a processor / software (including digital signal processors, software, and memory that work together to enable a device such as a mobile phone or server to perform various functions), and (c) a circuitry that requires software or firmware for operation, such as a microprocessor or a portion of a microprocessor, even if the software or firmware does not actually exist. This definition of "circuit" or "logic" applies to all uses of the term in this application, including in any claim. As a further example, the term "circuit" or "logic" as used in this application also covers implementations of a processor (or processors) or a portion of a processor and its (or their) accompanying software and / or firmware. Where applicable to a particularly stated element, the term "circuit" or "logic" also covers integrated circuits, such as memory devices.

[0052] In this document, the terms “first,” “second,” “third,” etc., are used as labels for nouns; they precede the nouns and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, although these terms can be used to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0053] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on those factors or at least partially on those factors. Consider the phrase "A is determined based on B." Although B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0054] Here, a data entry, the data of an entry, a piece of data, or a data item can be a sequence of bits. For example, a data entry can include the contents of a file, a portion of that file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a series of bits. According to an embodiment, a data entry can include discrete objects. According to another embodiment, a data entry can include units of information processed or disposed of for data input / output operations. According to another embodiment, a data entry can include units of information within a transmission packet between two different components.

[0055] The embodiments described herein can provide devices and methods for improving data input / output operations of memory systems or data processing systems.

[0056] Embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0057] Figure 1 A memory system according to an embodiment of the present disclosure is illustrated. The memory system 110 can store data entries and output the stored data entries. The memory system 110 may include areas capable of storing data entries, and control means capable of performing operations for storing, erasing, or retrieving data entries. Reference will be made later. Figures 2 to 3 Examples of components included in memory system 110 are described.

[0058] Reference Figure 1 The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and controller 130 included in the memory system 110 may be physically separate components. The memory device 150 and controller 130 may be interconnected via at least one data path or at least one communication line. For example, the data path and communication line may include channels and / or pathways.

[0059] According to an embodiment, the memory device 150 and the controller 130 can be functionally separate components. Furthermore, according to an embodiment, the memory device 150 and the controller 130 can be implemented using a single chip or multiple chips.

[0060] The controller 130 may include a flash translation layer (FTL) 240 and an input / output control module 260. The flash translation layer (FTL) 240 included in the controller 130 can perform data processing operations for transferring data from external devices (e.g., host 102, see below). Figure 2 Data entries (e.g., host data) are transmitted to memory device 150 for storage. Because the address scheme used by the external device (e.g., logical address scheme) and the address scheme used within memory system 110 (e.g., physical address scheme) are different, the flash translation layer (FTL) 240 can determine the location where the data entries are stored in memory device 150. Furthermore, the flash translation layer (FTL) 240 can generate mapping information or mapped data entries to associate the logical and physical addresses of the data entries. Here, the logical address of the data entry can be determined by host 102, while the physical address of the data entry can be determined by memory system 110.

[0061] The input / output control module 260 can control the operation of storing data entries transferred from the flash translation layer (FTL) 240 in the memory device 150. The memory device 150 may include multiple memory planes, each including multiple non-volatile memory cells. Data input / output operations can be performed in parallel within the memory device 150 to improve input / output performance. For example, when the input / output control module 260 sends a read command to the memory device 150, each of the multiple memory planes in the memory device 150 can read data entries stored in multiple memory cells and output the read data entries to the input / output control module 260 via a channel. Furthermore, the input / output control module 260 can schedule data input / output operations performed in multiple memory planes or multiple regions, such as the first non-volatile cell region 292 and the second non-volatile cell region 294.

[0062] According to an embodiment, the input / output control module 260 may be included in... Figures 2 to 3 The memory interface 142 shown is included. According to another embodiment, the input / output control module 260 may be arranged in the flash memory translation layer (FTL) 240 and... Figure 2 and Figure 3 The memory interface 142 shown is between.

[0063] Reference Figure 1 The memory device 150 may include multiple regions, such as a first non-volatile cell region 292 and a second non-volatile cell region 294. For example, the multiple regions may be included in a single memory die or a single memory plane. The memory die may include at least one of the memory planes. A memory die can be understood as a component type implemented on a physically distinguishable substrate. Each memory die may be connected to the controller 130 via a data path and includes an interface for exchanging data entries and signals with the controller 130.

[0064] According to an embodiment, the memory device 150 may include multiple memory planes. A memory plane may include at least one memory block, drive circuitry configured to control an array comprising multiple non-volatile memory cells, and at least one buffer configured to temporarily store data input to or output from the multiple non-volatile memory cells. A memory plane can be understood as a logical or physical partition comprising multiple components.

[0065] Multiple regions, such as the first non-volatile cell region 292 and the second non-volatile cell region 294, may include multiple memory blocks 152, 154, and 156 (see [link to documentation]). Figure 2A memory block can be understood as a set of non-volatile memory cells from which data is erased together during an erase operation. Memory blocks 152, 154, and 156 may include pages, which are sets of non-volatile memory cells that store data together during programming operations or output data together during read operations. For example, data output from a page can be output to controller 130 via data latches and cache latches. Each of memory blocks 152, 154, and 156 may include multiple pages. (See reference...) Figure 1 The internal configuration of the described memory device 150 can be changed in response to the operational performance of the memory system 110. Embodiments of this disclosure are not limited to those described herein. Figure 1 The internal configuration is described. See below for further details. Figure 5 The configuration and operation of memory device 150 are described.

[0066] Reference Figure 1 The memory system 110 includes multiple regions 292, 294, which may include multiple non-volatile memory cells. For example, the multiple regions 292, 294 may include a first non-volatile cell region 292 and a second non-volatile cell region 294. The first non-volatile cell region 292 and the second non-volatile cell region 294 may include multiple memory cells, each memory cell being configured to store multiple bits of data.

[0067] According to an embodiment, the first non-volatile cell region 292 may store data entries, while the second non-volatile cell region 294 may store flags. Here, data entries may include data from an external device (e.g., reference 110) obtained by the memory system 110 from the external device. Figure 2 and Figure 3 The host 102 receives write data or metadata for internal operations in the memory system 110. Flags may include information indicating the programming state of a non-volatile memory cell included in the first non-volatile cell region 292. In another embodiment, data other than flags may be stored in a second non-volatile cell region 294. According to an embodiment, flags may be stored in volatile memory included in or used by the controller 130 (e.g., ...). Figure 2 and Figure 3 The memory 144 described in the document.

[0068] According to an embodiment, the first non-volatile cell region 292 and the second non-volatile cell region 294 included in the memory system 110 can store different types of data. For example, the first non-volatile cell region 292 can store data entries to be stored in the memory system 110, transferred from an external device. The second non-volatile cell region 294 can store parity information of the data entries stored in the first non-volatile cell region 292. Here, when an interruption or error occurs during the operation of programming data into the first non-volatile cell region 292, the parity information can be used to recover the data programmed into the first non-volatile cell region 292.

[0069] The operation of programming multiple bits of data into a first non-volatile cell region 292, which includes memory cells capable of storing multiple bits of data, can be performed in several steps. Alternatively, multiple programming operations can be performed in the first non-volatile cell region 292 to program multiple bits of data into it. According to an embodiment, the memory system 110 can perform two-step or multi-step programming operations to program multiple bits of data. In another embodiment, the memory system 110 can perform fuzzy programming and fine programming operations to program multiple bits of data. Referring later... Figures 6 to 8 Describes the operation performed by memory system 110 to store multiple bits of data.

[0070] A one-shot programming operation can be performed through multiple programming operations, in which multiple ISPP step pulses are applied consecutively to program multiple bits of data into a non-volatile memory cell until the non-volatile memory cell connected to a specific word line of the first non-volatile cell region 292 is fully programmed with multiple bits of data. In a one-shot programming operation, multiple programming pulses are applied alternately to multiple word lines to perform multiple programming operations on multiple bits of data. When a programming operation is performed through a specific word line, another programming operation can be performed without going through another word line. However, as the integration density of the first non-volatile cell region 292 increases, a significant amount of inter-cell interference can occur between non-volatile memory cells when there is no programming operation interleaving between adjacent word lines (e.g., between the word line performing the programming operation and another word line immediately adjacent to it).

[0071] To reduce interference during programming operations, a two-step programming method can be used to store multi-bit data in non-volatile memory cells included in the first non-volatile cell region 292. In the two-step programming method, LSB data can first be programmed into a non-volatile memory cell having a threshold voltage corresponding to the erase state (first-step programming operation), and then MSB data can be programmed into a non-volatile memory cell (second-step programming operation). For example, after an LSB data entry is programmed into a non-volatile memory cell connected to a specific word line, another LSB data entry can be programmed into a non-volatile memory cell connected to another word line adjacent to the specific word line. By programming LSB data entries into non-volatile memory cells connected to multiple word lines, and then sequentially programming MSB data entries into non-volatile memory cells after the LSB data entries are programmed, inter-cell interference can be reduced.

[0072] In memory system 110, the size of data entries stored in non-volatile memory cells connected to multiple word lines via a two-step or multi-step programming method is larger than the size of data entries programmed into non-volatile memory cells connected to a single word line. Because a large number of data entries are alternately programmed into non-volatile memory cells connected to multiple word lines via a two-step or multi-step programming method, the programming operation can take a long time. Therefore, the time spent holding write data in data buffer 270, which is configured to store write data to be programmed into the first non-volatile cell region 292, may increase.

[0073] As the memory device 150 is configured to store more data, the size of the data entries stored in the first non-volatile cell region 292 increases. For example, the size of the pages included in the first non-volatile cell region 292 increases. When it is determined that the amount of write data to be programmed into the plurality of non-volatile memory cells included in the first non-volatile cell region 292 is sufficient, the plurality of non-volatile memory cells included in the first non-volatile cell region 292 can be programmed with multiple bits of data. The programming operation of the plurality of non-volatile memory cells can be completed when the plurality of non-volatile memory cells are programmed from least significant bit (LSB) data to most significant bit (MSB) data.

[0074] On the other hand, when the size of the write data is insufficient, multiple bits of data may not be programmed into the multiple non-volatile memory cells included in the first non-volatile cell region 292. When some bits of data (e.g., LSB data) are programmed into multiple non-volatile memory cells and no more data is written, it is impossible to program the MSB data in the corresponding non-volatile memory cell. In this case, programming the corresponding non-volatile memory cell may not be possible.

[0075] To avoid the programming operation failing, the controller 130 can program virtual data, rather than write data, to the corresponding non-volatile memory cell. Virtual data can be considered useless data, but its advantage lies in the ability to quickly complete the programming operation to the corresponding non-volatile memory cell. When the programming operation is complete, the controller 130 can delete or release the write data stored in the data buffer 270. Therefore, the resource utilization in the memory system 110 can be increased.

[0076] The size of the data buffer 270 in memory 144 may not be fixed, but can be dynamically established. If the controller 130 does not delete the written data stored in the data buffer 270 while the programming operation is incomplete, the resource utilization in memory system 110 will be reduced. When written data remains in data buffer 270, memory system 110 may not be able to obtain resources for another input / output operation, thus potentially reducing the I / O performance of memory system 110.

[0077] Even if written data is programmed into a non-volatile memory cell, the memory system 110 should retain the written data in the data buffer 270 when the programming operation for the corresponding non-volatile memory cell has not fully programmed multiple bits of data. This is because errors are highly likely to occur when reading data programmed into a non-volatile memory cell while the programming operation for the non-volatile memory cell has not fully programmed multiple bits of data. According to embodiments of this disclosure, the level of the read voltage can be changed in response to the programming state of the non-volatile memory cell. If the level of the read voltage is adjusted, the probability of errors occurring when reading a non-volatile memory cell when the programming operation is not complete (e.g., when some bits of multiple bits of data are programmed) may be reduced. Therefore, the bit data stored in the non-volatile memory cell can be read when some bits of multiple bits of data are stored in the non-volatile memory cell (i.e., MSB data has not been programmed into the non-volatile memory cell). Therefore, the controller 130 can release or delete the write data corresponding to the bit data programmed into the non-volatile memory cell from the data buffer 270, thereby improving the resource utilization of the memory system 110.

[0078] The memory system 110 can adjust the level of the read voltage applied to the non-volatile memory cells and control the data buffer 270 based on a programming operation regarding whether some bits of data among multiple bits of data are programmed into the non-volatile memory cells, even if the non-volatile memory cells are not fully programmed with multiple bits of data. According to an embodiment, the memory device 150 can program a flag corresponding to the programming state of the non-volatile memory cells included in the first non-volatile memory region 292 into the second non-volatile memory region 294. For example, after the memory device 150 programs LSB data into the non-volatile memory cells included in the first non-volatile memory region 292, a flag corresponding to the LSB data can be programmed into the non-volatile memory cells included in the second non-volatile memory region 294. After the memory device 150 programs the center significant bit (CSB) data into the non-volatile memory cells in the first non-volatile memory region 292 that have already been programmed with LSB data, the flag corresponding to the CSB data can be updated in the second non-volatile memory region 294. According to an embodiment, the third bit data, the fourth bit data, or more bits of data can be stored in a memory cell included in the first non-volatile cell region 292, and the flag stored in the second non-volatile cell region 294 can be updated or stored based on the third bit data, the fourth bit data, or more bits of data programmed into the memory cell included in the first non-volatile cell region 292.

[0079] For example, when the first programming operation is completed in the first non-volatile cell region 292, the memory system 110 can recognize that at least some bits of data corresponding to the first programming operation have been programmed into the non-volatile memory cells of the first non-volatile cell region 522. After the first programming operation is completed in the first non-volatile cell region 292 of the memory system 110, a second programming operation can be performed in the first non-volatile cell region 292, or before performing the second programming operation, a read operation on at least some bits of data that have been programmed by the first programming operation can be performed in the first non-volatile cell region 292. Whenever a step-by-step (or multi-step) programming operation is completed in the first non-volatile cell region 292, the memory device 150 can notify the controller 130 that the programming operation of the corresponding step has been completed. Here, each programming operation may include a programming operation for programming at least one bit of data into the non-volatile memory cells included in the first non-volatile cell region 292.

[0080] The controller 130 can release or delete some of the written data stored in the data buffer 270 in response to the completion of each programming operation. This written data corresponds to at least some bits of data programmed into the memory device 150. When a read command is input from an external device to retrieve data deleted from the data buffer 270, the controller 130 can perform a read operation on at least some bits of data programmed into the non-volatile memory cell of the memory device 150, even though the MSB data has not been programmed into the corresponding non-volatile memory cell.

[0081] During step-by-step programming of non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells in the first non-volatile cell region 292 can change. As more bits of data are programmed into the corresponding non-volatile memory cells, that is, as more programming operations to program the bits of data into the corresponding non-volatile memory cells are completed, the threshold voltage distribution of the non-volatile memory cells shifts in a specific direction (e.g., Figure 10 Offset to the right along the horizontal axis (as shown). (Refer to...) Figure 10 When the third bit of data is programmed into the non-volatile memory cell, the threshold voltage distribution corresponding to the LSB data can be shifted more to the right than when the second bit of data is stored in the non-volatile memory cell. Therefore, the memory system 110 can change the level of the read voltage applied to read the data stored in the non-volatile memory cell in response to the programming state of the non-volatile memory cell.

[0082] Before performing a read operation on the bit data programmed into the first non-volatile cell region 292, the controller 130 may check the programming state of the non-volatile memory cells included in the first non-volatile cell region 292. According to an embodiment, if a flag indicating the programming state of the non-volatile memory cells included in the first non-volatile cell region 292 is stored in a second non-volatile cell region 294 of the memory device 150, the controller 130 may read the flag in the second non-volatile memory cell 294 to identify the programming state of the non-volatile memory cells included in the first non-volatile cell region 292. Hereinafter, reference will be made to… Figures 11 to 13 Embodiments of this disclosure are described.

[0083] According to an embodiment, when there is no area for storing markers in the memory device 150, the controller 130 may perform an operation to check the programming state of the first non-volatile cell region 292 before performing a read operation in the first non-volatile cell region 292. Here, the programming state check operation may include a check operation (e.g., a state check command operation) for checking the operating state of the memory device 150, which includes a step program operation to determine whether a step (or multi-step) programming operation has been completed. Referring below... Figures 14 to 18 Embodiments of this disclosure are described.

[0084] In the following text, reference will be made to Figures 2 to 18 The operation of the above-described memory system will be described in detail. Specifically, refer to... Figures 2 to 4 Describe the controllers included in the memory system, and refer to Figure 5 Describe the non-volatile memory devices included in the memory system. Further, reference will be made to... Figures 6 to 8 Describes systems and schemes for programming multiple data entries and parity entries into a memory device.

[0085] Figure 2 and Figure 3 This illustrates some operations that can be performed by the memory system 110 according to one or more embodiments of the present disclosure.

[0086] Reference Figure 2 The data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as memory system 110. For example, the host 102 and memory system 110 may be interconnected via a data bus, host cable, etc. to perform data communication.

[0087] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 may be considered as fundamentally separate components or elements. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a path.

[0088] According to embodiments, the memory device 150 and the controller 130 may be functionally divided components or elements. Further, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to a request from an external device. For example, when the controller 130 performs a read operation in response to a read request from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0089] like Figure 2 As shown, memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together by a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages, which are groups of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages.

[0090] For example, memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition, which includes at least one memory block, drive circuitry capable of controlling an array comprising multiple non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0091] Additionally, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a set of components implemented on a practically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging items and signals with the controller 130.

[0092] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Depending on the performance of the memory system 110, Figure 1 and Figure 2 The internal configuration of the memory device 150 shown may differ. The embodiments disclosed herein are not limited to those described above. Figure 2 The internal configuration shown.

[0093] Reference Figure 2The memory device 150 may include a voltage supply circuit 170 capable of supplying at least some voltages to the memory blocks 152, 154, and 156. The voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells included in the memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells included in the memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read operation or programming operation performed on the selected non-volatile memory cell, the voltage supply circuit 170 may supply the pass voltage Vpass to the selected non-volatile memory cell. During the erase operation that erases the data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 can supply erase voltage Vers to the memory blocks.

[0094] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on the type of operation being performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd may be needed to identify or read multiple data entries. Memory device 150 may include a table containing information corresponding to multiple levels of read voltage Vrd corresponding to multiple data entries. For example, the table may include bias values ​​stored in a register, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​of read voltage Vrd used for read operations may be limited to a preset range. Moreover, the bias values ​​may be quantized.

[0095] The host 102 may include portable electronic devices, such as mobile phones, MP3 players, and laptops, or non-portable electronic devices, such as desktop computers, game consoles, TVs, and projectors.

[0096] Host 102 may also include at least one operating system (OS) that controls the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operatively coupled to memory system 110, and a user intended to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, based on the mobility of host 102, OS can be classified as general-purpose operating system and mobile operating system. Based on system requirements or user environment, general-purpose operating systems can be categorized as personal operating systems and enterprise operating systems. Compared to personal operating systems, enterprise operating systems can be specifically designed to ensure and support high-performance computing.

[0097] A mobile operating system can be used to support services or functions for mobility, such as power-saving features. Host 102 may include multiple operating systems. Host 102 can run multiple operating systems associated with memory system 110 corresponding to user requests. Host 102 can send multiple commands corresponding to user requests to memory system 110, thereby executing operations corresponding to multiple commands within memory system 110.

[0098] The controller 130 in the memory system 110 can control the memory device 150 in response to requests or commands input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102, and can perform a write operation (or programming operation) to store data input from the host 102 in the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0099] According to an embodiment, controller 130 may include host interface 132, processor 134, error correction circuitry 138, power management unit (PMU) 140, memory interface 142, and memory 144. Regarding memory system 110, as... Figure 2 The components included in the controller 130 shown can vary depending on the structure, function, and operational performance.

[0100] For example, depending on the host interface protocol, the memory system 110 can be implemented using any of a variety of storage devices that can be electrically connected to the host 102. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of the memory system 110, these components can be added to or omitted from the controller 130.

[0101] Both host 102 and memory system 110 may include a controller or an interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include a device capable of sending signals, data, etc., to host 102 or receiving signals, data, etc., from host 102.

[0102] The host interface 132 included in controller 130 can receive signals, commands (or requests), and / or data input from host 102 via a bus. For example, host 102 and memory system 110 can use a predetermined set of rules or procedures or preset interfaces for data communication to send and receive data between them. Examples of multiple sets of rules or procedures for data communication standards or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industrial Processor Interface (MIPI), etc. According to an embodiment, host interface 132 is a layer for exchanging data with host 102 and is driven by or implemented using firmware called the Host Interface Layer (HIL). According to an embodiment, host interface 132 may include a command queue.

[0103] Electronic Integrated Drive (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master and slave by using the positions or DIP switches to which the multiple memory systems 110 are connected. The memory system 110 set as master can be used as the main memory device. IDE (ATA) can include, for example, Fast ATA, ATAPI, and Enhanced IDE (EIDE).

[0104] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Electronic Drive (IDE) devices. The 40 wires in an IDE interface can be reduced to six wires in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. The SATA interface has been widely used due to its faster data transmission and reception rates and its lower resource consumption in the host 102 for data transmission and reception. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. Furthermore, the SATA interface supports hot-plugging, allowing external devices to be attached to or detached from the host 102 even while data communication between the host 102 and another device is in progress. Therefore, even when the host 102 is powered on, the memory system 110 can be connected or disconnected as an additional device, just like a device supported by Universal Serial Bus (USB). For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or removed from the host 102 like an external hard drive.

[0105] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI can provide higher transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, it is easy to connect or disconnect devices such as memory system 110 from the host 102. SCSI can support connecting up to 15 other devices to a single transceiver included in the host 102.

[0106] Serial SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed using a serial data communication scheme. SAS supports the connection between the host 102 and peripheral devices via serial cables instead of parallel cables, making it easy to manage equipment and enhance or improve operational reliability and communication performance. SAS can support connecting up to eight external devices to a single transceiver included in the host 102.

[0107] High-speed non-volatile memory (NVMe) is an interface based at least on high-speed peripheral component interconnect (PCIe), which is designed to improve the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, 82 pins, etc.) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication exceeding several hundred MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). According to embodiments, PCIe schemes can achieve bandwidths from tens to several gigabits per second. NVMe can support faster operating speeds than hard drives for memory systems 110, such as SSDs.

[0108] According to one embodiment, the host 102 and the memory system 110 can be connected via a Universal Serial Bus (USB). USB is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between the host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as the memory system 110, can be connected to a single transceiver included in the host 102.

[0109] Reference Figure 2Error correction circuit 138 can correct error bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on the data to be programmed into memory device 150 to generate encoded data with added check bits, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct error bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful or unsuccessful, and outputs a command signal, such as a correction success signal or a correction failure signal, based on the result of error correction decoding. Error correction circuit 138 can use check bits generated for the data stored in memory device 150 during the ECC encoding process to correct error bits in the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, error correction circuit 138 may not correct the error bits, but may instead output a correction failure signal indicating that the correction of error bits failed.

[0110] According to embodiments, the error correction circuit 138 can perform error correction operations based on codes such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the aforementioned codes.

[0111] For example, the ECC decoder can perform hard-decision decoding or soft-decision decoding on data sent from memory device 150. Hard-decision decoding can be understood as one of two methods broadly classified for error correction. Hard-decision decoding may include the operation of correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler than soft-decision decoding, and the processing speed can be faster.

[0112] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantization values, such as multi-bit data, approximations, analog values, etc., to correct erroneous bits based on the two or more quantization values. Controller 130 can receive two or more letters or quantization values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantization values ​​as a combination of information such as conditional probabilities or likelihoods.

[0113] According to an embodiment, the ECC decoder can use low-density parity-check and generator matrix (LDPC-GM) codes, which are part of a method designed for soft-decision decoding. The low-density parity-check (LDPC) code uses an algorithm that reliably uses values ​​that can be read from the memory device 150 in several bits, rather than simply using data 1 or 0 as in hard-decision decoding, and iteratively repeats this process through message exchange to improve the reliability of the values. The value is then finally determined to be data 1 or 0. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from a non-volatile memory cell is decoded as 0 or 1. Compared to hard-decision decoding, soft-decision decoding can determine the value stored in a non-volatile memory cell based on random information. Regarding bit flips that can be considered errors that may occur in the memory device 150, soft-decision decoding can provide an improved probability of correcting errors and recovering data, as well as providing the reliability and stability of the corrected data. The LDPC-GM code can have a scheme where the internal LDGM code can be concatenated with a high-speed LDPC code.

[0114] According to embodiments, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can have a scheme using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0115] According to an embodiment, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes, such as Hamming codes, and can be repeatedly decoded in both row and column directions to improve the reliability of the values.

[0116] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, such as the voltage supplied to the controller 130, and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to cause the memory system 110 to perform an emergency backup of its current state when the power supply to the memory system 110 is unstable. According to an embodiment, the PMU 140 may include a device or component capable of accumulating power that can be used in an emergency.

[0117] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, allowing the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0118] For example, when memory device 150 includes NAND flash memory, memory interface 142 includes a NAND flash memory controller (NFC). Memory interface 142 can provide an interface for processing commands and data between controller 130 and memory device 150. According to embodiments, memory interface 142 can be implemented by or driven by firmware called a flash interface layer (FIL) to exchange data with memory device 150.

[0119] According to an embodiment, memory interface 142 may support an Open NAND Flash Interface (ONFi), switching modes, etc., for data input / output with memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between controller 130 and memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0120] Memory 144 can serve as working memory for either memory system 110 or controller 130 when temporarily storing transaction data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store data entries read from memory device 150 in response to a read request from host 102 before outputting read data entries to host 102. Additionally, controller 130 can temporarily store write data entries input from host 102 in memory 144 before programming write data entries into memory device 150. When controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of memory device 150, data transferred between controller 130 and memory device 150 in memory system 110 can be temporarily stored in memory 144.

[0121] In addition to read or write data entries, memory 144 may store information for inputting or outputting data between host 102 and memory device 150, such as mapped data, read requests, programming requests, etc. According to embodiments, memory 144 may include one or more of command queues, program memory, data memory, write buffers / caches, read buffers / caches, data buffers / caches, mapping buffers / caches, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data subject to programming operations.

[0122] In this embodiment, memory 144 may be implemented using volatile memory. For example, memory 144 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 As shown, for example, memory 144 is disposed within controller 130, but the embodiment is not limited thereto. Memory 144 may be located within or outside controller 130. For example, memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and / or signals between memory 144 and controller 130.

[0123] Processor 134 can control all operations of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to a write or read request input from host 102. According to an embodiment, processor 134 can run firmware to control programming or reading operations in memory system 110. In this document, firmware may be referred to as a flash translation layer (FTL). Reference will be made later. Figure 3 and Figure 4Examples of FTL described in detail. According to embodiments, processor 134 can be implemented using a microprocessor, a central processing unit (CPU), etc.

[0124] According to an embodiment, the memory system 110 can be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores, which are considered different processing regions. For example, when multiple cores in a multi-core processor independently drive or run multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0125] The processor 134 in the controller 130 can execute operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent as setting commands from the host 102 can be considered foreground operations. Background operations that can be performed by the controller 130 without commands sent from the host 102 include garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0126] According to embodiments, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection independently of the host 102 (e.g., automatic GC).

[0127] When the memory device 150 includes multiple dies (or chips), each comprising non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups, including at least some of the multiple planes, dies, or chips included in the memory device 150, and multiple groups of requests or commands can be processed individually or in parallel within each plane, each chip, or each chip.

[0128] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 allocates and stores data in multiple dies via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel in multiple dies or planes. This processing method or scheme can be considered as interleaving. Since the data input / output speed of memory system 110 is increased by operating in an interleaved manner, the data I / O performance of memory system 110 can be improved.

[0129] As an example and not a limitation, controller 130 may identify the state of multiple channels (or pathways) associated with multiple memory dies included in memory device 150. Controller 130 may determine the state of each channel or pathway as one of a busy state, ready state, active state, idle state, normal state, and / or abnormal state. Determining which channel (and / or data) the controller transmits instructions (and / or data) through may be associated with a physical block address. Controller 130 may reference descriptors transmitted from memory device 150. Descriptors may include blocks or pages describing parameters about memory device 150. Descriptors may have a predetermined format or structure. For example, descriptors may include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 may refer to or use descriptors to determine which channel(s) or pathway is used to exchange instructions or data.

[0130] Reference Figure 2 As shown, the memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. Memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0131] In an embodiment, each memory block 152, 154, or 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, and 156. The configuration of the memory device 150 can be varied depending on the performance of the memory system 110.

[0132] Figure 2The diagram illustrates more than 150 memory blocks 152, 154, and 156, including memory devices. Depending on the number of bits that can be stored in a single memory cell, the memory blocks 152, 154, and 156 can be any of single-level cell (SLC) memory blocks, multi-level cell (MLC) memory blocks, etc. An SLC memory block comprises multiple pages implemented from memory cells, each memory cell storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented from memory cells, each memory cell storing multiple bits of data, such as two or more bits of data. Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0133] In one embodiment, the memory device 150 may be implemented using an MLC memory block such as a two-level cell (DLC) memory block, a three-level cell (TLC) memory block, a four-level cell (QLC) memory block, or a combination thereof. A DLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 4 bits of data. In another embodiment, the memory device 150 may be implemented using a block comprising multiple pages implemented from memory cells, each memory cell capable of storing five or more bits of data.

[0134] According to an embodiment, the controller 130 can use the MLC memory blocks included in the memory device 150 as SLC memory blocks that store one bit of data in one memory cell. The data input / output speed of a Multi-Level Cell (MLC) memory block can be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use the MLC memory block as an SLC buffer to temporarily store data, because a buffer may require a higher data input / output speed to improve the performance of the memory system 110.

[0135] Furthermore, according to an embodiment, the controller 130 can program data into the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data rewriting. However, the controller 130 can use the feature of the MLC being able to store multiple bits of data to program one bit of data into the MLC multiple times. For an MLC rewrite operation, when one bit of data is programmed into the MLC, the controller 130 can store the number of programming times as separate operation information. According to an embodiment, before programming another one bit of data into the same MLC that already stores one bit of data, an operation to uniformly equalize the threshold voltage of the MLC can be performed.

[0136] In one embodiment, the memory device 150 is implemented as a non-volatile memory, such as flash memory, for example, NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), and spin-transfer torque magnetic random access memory (STT-MRAM).

[0137] Reference Figure 3 The controller 130 in the memory system operates together with the host 102 and the memory device 150. As shown, the controller 130 includes a host interface 132, a flash translation layer (FTL) 240, a memory interface 142, and a pre-referenced interface. Figure 2 Identified memory 144.

[0138] According to an embodiment, the flash translation layer (FTL) 240 may include Figure 2 The error correction circuit 138 is shown. In another embodiment, the error correction circuit 138 may be implemented as a separate module, circuit, firmware, etc., and the controller 130 may include the error correction circuit 138 or the error correction circuit 138 may be associated with the controller 130.

[0139] Host interface 132 can process commands, data, etc., sent from host 102. By way of example and not limitation, host interface 132 may include command queue 56, buffer manager 52, and event queue 54. Command queue 56 can sequentially store commands, data, etc., received from host 102 and output them to buffer manager 52, for example, in the order they are stored in command queue 56. Buffer manager 52 can classify, manage, or adjust commands, data, etc., received from command queue 56. Event queue 54 can sequentially send events to process commands, data, etc., received from buffer manager 52.

[0140] Multiple commands or data with the same characteristics can be sent from host 102, or multiple commands and data with different characteristics can be sent to memory system 110 after being mixed or interleaved by host 102. For example, multiple commands for reading data (i.e., read commands) can be transmitted, or commands for reading data (i.e., read commands) and commands for programming / writing data (i.e., write commands) can be sent to memory system 110 alternately. Host interface 132 can store commands, data, etc., sent from host 102 sequentially in command queue 56. Then, host interface 132 can estimate or predict what type of internal operation the controller 130 will perform based on the characteristics of the commands, data, etc., already sent from host 102. Host interface 132 can determine their processing order and priority based on the characteristics of commands, data, etc.

[0141] Based on the characteristics of commands, data, etc., sent from host 102, buffer manager 52 in host interface 132 is configured to determine whether the buffer manager should store commands, data, etc., in memory 144, or whether the buffer manager 52 should pass commands, data, etc., to flash translation layer (FTL) 240. Event queue 54 receives events sent from buffer manager 52, which will be internally processed by memory system 110 or controller 130 in response to commands, data, etc., and the event queue 54 transmits these events to flash translation layer (FTL) 240 in the order they were entered into the event queue 54.

[0142] According to an embodiment, Figure 3 The flash translation layer (FTL) 240 shown can implement a multi-threaded scheme to perform data input / output (I / O) operations. A multi-threaded FTL can be implemented using a multi-core processor with a multi-threaded scheme included in the controller 130.

[0143] According to an embodiment, the Flash Translation Layer (FTL) 240 may include a Host Request Manager (HRM) 46, a Mapping Manager (MM) 44, a Status Manager 42, and a Block Manager 48. The HRM 46 manages events sent from the event queue 54. The MM 44 processes or controls mapped data. The Status Manager 42 performs garbage collection (GC) or wear leveling (WL). The Block Manager 48 executes commands or instructions on blocks in the memory device 150.

[0144] By way of example and not limitation, the Host Request Manager (HRM) 46 may use the Mapping Manager (MM) 44 and the Block Manager 48 to handle requests based on read commands and programming commands, as well as events passed from the Host Interface 132. The HRM 46 may send a query request to the Mapping Manager (MM) 44 to determine the physical address corresponding to the logical address entered along with the event. The HRM 46 may send a read request and the physical address to the Memory Interface 142 to process the read request, i.e., process the event. In one embodiment, the HRM 46 may send a programming request (or write request) to the Block Manager 48 to program data into a specific empty page in the Memory Device 150 where no data is stored, and then send a mapping update request corresponding to the programming request to the Mapping Manager (MM) 44 to update the item related to the programmed data in the information that maps logical addresses and physical addresses to each other.

[0145] Block manager 48 can convert programming requests passed from host request manager (HRM) 46, mapping manager (MM) 44, and / or status manager 42 into flash memory programming requests for memory device 150 to manage flash memory blocks in memory device 150. To maximize or enhance the programming or write performance of memory system 110, block manager 48 can collect programming requests and send flash memory programming requests for multi-plane and single-programming operations to memory interface 142. In embodiments, block manager 48 sends multiple flash memory programming requests to memory interface 142 to enhance or maximize the parallel processing of multi-channel and multi-directional flash memory controllers.

[0146] In this embodiment, the block manager 48 can manage blocks in the memory device 150 based on the number of valid pages, selecting and erasing blocks without valid pages when free blocks are needed, and selecting blocks containing the minimum number of valid pages when it is determined that garbage collection should be performed. The state manager 42 can perform garbage collection to move valid data stored in the selected blocks to empty blocks and erase the data stored in the selected blocks, so that the memory device 150 can have enough free blocks (i.e., empty blocks without data). When the block manager 48 provides information about the blocks to be erased to the state manager 42, the state manager 42 can check all flash pages of the block to be erased to determine whether each page of the block is valid.

[0147] For example, to determine the validity of each page, state manager 42 can identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine whether each page is valid, state manager 42 can compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. State manager 42 sends a programming request to block manager 48 for each valid page. When the programming operation is complete, the mapping table can be updated through mapping manager 44.

[0148] Mapping manager 44 manages mapping data, such as logical-physical mapping tables. Mapping manager 44 can handle various requests, such as queries and updates generated by host request manager (HRM) 46 or status manager 42. Mapping manager 44 can store the entire mapping table in memory device 150, such as flash / non-volatile memory, and cache mapping entries according to the storage capacity of memory 144. When a mapping cache miss occurs while processing a query or update request, mapping manager 44 can send a read request to memory interface 142 to load the relevant mapping table stored in memory device 150. When the number of dirty cache blocks in mapping manager 44 exceeds a certain threshold, a programming request can be sent to block manager 48 to form clean cache blocks, and the dirty mapping table can be stored in memory device 150.

[0149] During garbage collection, State Manager 42 copies valid pages to the free block, and Host Request Manager (HRM) 46 can program the latest version of the data for the same logical address of the page and simultaneously issue an update request. Map Manager 44 will not perform a mapping update if State Manager 42 requests a mapping update while the copying of valid pages has not been completed correctly. This is because when State Manager 42 requests a mapping update and subsequently completes the copying of valid pages, the mapping request is issued with the old physical address. Map Manager 44 can perform a mapping update operation to ensure accuracy if the latest mapping table still points to the old physical address, or if only the latest mapping table still points to the old physical address.

[0150] Figure 4 Embodiments according to this disclosure are shown Figures 1 to 3 The internal configuration of the controller is shown.

[0151] Reference Figure 4 The Flash Translation Layer (FTL) 240 in the controller 130 can be divided into three layers: Address Translation Layer (ATL); Virtual Flash Layer (VFL); and Flash Interface Layer (FIL).

[0152] For example, the Address Translation Layer (ATL) can translate a logical address LA sent from the file system into a logical page address. The ATL can perform address translation processes related to the logical address space. That is, the ATL can perform address translation processes based on mapping information that maps the logical page address LPA of flash memory to the logical address LA sent from the host. This logical-to-logical address mapping information (hereinafter referred to as L2L mapping) can be stored in the area of ​​the memory device 150 where metadata is stored.

[0153] The Virtual Flash Module (VFL) can translate the Logical Page Address (LPA) mapped by the Address Translation Layer (ATL) into a Virtual Page Address (VPA). Here, the Virtual Page Address (VPA) can correspond to the physical address of the virtual memory device. That is, the Virtual Page Address (VPA) can correspond to memory blocks 152, 154, and 156 in memory device 150. If bad blocks exist in memory blocks 152, 154, and 156 in memory device 150, the VFL can exclude these bad blocks. Furthermore, the VFL can include a recovery algorithm for scanning a scan area to recover the Logical-to-Virtual Address Mapping (L2V) information stored in memory device 150 and the mapping information in the data area used to store user data. The recovery algorithm can recover the L2V information. Based on the L2V information recovered by the recovery algorithm, the VFL can perform an address translation process regarding the virtual address space.

[0154] The Flash Interface Layer (FIL) translates the virtual page addresses of the Virtual Flash Layer (VFL) into physical page addresses for the memory device 150. The FIL performs low-level operations that interface with the memory device 150. For example, the FIL may include low-level drivers for controlling the hardware of the memory device 150, error correction codes (ECC) for checking and correcting errors in data sent from the memory device 150, and modules for performing functions such as Bad Block Management (BBM).

[0155] Figure 5 A memory device according to an embodiment of the present disclosure is shown. Specifically, Figure 5 The memory cell array circuitry in a memory die or memory plane included in a memory device 150 according to an embodiment of the present disclosure is schematically shown.

[0156] Reference Figure 5The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1 connected to corresponding bit lines of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in respective columns of the memory bank 330, and each cell string 340 may include at least one drain select transistor (DST) and at least one source select transistor (SST). The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor (DST) and the source select transistor (SST). Each of the non-volatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC) storing a multi-bit data entry per cell. The cell string 340 may be electrically connected to corresponding bit lines of the bit lines BL0 to BLm-1.

[0157] exist Figure 5 In the illustrated embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as NOR flash memory, hybrid flash memory that combines or mixes at least two different types of memory cells, or single-chip NAND flash memory with the controller embedded in a single memory chip. In embodiments, memory group 330 may include flash memory cells that include a charge-fetch flash (CTF) layer comprising a conductive floating gate or an insulating layer.

[0158] Figure 5 An embodiment of a memory system 110 that may include a memory device 150 is illustrated. In this embodiment, a memory group 330 in the memory device 150 may include one or more memory blocks 152, 154, 156. According to the embodiment, the memory device 150 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure or a vertical structure. Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first to a third direction, such as the x-axis, y-axis, and z-axis directions.

[0159] Memory bank 330, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple virtual word lines DWL, and multiple common source lines CSL. In an embodiment, memory bank 330 may include, for example, multiple NAND strings NS that may each correspond to a cell string 340. Each NAND string NS may include multiple memory cells MC and may be connected to corresponding bit lines in the bit lines BL. Additionally, the string select transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cells MC may be arranged between the string select transistor SST and the drain select transistor DST.

[0160] Reference Figure 5 The memory device 150 may include a voltage supply circuit 170, which supplies word line voltages to each word line according to an operating mode, such as one or more predetermined voltages, like programming voltage, read voltage, and pass voltage, or it may supply voltage to a block (e.g., a well region) forming each memory block including memory cells MC. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of the control circuit 180. Moreover, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data entries from each other. Multiple variable read voltages can be applied to the non-volatile memory cells in the memory group 330.

[0161] In response to control by the control circuitry, one of the memory blocks (or sectors) in the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied to the selected word line and the unselected word line, respectively. The voltage supply circuitry 170 may include voltage generation circuitry for generating target voltages with various levels (see, for example, see...). Figures 6 to 8 ).

[0162] In an embodiment, the voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. The second power supply voltage VPP may have a higher voltage level, for example, two times or more higher than the voltage level of the first power supply voltage VCC. For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V.

[0163] According to an embodiment, the voltage supply circuit 170 may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory group 330. The voltage generation circuit may use a second supply voltage VPP to generate a target voltage that can have a higher voltage level than the second supply voltage VPP.

[0164] The memory device 150 may further include a read / write circuit 320 controlled by control circuitry 180. The read / write circuit 320 may operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 may operate as a sense amplifier for reading data entries from the memory cell array. In programming operations, the read / write circuit 320 may operate as a write driver that controls the potential of the bit lines based on the data to be stored in the memory cell array. The read / write circuit 320 may receive data entries to be programmed into the cell array from a page buffer during programming operations. The read / write circuit 320 may drive the bit lines based on the input data entries. For this purpose, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column (or each bit line) or each column pair (or each bit line pair). According to an embodiment, each of the page buffers 322, 324, 326 may include a plurality of latches.

[0165] Page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serialization circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential delays when sending data from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without waiting. According to an embodiment, the input / output device may include a reference... Figure 6 The input / output control circuit (not shown) is described. Further, refer to... Figure 5 The page buffers 322, 324, and 326 described may include references Figure 6 The described data register (not shown).

[0166] According to an embodiment, the memory device 150 may receive a write command, a write data entry, and information about the location of the write data entry to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., for a programming operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the programming operation.

[0167] When multiple data entries are programmed into the non-volatile memory cells included in memory bank 330, the error rate may be higher than when storing single data entries in non-volatile memory cells. For example, errors in non-volatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data entries stored between non-volatile memory cells should be reduced.

[0168] To this end, memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively narrow the threshold voltage distribution of non-volatile memory cells. In embodiments, memory device 150 can use ISPP operations for multi-step programming operations. For example, memory device 150 can divide programming operations into least significant bit (LSB) programming operations and most significant bit (MSB) operations according to a predetermined order between non-volatile memory cells or pages.

[0169] Figure 6 A first example of programming multi-bit data into a non-volatile memory cell is shown according to an embodiment of the present disclosure. Figure 6 This illustrates a two-step programming operation for programming 2-bit data into a non-volatile memory cell.

[0170] Reference Figure 6 Before the data programming operation, the non-volatile memory cell can have a threshold voltage corresponding to the erase state. When the first programming operation is performed, LSB data can be programmed into the non-volatile memory cell. Subsequently, when the second programming operation is performed, MSB data can be programmed into the non-volatile memory cell. Through the first and second programming operations, the threshold voltage of the non-volatile memory cell can belong to one of four different states: ER, P1, P2, and P3. These four different threshold voltage states ER, P1, P2, and P3 can correspond to different 2-bit data '11', '01', '00', and '10'.

[0171] Due to various reasons such as resource constraints, interruptions or delays, and power issues, memory device 150 may require a long time to program multiple bits of data into non-volatile memory cells. (See reference...) Figure 1 and Figure 6As described, when the first programming operation is completed, the memory device 150 can notify the controller 130 of LSB data completion. Thereafter, the memory device 150 can program the MSB data into the non-volatile memory cell that already has the LSB data programmed in the second programming operation. When the second programming operation is completed, the memory device 150 can send an MSB data completion notification to the controller 130.

[0172] Figure 7 A second example of programming multi-bit data into a non-volatile memory cell is shown according to an embodiment of the present disclosure. Figure 7 This illustrates a three-step programming operation for programming 3-bit data into a non-volatile memory cell.

[0173] Before data programming operations, non-volatile memory cells can have corresponding... Figure 6 The threshold voltage for the erase state is shown. (Refer to...) Figure 7 When performing the first programming operation, LSB data can be programmed into the non-volatile memory cell. Subsequently, when performing the second programming operation, CSB data can be programmed into the non-volatile memory cell that already has LSB data programmed. Then, the MSB data can be programmed into the non-volatile memory cell through the third programming operation. Through the first to third programming operations, the threshold voltage of the non-volatile memory cell can belong to eight different threshold voltage states. The eight different threshold voltage states of the non-volatile memory cell correspond to three bits of data (e.g., '111', '011', '101', '001', '110', '010', '100', '000').

[0174] Through a three-step programming process, the memory device 150 may require a considerable amount of time to store multiple bits of data. (See reference...) Figure 1 and Figure 7 Upon completion of the first programming operation, the memory device 150 can notify the controller 130 of the LSB data programming completion. Subsequently, the memory device 150 can program the CSB data through the second programming operation. Upon completion of the second programming operation, the memory device 150 can notify the controller 130 of the CSB data programming completion. Subsequently, the memory device 150 can program the MSB data through the third programming operation. Upon completion of the third programming operation, the memory device 150 can provide the controller 130 with an MSB data completion notification.

[0175] Despite Figure 7 The document describes programming 3-bit data into a non-volatile memory cell using a three-step programming operation; however, according to an embodiment, 3-bit data can be programmed using a two-step programming operation. In the case of programming 3-bit data using a two-step programming operation, the memory device 150 can send a completion message for the LSB data to the controller 130 after the first programming step, and a completion message for the CSB and MSB data to the controller 130 after the second programming step.

[0176] According to an embodiment, the controller 130 may delete or erase the data buffer 270 (see reference 150) based on a completion notification transmitted from the memory device 150. Figure 1 Some of the written data is stored in the memory. As a result, the memory system 110 can increase the utilization of internal resources.

[0177] Reference Figure 7 The 3-bit data programmed into non-volatile memory can include LSB (least significant bit) data, CSB (center significant bit) data, and MSB (most significant bit) data, which correspond to the low-order, middle-order, and high-order bits, respectively. For example, controller 130 can program three pages of data across a set of non-volatile memory cells connected to a single word line. The three pages of data correspond to the low-order, middle-order, and high-order bits of each non-volatile memory cell. The three pages of data can include LSB page data, CSB page data, and MSB page data.

[0178] Figure 8 A third example of programming multi-bit data into a non-volatile memory cell is shown according to embodiments of the present disclosure. Figure 8 This illustrates another three-step programming operation for storing 3-bit data in a non-volatile memory cell.

[0179] Reference Figure 8 Prior to the data programming operation, the non-volatile memory cell may have a threshold voltage corresponding to the erase state. The memory device 150 may perform a partial programming operation based on the LSB data stored in the non-volatile memory cell. Here, the partial programming operation may include a binary programming operation to significantly increase the threshold voltage of the non-volatile memory cell based on the LSB data by applying a large ISPP step pulse. After performing the binary programming operation, the memory device 150 may provide the controller 130 with an LSB data completion notification.

[0180] Following the binary programming operation, the memory device 150 can program the non-volatile memory cells based on CSB and MSB data. In this step, the threshold voltage of the non-volatile memory cells can be increased based on an ISPP step pulse smaller than that of the binary programming operation, for example, by applying a lower-level pulse for a shorter time or applying the same-level pulse. This process can be referred to as fuzzy programming. Subsequently, the memory device 150 can perform fine programming to narrow the width of the threshold voltage distribution across the non-volatile memory cells. Fine programming can use an ISPP step pulse smaller than that of the fuzzy programming operation.

[0181] Unlike binary programming or fuzzy programming, fine programming is performed to narrow the width of the multiple threshold voltage distributions for a non-volatile memory cell. The possibility of errors may increase during fine programming. Therefore, even after binary and fuzzy programming operations are completed, memory device 150 can store the programmed bit data (all bit values) in an SLC buffer. According to an embodiment, memory device 150 can notify controller 130 of fuzzy programming completion after fuzzy programming is completed. Furthermore, after fine programming, memory device 150 transmits fine programming completion notification to controller 130.

[0182] As mentioned above, refer to Figures 6 to 8 The process of storing multi-bit data in memory device 150 can be performed through multi-step programming operations, and memory device 150 can output a completion notification upon completion of each programming operation. Controller 130 can erase or delete data based on the completion notification transmitted from memory device 150. Figure 1 The data stored in the data buffer 270 shown.

[0183] According to an embodiment, write data can be similar to that programmed into the first non-volatile cell region 292 to the reference. Figure 1 The flags stored in the second non-volatile cell region 294 are used for programming. In the case where multiple bits of data are stored in the first non-volatile cell region 292, the controller 130 can... Figure 2 The error correction circuit 138 shown is used to detect and correct errors. However, a flag is information indicating a programming state, not data or information processed by an error correction mechanism based on error correction codes. Therefore, the error correction circuit 138 does not check or process the flag to detect and correct errors included in the flag.

[0184] Figure 9A first example of programming operations performed within a memory system according to another embodiment of the present disclosure is shown.

[0185] Reference Figure 9 The programming process can be performed from an external device (e.g., Figures 2 to 3 The write command and write data input by the host 102 shown in the figure, or the internal operation (e.g., garbage collection, wear leveling, data migration, etc.) performed by the controller 130, are initiated (operation 708).

[0186] The non-volatile memory cells included in the first non-volatile cell region 292 of the memory device 150 can store multiple bits of data. The multiple bits of data stored in the non-volatile memory cells can be programmed in LSB to MSB order. The multiple bits of data can be stored in the non-volatile memory cells through at least two programming operations or multiple programming operations corresponding to the number of bits of the multiple bits of data.

[0187] When the programming operation begins (operation 708), the memory system 110 can perform a step programming operation on at least one bit of data among multiple bits of data (operation 710). Here, the step programming operation corresponding to at least one bit of data may include a programming operation on LSB data stored in a non-volatile memory cell.

[0188] After the bit data is programmed into a non-volatile memory cell in the first non-volatile cell region 292 (operation 710), the memory system 110 can store a flag corresponding to the programmed bit data (operation 712). According to an embodiment, the memory system 110 can store the flag information in a second non-volatile cell region 294 corresponding to the non-volatile memory cell in the first non-volatile cell region 292.

[0189] The memory system 110 can continue the step-programming operation until multiple bits of data are programmed into the non-volatile memory cell. The memory system 110 can perform another step-programming operation on another bit of the multiple bits of data (operation 714). After step-programming the other bit, the memory system 110 can update or store the flag corresponding to the programmed bit data (operation 716).

[0190] The memory system 110 can check whether all multi-bit data has been programmed (operation 718). According to an embodiment, a non-volatile memory cell can be programmed with multi-bit data in the order of LSB data to MSB data. The memory system 110 can check whether MSB data has been programmed into the non-volatile memory cell to determine whether the non-volatile memory cell has multi-bit data programmed.

[0191] When not all the multi-bit data has been programmed (No in operation 718), the memory system 110 may perform another step programming operation on another of the multi-bit data (operation 714). When all the multi-bit data has been programmed (Yes in operation 718), the memory system 110 may terminate the programming operation process (operation 720).

[0192] Figure 10 This illustrates the level variation of the read voltage for LSB data based on the programming state of a non-volatile memory cell, according to an embodiment of this disclosure. Specifically, Figure 10 The changes in threshold voltage distribution based on three different programming methods using multi-bit data are described.

[0193] In the first programming method (Case 1), each bit of the multi-bit data is programmed step-by-step. In a non-volatile memory cell with data erased, the LSB data can be programmed via the first programming operation (first PGM). Subsequently, the second bit of data can be programmed into the non-volatile memory cell already programmed with LSB data via the second programming operation (first PGM). Through the third programming operation (third PGM), the third bit of data can be programmed into the non-volatile memory cell programmed with the second bit of data. Through the fourth programming operation (fourth PGM), the fourth bit of data (i.e., the MSB data) can be programmed into the non-volatile memory cell programmed with the third bit of data. Figure 10 In the first programming method shown (Case 1), 4 bits of data can be stored in a non-volatile memory cell, but the number of bits of multi-bit data stored in each non-volatile memory cell can vary depending on the embodiment.

[0194] Reference Figure 10 Each time a step programming operation is performed using the first programming method (Case 1), the threshold voltage distribution associated with the LSB data is shifted or altered. Typically, after all the multi-bit data has been programmed, the memory device 150 applies a read voltage (LSB data read) to read the LSB data from the non-volatile memory cell. However, because the threshold voltage distribution of the LSB data may change before all the multi-bit data has been programmed, the read voltage (LSB read) used to read the LSB data before all the multi-bit data has been programmed should be changed based on the programming state of the non-volatile memory cell. If the level of the read voltage does not change, many errors will occur in the non-volatile memory cell, making it difficult to accurately read the LSB data from the non-volatile memory cell. Although in Figure 10 The adjustment of the read voltage level used to obtain LSB data has already been described, but the memory system 110 can change the read voltage level used to obtain bit data that is different from LSB data.

[0195] In the second programming method (Case 2), the LSB and MSB data within the multi-bit data are programmed through separate step programming operations, and multiple bits of data between the LSB and MSB data can be programmed simultaneously. In a non-volatile memory cell with data deleted or erased, the LSB data can be programmed via the first programming operation (first PGM). Subsequently, the multi-bit data can be programmed into the non-volatile memory cell with the programmed LSB data via the second programming operation (second PGM). The MSB data can be programmed into the non-volatile memory cell with the multi-bit data via the third programming operation (third PGM). Figure 10 In the second programming method (Case 2), the case where 4 bits of data can be stored in the non-volatile memory cell is described as an example, but the number of bits of multi-bit data stored in the non-volatile memory cell may vary depending on the embodiment.

[0196] In the third programming method (Case 3), two bits of data from a multi-bit dataset can be programmed step-by-step. In a non-volatile memory cell that has been deleted or erased, the two bits, including the LSB data, can be programmed via a first programming operation (first PGM). Subsequently, a second programming operation (second PGM) can be used to program another two bits, including the MSB data, into the non-volatile memory cell that already contains the two bits including the LSB data. Figure 10 In the third programming method (Case 3), the case where 4 bits of data can be stored in the non-volatile memory cell is described as an example, but the number of bits of multi-bit data programmed into each non-volatile memory cell can vary depending on the embodiment.

[0197] Even when multi-bit data is programmed into a non-volatile memory cell using the second programming method (Case 2) and the third programming method (Case 3), as in the first programming method (Case 1), the threshold voltage distribution corresponding to the LSB data can be shifted or altered. The memory system 110 can change the level of the read voltage used to obtain the LSB data in response to changes in the threshold voltage distribution of the non-volatile memory cell. Using this method, the memory system 110 can accurately read the LSB data programmed into the non-volatile memory cell even before the MSB data is programmed into the non-volatile memory cell. (Refer to...) Figures 6 to 8Before the MSB data is programmed into the corresponding memory cell, the LSB data or CSB data can be stored in a specific memory cell. For example, after the LSB data or CSB data is programmed into a specific memory cell and before the MSB data is programmed into it, the controller 130 can read the LSB data or CSB data programmed into the corresponding memory cell. Furthermore, before the formation of the threshold voltage distribution corresponding to the multi-bit data including the MSB data is completed, the controller 130 can read the LSB data or CSB data stored in the corresponding memory cell. Therefore, before the corresponding memory cell is fully programmed with multi-bit data, the memory system 110 can read the data from the memory cell. Figure 1 The data buffer 270 shown releases or deletes some programmed bit data.

[0198] Figure 11 A first example of a read operation performed within a memory system according to another embodiment of the present disclosure is shown.

[0199] Reference Figure 1 and Figure 11 The first non-volatile cell region 292 in the memory device 150 can store multiple bits of data, while the second non-volatile cell region 294 can store flags.

[0200] Reference Figure 11 A read operation can be performed by controller 130 to obtain data stored in memory device 150 (operation 808). Typically, after a non-volatile memory cell included in memory device 150 is programmed with multiple bits of data, controller 130 may attempt to read the multiple bits of data programmed into the corresponding non-volatile memory cell. However, in embodiments of this disclosure, controller 130 may perform a read operation on a non-volatile memory cell with a programmed state that has no programmed MSB data.

[0201] When a read operation begins (operation 808), the memory system 110 can read a flag corresponding to the location of the read data (operation 810). Because the flag indicates the programming state of the non-volatile memory cell storing the read data, the memory system 110 can set or adjust the level of the read voltage used to read the non-volatile memory cell to perform the read operation based on the flag (operation 812). Figure 10As shown, the threshold voltage distribution corresponding to the bit data stored in the non-volatile memory cell can vary according to the programming state (e.g., how many bits of data are programmed into it), and the level of the read voltage should be adjusted or changed in response to the programming state to avoid errors in reading data corresponding to the bit data programmed into the non-volatile memory cell. For example, the memory system 110 can select the level of the read voltage from a preset read voltage table according to a flag, calculate or determine the level of the read voltage by applying the flag to a preset arithmetic expression, etc.

[0202] When the read voltage level is determined (operation 812), the memory system 110 can apply a read voltage with the determined level to the non-volatile memory cell corresponding to the location of the read data to perform a read operation (operation 814). After performing the read operation on the non-volatile memory cell (operation 814), the memory system 110 can output the read data obtained through the read operation (operation 816). Here, the read data can be transferred from the memory device 150 to the controller 130. According to an embodiment, when a read operation is performed in response to a read command input from an external device, the controller 130 can output the read data to the external device. When the read data is output (operation 816), the memory system 110 can terminate the read operation (operation 818).

[0203] Figure 12 Embodiments according to this disclosure are shown Figure 11 The operation margin for the read operation is shown.

[0204] Reference Figure 12 This section describes two different read operations performed by memory system 110. First, a first read operation (FIRST READ OP.) can be performed when all multi-bit data has been programmed into the non-volatile memory cell included in memory device 150. Controller 130 can send a first read command (first read CMD), the address of the non-volatile memory cell, and a second read command (second read CMD) to memory device 150. In this case, the address of the non-volatile memory cell can include a physical address translated by flash translation layer 240 in controller 130. During the read operation margin tR, in response to the read command and address, memory device 150 can output the read data obtained from the non-volatile memory cell.

[0205] Furthermore, a third read operation (THIRD READ OP.) can be performed when not all multi-bit data is programmed into the non-volatile memory cells included in the memory device 150. Unlike the first read operation (FIRST READ OP.), the third read operation (THIRD READ OP.) includes an additional operation (additional CMD & ADD loop) for reading flags in the memory device 150 before sending the first read command (first read CMD), the address of the non-volatile memory cell, and the second read command (second read CMD). Here, the additional operation (additional CMD & ADD loop) may include sending the read command (additional CMD) and the address of the flag to the memory device 150 and having the memory device 150 output information about the flag to the controller 130, the address of which is used by the controller 130 to determine the programming state of the non-volatile memory cell, which is the target of the third read operation (THIRD READ OP.).

[0206] Figure 13 The illustration shows a read voltage having a level determined in response to a flag, according to an embodiment of the present disclosure.

[0207] Reference Figure 13 This will describe an example of programming 4 bits of data into a non-volatile memory cell in memory device 150 through a two-step programming operation. It can be similar to... Figure 10 The third programming method (Case 3) shown is used to program non-volatile memory cells. Programming a 4-bit non-volatile memory cell through a two-step programming operation can result in one of three programming states. The first programming state is the erased state, where the data in the non-volatile memory cell has been erased. The second programming state is where some bits of data (i.e., 2 out of the 4 bits) are programmed into the non-volatile memory cell through the first programming operation (first PGM). The 2 bits programmed into the non-volatile memory cell can include LSB data. The third programming state is where all 4 bits of data from the LSB to the MSB are programmed into the non-volatile memory cell through the second programming operation (second PGM).

[0208] In an embodiment, when a first-step programming operation (first PGM) is performed on a non-volatile memory cell, four threshold voltage distributions corresponding to two bits of data, including LSB data, can be generated. According to an embodiment, some of the non-volatile memory cells programmed with specific location data can be used as flag cells. These flags can indicate the current programming state of the non-volatile memory cell. For example, the threshold voltage distribution corresponding to the erase state (e.g., data '1' and '11') can be used as a flag. Comparing before and after the first-step programming operation (first PGM), the width of the threshold voltage distribution after the first-step programming operation (first PGM) (e.g., the data '11') may be narrower than the width of the threshold voltage distribution before performing the first-step programming operation (first PGM) (e.g., the data '1'). If it is determined that the width of the threshold voltage distribution used as a flag has narrowed, the memory system 110 can recognize that the first-step programming operation (first PGM) has been performed on the non-volatile memory cell.

[0209] When a flag check operation identifies that the first step of programming (first PGM) has been performed on a non-volatile memory cell, the memory system 110 can change or adjust the level of the read voltage (LSB read) applied for reading LSB data based on the flag.

[0210] After performing a second programming operation (second PGM) on a non-volatile memory cell that has already been programmed with 2 bits of data including LSB data, the flags can also be updated or changed. (See reference...) Figure 13 Another threshold voltage distribution corresponding to another value (e.g., data '00' and '0000') can be used as a marker. Comparing before and after the second programming operation (second PGM), the width of the threshold voltage distribution after the second programming operation (second PGM) (e.g., data '0000') may be narrower than the width of the threshold voltage distribution before performing the second programming operation (second PGM) (e.g., data '00'). The memory system 110 can identify that the second programming operation (second PGM) has been completed in the non-volatile memory cell based on the change in the threshold voltage distribution used as a marker, thereby corresponding to a change in the programming state of the non-volatile memory cell or adjusting the level of the read voltage (LSB read) applied for reading LSB data.

[0211] Reference Figure 13According to another embodiment, an additional flag memory cell configured to store a single bit of data can be used to store flags. For example, instead of a non-volatile memory cell storing 4 bits of data, a non-volatile memory cell included in an SLC memory block in memory device 150 can be used as a flag cell. After performing a first-step programming operation (first PGM) on the non-volatile memory cell, data '1' is programmed into the flag memory cell. If data '1' is programmed into the flag memory cell, the width of the threshold voltage distribution corresponding to data '1' may be narrower compared to the erase state. Further, after performing a second-step programming operation (second PGM) on the non-volatile memory cell, data '0' is programmed into the flag memory cell. If data '0' is programmed into the flag memory cell, the threshold voltage distribution of the flag memory cell may be shifted to the right. Therefore, the configuration of the flag memory cell and the method of storing the programming state of the non-volatile memory cell in the flag memory cell can vary depending on how memory system 110 or memory device 150 programs multiple bits of data into the non-volatile memory cell.

[0212] Figure 14 A second example of a read operation performed within a memory system according to another embodiment of the present disclosure is shown. Figure 14 Another embodiment is shown, wherein the first non-volatile cell region 292 and the second non-volatile cell region 294 in the memory device 150 are both used to store data entries, and no additional flags are stored separately.

[0213] Reference Figure 14 A read operation can be performed by the controller 130 to read data entries stored in the memory device 150 (operation 908). Typically, after multiple bits of data have been programmed into the non-volatile memory cells included in the memory device 150, the controller 130 may attempt to perform a read operation to read the multiple bits of data programmed into the non-volatile memory cells. However, even if the non-volatile memory cells included in the memory device 150 are fully programmed with multiple bits of data, the controller 130 may perform a read operation to read some bits of data from the multiple bits of data in the non-volatile memory cells.

[0214] When a read operation begins (operation 908), the memory system 110 may perform an operation (operation 910) to check the programming status of a non-volatile memory cell corresponding to the location of the read data. For example, the memory device 150 or controller 130 may store status information indicating whether a step-by-step programming operation performed on the non-volatile memory cell corresponding to the location of the read data has been completed. To this end, according to embodiments, the memory device 150 or controller 130 may further include components such as registers for storing programming status. According to embodiments, the memory device 150 or controller 130 may store or update operation information or status information regarding the memory die or memory plane, and may store operation information or status information including whether a step-by-step programming operation has been completed. The memory system 110 may estimate or identify the programming status of a non-volatile memory cell for which a read operation is to be performed by utilizing status information regarding the non-volatile memory cell (e.g., programming operation result, page / block information).

[0215] The memory system 110 can set or adjust the level of the read voltage based on an estimated or identified programming state for a check operation (operation 912). See reference... Figure 10 As described, whenever a step programming operation is performed on a non-volatile memory cell, the threshold voltage level of the non-volatile memory cell can be shifted or changed according to the programmed bit data. The threshold voltage distribution corresponding to the bit data stored in the non-volatile memory cell can vary according to the programming state of the non-volatile memory cell. Therefore, the level of the read voltage should be adjusted or changed in response to the programming state to reduce errors in the bit data read or obtained from the non-volatile memory cell.

[0216] When the level of the read voltage is determined (operation 912), the memory system 110 can apply a read voltage with the determined level to the non-volatile memory cell corresponding to the location of the read data to perform a read operation (operation 914). After performing the read operation on the non-volatile memory cell (operation 914), the memory system 110 can output the read data obtained through the read operation (operation 916). Here, the read data can be transferred from the memory device 150 to the controller 130. According to an embodiment, when in response to data from, such as... Figure 2 and Figure 3 When a read operation is executed by inputting a read command to an external device of the host 102, the controller 130 can output the read data to the external device. When the read data is output (operation 916), the memory system 110 can terminate the read operation (operation 919).

[0217] Figure 15 Embodiments according to this disclosure are shown Figure 14 The operation margin for the read operation is shown.

[0218] Reference Figure 15 This section describes two different read operations performed by memory system 110. First, a first read operation (FIRST READ OP.) can be performed when all multi-bit data has been programmed into the non-volatile memory cell included in memory device 150. Controller 130 can send a first read command (first read CMD), the address of the non-volatile memory cell, and a second read command (second read CMD) to memory device 150. In this case, the address of the non-volatile memory cell can include a physical address translated by flash translation layer 240 in controller 130. During the read operation margin tR, in response to the read command and address, memory device 150 can output the read data obtained from the non-volatile memory cell.

[0219] Furthermore, a second read operation (SECOND READ OP.) can be performed when not all multi-bit data is programmed into the non-volatile memory cells included in the memory device 150. Unlike the first read operation (FIRST READ OP.), the second read operation (SECOND READ OP.) may include additional operations (program step prompts) to check the programming state of the memory device 150 before sending the first read command (first read CMD), the address of the non-volatile memory cell, and the second read command (second read CMD) executed by the controller 130. For example, in the additional operations (program step prompts) for checking the programming state, the controller 130 may check a register configured to store the programming state of the non-volatile memory cell, which is the target of the second read operation (SECOND READ OP.). According to an embodiment, the controller 130 may store in a register whether the step-by-step programming operation performed on the non-volatile memory cell has been completed, and the controller 130 may check the programming state before performing a read operation on the corresponding non-volatile memory cell. When the memory device 150 stores in a register whether the step-by-step programming operation performed in the non-volatile memory cell has been completed, the controller 130 can check the programming status through operations such as transmitting status check commands to check the status information stored in the memory device 150.

[0220] Reference Figure 12 and Figure 15 In reference Figure 12 In the described embodiments, an additional flag reading operation is performed, while in the reference... Figure 15In the described embodiments, the programming status regarding whether the programming operation is complete can be checked without performing a read operation. Because the operation margin of the check operation (programming step prompt) for checking the programming status of the non-volatile memory cell is smaller than the operation margin of the additional operation (additional CMD & ADD loop) used as a flag for reading the non-volatile memory cell, the operation speed of the read operation can be improved.

[0221] Figure 16 The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a first programming method is shown in an embodiment of the present disclosure.

[0222] Reference Figure 16 It can store 4 bits of data in a non-volatile memory cell, and the 4 bits of data can be programmed sequentially in four programming steps. (See reference...) Figure 16 The described programming methods can be compared with the reference Figure 10 The first programming method described (Case 1) is basically the same.

[0223] When performing a step-by-step programming operation using the first programming method (Case 1), the change in the threshold voltage of the non-volatile memory cell can be predicted in advance because it is related to the operating characteristics. The memory system 110 can identify the programming state of the non-volatile memory cell by checking the status information indicating whether the step-by-step programming operation is complete.

[0224] When the memory system 110 identifies the programming state of a non-volatile memory cell, the memory system 110 can adjust or change the level of the read voltage (LSB read) applied to the non-volatile memory cell for reading LSB data based on the programming state. For example, as more bits of data are programmed into the non-volatile memory cell with the increase of the number of programming operations completed, the level of the read voltage (LSB read) applied to read the LSB data will increase.

[0225] Figure 17 The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a second programming method is shown in an embodiment of the present disclosure.

[0226] Reference Figure 17 It can store 4 bits of data in a non-volatile memory cell, and the 4 bits of data can be programmed sequentially in three steps. (See reference...) Figure 17 The described programming methods can be compared with the reference Figure 10 The second programming method (case 2) described is basically the same.

[0227] When performing step-by-step programming operations using the second programming method (Case 2), the threshold voltage change of the non-volatile memory cell can be estimated or inferred in advance because it is related to the operating characteristics. The memory system 110 can identify the programming state of the non-volatile memory cell by checking status information including whether the step-by-step programming operation is complete. According to an embodiment, the status information recorded in a register and stored in the controller 130 or memory device 150 may include information indicating whether the step-by-step programming operation is complete.

[0228] When the memory system 110 recognizes the programming state of a non-volatile memory cell, it can adjust or change the level of the read voltage (LSB read) applied to read LSB data according to the programming state. For example, as more bits of data are programmed into the non-volatile memory cell as the number of step programming operations increases, the level of the read voltage (LSB read) applied to read LSB data will increase.

[0229] Figure 18 The threshold voltage variation of a non-volatile memory cell configured to store 4 bits of data according to a third programming method is shown in an embodiment of the present disclosure.

[0230] Reference Figure 18 It can store 4 bits of data in a non-volatile memory cell, and the 4 bits of data can be programmed sequentially in two programming steps. (See reference...) Figure 18 The described programming methods can be compared with the reference Figure 10 The third programming method (case 3) described is basically the same.

[0231] When each step of the two-step programming operation is performed using the third programming method (Case 3), the threshold voltage change of the non-volatile memory cell can be estimated or inferred due to the operational characteristics. The memory system 110 can identify the programming state of the non-volatile memory cell by checking programming success / failure status information, including whether the step programming operation has been completed.

[0232] When the memory system 110 identifies the programming state of a non-volatile memory cell, the memory system 110 can adjust the level of the read voltage (LSB read) applied to read LSB data based on the programming state. For example, the memory system 110 may include a read voltage meter that includes information about the read voltage level corresponding to the threshold voltage change of the non-volatile memory cell according to each step of the two-step programming operation. Based on the read voltage meter, the memory system 110 can change or adjust the level of the read voltage (LSB read) applied to read LSB data based on the programming state.

[0233] As described above, the memory system according to embodiments of the present disclosure can provide an apparatus and method for reading bit data stored in a non-volatile memory cell configured to store multiple bits of data, even if only some of the multiple bits of data are stored in the non-volatile memory cell, thereby making efficient use of resources, because the memory system does not have to keep the written data in a data buffer to ensure data safety during the one-time programming of data performed within the memory system.

[0234] Furthermore, according to embodiments of this disclosure, when the write data stored in a non-volatile memory cell capable of storing multi-bit data is insufficient, the memory system does not need to program the virtual data. The memory system can program only some bits of data without programming the virtual data into the non-volatile memory cell, and perform read operations on the programmed bits of data in the non-volatile memory cell, even if not all multi-bit data is programmed into the non-volatile memory cell. The memory system does not need to program the virtual data into the memory device including the non-volatile memory cell.

[0235] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the computer, processor, controller, or other signal processing device described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0236] Furthermore, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be volatile or non-volatile memory or other storage device that may be detachably or permanently coupled to a computer, processor, controller, or other signal processing device for executing code or instructions for performing embodiments of the methods or operating apparatus described herein.

[0237] For example, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in, for example, non-transitory logic comprising hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may be, for example, any of various integrated circuits including, but not limited to, application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0238] When implemented at least partially in software, the controller, processor, control circuitry, device, module, unit, multiplexer, logic circuitry, interface, decoder, driver, generator, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those other than those described herein. Because the algorithms underlying the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions implementing the operation of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor that performs the methods described herein.

[0239] Although the teachings have been shown and described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A memory device, comprising: The first memory bank includes a first non-volatile memory cell that stores multiple bits of data; as well as Control device: Perform multiple programming operations to store the multi-bit data in the first non-volatile memory unit; During the execution of the plurality of programming operations, based on the programming state of the first non-volatile memory cell, before the most significant bit among the plurality of bits is programmed into the first non-volatile memory cell, in response to a read command, a read operation is performed to retrieve the bit data among the plurality of bits that has already been programmed into the first non-volatile memory cell; and Output the bit data obtained in response to the read command. The memory device further includes a data buffer, which temporarily stores write data including the multi-bit data to be stored in the first non-volatile memory cell. After the bit data has been programmed into the first non-volatile memory cell and before all the data in the multi-bit data has been programmed into the first non-volatile memory cell, the control device further removes the portion of the written data corresponding to the bit data from the data buffer.

2. The memory device according to claim 1, wherein, The memory device determines the programming state based on the number of bits of data programmed into the first non-volatile memory cell from the multi-bit data.

3. The memory device according to claim 2, wherein, The control device further changes the level of the read voltage applied to the first non-volatile memory cell during the read operation according to the programming state of the first non-volatile memory cell.

4. The memory device according to claim 1, wherein, As the number of bits of data programmed into the first non-volatile memory cell increases, the control device further increases the level of the read voltage to be applied to the first non-volatile memory cell to read the least significant bit of data.

5. The memory device according to claim 1, wherein, The control device executes the plurality of programming operations in the first non-volatile memory unit in the order of least significant bit data to most significant bit data among the plurality of bits.

6. The memory device according to claim 1, The system further includes a second memory bank, which includes second non-volatile memory cells that store flags corresponding to the programming state of the first non-volatile memory cell. in, Before performing the read operation on the first non-volatile memory cell, the control device further reads the flag stored in the second non-volatile memory cell to identify the programming state of the first non-volatile memory cell.

7. The memory device according to claim 6, wherein, The control device further performs the error correction operation on the data obtained from the first memory group while skipping the error correction operation on the flag obtained from the second memory group.

8. The memory device of claim 1, further comprising a register that records information indicating whether a programming operation for the bit data most recently programmed into the first non-volatile memory cell among the plurality of bit data has been completed.

9. The memory device according to claim 8, wherein, The control device further performs a programming status check operation on the first non-volatile memory cell based on the information recorded in the register to identify the programming status.

10. A method of operating a memory system, comprising: The write data input from the host is temporarily stored in a data buffer, and the write data includes multiple bits of data to be stored in the first non-volatile memory cell; The least significant bit of the multi-bit data is programmed into the first non-volatile memory cell storing the multi-bit data; Before programming the most significant bit of the multi-bit data into the first non-volatile memory cell, a read operation is performed on the least significant bit of the data programmed into the first non-volatile memory cell in response to a read command. In response to the read command, the least significant bit data is output to the host; and After the least significant bit data has been programmed into the first non-volatile memory cell, and before all data in the multi-bit data has been programmed into the first non-volatile memory cell, the portion of the written data corresponding to the least significant bit data is removed from the data buffer.

11. The method of claim 10, further comprising: A flag is programmed into a second non-volatile memory cell, the flag indicating whether the programming of the least significant bit data in the first non-volatile memory cell is complete; In the first non-volatile memory cell, the bits of data other than the least significant bit are programmed; and The flag is updated in response to whether programming of the bit data other than the least significant bit data is complete.

12. The method of claim 11, further comprising: When the bit data other than the least significant bit data is the most significant bit data, the programming operation on the first non-volatile memory cell is terminated after the programming of the bit data is completed. When the bit data other than the least significant bit data is not the most significant bit data, the other bit data other than the least significant bit data is programmed in the first non-volatile memory unit. and The flag is updated based on whether programming of another data point other than the least significant bit is complete.

13. The method of claim 10, further comprising: After the programming of the least significant bit data is completed, an indicator indicating whether the programming of the least significant bit data is complete is stored in a register; The bit data, excluding the least significant bit data, is programmed into the first non-volatile memory cell. and The indicator in the register is updated based on the completion of programming of the bit data excluding the least significant bit data.

14. The method of claim 10, wherein, Performing the read operation includes: The read voltage level is determined based on the programming state of the first non-volatile memory cell; and The least significant bit data is read from the first non-volatile memory cell by applying the read voltage with a defined level to the first non-volatile memory cell.

15. The method of claim 14, further comprising: The programming state is determined based on the number of bits of data programmed into the first non-volatile memory cell from the multi-bit data.

16. The method of claim 15, wherein, The multi-bit data is programmed into the first non-volatile memory cell in the order of the least significant bit to the most significant bit, and As the number of bits of data programmed into the first non-volatile memory cell increases, the level of the read voltage increases.

17. A memory system comprising: A memory die, including a first non-volatile memory cell that stores multiple bits of data; as well as Before the most significant bit of the plurality of bits is programmed into the first non-volatile memory cell, the controller, in response to a read command, reads the bit data that has been programmed into the first non-volatile memory cell according to the programming state of the first non-volatile memory cell, said bit data being a portion of the plurality of bits. The memory system further includes a data buffer that temporarily stores write data including the multi-bit data to be stored in the first non-volatile memory cell, and after the bit data has been programmed into the first non-volatile memory cell and before all the data in the multi-bit data has been programmed into the first non-volatile memory cell, the controller further removes the portion of the write data corresponding to the bit data from the data buffer.

18. The memory system according to claim 17, in, The controller determines the programming state based on the number of bits of data programmed into the first non-volatile memory cell from the multi-bit data, and The controller determines the level of the read voltage based on the programming state, and performs a read operation to acquire the bit data by applying the read voltage to the first non-volatile memory cell.

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