A stacked structure of a chip substrate

Abstract

The application belongs to the technical field of chip packaging, and discloses a laminated structure of a chip substrate. The laminated structure of the chip substrate comprises first to sixth wiring layers from top to bottom, and each wiring layer comprises a core wiring area. In the core wiring area, the first wiring layer is used for laying a first power plane, the second wiring layer is used for laying a ground plane, the third wiring layer is used for laying a second power plane, the fourth wiring layer is used for laying a third power plane, the fifth wiring layer is used for laying the ground plane, and the sixth wiring layer is used for laying the first power plane. The laminated structure of the chip substrate provided by the application can realize the laying of the power plane and the ground plane of the chip substrate by using only six layers of substrates, reduces the wiring layers of the chip substrate to six layers, reduces the total thickness of the chip substrate by nearly half, thereby reducing the production cost of the chip and reducing the thickness and volume of the finished chip.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, specifically to a stacked structure of a chip substrate. Background Technology

[0002] High-frequency and high-speed chips have high requirements for power supply performance and high-speed signal performance during packaging design. In order to ensure the requirements of high-speed signal and power supply performance, the traditional high-frequency and high-speed chip substrate has a stacked structure of at least 10 wiring layers. The finished chip obtained by the traditional high-frequency and high-speed chip substrate is thick and large. Summary of the Invention

[0003] The purpose of this application is to provide a stacked structure for a chip substrate that reduces the number of stacked layers, thereby reducing the thickness and volume of the finished chip and thus reducing the chip production cost.

[0004] This application provides a stacked structure for a chip substrate, wherein the chip substrate includes a first to a sixth wiring layer from top to bottom, and each wiring layer includes a core wiring region.

[0005] In the core routing area, the first routing layer is used to lay the first power plane, the second routing layer is used to lay the ground plane, the third routing layer is used to lay the second power plane, the fourth routing layer is used to lay the third power plane, the fifth routing layer is used to lay the ground plane, and the sixth routing layer is used to lay the first power plane.

[0006] In some embodiments, each of the routing layers further includes a high-speed serial signal routing area and a high-speed input / output interface routing area;

[0007] In the high-speed serial signal routing area, the first routing layer is used to lay the fourth power plane and fan out the high-speed serial signal of the transmitting end; the second routing layer is used to lay the ground plane and fan out the clock signal; the third routing layer is used to lay the fourth power plane and the fifth power plane; the fourth routing layer is used to lay the ground plane; the fifth routing layer is used to lay the fourth power plane, fan out the high-speed serial signal of the receiving end, and fan out the clock signal of the jumper; and the sixth routing layer is used to lay the ground plane.

[0008] In the high-speed input / output interface routing area, the first routing layer is used to lay the sixth power plane and fan out the first high-speed differential signal; the second routing layer is used to lay the ground plane; the third routing layer is used to lay the sixth power plane; the fourth routing layer is used to lay the ground plane; the fifth routing layer is used to lay the sixth power plane and fan out the second high-speed differential signal; the sixth routing layer is used to lay the ground plane and fan out the first high-speed differential signal of the jumper and the second high-speed differential signal of the jumper.

[0009] In some embodiments, the wiring material of the first to sixth wiring layers is a conductive metal.

[0010] In some embodiments, the trace material of the first to sixth trace layers is metallic copper.

[0011] In some embodiments, the thickness of the first routing layer, the second routing layer, the fifth routing layer, and the sixth routing layer is 10 micrometers to 20 micrometers, and the thickness of the third routing layer and the fourth routing layer is 15 micrometers to 29 micrometers.

[0012] In some embodiments, a first dielectric layer is provided between the first routing layer and the second routing layer, a second dielectric layer is provided between the second routing layer and the third routing layer, a third dielectric layer is provided between the third routing layer and the fourth routing layer, a fourth dielectric layer is provided between the fourth routing layer and the fifth routing layer, and a fifth dielectric layer is provided between the fifth routing layer and the sixth routing layer.

[0013] In some embodiments, the first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are resin materials, and the third dielectric layer is a core board material.

[0014] In some embodiments, the thickness of the first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer is 24 micrometers to 36 micrometers, and the thickness of the third dielectric layer is 370 micrometers to 450 micrometers.

[0015] In some embodiments, the chip substrate further includes a first solder resist layer and a second solder resist layer;

[0016] The first solder mask layer is disposed above the first trace layer, and the second solder mask layer is disposed below the sixth trace layer.

[0017] In some embodiments, the thickness of both the first solder mask layer and the second solder mask layer is 13.5 micrometers to 28.5 micrometers.

[0018] This application provides a chip substrate stacked structure. Compared with the traditional chip substrate stacked structure, the number of wiring layers of the chip substrate is reduced from 10 layers to 6 layers, which reduces the total number of layers of the chip substrate by nearly half, thereby reducing the chip production cost, as well as the thickness and volume of the finished chip. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A planar structure diagram of an FPGA chip provided in an embodiment of this application is shown.

[0021] Figure 2 This illustration shows a schematic diagram of a high-speed signal in an FPGA chip according to an embodiment of this application. Detailed Implementation

[0022] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0024] High-frequency and high-speed FPGA chips have high requirements for power supply performance and high-speed signal performance during packaging design. In order to ensure the requirements of high-speed signal and power supply performance, the traditional high-frequency and high-speed FPGA chip substrate has a stacked structure of at least 10 wiring layers. The finished chip obtained by the traditional high-frequency and high-speed chip substrate is also relatively thick and large. The stacked structure of the traditional high-frequency and high-speed chip substrate is shown in Table 1 and Table 2 below.

[0025] Table 1

[0026] L1 Power supply 1 Power supply 5 Power supply 1 L2 GND TX / GND GND / Sigal L3 GND / Sigal GND GND L4 GND RX / GND GND / Sigal L5 Power Supply 2 / Power Supply 3 GND Power Supply 7 L6 Power supply 1 Power supply 5 Power supply 8 L7 GND GND GND L8 Power Supply 2 GND GND / Sigal L9 GND Power Supply 6 Power supply 1 L10 Power Supply 4 GND GND

[0027] As shown in Table 1, a traditional high-frequency high-speed chip substrate includes a core routing area, a high-speed serial signal routing area, and a high-speed input / output interface routing area. The chip substrate includes ten routing layers from top to bottom, L1 to L10. In the core routing area, L1 layer is used for power supply 1, L2 layer is used for the GND plane, L3 layer is used for the GND plane, and fan-out static lines and other stray signals (represented by sigal in Table 1) are used. L4 layer is used for the GND plane, L5 layer is used for power supply 2 and power supply 3, L6 layer is used for power supply 1, L7 layer is used for the GND plane, L8 layer is used for power supply 2, L9 layer is used for the GND plane, and L10 layer is used for power supply 4.

[0028] In the high-speed serial signal routing area, power supply 5 is laid on layer L1, GND plane is laid on layer L2, and high-speed serial signal of the transmitting end is fanned out on layer L3, GND plane is laid on layer L4, and high-speed serial signal of the receiving end is fanned out on layer L5, power supply 5 is still laid on layer L6, GND plane is laid on layer L7, GND plane is laid on layer L8, power supply 6 is laid on layer L9, and GND plane is laid on layer L10.

[0029] In the high-speed input / output interface routing area, power supply 1 is laid on layer L1, a GND plane and a set of high-speed differential signals of the fan-out chip are laid on layer L2, a GND plane and a GND plane and another set of high-speed differential signals of the fan-out chip are laid on layer L3, layer L4, and another set of high-speed differential signals of the fan-out chip are laid on layer L5, power supply 7 is laid on layer L6, power supply 8 is laid on layer L7, a GND plane is laid on layer L8, and the jumper-required parts of the high-speed differential signals of layers L2 and L4 are fanned out on layer L8. Power supply 1 is still laid on layer L9, and a GND plane is laid on layer L10.

[0030] It should be clarified that in the field of chip packaging design, various signals may require different types of power supplies, and each type of power supply is an independent power supply. Therefore, in fact, the power supplies 1 to 8 mentioned above will be determined according to the chip type and chip requirements. The differences between the power supplies 1 to 8 usually include differences in voltage, current and related communication / power protocols. The purpose of this application embodiment is to provide a stacked structure of a chip substrate, so the differences in power supplies used in chip packaging design will not be further explained.

[0031] Table 2

[0032]

[0033]

[0034] As shown in Table 2, traditional high-frequency and high-speed chip substrates include dielectric layers between each trace layer. The dielectric layer between L5 and L6 is made of core material, while the dielectric layers between the remaining layers are made of resin material (ABF, Ajinomoto Build-up Film). The dielectric layer between L5 and L6 is 820 micrometers thick. Because the Core layer is too thick, the main parts of the two sets of high-speed differential signals can only be fanned out above the Core layer, namely the L1 and L4 layers.

[0035] In view of the problems of traditional chip substrates having many wiring layers and thick chip substrates, embodiments of this application provide a stacked structure of a chip substrate. The chip substrate includes a first to a sixth wiring layer from top to bottom (i.e., from the top end to the bottom end of the chip substrate). Each wiring layer includes a core wiring region. Table 3 shows the wiring layers of each layer in the core wiring region of the stacked structure of the chip substrate provided in this application embodiment, as shown in Table 3 below:

[0036] L1 First power supply L2 GND L3 Second power supply L4 Third power supply L5 GND L6 First power supply

[0037] As shown in Table 3, in the core routing area, the first routing layer L1 is used to lay the first power plane, the second routing layer L2 is used to lay the ground plane GND, the third routing layer L3 is used to lay the second power plane, the fourth routing layer L4 is used to lay the third power plane, the fifth routing layer L5 is used to lay the ground plane GND, and the sixth routing layer L6 is used to lay the first power plane.

[0038] The chip substrate stacked structure provided in this application embodiment, compared with the traditional chip substrate stacked structure, only requires 6 substrate layers to realize the laying of the power plane and ground plane of the chip substrate, reducing the wiring layers of the chip substrate from 10 layers to 6 layers, reducing the total number of layers of the chip substrate by nearly half, thereby reducing the chip production cost, as well as the thickness and volume of the finished chip.

[0039] It should be clear that in the field of chip packaging design, various signals may require different types of power supplies, and each type of power supply is an independent power supply. Therefore, in practical applications, the type of power supply of the chip should be determined according to the chip requirements. Usually, the type of power supply can be distinguished by voltage, current and related communication / power protocols. The purpose of this application is to provide a stacked structure of a chip substrate, so the power supply used in chip packaging design will not be further described.

[0040] This application provides a stacked structure for a chip substrate. The first power supply, second power supply, and third power supply are all commonly used power supply types in chip packaging design by those skilled in the art, and each corresponds to an independent power supply. In some embodiments, in an FPGA chip substrate, the first power supply is a 1V power supply, the second power supply is a 1.8V power supply, and the third power supply is a 1V power supply. One difference between the first power supply and the third power supply is that the dynamic current of the first power supply is higher than that of the third power supply. This application only illustrates the distinction between the above power supply types by voltage and current, but it does not mean that the above power supply types only include the difference between voltage and current. The specific differences between the above power supply types involve chip power supply technology, which has departed from the solution provided in this application and all belong to the prior art. Therefore, this application will not describe them.

[0041] In some embodiments, the stacked structure of the chip substrate provided in this application further includes a high-speed serial signal routing area and a high-speed input / output interface routing area in each routing layer; Table 4 shows the routing of each layer of the high-speed serial signal routing area and the high-speed input / output interface routing area of ​​the stacked structure of the chip substrate provided in this application, as shown in Table 4 below:

[0042] L1 TX / Fourth Power Supply Sigal / Sixth Power Supply L2 Clk / GND GND L3 Fourth power supply / Fifth power supply L Sixth Power Supply L4 GND GND L5 RX / Clk / Fourth Power Supply Sigal / Sixth Power Supply L6 GND Sigal / GND

[0043] As shown in Table 4, in the high-speed serial signal routing area, the first routing layer L1 is used to lay the fourth power plane and the high-speed serial signal TX of the fan-out transmitter; the second routing layer L2 is used to lay the ground plane GND and the fan-out clock signal Clk; the third routing layer L3 is used to lay the fourth and fifth power planes; the fourth routing layer L4 is used to lay the ground plane GND; the fifth routing layer L5 is used to lay the fourth power plane, the high-speed serial signal RX of the fan-out receiver, and the clock signal Clk of the fan-out jumper; and the sixth routing layer L6 is used to lay the ground plane GND. Optionally, in some embodiments, in an FPGA chip substrate, the high-speed serial signal routing is implemented through a SerDes module, that is, in the high-speed serial signal routing area of ​​the FPGA chip, the transmitter refers to the transmitter of the SerDes module, and the receiver refers to the receiver of the SerDes module.

[0044] The purpose of the first routing layer is to fan out the high-speed serial signal from the transmitting end. Specifically, this is achieved by first laying the fourth power plane and then fanning out the high-speed differential signal within the fourth power plane. The purpose of the second routing layer is to fan out the clock signal. This is achieved by first laying the ground plane and then fanning out the clock signal within the ground plane. The third routing layer lays out the fourth and fifth power planes, dividing the routing layer into two regions for laying out the fourth and fifth power planes respectively. The purpose of the fifth routing layer is to fan out the high-speed serial signal from the receiving end and the jumper clock signal. This is achieved by first laying out the fourth power plane and then fanning out the high-speed serial signal from the receiving end and the jumper clock signal within the fourth power plane. The jumper clock signal refers to the fact that the second routing layer cannot fan out all the clock signals, so the remaining clock signals are fanned out through the fifth routing layer.

[0045] As shown in Table 4, in the high-speed input / output interface routing area, the first routing layer L1 is used to lay the sixth power plane and fan out the first high-speed differential signal; the second routing layer L2 is used to lay the ground plane GND; the third routing layer L3 is used to lay the sixth power plane; the fourth routing layer L4 is used to lay the ground plane GND; the fifth routing layer L5 is used to lay the sixth power plane and fan out the second high-speed differential signal; and the sixth routing layer L6 is used to lay the ground plane GND and fan out the first high-speed differential signal and the second high-speed differential signal of the jumper.

[0046] The purpose of the first routing layer is to fan out the first high-speed differential signal by first laying the sixth power plane and then fanning out the first high-speed differential signal within the sixth power plane. The purpose of the fifth routing layer is to fan out the second high-speed differential signal by first laying the sixth power plane and then fanning out the second high-speed differential signal within the sixth power plane. The purpose of the sixth routing layer is to lay the jumper portion of the first and second high-speed differential signals by first laying the ground plane and then fanning out the jumper portion of the first and second high-speed differential signals within the ground plane. The first and second high-speed differential signals of the jumpers refer to the fact that the first and second routing layers cannot fan out all of the first and second high-speed differential signals, so the remaining first and second high-speed differential signals are fanned out through the fifth routing layer.

[0047] It should be clarified that in the embodiments of this application, the first high-speed differential signal and the second high-speed differential signal represent multiple high-speed differential signals, rather than a single high-speed differential signal. Figure 1 This application provides a planar structural diagram of an FPGA chip according to an embodiment of the present application. Figure 1As shown, a typical FPGA chip consists of a core region at the center of the die and a peripheral region (including serdes and HP / HR) surrounding the core region. The core region at the center of the die typically includes power and ground bumps, while the peripheral region of the die typically includes various high-speed signals. Figure 1 In short, a high-speed signal in a region is called a bank of high-speed signals. Typically, a chip includes multiple banks. Taking the case where the high-speed signals and power supply bumps in each bank are arranged in the same way as an example, Figure 2 This illustration shows a schematic diagram of a high-speed signal in an FPGA chip according to an embodiment of this application, such as... Figure 2 As shown, a bank includes two high-speed differential signals, corresponding to the first and second high-speed differential signals of the bank, respectively. Adjacent to the high-speed differential signals are the power supply bump and ground bump within the bank. (The remaining text appears to be incomplete and requires further context.) Figure 1 and attached Figure 2 The example is only used to illustrate the location of the first and second high-speed differential signals in a chip within a bank.

[0048] In some embodiments, the stacked structure of a chip substrate provided in this application includes a fourth power supply, a fifth power supply, and a sixth power supply, which are commonly used power supply types in chip packaging design by those skilled in the art, each corresponding to an independent power supply. In some embodiments, in an FPGA chip substrate, the fourth power supply is a 1V analog power supply, the fifth power supply is a 1.8V analog power supply, and the sixth power supply is a 3.3V input / output port power supply. The fourth and fifth power supplies are independent power supplies in the high-speed serial signal trace area, and the sixth power supply is an independent power supply in the high-speed input / output interface trace area. This application only illustrates how voltage and current can be used to distinguish the above power supply types, but it does not imply that the above power supply types only include differences in voltage and current. The specific differences in the above power supply types involve chip power supply technology, which deviates from the solution provided in this application and belongs to the prior art; therefore, this application will not describe them.

[0049] Table 5 shows the stacking configuration of the chip substrate provided in the embodiments of this application, as follows:

[0050] Table 5.

[0051] soldermask 21 ±7.5 L1 Metal 15 ±5 ABF 30 ±6 L2 Metal 15 ±5 ABF 30 ±6 L3 Metal 22 ±7 Core 410 ±40 L4 Metal 22 ±7 ABF 30 ±6 L5 Metal 15 ±5 ABF 30 ±6 L6 Metal 15 ±5 soldermask 21 ±7.5

[0052] As shown in Table 5, in some embodiments, the chip substrate stack structure provided in this application provides a conductive metal as the wiring material for the first to sixth wiring layers. Specifically, the conductive metal can be any metal with conductive properties, and the better the conductivity, the higher the chip performance.

[0053] As shown in Table 5, in some embodiments, the chip substrate stack structure provided in this application uses copper as the trace material for the first to sixth trace layers. Based on the cost and conductivity of conductive metals, copper is a more cost-effective choice as the trace material for the first to sixth trace layers.

[0054] As shown in Table 5, in some embodiments, the chip substrate stack structure provided in this application has a thickness of 10 micrometers to 20 micrometers for the first wiring layer, the second wiring layer, the fifth wiring layer and the sixth wiring layer, and a thickness of 15 micrometers to 29 micrometers for the third wiring layer and the fourth wiring layer.

[0055] As shown in Table 5, in some embodiments, the stacked structure of the chip substrate provided in this application embodiment has a first dielectric layer between the first wiring layer and the second wiring layer, a second dielectric layer between the second wiring layer and the third wiring layer, a third dielectric layer between the third wiring layer and the fourth wiring layer, a fourth dielectric layer between the fourth wiring layer and the fifth wiring layer, and a fifth dielectric layer between the fifth wiring layer and the sixth wiring layer.

[0056] As shown in Table 5, in some embodiments, the chip substrate stacked structure provided in this application embodiment has a first dielectric layer, a second dielectric layer, a fourth dielectric layer and a fifth dielectric layer made of resin material (ABF material), and a third dielectric layer made of core material (Core material).

[0057] As shown in Table 5, in some embodiments, the chip substrate stack structure provided in this application has a thickness of 24 micrometers to 36 micrometers for the first dielectric layer, the second dielectric layer, the fourth dielectric layer and the fifth dielectric layer, and a thickness of 370 micrometers to 450 micrometers for the third dielectric layer.

[0058] As shown in Table 5, in some embodiments, the chip substrate stacked structure provided in this application further includes a first solder mask and a second solder mask.

[0059] The first solder mask layer is placed above the first trace layer, and the second solder mask layer is placed below the sixth trace layer.

[0060] As shown in Table 5, in some embodiments, the thickness of the first solder resist layer and the second solder resist layer in the stacked structure of the chip substrate provided in this application are both 13.5 micrometers to 28.5 micrometers.

[0061] This application provides a chip substrate stack structure that, compared to existing technologies, reduces the number of wiring layers in the chip substrate from 10 to 6, decreasing the total number of layers by nearly half. This reduces chip production costs, the thickness of the finished chip, and its volume. Specifically, the thickness of the core material is reduced from approximately 820 micrometers to approximately 410 micrometers, enabling the second high-speed differential signal to be fanned out below the dielectric layer fabricated from the core material.

[0062] On the other hand, the stacked structure of the chip substrate provided in this application optimizes the power supply configuration and high-speed differential signal configuration of each layer of the chip substrate, as shown in Tables 3 and 4. Some simulation results based on the stacked structure of the chip substrate provided in this application are shown in Tables 6 and 7.

[0063] Table 6

[0064]

[0065] Table 7

[0066] 6-layer substrate 14.4db 0.59db 30.35db 10-layer substrate 14.1db 0.58db 32.78db

[0067] As shown in Tables 6 and 7, after the chip substrate stack is reduced to 6 layers, the voltage drop and loop inductance of the power supply are better than those of a 10-layer chip substrate because the thickness of the substrate core dielectric layer is reduced. The insertion loss and return loss of high-speed differential signals are close to those of a 10-layer chip substrate. Although the far-end crosstalk is increased by 2.4 dB compared to a 10-layer chip substrate, it is still within the quality range of high-speed differential signals. That is, the stack structure of the chip substrate provided in this application embodiment has performance that is not much different from that of a 10-layer chip substrate, and the substrate thickness is reduced by about half, resulting in lower chip production costs. In addition, this application embodiment reduces the substrate thickness of the chip while ensuring performance, thereby reducing the thickness and volume of the finished chip, making the finished chip smaller and applicable to smaller scenarios.

[0068] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A stacked structure for a chip substrate, characterized in that, The chip substrate includes a first to a sixth wiring layer from top to bottom, and each wiring layer includes a core wiring area. In the core routing area, the first routing layer is used to lay the first power plane, the second routing layer is used to lay the ground plane, the third routing layer is used to lay the second power plane, the fourth routing layer is used to lay the third power plane, the fifth routing layer is used to lay the ground plane, and the sixth routing layer is used to lay the first power plane. Each of the aforementioned routing layers also includes a high-speed serial signal routing area and a high-speed input / output interface routing area; In the high-speed serial signal routing area, the first routing layer is used to lay the fourth power plane and fan out the high-speed serial signal of the transmitting end; the second routing layer is used to lay the ground plane and fan out the clock signal; the third routing layer is used to lay the fourth power plane and the fifth power plane; the fourth routing layer is used to lay the ground plane; the fifth routing layer is used to lay the fourth power plane, fan out the high-speed serial signal of the receiving end, and fan out the clock signal of the jumper; and the sixth routing layer is used to lay the ground plane. In the high-speed input / output interface routing area, the first routing layer is used to lay the sixth power plane and fan out the first high-speed differential signal; the second routing layer is used to lay the ground plane; the third routing layer is used to lay the sixth power plane; the fourth routing layer is used to lay the ground plane; the fifth routing layer is used to lay the sixth power plane and fan out the second high-speed differential signal; the sixth routing layer is used to lay the ground plane and fan out the first high-speed differential signal of the jumper and the second high-speed differential signal of the jumper. The thickness of the first, second, fifth, and sixth wiring layers is 10 to 20 micrometers, and the thickness of the third and fourth wiring layers is 15 to 29 micrometers.

2. The stacked structure of the chip substrate as described in claim 1, characterized in that, The trace material for the first to sixth trace layers is conductive metal.

3. The stacked structure of the chip substrate as described in claim 2, characterized in that, The trace material for the first to sixth trace layers is metallic copper.

4. The stacked structure of the chip substrate as described in claim 1, characterized in that, A first dielectric layer is provided between the first routing layer and the second routing layer, a second dielectric layer is provided between the second routing layer and the third routing layer, a third dielectric layer is provided between the third routing layer and the fourth routing layer, a fourth dielectric layer is provided between the fourth routing layer and the fifth routing layer, and a fifth dielectric layer is provided between the fifth routing layer and the sixth routing layer.

5. The stacked structure of the chip substrate as described in claim 4, characterized in that, The first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are made of resin material, and the third dielectric layer is made of core board material.

6. The stacked structure of the chip substrate as described in claim 4, characterized in that, The thicknesses of the first dielectric layer, the second dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are 24 micrometers to 36 micrometers, and the thickness of the third dielectric layer is 370 micrometers to 450 micrometers.

7. The stacked structure of the chip substrate as described in claim 1, characterized in that, The chip substrate further includes a first solder resist layer and a second solder resist layer; The first solder mask layer is disposed above the first trace layer, and the second solder mask layer is disposed below the sixth trace layer.

8. The stacked structure of the chip substrate as described in claim 7, characterized in that, The thickness of both the first solder mask layer and the second solder mask layer is 13.5 micrometers to 28.5 micrometers.

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