半导体器件的版图结构
By designing the length difference of the floating gate pattern in the layout structure of semiconductor devices and reducing the chamfer at the top corner, the problem of excessive leakage current in flash memory devices is solved, and the reliability of the devices is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED NOVA TECH - XIANFENG (SHAOXING) CORP
- Filing Date
- 2023-10-10
- Publication Date
- 2026-07-17
AI Technical Summary
Existing flash memory devices suffer from excessive leakage current, especially as the size of memory cells shrinks, which can lead to reliability issues.
Design a layout structure for a semiconductor device, wherein a floating gate pattern has a first side and a second side opposite each other in a first direction, the first side being closer to the first pattern and the length of the first side being greater than that of the second side. This design reduces the chamfer at the top corner of the floating gate, increases the effective channel length in the edge region, and reduces leakage current.
By improving the leakage current in the edge region of the floating gate, the effective channel length deviation between the center region and the edge region of the floating gate is reduced, effectively reducing leakage current and improving the reliability of the device.
Smart Images
Figure CN117393557B_ABST