A fractional order hyperchaotic model, circuit and module based on double memristor

Abstract

This invention relates to the field of hyperchaotic circuit design technology, and more specifically, to a fractional-order hyperchaotic model, circuit, and module based on dual memristors. The invention provides a fractional-order hyperchaotic model and circuit based on dual memristors, organically combining a non-chaotic circuit section, a magnetically controlled memristor, and a charge-controlled memristor to achieve a hyperchaotic state. Verification has shown that this circuit exhibits complex dynamic behavior and its output signal possesses stronger hyperchaotic characteristics, which can improve security in applications such as secure communication. This invention solves the problems of low complexity and low security in existing integer-order chaotic systems.

Description

Technical Field

[0001] This invention relates to the field of hyperchaotic circuit design technology, and more specifically, to a fractional-order hyperchaotic model based on dual memristors, a fractional-order hyperchaotic circuit built based on the model, and a hyperchaotic signal generation module based on the circuit layout. Background Technology

[0002] Chaos is the unpredictable random motion of deterministic dynamic systems that are sensitive to initial conditions. Currently, chaos can be divided into chaotic systems and hyperchaotic systems. Hyperchaotic systems are characterized by having two or more positive Lyapunov exponents, whose chaotic dynamics unfold simultaneously in multiple directions, generating more complex attractors. Therefore, hyperchaotic systems possess higher complexity and stronger randomness and unpredictability, giving them a greater advantage in practical applications such as chaotic communication and chaotic encryption.

[0003] In their research on chaos, researchers have discovered that fractional-order systems also exhibit chaotic phenomena. With the continuous refinement of chaos theory and the emergence of fractional-order characteristics in many practical engineering and physical systems, fractional calculus reflects natural phenomena more accurately than integer calculus. The dynamics of fractional-order systems depend not only on the system's parameters but also on its order. More importantly, extensive research indicates that fractional-order systems exist in real life, while integer-order systems are a special case of fractional-order systems.

[0004] Currently, the most common approach is to construct memristor circuits by configuring various memristors in traditional circuits to achieve chaos. Most existing research on chaotic systems is based on integer-order systems, but ordinary integer-order chaotic systems have low complexity, poor performance in secure communication, low security, and are easily cracked. Therefore, the inventors focused on hyperchaotic systems and considered using fractional-order implementations. However, fractional-order implementations are more difficult than integer-order implementations, and there is currently limited research on fractional-order systems. Through numerous experiments, the inventors finally constructed a fractional-order hyperchaotic circuit for application in secure communication. Summary of the Invention

[0005] Therefore, it is necessary to address the issues of low complexity and low security of existing integer-order chaotic systems by providing a fractional-order hyperchaotic model, circuit, and module based on dual memristors.

[0006] This invention is achieved using the following technical solution:

[0007] In a first aspect, the present invention provides a fractional-order hyperchaotic model based on dual memristors, comprising: a non-chaotic circuit section and a dual memristor section.

[0008] The non-chaotic circuit section provides a three-dimensional basic model. The dual memristor section, connected to the non-chaotic circuit section, introduces three nonlinear terms into the basic model to form a five-dimensional model with hyperchaotic characteristics. The dual memristor section includes a magnetically controlled memristor and a charge-controlled memristor.

[0009] The dynamic model equations of the five-dimensional model are:

[0010]

[0011] In the formula, x, y, z, u, w are five-dimensional state variables; a1, b1, a2, b2, c, d, e, f, g, k are constants; D q This indicates that the derivative is performed q times.

[0012] The implementation of this fractional-order hyperchaotic model based on dual memristors is carried out according to the method or process of embodiments of this disclosure.

[0013] Secondly, the present invention provides a fractional-order hyperchaotic circuit based on dual memristors, which is constructed based on the fractional-order hyperchaotic model based on dual memristors disclosed in the first aspect.

[0014] The implementation of this fractional-order hyperchaotic circuit based on dual memristors is carried out according to the method or process of embodiments of this disclosure.

[0015] Thirdly, the present invention provides a hyperchaotic signal generation module that adopts the circuit layout of the fractional-order hyperchaotic circuit based on dual memristors disclosed in the second aspect.

[0016] The implementation of this hyperchaotic signal generation module is based on the method or process of an embodiment of this disclosure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] This invention provides a fractional-order hyperchaotic model and circuit based on dual memristors. It organically combines a non-chaotic circuit section, a magnetically controlled memristor, and a charge-controlled memristor to achieve a hyperchaotic state. Verification has shown that this circuit exhibits complex dynamic behavior and its output signal possesses stronger hyperchaotic characteristics, which can improve security in applications such as secure communication. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a structural diagram of a fractional-order hyperchaotic model based on dual memristors provided in Embodiment 1 of the present invention;

[0021] Figure 2 for Figure 1 DC-VI diagram of a magnetically controlled memristor;

[0022] Figure 3 for Figure 1 DC-VI diagram of a Sino-Dutch controlled memristor;

[0023] Figure 4 This is a bifurcation diagram of the fractional-order hyperchaotic model in Embodiment 1 of the present invention as a function of fractional-order q;

[0024] Figure 5 This is a Lyapunov exponent diagram of the fractional-order hyperchaotic model in Embodiment 1 of the present invention;

[0025] Figure 6 The Matlab simulation phase diagram of the fractional-order hyperchaotic model in Embodiment 1 of the present invention at q = 0.8;

[0026] Figure 7 The image shows the time-domain simulation of the fractional-order hyperchaotic model in Embodiment 1 of this invention at q = 0.8 using Matlab.

[0027] Figure 8 for Figure 7 Enlarged image from 900 to 1000 seconds;

[0028] Figure 9 The circuit diagram is provided in Embodiment 1 of the present invention for a fractional-order hyperchaotic circuit based on dual memristors;

[0029] Figure 10 for Figure 9 Circuit diagram of the chaotic circuit section in Central Africa;

[0030] Figure 11 for Figure 9 Circuit diagram of a magnetically controlled memristor;

[0031] Figure 12 for Figure 9 Circuit diagram of a medium-sized controlled memristor;

[0032] Figure 13 for Figure 9 Circuit diagram of C1 to C5;

[0033] Figure 14 The figure shows the Multisim simulation results of the fractional-order hyperchaotic circuit in Embodiment 2 of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] Example 1

[0038] See Figure 1 This embodiment 1 provides a fractional-order hyperchaotic model based on dual memristors. From the perspective of dynamic model analysis, this fractional-order hyperchaotic model based on dual memristors is divided into: a non-chaotic circuit section and a dual memristor section.

[0039] ① The non-chaotic circuit section is used to provide a three-dimensional basic model.

[0040] The dynamic model equations of the three-dimensional basic model are:

[0041]

[0042] In the formula, d, e, k, and f are constants, and x, y, and z represent state variables.

[0043] ② The dual memristor section is connected to the non-chaotic circuit section to introduce three nonlinear terms into the basic model to form a five-dimensional model with hyperchaotic characteristics.

[0044] The dual memristor section includes a magnetically controlled memristor and a charge-controlled memristor.

[0045] The dynamic model equation of the magnetically controlled memristor is as follows:

[0046]

[0047] In the formula, i represents the current flowing through the magnetically controlled memristor, v represents the voltage through the magnetically controlled memristor, Wq(u) represents the memconductance of the magnetically controlled memristor, u is the state variable (i.e., the magnetic flux of the magnetically controlled memristor), and a1 and b1 are constants.

[0048] See Figure 2 The DC-VI plot of the magnetically controlled memristor is shown. It can be seen that the area of ​​the closed curve decreases with the increase of the input frequency, and the closed curve presents an "8" shape, which is consistent with the characteristics of the magnetically controlled memristor.

[0049] The dynamic model equation of the load-controlled memristor is:

[0050]

[0051] In the formula, i′ represents the current flowing through the charge-controlled memristor, v′ represents the voltage through the charge-controlled memristor, Mq(w) represents the memconductance of the charge-controlled memristor, w is the state variable (i.e. the charge of the charge-controlled memristor), and a2 and b2 are constants.

[0052] See Figure 3 The DC-VI diagram of the charge-controlled memristor is shown, and it can be seen that it conforms to the characteristics of a charge-controlled memristor.

[0053] Therefore, the dynamic model equations for the entire five-dimensional model are:

[0054]

[0055] Based on the above dynamic model equations, the inventors used Matlab software for simulation, employing the Adomain algorithm. The corresponding parameter values ​​were: a1 = 1, a2 = 2, b1 = 0.1, b2 = -1, c = -1, d = 1, e = 0.5, f = 1, g = 0.1, k = 0.1. The initial values ​​of x, y, z, u, and w were (0.02, 0.01, 0, 0, 0), resulting in the bifurcation diagram of the model as a function of order q, as shown below. Figure 4 As shown, the corresponding Lyapunov index diagram is as follows: Figure 5 As shown, two Lyapunov exponents are greater than 0, indicating that the model has entered a hyperchaotic state. The phase diagram for q = 0.8 is shown below. Figure 6 As shown, where, Figure 6 (a) shows the xy plane; Figure 6 (b) shows the zw plane, indicating that the model has complex hyperchaotic characteristics.

[0056] See Figures 7-8 The simulation time-domain plot is shown; among them, from Figure 7 It can be seen that the time-domain waveforms are inconsistent, which further illustrates that the phase diagram is chaotic; Figure 8It is to intercept Figure 7 In the 900-1000s time range, it can be seen that the time-domain waveforms are of varying sizes.

[0057] Example 2

[0058] Based on the fractional-order hyperchaotic model using dual memristors in Example 1, the inventors constructed the circuit. See details... Figure 9 This is a circuit structure diagram of the fractional-order hyperchaotic circuit based on dual memristors provided in Embodiment 1.

[0059] In summary, the mathematical model of this fractional-order hyperchaotic circuit based on dual memristors is as follows:

[0060]

[0061] The meanings of the parameters in this formula will be explained in the following sections and will not be explained here.

[0062] Still following the classification method of dynamic models, Figure 9 The circuit is divided into a non-chaotic circuit section, a magnetically controlled memristor, and a charge-controlled memristor.

[0063] ①See Figure 10 The non-chaotic circuit section includes: amplifiers U1 to U6, resistors R0, R3 to R6, resistors Re1 to Re6, and fractional capacitors C1 to C3.

[0064] The positive input terminals of U1, U2, U3, U4, U5, and U6 are grounded. The input terminal of R0 is connected to the output terminal of U6, and its output terminal is connected to the inverting input terminal of U1. The input terminal of R3 is connected to the output terminal of U4, and its output terminal is connected to the inverting input terminal of U3. The input terminal of R4 is connected to the output terminal of U5, and its output terminal is connected to the inverting input terminal of U3. The input terminal of R5 is connected to the output terminal of U5, and its output terminal is connected to the inverting input terminal of U3. The input terminal of R6 is connected to the output terminal of U4, and its output terminal is connected to the inverting input terminal of U5. The input terminal of Re1 is connected to the output terminal of U1, and its output terminal is connected to the inverting input terminal of U2. The input terminal of Re2 is connected to the inverting input terminal of U2, and its output terminal is connected to the output terminal of U2. The input terminal of Re3 is connected to the output terminal of U3, and its output terminal is connected to the inverting input terminal of U4. The input terminal of Re4 is connected to the inverting input terminal of U4, and its output terminal is connected to the output terminal of U4. The input terminal of Re5 is connected to the output terminal of U5, and its output terminal is connected to the inverting input terminal of U6. The input of Re6 is connected to the inverting input of U6, and its output is connected to the output of U6. The input of C1 is connected to the inverting input of U1, and its output is connected to the output of U1. The input of C2 is connected to the inverting input of U3, and its output is connected to the output of U3. The input of C3 is connected to the inverting input of U5, and its output is connected to the output of U5.

[0065] Among them, the output terminal of U1 serves as the positive x-direction output of the chaotic signal; the output terminal of U2 serves as the negative x-direction output of the chaotic signal; the output terminal of U3 serves as the positive y-direction output of the chaotic signal; the output terminal of U4 serves as the negative y-direction output of the chaotic signal; the output terminal of U5 serves as the positive z-direction output of the chaotic signal; and the output terminal of U6 serves as the negative z-direction output of the chaotic signal.

[0066] Based on the non-chaotic circuit section constructed from the above circuit, its mathematical model can be written as:

[0067]

[0068] Among them, v x v y v z These are the voltage values ​​across C1, C2, and C3, respectively.

[0069] ②See Figure 11 The magnetically controlled memristor includes: operational amplifier U7, multipliers M1 to M2, resistors R1 to R2, resistor R8, and fractional capacitor C4.

[0070] The positive input terminal of U7 is grounded. The output terminal of R8 is connected to the inverting input terminal of U7, and its input terminal is connected to the output terminal of U2. The input terminal of C4 is connected to the inverting input terminal of U7, and its output terminal is connected to the output terminal of U7. One input terminal of M1 is connected to the output terminal of U7, and the other input terminal is connected to the output terminal of U1. One input terminal of M2 is connected to the output terminal of M1, and the other input terminal is connected to the output terminal of U7. The input terminal of R1 is connected to the output terminal of U7, and its output terminal is connected to the inverting input terminal of U1. The input terminal of R2 is connected to the output terminal of M2, and its output terminal is connected to the inverting input terminal of U1.

[0071] Among them, the output of U7 serves as the u-direction output of the chaotic signal.

[0072] Based on the above circuit configuration, the mathematical model of the magnetically controlled memristor can be written as:

[0073]

[0074] Among them, v u is the voltage across C4; i is the current flowing through the magnetically controlled memristor.

[0075] ③See Figure 12 The charge-controlled memristor includes: operational amplifier U8, DC power supply V, multipliers M3 to M4, and resistors R9 to R1. 10 , resistor R7, fractional capacitor C5.

[0076] The positive input terminal of U8 is grounded. The negative terminal of V is grounded. One input terminal of M3 is connected to the output terminal of U6, and the other input terminal is connected to the output terminal of U8. One input terminal of M4 is connected to the output terminal of U5, and the other input terminal is connected to the output terminal of U5. The input terminal of R7 is connected to the output terminal of M3, and the output terminal is connected to the inverting input terminal of U5. The input terminal of R9 is connected to the output terminal of M4, and the output terminal is connected to the inverting input terminal of U8. 10 The input terminal of C5 is connected to the positive terminal of V, and the output terminal is connected to the inverting input terminal of U8. The input terminal of C5 is connected to the inverting input terminal of U8, and the output terminal is connected to the output terminal of U8.

[0077] Among them, the output of U8 is used as the w-direction output of the chaotic signal.

[0078] Based on the above circuit configuration, the mathematical model of the load-controlled memristor can be written as:

[0079]

[0080] Among them, v w V is the voltage across C5; v′ represents the voltage across the charge-controlled memristor.

[0081] Additionally, it should be noted that C1, C2, C3, C4, and C5 have the same structure, but their capacitance values ​​differ. Specifically, C... N Including resistor Rc1 N ~Rc5 N capacitor C1 N ~c5 N ;N∈[1,5].

[0082] See Figure 13 Rc1 N c1 N They are connected in parallel and form the first parallel section; Rc2 N c2 N They are connected in parallel, forming a second parallel section; Rc3 N c3 N They are connected in parallel and form a third parallel unit; Rc4 N c4 N They are connected in parallel, forming the fourth parallel section; Rc5 N c5 N They are connected in parallel to form the fifth parallel section; the first, second, third, fourth, and fifth parallel sections are connected in series in sequence.

[0083] To verify the feasibility of the above circuit, the inventors used Multisim software for simulation.

[0084] Among them, amplifiers U1 to U8 use AD711JN; multipliers M1 to M4 use MULTIPLIER;

[0085] R0=R1=R2=R5=R6=R7=R9=R 10 =10kΩ; R3=200kΩ; R4=20kΩ; R8=100kΩ;

[0086] Re1=Re2=Re3=Re4=Re5=Re6=15kΩ; V is 2V;

[0087] C1=0.188μF; C2=0.761μF; C3=0.452μF; C4=0.254μF; C5=0.139μF.

[0088] The Multisim simulation results for q = 0.8 are shown in the figure below. Figure 14 As shown. Among them, Figure 14 (a) shows the xy plane; Figure 14 (b) illustrates the zw plane. (By comparing with...) Figure 10 By comparison, we can see Figure 14 chaotic state and Figure 10 The chaotic states are the same, indicating that the above circuit can achieve hyperchaos.

[0089] Example 3

[0090] This embodiment 3 discloses a hyperchaotic signal generation module, which adopts the circuit layout of the fractional-order hyperchaotic circuit based on dual memristors disclosed in embodiment 2. The modular packaging facilitates the promotion and application of the aforementioned fractional-order hyperchaotic circuit.

[0091] The pins of this hyperchaotic signal generation module include: GND pin, x-axis output pin, y-axis output pin, z-axis output pin, u-axis output pin, and w-axis output pin.

[0092] The GND pin is used to ground the positive input terminals of U1, U2, U3, U4, U5, U6, U7, and U8. The x-axis output pin is used to connect to the output terminal of U1 or U2. The y-axis output pin is used to connect to the output terminal of U3 or U4. The z-axis output pin is used to connect to the output terminal of U5 or U6. The u-axis output pin is used to connect to the output terminal of U7. The w-axis output pin is used to connect to the output terminal of U8.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A fractional-order hyperchaotic circuit based on dual memristors, characterized in that, include: The non-chaotic circuit section is used to provide a three-dimensional basic model; as well as The dual memristor section, connected to the non-chaotic circuit section, is used to introduce three nonlinear terms into the basic model to form a five-dimensional model with hyperchaotic characteristics; wherein, the dual memristor section includes a magnetically controlled memristor and a charge-controlled memristor. The dynamic model equations of the five-dimensional model are as follows: ； In the formula, x , y , z , u , w It is a five-dimensional state variable; a 1. b 1. a 2. b 2. c , d , e , f , g , k It is a constant; D q Indicates to proceed q Second differential; q Indicates the order.

2. The fractional-order hyperchaotic circuit based on dual memristors according to claim 1, characterized in that, The non-chaotic circuit section includes: operational amplifiers U1~U6, resistors R0, resistors R3~R6, resistors Re1~Re6, and fractional capacitors C1~C3; The positive input terminals of U1, U2, U3, U4, U5, and U6 are grounded; The input terminal of R0 is connected to the output terminal of U6, and the output terminal is connected to the inverting input terminal of U1; The input of R3 is connected to the output of U4, and the output is connected to the inverting input of U3. The input of R4 is connected to the output of U5, and the output is connected to the inverting input of U3. The input terminal of R5 is connected to the output terminal of U1, and the output terminal is connected to the inverting input terminal of U5. The input terminal of R6 is connected to the output terminal of U4, and the output terminal is connected to the inverting input terminal of U5; The input of Re1 is connected to the output of U1, and the output is connected to the inverting input of U2. The input of Re2 is connected to the inverting input of U2, and the output is connected to the output of U2. The input of Re3 is connected to the output of U3, and the output is connected to the inverting input of U4. The input of Re4 is connected to the inverting input of U4, and the output is connected to the output of U4. The input of Re5 is connected to the output of U5, and the output is connected to the inverting input of U6. The input of Re6 is connected to the inverting input of U6, and the output is connected to the output of U6. The input terminal of C1 is connected to the inverting input terminal of U1, and the output terminal is connected to the output terminal of U1; The input terminal of C2 is connected to the inverting input terminal of U3, and the output terminal is connected to the output terminal of U3; The input terminal of C3 is connected to the inverting input terminal of U5, and the output terminal is connected to the output terminal of U5.

3. The fractional-order hyperchaotic circuit based on dual memristors according to claim 2, characterized in that, The mathematical model of the non-chaotic circuit section is as follows: ； in, v x , v y , v z These are the voltage values ​​across C1, C2, and C3, respectively.

4. The fractional-order hyperchaotic circuit based on dual memristors according to claim 2, characterized in that, The magnetically controlled memristor includes: operational amplifier U7, multipliers M1~M2, resistors R1~R2, resistor R8, and fractional capacitor C4; The positive input terminal of U7 is grounded; The output of R8 is connected to the inverting input of U7, and the input is connected to the output of U2. The input terminal of C4 is connected to the inverting input terminal of U7, and the output terminal is connected to the output terminal of U7; One input terminal of M1 is connected to the output terminal of U7, and the other input terminal is connected to the output terminal of U1; One input terminal of M2 is connected to the output terminal of M1, and the other input terminal is connected to the output terminal of U7; The input terminal of R1 is connected to the output terminal of U7, and the output terminal is connected to the inverting input terminal of U1. The input of R2 is connected to the output of M2, and the output is connected to the inverting input of U1.

5. The fractional-order hyperchaotic circuit based on dual memristors according to claim 4, characterized in that, The mathematical model of the magnetically controlled memristor is: ； in, v x This is the voltage across C1; v u This is the voltage value across C4; i This represents the current flowing through the magnetically controlled memristor.

6. The fractional-order hyperchaotic circuit based on dual memristors according to claim 4, characterized in that, The load-controlled memristor includes: operational amplifier U8, DC power supply V, multipliers M3~M4, and resistors R9~R 10 , resistor R7, fractional capacitor C5; The positive input terminal of U8 is grounded; The negative terminal of V is grounded; One input terminal of M3 is connected to the output terminal of U6, and the other input terminal is connected to the output terminal of U8; One input terminal of M4 is connected to the output terminal of U5, and the other input terminal is connected to the output terminal of U5; The input of R7 is connected to the output of M3, and the output is connected to the inverting input of U5. The input of R9 is connected to the output of M4, and the output is connected to the inverting input of U8. R 10 The input terminal is connected to the positive terminal of V, and the output terminal is connected to the inverting input terminal of U8; The input of C5 is connected to the inverting input of U8, and the output is connected to the output of U8.

7. The fractional-order hyperchaotic circuit based on dual memristors according to claim 6, characterized in that, The mathematical model of the charge-controlled memristor is: ； in, v z This is the voltage value across C3; v w This is the voltage value across C5; This indicates the voltage across the charge-controlled memristor.

8. The fractional-order hyperchaotic circuit based on dual memristors according to claim 6, characterized in that, C1, C2, C3, C4, and C5 have the same structure; among them, C N Including resistor Rc1 N ~Rc5 N capacitor C1 N ~c5 N N∈[1,5]; Rc1 N c1 N They are connected in parallel and form the first parallel section; Rc2 N c2 N They are connected in parallel, forming a second parallel section; Rc3 N c3 N They are connected in parallel and form a third parallel section; Rc4 N c4 N They are connected in parallel, forming the fourth parallel section; Rc5 N c5 N They are connected in parallel to form the fifth parallel section; the first, second, third, fourth, and fifth parallel sections are connected in series in sequence.

9. A hyperchaotic signal generation module, characterized in that, The circuit layout of the fractional-order hyperchaotic circuit based on dual memristors as described in any one of claims 1-8 is adopted.

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