A communication control method and apparatus

Abstract

The application discloses a communication control method and device. The method is applied to a processor in an electronic device. The processor is connected with an Ethernet port through an Ethernet controller. The Ethernet controller writes data sent by the Ethernet port into a storage area in the Ethernet controller, so that the processor can read the data from the storage area. The method comprises the following steps: in response to an interrupt flag, detecting whether there is a data read / write exception in the storage area; the interrupt flag is set by the Ethernet controller after the data sent by the Ethernet port is written into the storage area; wherein the storage area has a first pointer and a second pointer. The first pointer is used for pointing to a tail address before the data is written into the storage area. The second pointer is used for pointing to a tail address after the data is written into the storage area, so that the processor can read the data between the first pointer and the second pointer. If there is a data read / write exception in the storage area, the first pointer is controlled to point to a position pointed to by the second pointer.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a communication control method and apparatus. Background Technology

[0002] Ethernet, as a mainstream communication technology, is widely used in various industries. As the application of Ethernet in the industrial field gradually becomes more widespread, the demand for Ethernet ports is increasing.

[0003] Currently, the parallel bus interface of the Central Processing Unit (CPU) is extended to an Ethernet port through an external Ethernet controller. The Ethernet controller is equipped with memory to enable data transmission between the CPU and the Ethernet port.

[0004] However, if interference such as radiation or operational mechanisms occurs, it may affect the data errors in the memory of the Ethernet controller, affect the normal movement of the read and write pointers, and cause abnormal data read and write of the Ethernet controller. This will result in the data sent from the Ethernet port not being written to the Ethernet controller normally, thus causing abnormal communication between the CPU and the Ethernet port. Summary of the Invention

[0005] In view of this, this application provides a communication control method and apparatus to solve the technical defects in the prior art where communication abnormalities occur between the processor and the Ethernet port, as follows:

[0006] A communication control method is applied to a processor in an electronic device, wherein the processor is connected to an Ethernet port via an Ethernet controller, and the Ethernet controller writes data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area.

[0007] The method includes:

[0008] In response to an interrupt flag, the system detects whether there is a data read / write error in the storage area; the interrupt flag is set by the Ethernet controller after writing data sent from the Ethernet port into the storage area.

[0009] The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer.

[0010] If a data read / write error occurs in the storage area, the first pointer is controlled to point to the position pointed to by the second pointer.

[0011] The above method, preferably, includes at least the following steps in detecting whether there are data read / write anomalies in the storage area:

[0012] Obtain the status value from the status register in the Ethernet controller; the status value indicates whether data has been written to the storage area.

[0013] If the status value indicates that no data has been written to the storage area, it is determined that there is a data read / write anomaly in the storage area.

[0014] The above method, preferably, includes at least the following steps in detecting whether there are data read / write anomalies in the storage area:

[0015] Obtain the diagnostic value from the diagnostic register in the Ethernet controller; the diagnostic value indicates that a pointer anomaly exists in the storage area.

[0016] If the diagnostic value indicates that there is a pointer anomaly in the storage area, it is determined that there is a data read / write anomaly in the storage area.

[0017] Preferably, the diagnostic value is obtained through the following method:

[0018] Obtain the address length between the first pointer and the second pointer;

[0019] The address length is compared with the length of the data recorded in the data written to the storage area;

[0020] If the address length is inconsistent with the data length, the diagnostic value indicates that there is a pointer anomaly in the storage area;

[0021] If the address length is consistent with the data length, the diagnostic value indicates that there is no pointer anomaly in the storage area.

[0022] The above method, preferably, includes at least the following steps in detecting whether there are data read / write anomalies in the storage area:

[0023] Obtain the header information corresponding to the data written to the storage area;

[0024] Based on the header information, the correctness of the data written to the storage area is verified;

[0025] If the data written to the storage area fails the verification, it is determined that there is a data read / write anomaly in the storage area.

[0026] Preferably, if a data read / write anomaly occurs in the storage area, the method further includes:

[0027] If the processor reads the target data between the first pointer and the second pointer, it discards the target data.

[0028] Preferably, if there are no data read / write anomalies in the storage area, the method further includes:

[0029] Read data between the first pointer and the second pointer;

[0030] Control the first pointer to point to the position pointed to by the second pointer.

[0031] A communication control device includes a processor configured in an electronic device. The processor is connected to an Ethernet port via an Ethernet controller. The Ethernet controller writes data sent from the Ethernet port into a storage area in the Ethernet controller, so that the processor can read data from the storage area.

[0032] The device includes:

[0033] An anomaly detection unit is used to detect whether there is a data read / write anomaly in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area; if there is a data read / write anomaly in the storage area, the pointer control unit is triggered;

[0034] The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer.

[0035] A pointer control unit is used to control the first pointer to point to the position pointed to by the second pointer.

[0036] A storage medium for storing a computer program executed by a processor in an electronic device, the processor being connected to an Ethernet port via an Ethernet controller, the Ethernet controller writing data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area;

[0037] The computer program is executed by the processor to: detect whether there is a data read / write error in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area;

[0038] The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer.

[0039] If a data read / write error occurs in the storage area, the first pointer is controlled to point to the position pointed to by the second pointer.

[0040] An electronic device, comprising:

[0041] processor;

[0042] Ethernet controller;

[0043] The processor is connected to an Ethernet port via an Ethernet controller. The Ethernet controller writes the data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area.

[0044] The processor is used for:

[0045] In response to an interrupt flag, the system detects whether a data read / write error exists in the storage area. The interrupt flag is set by the Ethernet controller after writing data sent from the Ethernet port into the storage area. The storage area has a first pointer and a second pointer. The first pointer points to the end address of the storage area before data is written, and the second pointer points to the end address of the storage area after data is written, enabling the processor to read data between the first and second pointers. If a data read / write error exists in the storage area, the system controls the first pointer to point to the position pointed to by the second pointer.

[0046] As can be seen from the above technical solutions, in the communication control method and apparatus disclosed in this application, after the Ethernet controller writes the data sent from the Ethernet port into the storage area, the processor responds to the set interrupt flag and detects whether there is a data read / write error in the storage area. If there is a read / write error, the pointer pointing to the tail address of the storage area before the data was written is moved to be consistent with the pointer pointing to the tail address of the storage area after the data was written. Therefore, even if there is a previous data read / write error, it will not affect the next data read / write in the storage area because both pointers are pointing to the tail address in the storage area. This prevents continuous read / write errors in the storage area and avoids the Ethernet port from hanging due to continuous read / write errors. Consequently, a data read / write error in the storage area will not affect the subsequent normal communication between the processor and the Ethernet port, thereby improving the reliability of communication. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A flowchart of a communication control method provided in Embodiment 1 of this application;

[0049] Figure 2 This is a block diagram of the physical layer structure for the parallel bus to Ethernet converter in this application;

[0050] Figure 3 This is a schematic diagram of pointers in the SRAM of an Ethernet controller.

[0051] Figure 4 A diagram illustrating the data structure for backing up data in SRAM;

[0052] Figure 5 This is a schematic diagram of the structure of a communication control device provided in Embodiment 2 of this application;

[0053] Figure 6 This is another structural schematic diagram of a communication control device provided in Embodiment 2 of this application;

[0054] Figure 7 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of this application;

[0055] Figure 8 This is a block diagram of the physical layer structure for a conventional parallel bus to Ethernet converter.

[0056] Figure 9 This is a schematic diagram of the Ethernet controller receiving pointer under abnormal conditions;

[0057] Figure 10 This is a flowchart illustrating the process for fault diagnosis in control systems applicable to the industrial field. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0059] refer to Figure 1The diagram shown is a flowchart illustrating the implementation of a communication control method according to Embodiment 1 of this application. This method can be applied to a processor in an electronic device, which can be a computer or server, or other devices capable of transmitting data via an Ethernet port. The processor can be a central processing unit (CPU), such as... Figure 2 As shown, the electronic device also includes an Ethernet controller. The processor is connected to the Ethernet controller via a parallel bus interface. The Ethernet controller is connected to an Ethernet port. The Ethernet port receives data sent from other connected devices or networks and sends the data to the Ethernet controller. The Ethernet controller writes the data sent from the Ethernet port into its storage area, such as a static random-access memory (SRAM), so that the processor can read data from the storage area via the parallel bus interface, thus realizing data communication between the Ethernet port and the processor.

[0060] Specifically, the processor can perform the following processing:

[0061] Step 101: In response to the interrupt flag, check if there is a data read / write error in the storage area. If there is a data read / write error in the storage area, proceed to step 102.

[0062] The storage area has a first pointer and a second pointer. The first pointer points to the end address of the storage area before data is written to it, and the second pointer points to the end address of the storage area after data is written to it, so that the processor can read data between the first pointer and the second pointer.

[0063] It should be noted that the interrupt flag is set by the Ethernet controller after the data sent from the Ethernet port is written to the storage area.

[0064] For example, initially, both the first and second pointers point to the tail address in the memory area, indicating that there is no new data to be transmitted in the memory area. Based on this, after receiving data, the Ethernet port sends the data to the Ethernet controller. The Ethernet controller then writes the data sent from the Ethernet port into the memory area starting at the address following the tail address pointed to by the first pointer, such as MDPA (MEMORY DATA READPOINTER ADDRESS). It moves the second pointer, such as RWPA (RX SRAM WRITE POINTER ADDRESS), to the current tail pointer in the memory area, i.e., the tail address of the data being written. Figure 3As shown, the Ethernet controller then sets an interrupt flag. Upon detecting the interrupt flag, the processor can read data using addresses between MDPA and RWPA. After reading, the MDPA is moved to match the RWPA. However, data read / write anomalies may occur during this process, such as an interrupt flag indicating no data in the storage area, data errors, or pointer errors. Therefore, in this embodiment, after detecting the interrupt flag in the processor, anomaly detection can be performed first to determine whether there is a data read / write anomaly in the storage area.

[0065] Step 102: Control the first pointer to point to the position pointed to by the second pointer.

[0066] For example, in this embodiment, after an interrupt flag is detected in the processor, an abnormal data read / write operation in the storage area is detected. In order to avoid continued abnormalities, MDPA is moved to the position pointed to by RWPA. Thus, for the Ethernet controller, if new data is sent from the Ethernet port, normal data read / write can still be performed according to the two pointers. In this way, the previous data read / write abnormality will not affect the next data read / write.

[0067] As can be seen from the above technical solution, in the communication control method provided in Embodiment 1 of this application, after the Ethernet controller writes the data sent from the Ethernet port into the storage area, the processor responds to the set interrupt flag and detects whether there is a data read / write error in the storage area. If there is a read / write error, the pointer pointing to the tail address of the storage area before the data was written is moved to be consistent with the pointer pointing to the tail address of the storage area after the data was written. Therefore, even if there is a previous data read / write error in this embodiment, it will not affect the next data read / write in the storage area because both pointers are pointing to the tail address in the storage area. This avoids the situation of continuous read / write errors in the storage area, thus preventing the Ethernet port from hanging due to continuous read / write errors. Consequently, a data read / write error in the storage area will not affect the subsequent normal communication between the processor and the Ethernet port, thereby improving the reliability of communication.

[0068] In one implementation, when a data read / write exception is detected in the storage area in step 101, if the processor reads the target data between the first pointer and the second pointer, the target data is discarded to prevent the processor from using incorrect data.

[0069] Furthermore, in this embodiment, if no data read / write anomaly is detected in the storage area in step 101, that is, if there is no data read / write anomaly in the storage area, the processor can then read data between the first pointer and the second pointer to ensure the accuracy of the data read by the processor.

[0070] In the specific implementation, when no data read / write abnormality is detected in the storage area in step 101, the processor reads data between the first pointer and the second pointer, and then controls the first pointer to point to the position pointed to by the second pointer, so that the Ethernet controller can write the newly sent data from the Ethernet port into the storage area, thereby realizing normal communication between the processor and the Ethernet port.

[0071] For example, when the CPU detects that there is no data read / write error in the SRAM, it copies network data from the SRAM and controls WDPA to move to the location pointed to by RWPA, so that the new data can be read and written normally in the SRAM.

[0072] Based on the above implementation scheme, step 101 can detect whether there is an abnormal data read / write operation in the storage area through at least one of the following methods:

[0073] In one implementation, the status value in the status register of the Ethernet controller is obtained; the status value indicates whether data has been written to the storage area; if the status value indicates that no data has been written to the storage area, it is determined that there is a data read / write anomaly in the storage area.

[0074] In one implementation, a diagnostic value is obtained from the diagnostic register in the Ethernet controller; the diagnostic value indicates that a pointer abnormality exists in the storage area; if the diagnostic value indicates that a pointer abnormality exists in the storage area, it is determined that a data read / write abnormality exists in the storage area.

[0075] In one implementation, the header information corresponding to the data written to the storage area is obtained; the correctness of the data written to the storage area is verified based on the header information; if the data written to the storage area fails the verification, it is determined that there is a data read / write anomaly in the storage area.

[0076] It should be noted that in different embodiments, the execution order of the above implementation methods in step 101 may be different. Different technical solutions resulting from different implementation methods in step 101 and different execution orders of implementation methods are all within the protection scope of this application.

[0077] In one embodiment, step 101 can detect whether there is an abnormal data read / write operation in the storage area in the following way:

[0078] First, obtain the status value in the status register of the Ethernet controller. This status value indicates whether data has been written to the storage area. Then, judge the status value. If the status value indicates that no data has been written to the storage area, then it can be determined that there is a data read / write abnormality in the storage area.

[0079] If the status value indicates that data has been written to the storage area, then it can be preliminarily determined that there may be no data read / write anomalies in the storage area, but there may be other data read / write anomalies, such as pointer anomalies or inaccurate data.

[0080] For example, a status value of 1 indicates that data has been written to the storage area, but there may be other data read / write anomalies in the storage area. A status value of 0 indicates that no data has been written to the storage area, but because an interrupt flag indicates that the Ethernet controller has already written data to the storage area, it can be determined that there is a data read / write anomaly in the storage area.

[0081] In one embodiment, step 101 can detect whether there is an abnormal data read / write operation in the storage area in the following way:

[0082] First, obtain the diagnostic value in the diagnostic register of the Ethernet controller. This diagnostic value indicates that there is a pointer abnormality in the storage area. Then, judge the diagnostic value. If the diagnostic value indicates that there is a pointer abnormality in the storage area, then it can be determined that there is a data read / write abnormality in the storage area.

[0083] If the diagnostic value indicates that there is no pointer anomaly in the storage area, then it can be preliminarily determined that there may be no data read / write anomaly in the storage area, but there may be other data read / write anomalies, such as no data in the storage area or inaccurate data.

[0084] For example, a diagnostic value of 1 indicates a pointer anomaly in the storage area, confirming a data read / write anomaly. A status value of 0 indicates no pointer anomaly in the storage area, but other data read / write anomalies may exist.

[0085] In the specific implementation, the diagnostic value in the diagnostic register can be obtained in the following ways:

[0086] First, obtain the address length between the first pointer and the second pointer;

[0087] Then, the address length is compared with the data length recorded in the data written to the storage area. If the address length and the data length are inconsistent, it can be determined that there is a pointer anomaly in the storage area, such as a diagnostic value of 1. If the address length and the data length are consistent, it can be determined that there is no pointer anomaly in the storage area, such as a diagnostic value of 0.

[0088] For example, such as Figure 4The diagram shows the data structure of the data written to the storage area, including: a field for the diagnostic value of the diagnostic register, a field representing the reception status (i.e., the physical layer status), a field for the packet length (i.e., the recorded data length), and a field for network data. The diagnostic value is determined based on the packet length and the address length between MDPA and RWPA. If the two lengths are the same, the diagnostic value is 0; if they are different, the diagnostic value is 1. Based on this, this embodiment determines whether a pointer anomaly exists in the storage area according to the diagnostic value of the diagnostic register recorded in the data written to the storage area. If a pointer anomaly exists, it can be determined that a data read / write anomaly exists in the storage area.

[0089] In one embodiment, step 101 can detect whether there is an abnormal data read / write operation in the storage area in the following way:

[0090] First, obtain the header information corresponding to the data written to the storage area;

[0091] Then, based on the header information, the correctness of the data written to the storage area is checked. If the data written to the storage area fails the check, it can be determined that there is a data read / write anomaly in the storage area.

[0092] The header information can be the frame check sequence (FCS) of the Ethernet frame, which can be used to detect the correctness of data during data frame transmission. For example, the parallel bus driver in the CPU can use the Ethernet controller's CMD commands, such as MEMORY DATA READ COMMAND, to read the header information of data in SRAM for data correctness verification, to check whether there are any errors in the data during data frame transmission. If the data fails the verification, it can be determined that there is a data read / write anomaly in the SRAM.

[0093] In one embodiment, step 101 can detect whether there is an abnormal data read / write operation in the storage area in the following way:

[0094] First, obtain the status value in the status register of the Ethernet controller. This status value indicates whether data has been written to the storage area. Then, judge the status value. If the status value indicates that no data has been written to the storage area, then it can be determined that there is a data read / write abnormality in the storage area.

[0095] If the status value indicates that data has been written to the storage area, obtain the diagnostic value in the diagnostic register of the Ethernet controller. This diagnostic value indicates that there is a pointer abnormality in the storage area. Then, judge the diagnostic value. If the diagnostic value indicates that there is a pointer abnormality in the storage area, then it can be determined that there is a data read / write abnormality in the storage area.

[0096] If the diagnostic value indicates that there is no pointer anomaly in the storage area, obtain the header information corresponding to the data written to the storage area; then, based on the header information, perform a correctness check on the data written to the storage area. If the data written to the storage area fails the check, it can be determined that there is a data read / write anomaly in the storage area; if the data written to the storage area passes the check, it can be determined that there is no data read / write anomaly in the storage area.

[0097] For example, after detecting an interrupt flag, the CPU obtains the status value from the Ethernet controller's status register. A status value of 0 indicates that no data has been written to the storage area, but the interrupt flag indicates that the Ethernet controller has already written data to the storage area, thus confirming a data read / write error. If the status value is 1, the CPU obtains the diagnostic value from the diagnostic register. A diagnostic value of 1 indicates a pointer error in the storage area, confirming a data read / write error. If the diagnostic value is 0, the parallel bus driver in the CPU uses Ethernet controller CMD commands such as MEMORY DATA READ COMMAND to read the header information of the data in SRAM for data correctness verification, checking for errors during data frame transmission. If the data fails the verification, a data read / write error in SRAM is confirmed. Furthermore, if the data passes the verification, no data read / write error in SRAM is confirmed. In this case, the CPU can copy network data from SRAM and control WDPA to move to the location pointed to by RWPA to facilitate normal reading and writing of new data in SRAM.

[0098] refer to Figure 5 This is a schematic diagram of a communication control device provided in Embodiment 2 of this application. The device can be configured in a processor in an electronic device. The processor is connected to an Ethernet port through an Ethernet controller. The Ethernet controller writes the data sent from the Ethernet port into the storage area of ​​the Ethernet controller so that the processor can read the data from the storage area.

[0099] The device includes the following units:

[0100] An anomaly detection unit 501 is used to detect whether there is a data read / write anomaly in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area; if there is a data read / write anomaly in the storage area, the pointer control unit 502 is triggered;

[0101] The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer.

[0102] The pointer control unit 502 is used to control the first pointer to point to the position pointed to by the second pointer.

[0103] As can be seen from the above technical solution, in the communication control device provided in Embodiment 2 of this application, after the Ethernet controller writes the data sent from the Ethernet port into the storage area, the processor responds to the set interrupt flag and detects whether there is a data read / write error in the storage area. If there is a read / write error, the pointer pointing to the tail address of the storage area before the data was written is moved to be consistent with the pointer pointing to the tail address of the storage area after the data was written. Therefore, even if there is a previous data read / write error in this embodiment, it will not affect the next data read / write in the storage area because both pointers are pointing to the tail address in the storage area. This prevents continuous read / write errors in the storage area and avoids the Ethernet port from hanging due to continuous read / write errors. Consequently, a data read / write error in the storage area will not affect the subsequent normal communication between the processor and the Ethernet port, thereby improving the reliability of communication.

[0104] In one implementation, the anomaly detection unit 501 is at least configured to: obtain a status value in the status register of the Ethernet controller; the status value indicates whether data has been written to the storage area; if the status value indicates that no data has been written to the storage area, determine that there is a data read / write anomaly in the storage area.

[0105] In one implementation, the anomaly detection unit 501 is at least configured to: obtain a diagnostic value in the diagnostic register of the Ethernet controller; the diagnostic value indicates that a pointer anomaly exists in the storage area; if the diagnostic value indicates that a pointer anomaly exists in the storage area, determine that a data read / write anomaly exists in the storage area.

[0106] The diagnostic value is obtained by: obtaining the address length between the first pointer and the second pointer; comparing the address length with the data length recorded in the data written to the storage area; if the address length and the data length are inconsistent, determining that the diagnostic value indicates that there is a pointer anomaly in the storage area; if the address length and the data length are consistent, determining that the diagnostic value indicates that there is no pointer anomaly in the storage area.

[0107] In one implementation, the anomaly detection unit 501 is at least used to: obtain header information corresponding to the data written in the storage area; perform correctness verification on the data written in the storage area based on the header information; and determine that there is a data read / write anomaly in the storage area if the data written in the storage area fails the verification.

[0108] In one implementation, the apparatus in this embodiment may further include the following units, such as... Figure 6 As shown:

[0109] The data processing unit 503 is configured to discard the target data if the processor reads the target data between the first pointer and the second pointer when the anomaly detection unit 501 detects a data read / write anomaly in the storage area.

[0110] In addition, the data processing unit 503 is also used to: read data between the first pointer and the second pointer when the anomaly detection unit 501 detects that there is no data read / write anomaly in the storage area; and trigger the pointer control unit 502 to control the first pointer to point to the position pointed to by the second pointer.

[0111] It should be noted that the specific implementation of each unit in this embodiment can be referred to the corresponding content above, and will not be described in detail here.

[0112] In addition, Embodiment 3 of this application also provides a storage medium for storing a computer program, which is executed by a processor in an electronic device. The processor is connected to an Ethernet port through an Ethernet controller, and the Ethernet controller writes the data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area.

[0113] The computer program is executed by the processor to: detect whether there is a data read / write error in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area;

[0114] The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer.

[0115] If a data read / write error occurs in the storage area, the first pointer is controlled to point to the position pointed to by the second pointer.

[0116] refer to Figure 7 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of this application. The electronic device may include the following structure:

[0117] Processor 701;

[0118] Ethernet Controller 702;

[0119] The processor 701 is connected to the Ethernet port 703 via the Ethernet controller 702. The Ethernet controller 702 writes the data sent from the Ethernet port 703 into the storage area of ​​the Ethernet controller 702 so that the processor 701 can read the data from the storage area.

[0120] The processor 701 is used for:

[0121] In response to an interrupt flag, the system detects whether there is a data read / write error in the storage area. The interrupt flag is set by the Ethernet controller 702 after writing data sent from the Ethernet port 703 into the storage area. The storage area has a first pointer and a second pointer. The first pointer points to the end address of the storage area before data is written, and the second pointer points to the end address of the storage area after data is written, so that the processor 701 can read data between the first pointer and the second pointer. If there is a data read / write error in the storage area, the system controls the first pointer to point to the position pointed to by the second pointer.

[0122] As can be seen from the above technical solutions, in the electronic device provided in Embodiment 4 of this application, after the Ethernet controller writes the data sent from the Ethernet port into the storage area, the processor responds to the set interrupt flag and detects whether there is a data read / write error in the storage area. If there is a read / write error, the pointer pointing to the tail address of the storage area before the data was written is moved to be consistent with the pointer pointing to the tail address of the storage area after the data was written. Therefore, even if there is a previous data read / write error in this embodiment, it will not affect the next data read / write in the storage area because both pointers are pointing to the tail address in the storage area. This prevents continuous read / write errors in the storage area and avoids the Ethernet port from hanging due to continuous read / write errors. Consequently, a data read / write error in the storage area will not affect the subsequent normal communication between the processor and the Ethernet port, thereby improving the reliability of communication.

[0123] Taking control systems in the industrial field as an example, the parallel bus of the equipment containing the control system is extended to an Ethernet port via Ethernet control. In this case, fault diagnosis during parallel bus to Ethernet communication is particularly critical. Currently, the conventional method for fault diagnosis of parallel bus to Ethernet conversion is to monitor the status register of an external Ethernet controller. However, this method cannot accurately diagnose faults when the Ethernet port is interfered with, resulting in low diagnostic reliability. There may be cases where the Ethernet port is malfunctioning, leading to abnormal communication between the control system and Ethernet.

[0124] In view of this, this application proposes a communication control scheme, namely a fault diagnosis and processing scheme based on parallel bus to Ethernet, which can promptly diagnose and record fault states on-site. Furthermore, the processing mechanism avoids the time overhead caused by resets, ensuring the integrity and correctness of data frames after the physical layer link is restored. The fault diagnosis and processing scheme of this application is described in detail below:

[0125] First, such as Figure 8 The diagram shows a typical physical layer architecture for a parallel bus to Ethernet converter. The CPU's parallel bus interface communicates with the Ethernet port through an Ethernet controller. The Ethernet controller is configured with SRAM and a memory management module, and data reading and writing during communication are achieved through the conversion between the physical layer (PHY) and the data link layer (MAC).

[0126] like Figure 3 The diagram shows pointers in the SRAM of the Ethernet controller. Before receiving data, RWPA is the header pointer updated by the Ethernet controller, and MDPA is the tail pointer that the Ethernet controller informs the CPU of, i.e., the tail pointer updated by the CPU after reading the data. After one data read is completed, RWPA equals MDPA.

[0127] like Figure 4 The diagram shows the data structure of the data backed up in SRAM. When RWPA is updated (data is written to SRAM), the interrupt flag (i.e., the interrupt flag mentioned earlier) is set. After the CPU checks the interrupt flag, it verifies the correctness of the diagnostic register in the Ethernet controller and determines whether there is data. If there is data, the CPU's parallel bus driver first obtains the Ethernet controller's receive status (such as physical layer status), data length, and data correctness, then performs data copying, and finally updates MDPA to match RWPA.

[0128] like Figure 9As shown in, it is a schematic diagram of a receive pointer of an Ethernet controller under abnormal conditions. When the Ethernet controller is interfered by external stress, such as radiation or the register operation mechanism of the chip itself, the MDPA pointer fails to be updated normally. For example, MDPA shifts by ±n bytes (does not move to be consistent with RWPA), resulting in abnormal update of read and write pointers. As a result, the position where the CPU is notified to read the data packet next time is at MDPA+n, and when the data at this position happens to be 0, the CPU will determine that there is no data when judging whether there is data, so the MDPA+n pointer will not change, and it is considered that there is no data every time an interrupt occurs, causing the receive interrupt signal to be continuously sent to the CPU. RWPA < MDPA+n (conventional Ethernet controller drivers avoid pointer wrapping), the status register monitored by the Ethernet controller itself is normal, and the CPU cannot diagnose the fault. The network port is in a hung state.

[0129] To diagnose the above failure, as Figure 10 As shown in, it is a processing flow chart for implementing fault diagnosis in the present application. To avoid the above situation, the present application diagnoses the receive pointer, and updates the tail pointer when an abnormality between the tail pointer and the head pointer is diagnosed, so as to ensure the normal operation of the Ethernet management chip. The specific process is as follows:

[0130] Step 1001: after completing one data write, update RWPA;

[0131] Step 1002: the CPU finds an interrupt flag by polling;

[0132] Step 1003: determine whether there is data through the status register of the Ethernet controller; if there is data, perform step 1004, and if there is no data, perform step 1005;

[0133] Step 1004: determine whether the diagnostic register of the Ethernet controller is correct, that is, determine whether there is a pointer abnormality through the diagnostic register; if the diagnostic register is incorrect, that is, there is a pointer abnormality, perform step 1005, and if the diagnostic register is correct, that is, there is no pointer abnormality, perform step 1006;

[0134] Step 1005: discard the data, and update MDPA to be consistent with RWPA; for example, after discarding, wait for new Ethernet data to update RWPA, and continue to poll for whether there is an interrupt flag;

[0135] Step 1006: the parallel bus driver reads the data header information through CMD;

[0136] Step 1007: determine whether the header information is correct, that is, use the header information to verify whether the data in the SRAM has an error during transmission; if the header information is correct, that is, there is no error in the data during transmission, perform step 1008, and if the header information is incorrect, perform step 1005;

[0137] Step 1008: Copy data and update MDPA to be consistent with RWPA.

[0138] Therefore, the core idea of ​​this application lies in diagnosing the process of parallel bus to Ethernet communication by monitoring the operation of the receiving pointer. This application adds pointer diagnostics to conventional Ethernet management chips and CPU-built-in diagnostic registers, improving the stability of parallel interface Ethernet solutions. Furthermore, by adjusting the tail pointer of the Ethernet management chip after detecting pointer abnormalities, this application avoids the time overhead caused by resets, providing a solution for Ethernet communication under harsh conditions.

[0139] It should be noted that the topology methods supported in this application, in addition to... Figure 8 The architecture shown also supports other bus types that rely on the receive pointer for data reception. Furthermore, the handling methods for Ethernet control chip anomalies in this application are not limited to adjusting the tail pointer; they also include adjusting the receive pointer or using algorithms to calculate and locate the head and tail pointers.

[0140] In summary, compared with conventional diagnostic methods that rely on the status registers of external Ethernet controllers, the diagnostic mechanism of this application provides more comprehensive coverage, avoiding the risks associated with network port malfunctions caused by abnormal read / write pointers. Furthermore, unlike the conventional approach of resetting the Ethernet controller when network port communication is abnormal, this application adjusts the tail pointer after diagnosing the pointer abnormality, reducing the delay caused by the reset chip re-establishing communication and improving the availability of the network port.

[0141] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0142] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0143] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0144] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication control method, characterized in that, A processor used in electronic devices, wherein the processor is connected to an Ethernet port via an Ethernet controller, and the Ethernet controller writes data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area; The method includes: In response to an interrupt flag, the system detects whether there is a data read / write error in the storage area; the interrupt flag is set by the Ethernet controller after writing data sent from the Ethernet port into the storage area. The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer. If a data read / write error occurs in the storage area, the first pointer is controlled to point to the position pointed to by the second pointer.

2. The method according to claim 1, characterized in that, Detecting whether there are data read / write anomalies in the storage area includes at least: Obtain the status value from the status register in the Ethernet controller; the status value indicates whether data has been written to the storage area. If the status value indicates that no data has been written to the storage area, it is determined that there is a data read / write anomaly in the storage area.

3. The method according to claim 1, characterized in that, Detecting whether there are data read / write anomalies in the storage area includes at least: Obtain the diagnostic value from the diagnostic register in the Ethernet controller; the diagnostic value indicates that a pointer anomaly exists in the storage area. If the diagnostic value indicates that there is a pointer anomaly in the storage area, it is determined that there is a data read / write anomaly in the storage area.

4. The method according to claim 3, characterized in that, The diagnostic values ​​are obtained in the following manner: Obtain the address length between the first pointer and the second pointer; The address length is compared with the length of the data recorded in the data written to the storage area; If the address length is inconsistent with the data length, the diagnostic value indicates that there is a pointer anomaly in the storage area; If the address length is consistent with the data length, the diagnostic value indicates that there is no pointer anomaly in the storage area.

5. The method according to claim 1, characterized in that, Detecting whether there are data read / write anomalies in the storage area includes at least: Obtain the header information corresponding to the data written to the storage area; Based on the header information, the correctness of the data written to the storage area is verified; If the data written to the storage area fails the verification, it is determined that there is a data read / write anomaly in the storage area.

6. The method according to claim 1, 2, 3 or 5, characterized in that, If a data read / write anomaly occurs in the storage area, the method further includes: If the processor reads the target data between the first pointer and the second pointer, it discards the target data.

7. The method according to claim 1, 2, 3 or 5, characterized in that, If there are no data read / write anomalies in the storage area, the method further includes: Read data between the first pointer and the second pointer; Control the first pointer to point to the position pointed to by the second pointer.

8. A communication control device, characterized in that, A processor configured in an electronic device, the processor being connected to an Ethernet port via an Ethernet controller, the Ethernet controller writing data sent from the Ethernet port into a storage area in the Ethernet controller, so that the processor can read data from the storage area; The device includes: An anomaly detection unit is used to detect whether there is a data read / write anomaly in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area; if there is a data read / write anomaly in the storage area, the pointer control unit is triggered; The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer. A pointer control unit is used to control the first pointer to point to the position pointed to by the second pointer.

9. A storage medium, characterized in that, The storage medium is used to store a computer program, which is executed by a processor in an electronic device. The processor is connected to an Ethernet port via an Ethernet controller, and the Ethernet controller writes data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area. The computer program is executed by the processor to: detect whether there is a data read / write error in the storage area in response to an interrupt flag; the interrupt flag is set by the Ethernet controller after writing the data sent from the Ethernet port into the storage area; The storage area has a first pointer and a second pointer. The first pointer is used to point to the end address before data is written to the storage area, and the second pointer is used to point to the end address after data is written to the storage area, so that the processor can read data between the first pointer and the second pointer. If a data read / write error occurs in the storage area, the first pointer is controlled to point to the position pointed to by the second pointer.

10. An electronic device, characterized in that, include: processor; Ethernet controller; The processor is connected to an Ethernet port via an Ethernet controller. The Ethernet controller writes the data sent from the Ethernet port into a storage area in the Ethernet controller so that the processor can read data from the storage area. The processor is used for: In response to an interrupt flag, the system detects whether there is a data read / write error in the storage area. The interrupt flag is set by the Ethernet controller after writing data sent from the Ethernet port into the storage area. The storage area has a first pointer and a second pointer. The first pointer points to the end address of the storage area before data is written, and the second pointer points to the end address of the storage area after data is written, so that the processor can read data between the first pointer and the second pointer. If there is a data read / write error in the storage area, the system controls the first pointer to point to the position pointed to by the second pointer.

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