Dynamic training method for area array detector

Abstract

The present application relates to the technical field of detector training, and particularly relates to a dynamic training method of a plane array detector, which comprises three training modes, a full-channel parallel training mode, a full-channel serial training mode and a partial-channel serial training mode. The full-channel parallel training mode is suitable for the case that the imaging controller has abundant resources, all channels are trained in parallel, the training state can be adjusted in real time, and the change of environmental conditions can be adapted. The full-channel serial training mode is suitable for the case that the imaging controller has insufficient resources and the redundant time between frames is sufficient to complete the serial training of all channels, all channels are trained one by one in series, and the training time length can be compressed. The partial-channel serial training mode is suitable for the case that the imaging controller has insufficient resources and the redundant time between frames is insufficient to complete the serial training of all channels, only part of channels are trained between frames, the channel number changes in a cyclic and increasing manner between different frames, and the training of all channels is completed gradually and cyclically, so that each channel of the plane array detector can be trained continuously and can adapt to the change of external environment.

Description

Technical Field

[0001] This invention relates to the field of detector training technology, and in particular to a dynamic training method for area array detectors based on aerospace applications. Background Technology

[0002] Before bit and word correction, area array detectors require the generation of relevant timing signals. Before channel correction, additional timing signals different from those before bit and word correction are needed. To reduce timing overhead, channel correction should only be performed after bit and word correction for all channels is complete; otherwise, each channel's training operation requires two timing operations. For inter-frame dynamic training of area array detectors, a serial training method performing training channel by channel sequentially reduces the internal resource consumption of the imaging controller, but the inter-frame redundancy time may be insufficient to train all channels. If the training operation of all channels is changed to a fully parallel method, the inter-frame redundancy time is sufficient, but the internal resources of the imaging controller may be insufficient. Summary of the Invention

[0003] In view of the above problems, the present invention proposes a dynamic training method for an area array detector. Based on the internal resources of the imaging controller and the inter-frame redundancy time of the area array detector, three training modes are provided to achieve a balance between the internal resources of the imaging controller and the inter-frame redundancy time of the area array detector.

[0004] This invention provides a dynamic training method for an area array detector, including a parallel training mode for all channels, a serial training mode for all channels, and a serial training mode for some channels; wherein, The parallel training mode for all channels is suitable for situations where the imaging controller has abundant resources. It performs parallel training on all channels, and the specific training method is as follows: After the imaging controller is powered on, the first master state machine for parallel training of all channels enters the training idle state. When the array detector is detected to be powered on, or a secondary training command or a dynamic training command is received, the first master state machine enters the training start state, sets the training enable signal to a high level, and starts the first sub-state machine for parallel training of all channels to perform bit correction, word correction and channel correction training in sequence. After the channel calibration training is completed, the first master state machine enters the training completion judgment state to determine whether the training is completed. When the training is determined to be completed, the first master state machine returns to the training idle state and sets the training enable signal to low level. The full-channel serial training mode is suitable for situations where imaging controller resources are limited and the inter-frame redundancy time is sufficient to complete the serial training of all channels. The specific training method for all channels is as follows: After the imaging controller is powered on, the second master state machine for serial training of all channels enters the training idle state to set the initial state. When the area array detector is detected to be powered on or a secondary training command is received, the second main state machine enters the setting bit training start state; when the area array detector is detected to have received a dynamic training command, the second main state machine enters the setting word training start state. In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The second sub-state machine for serial training of all channels is started to perform bit correction training. Then the second main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the second main state machine enters the setting word training start state. In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The second sub-state machine is started to perform word correction training. Then the second main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the second main state machine enters the channel training start state. In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the second sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the second main state machine enters the training idle state. The partial channel serial training mode is suitable for situations where the imaging controller has limited resources and the inter-frame redundancy time is insufficient to complete the serial training of all channels. Only a portion of the channels are trained between each frame, with the channel numbers cyclically increasing between different frames to gradually complete the training of all channels. The specific training method is as follows: After the imaging controller is powered on, the third master state machine for serial training of some channels enters the training idle state to set the initial state. When the area array detector is detected to be powered on or a secondary training command is received, the third main state machine enters the setting position training start state; when the area array detector is detected to have received a dynamic training command, the third main state machine enters the dynamic training start state. In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The third sub-state machine for serial training of some channels is started to perform bit correction training. Then the third main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the third main state machine enters the setting word training start state. In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The third sub-state machine is started to perform word correction training. Then the third main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the third main state machine enters the channel training start state. In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the third sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the third main state machine enters the training idle state. In the dynamic training start state, the dynamic training enable signal is set to high level, and the third sub-state machine is started to perform dynamic training of the specified channel. The dynamic training includes word correction training and channel correction training performed sequentially. After the dynamic training is completed, the third main state machine enters the dynamic training end judgment state to judge whether the dynamic training is completed. When the dynamic training is judged to be completed, the third main state machine returns to the training idle state and sets the dynamic training enable signal to low level.

[0005] Preferably, the number of specified channels m The value of is restricted as follows: ; in, P This refers to the inter-frame redundancy time of the array detector; This is the time required for single-channel training.

[0006] Preferably, the first sub-state machine includes a power-on waiting state, a preset period timing setting state before bit correction, a reset state before bit correction, a stable condition sampling state, a stable condition judgment state, a bit correction delay state, a state for calculating the sampling position, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset period timing setting state before channel correction, a channel correction state, and a processing state after single-channel training is completed; wherein, After the area array detector is powered on, the first sub-state machine enters the power-on waiting state. After the training enable signal is detected to be high, the first sub-state machine enters the preset cycle timing setting state before bit correction. In the preset period timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the first sub-state machine enters the reset state before word correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the first sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the first sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the first sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the first sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the first sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the first sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the first sub-state machine enters the word correction state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the first sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the first sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the first sub-state machine enters the processing state after single-channel training is completed. In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the first sub-state machine returns to the power-on waiting state.

[0007] Preferably, the second sub-state machine includes a power-on waiting state, a preset period timing setting state before bit correction, a reset state before bit correction, a stable condition sampling state, a stable condition judgment state, a bit correction delay state, a state for calculating the sampling position, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset period timing setting state before channel correction, a channel correction state, a bit correction completion processing state, a word correction completion processing state, and a channel correction completion processing state; wherein, After the area array detector is powered on, the second sub-state machine first enters the power-on waiting state. When the bit correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before bit correction. When the word correction indication signal is detected to be high, the second sub-state machine enters the word correction sub-state. When the channel correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the second sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the second sub-state machine enters the steady-state sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the second sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the second sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the second sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the second sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the second sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the second sub-state machine enters the bit-correction end processing state. In the bit correction completion processing state, a judgment is made on whether the bit correction is completed. If the bit correction is completed, the second sub-state machine returns to the power-on waiting state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the second sub-state machine enters the word correction end processing state. In the word correction completion processing state, a judgment is made on whether word correction has ended. If it is determined that word correction has ended, the second sub-state machine returns to the power-on waiting state. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the second sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or failed after a preset number of calibrations, the second sub-state machine enters the channel calibration end processing state. In the channel calibration completion processing state, a judgment is made on whether the channel calibration is completed. If the channel calibration is completed, the second sub-state machine returns to the power-on waiting state.

[0008] Preferably, when the area array detector is detected to be powered on or a secondary training command is received, the third sub-state machine includes a power-on waiting state, a preset period timing setting state before bit correction, a reset state before bit correction, a stable condition sampling state, a stable condition judgment state, a bit correction delay state, a state for calculating the sampling position, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset period timing setting state before channel correction, a channel correction state, a bit correction completion processing state, a word correction completion processing state, and a channel correction completion processing state; wherein, After the area array detector is powered on, the third sub-state machine first enters the power-on waiting state. When the bit correction indication signal is detected to be high, the third sub-state machine enters the preset cycle timing setting state before bit correction. When the word correction indication signal is detected to be high, the third sub-state machine enters the word correction sub-state. When the channel correction indication signal is detected to be high, the third sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the third sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the third sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the third sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the third sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the third sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the third sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the third sub-state machine enters the bit-corrected delayed state. In the post-bit correction delay state, the post-bit correction delay is performed. After the delay is completed, the third sub-state machine enters the bit correction end processing state. In the bit correction completion processing state, a judgment is made on whether the bit correction is completed. If the bit correction is completed, the third sub-state machine returns to the power-on waiting state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the third sub-state machine enters the word correction end processing state; In the word correction completion processing state, a judgment is made on whether word correction has ended. If it is determined that word correction has ended, the third sub-state machine returns to the power-on waiting state. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the third sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or failed after a preset number of calibrations, the third sub-state machine enters the channel calibration end processing state. In the channel calibration completion processing state, a judgment is made on whether the channel calibration is completed. If the channel calibration is completed, the third sub-state machine returns to the power-on waiting state.

[0009] Preferably, when the area array detector receives a dynamic training command, the dynamic training also includes bit correction training performed before word correction training. At this time, the third sub-state machine includes a power-on waiting state, a preset period timing setting state before bit correction, a reset state before bit correction, a stable condition sampling state, a stable condition judgment state, a bit correction delay state, a sampling position calculation state, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset period timing setting state before channel correction, a channel correction state, and a single-channel training completion processing state; wherein, After the area array detector is powered on, the third sub-state machine enters the power-on waiting state. After detecting that the dynamic training enable signal is high, the third sub-state machine enters the preset cycle timing setting state before bit correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the third sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the third sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the third sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the third sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the third sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the third sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the third sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the third sub-state machine enters the word correction state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the third sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the third sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the third sub-state machine enters the processing state after single-channel training is completed. In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the third sub-state machine returns to the power-on waiting state.

[0010] Compared with the prior art, the present invention can achieve the following beneficial effects: 1. For situations where there are many resources in the imaging controller, all channels are trained in parallel, which is time-saving and allows for real-time adjustment of the training status to adapt to changes in environmental conditions. 2. For situations where imaging controller resources are limited and the inter-frame redundancy time is long, all channels can be trained serially one by one. The entire training includes three steps of correction: bit correction, word correction, and channel correction for all channels. Only two timing operations are performed, which can compress the training time. 3. To address the issue of limited imaging controller resources and insufficient inter-frame redundancy time to complete serial training of all channels, only a subset of channels are trained sequentially between frames, with the channel numbers cyclically increasing between different frames. This method ensures that each channel of the area array detector is continuously trained, enabling it to adapt to changes in the external environment. Attached Figure Description

[0011] Figure 1 This is a diagram of an imaging system for an area array detector according to an embodiment of the present invention; Figure 2 This is a loop diagram of the first master state machine for parallel training of all channels according to an embodiment of the present invention; Figure 3This is a loop diagram of the first sub-state machine for parallel training of all channels according to an embodiment of the present invention; Figure 4 This is a loop diagram of the second master state machine for serial training of all channels according to an embodiment of the present invention; Figure 5 This is a loop diagram of the second sub-state machine for serial training of all channels according to an embodiment of the present invention; Figure 6 This is a loop diagram of the third master state machine for partial channel serial training provided in an embodiment of the present invention; Figure 7 This is a loop diagram of the third sub-state machine of partial channel serial training provided by an embodiment of the present invention during dynamic training.

[0012] The reference numerals in the figures include: camera controller 1, imaging controller power supply chip 2, imaging controller 3, detector power supply chip 4, area array detector 5, erasable main and backup flash 6, PROM 7, MRAM 8, cameralink chip 9, cameralink connector 10, 2711 chip 11, and 2711 connector 12. Detailed Implementation

[0013] In the following description, embodiments of the invention will be described with reference to the accompanying drawings. In the description below, the same modules are denoted by the same reference numerals. Where the same reference numerals are used, their names and functions are also the same. Therefore, their detailed description will not be repeated.

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0015] This invention provides a dynamic training method for an area array detector. The imaging system of the area array detector will be described in detail before the dynamic training method is described in detail.

[0016] Figure 1 An imaging system for an area array detector according to an embodiment of the present invention is shown.

[0017] like Figure 1As shown, the imaging system of the area array detector provided in this embodiment of the invention includes a camera controller 1, an imaging controller power supply chip 2, an imaging controller 3, a detector power supply chip 4, an area array detector 5, erasable main and backup flash memory 6, a PROM 7, an MRAM 8, a cameralink chip 9, a cameralink connector 10, a 2711 chip 11, and a 2711 connector 12. The camera controller 1 receives a primary power supply from an external source and generates the necessary power supplies. It also receives a second pulse from an external source and communicates with the outside via a 1553 bus. The camera controller 1 communicates with the imaging controller 3 via a 422 communication signal and provides the imaging controller 3 with second pulses. The imaging controller 3 is powered by the imaging controller power supply chip 2; the imaging controller 3 provides drive control signals to the area array detector 5 and provides power to the area array detector 5 through the detector power supply chip 4, and receives serial image data output by the area array detector 5; the imaging controller 3 is simultaneously connected to the PROM 7 and the erasable main and backup flash 6, and the imaging controller 3 is simultaneously connected to the MRAM 8 to update the correction coefficients and load the correction coefficients before each shooting; the imaging controller 3 can output image data through the cameralink chip 9 and cameralink connector 10, or through the 2711 chip 11 and 2711 connector 12, depending on the selection.

[0018] The imaging controller power supply chip 2 uses a DC-DC power module from the Lanzhou Institute of Space Technology Physics; the area array detector 5 uses an area array detector from Changchun Changguang Chenxin Optoelectronic Technology Co., Ltd.; the camera controller 1 uses a DSP chip; the imaging controller 3 uses an imaging controller and refresh chip from Shanghai Fudan Microelectronics Co., Ltd.; the detector power supply chip 4 uses an LDO from TI; the 2711 chip 11 uses a TLK2711 chip; the 2711 connector 12 uses a micro coaxial connector from Sichuan Huafeng; the cameralink chip 9 uses a DS90CR287; the cameralink connector 10 uses a 3M MDR26 connector; the erasable main and backup flash 6 uses products from Shanghai Fudan Microelectronics Group Co., Ltd.; the PROM 7 uses a product from Xilinx; and the MRAM 8 uses a product from Xi'an Microelectronics Technology Research Institute.

[0019] The dynamic training method for an area array detector provided in this invention includes three training modes: a parallel training mode for all channels, a serial training mode for all channels, and a serial training mode for some channels. The parallel training mode for all channels is suitable for situations where the imaging controller has abundant resources, and all channels are trained in parallel. The serial training mode for all channels is suitable for situations where the imaging controller has limited resources and the inter-frame redundancy time is sufficient to complete the serial training of all channels, and all channels are trained sequentially one by one. The serial training mode for some channels is suitable for situations where the imaging controller has limited resources and the inter-frame redundancy time is insufficient to complete the serial training of all channels, and only some channels are trained between each frame, with the channel numbers cyclically increasing between different frames to gradually complete the training of all channels.

[0020] Regardless of the training mode, it includes three types of training: bit correction training, word correction training, and channel correction training.

[0021] The specific training methods for the all-channel parallel training mode, the all-channel serial training mode, and the partial-channel serial training mode are described in detail below.

[0022] I. Parallel Training Mode for All Channels In the parallel training mode of all channels, all channels are trained in parallel. The parallel training includes three steps: bit correction of all channels, word correction of all channels, and channel correction of all channels. It has the characteristics of short time consumption, real-time adjustment of training status, and adaptability to changes in environmental conditions.

[0023] Figure 2 The loop of the first master state machine for parallel training of all channels according to an embodiment of the present invention is shown.

[0024] like Figure 2 As shown, the loop of the first master state machine for parallel training of all channels contains three states: training idle state, training start state, and training end judgment state.

[0025] After the imaging controller is powered on, the first main state machine enters the training idle state. When the power-on of the area array detector is detected, or a secondary training command or a dynamic training command is received, the first main state machine enters the training start state, sets the training enable signal to a high level, and starts the first sub-state machine for parallel training of all channels to perform bit correction, word correction, and channel correction training in sequence. After the channel correction training is completed, the first main state machine enters the training completion judgment state to determine whether the training is completed. When the training is determined to be completed, the first main state machine returns to the training idle state and sets the training enable signal to a low level.

[0026] After the array detector is powered on, power-on training is performed. Power-on training includes bit correction, word correction and channel correction training in sequence. Secondary training command is used to perform bit correction, word correction and channel correction training again. Dynamic training command is used to perform bit correction, word correction and channel correction training in sequence when the array detector is affected by temperature changes, etc. Of course, dynamic training command can also directly perform word correction and channel correction training.

[0027] Figure 3 The loop of the first sub-state machine for parallel training of all channels is shown according to an embodiment of the present invention.

[0028] like Figure 3 As shown, the first sub-state machine includes a power-on waiting state, a preset cycle timing setting state before bit correction, a reset state before bit correction, a stable sampling state, a stable judgment state, a bit correction delay state, a calculation of sampling position state, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset cycle timing setting state before channel correction, a channel correction state, and a processing state after single-channel training is completed.

[0029] After the area array detector is powered on, the first sub-state machine enters the power-on waiting state. After detecting that the training enable signal is high, the first sub-state machine enters the preset cycle timing setting state before bit correction.

[0030] In one specific embodiment, the period of the preset period timing setting state is set to 32. The specific setting method is existing technology, so it will not be described in detail here.

[0031] In the preset period timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the first sub-state machine enters the reset state before bit correction.

[0032] In the reset state before bit correction, a reset is performed before bit correction. After the reset is completed, the first sub-state machine enters the stable sampling state.

[0033] The above-mentioned reset refers to resetting the input delay unit iodelay inside the imaging controller; the reset operation is completed within one pixel clock cycle; the delay value is set by a counter, and when the counter receives the set delay value, such as 32, the reset is considered complete.

[0034] In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the first sub-state machine enters the bit correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit iodelay, the first sub-state machine enters the calculation sampling position state.

[0035] The sampling operation is completed within one pixel clock cycle; a delay value is set by a counter, and when the counter reaches the set delay value, such as 32, the reset is considered complete.

[0036] In the bit correction delay state, the bit correction is delayed. After the delay is completed, the first sub-state machine returns to the stable sampling state.

[0037] In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the first sub-state machine enters the reset state after bit correction.

[0038] The method for calculating the sampling location is existing technology, so it will not be described in detail here.

[0039] In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the first sub-state machine enters the bit-corrected delayed state.

[0040] In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the first sub-state machine enters the word correction state.

[0041] The purpose of delaying after bit correction is to set the final delay value; after iodelay is reset, it has returned to the default position, and at this time it is necessary to set the final delay value, which is the calculated sampling position.

[0042] In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the first sub-state machine enters the preset cycle timing setting state before channel correction.

[0043] The preset number of times depends on the bit width of the parallel data. As long as the preset number of times is greater than or equal to the bit width of the parallel data, it is fine. For example, if the parallel data is 12 bits, the preset number of times is greater than 12.

[0044] In the preset cycle timing setting state before channel calibration, the timing settings before channel calibration are performed. After the timing settings are completed, the first sub-state machine enters the channel calibration state.

[0045] In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the first sub-state machine enters the processing state after single-channel training is completed.

[0046] The preset number of channel calibration judgments is the same as above.

[0047] In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the first sub-state machine returns to the power-on waiting state.

[0048] II. Serial Training Mode for All Channels In the full-channel serial training mode, all channels are trained sequentially one by one. The entire training includes three steps: bit correction, word correction, and channel correction for all channels. Only two timing operations are performed, which can compress the training time.

[0049] Figure 4 The loop of the second master state machine for serial training of all channels provided according to an embodiment of the present invention is shown.

[0050] like Figure 4 As shown, the loop of the second master state machine for serial training of all channels includes training idle state, setting bit training start state, setting word training start state, setting channel training start state, bit training end judgment state, word training end judgment state, and channel training end judgment state.

[0051] After the imaging controller is powered on, the second master state machine enters the training idle state to set the initial state.

[0052] When the array detector is detected to be powered on or a secondary training command is received, the second main state machine enters the setting bit training start state; when the array detector is detected to have received a dynamic training command, the second main state machine enters the setting word training start state.

[0053] In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The second sub-state machine for serial training of all channels is started to perform bit correction training. Then, the second main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the second main state machine enters the setting word training start state.

[0054] In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The second sub-state machine is started to perform word correction training. Then, the second main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the second main state machine enters the channel training start state.

[0055] In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the second sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the second main state machine enters the training idle state.

[0056] Figure 4 The example shown is dynamic training that performs word correction and channel correction sequentially. This dynamic training can also include bit correction training before word correction training, i.e., performing bit correction, word correction and channel correction training sequentially.

[0057] Figure 5 The loop of the second sub-state machine, which is provided for serial training of all channels according to an embodiment of the present invention, is illustrated.

[0058] like Figure 5 As shown, the second sub-state machine includes a power-on waiting state, a preset cycle timing setting state before bit correction, a reset state before bit correction, a stable condition sampling state, a stable condition judgment state, a bit correction delay state, a calculation sampling position state, a reset state after bit correction, a delay state after bit correction, a word correction state, a preset cycle timing setting state before channel correction, a channel correction state, a bit correction end processing state, a word correction end processing state, and a channel correction end processing state.

[0059] After the area array detector is powered on, the second sub-state machine first enters the power-on waiting state. When the bit correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before bit correction. When the word correction indication signal is detected to be high, the second sub-state machine enters the word correction sub-state. When the channel correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before channel correction.

[0060] In the preset period timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the second sub-state machine enters the reset state before bit correction.

[0061] In the reset state before bit correction, a reset is performed before bit correction. After the reset is completed, the second sub-state machine enters the stable sampling state.

[0062] In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the second sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the second sub-state machine enters the calculation sampling position state.

[0063] In the bit correction delay state, the bit correction is delayed. After the delay is completed, the second sub-state machine returns to the stable sampling state.

[0064] In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the second sub-state machine enters the reset state after bit correction.

[0065] In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the second sub-state machine enters the bit-corrected delayed state.

[0066] In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the second sub-state machine enters the bit-correction end processing state.

[0067] In the bit correction completion processing state, a judgment is made on whether the bit correction is completed. If the bit correction is completed, the second sub-state machine returns to the power-on waiting state.

[0068] In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the second sub-state machine enters the word correction end processing state.

[0069] In the word correction completion processing state, a judgment is made on whether word correction has ended. If it is determined that word correction has ended, the second sub-state machine returns to the power-on waiting state.

[0070] In the preset cycle timing setting state before channel calibration, the timing settings before channel calibration are performed. After the timing settings are completed, the second sub-state machine enters the channel calibration state.

[0071] In the channel calibration state, when it is determined whether the channel calibration was successful or failed after a preset number of calibrations, the second sub-state machine enters the channel calibration end processing state.

[0072] In the channel calibration completion processing state, a judgment is made on whether the channel calibration is completed. If the channel calibration is completed, the second sub-state machine returns to the power-on waiting state.

[0073] III. Partial Channel Serial Training Mode In the partial channel serial training mode, only a subset of channels are trained between each frame, with the channel numbers cyclically increasing between different frames. This ensures that each channel of the area array detector is continuously trained, allowing it to adapt to changes in the external environment. For example, if there are 20 channels, but only 6 channels can be trained at a time, the training sequence would be: 1-6 for the first time, 7-12 for the second, 13-18 for the third, 19-20 and 1-4 for the fourth, 5-10 for the fifth, and so on.

[0074] Figure 6 The loop of the third master state machine for partial channel serial training provided according to an embodiment of the present invention is shown.

[0075] like Figure 6As shown, the loop of the third master state machine for partial channel serial training includes training idle state, setting bit training start state, setting word training start state, setting channel training start state, bit training end judgment state, word training end judgment state, channel training end judgment state, dynamic training start state, and dynamic training end judgment state.

[0076] After the imaging controller is powered on, the third master state machine for serial training of some channels enters the training idle state to set the initial state. When the area array detector is detected to be powered on or a secondary training command is received, the third main state machine enters the setting position training start state; when the area array detector is detected to have received a dynamic training command, the third main state machine enters the dynamic training start state. In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The third sub-state machine for serial training of some channels is started to perform bit correction training. Then the third main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the third main state machine enters the setting word training start state. In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The third sub-state machine is started to perform word correction training. Then the third main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the third main state machine enters the channel training start state. In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the third sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the third main state machine enters the training idle state. In the dynamic training start state, the dynamic training enable signal is set to high level, and the third sub-state machine is started to perform dynamic training of the specified channel. The dynamic training includes bit correction, word correction training and channel correction training performed sequentially, or word correction training and channel correction training performed sequentially. After the dynamic training is completed, the third main state machine enters the dynamic training end judgment state to judge whether the dynamic training of the specified number of channels has been completed. When it is judged that the dynamic training of the specified number of channels has been completed, the third main state machine returns to the training idle state and sets the dynamic training enable signal to low level.

[0077] Specify the number of channels m The value of is restricted as follows: ; in, P This refers to the inter-frame redundancy time of the array detector; This is the time required for single-channel training.

[0078] Upon powering on the array detector or receiving a secondary training command, the cyclic state of the third sub-state machine is... Figure 5 The second sub-state machine shown has the same cyclic state, so it will not be described again here.

[0079] Figure 7 The diagram illustrates the loop of a third sub-state machine for partial channel serial training provided by an embodiment of the present invention during dynamic training.

[0080] like Figure 7 As shown, when the array detector receives the dynamic training command, the cycle of the third sub-state machine includes the following states: power-on waiting state, preset period timing setting state before bit correction, reset state before bit correction, stable condition sampling state, stable condition judgment state, bit correction delay state, calculation of sampling position state, reset state after bit correction, delay state after bit correction, word correction state, preset period timing setting state before channel correction, channel correction state, and processing state after single-channel training is completed.

[0081] After the area array detector is powered on, the third sub-state machine enters the power-on waiting state. After detecting that the dynamic training enable signal is high, the third sub-state machine enters the preset cycle timing setting state before bit correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the third sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the third sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the third sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the third sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the third sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the third sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the third sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the third sub-state machine enters the word correction state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the third sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the third sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the third sub-state machine enters the processing state after single-channel training is completed. In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the third sub-state machine returns to the power-on waiting state.

[0082] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A dynamic training method for an area array detector, characterized in that, This includes parallel training mode for all channels, serial training mode for all channels, and serial training mode for some channels; among them, The parallel training mode for all channels is suitable for situations where the imaging controller has abundant resources. It performs parallel training on all channels, and the specific training method is as follows: After the imaging controller is powered on, the first master state machine for parallel training of all channels enters the training idle state. When the array detector is detected to be powered on, or a secondary training command or a dynamic training command is received, the first master state machine enters the training start state, sets the training enable signal to a high level, and starts the first sub-state machine for parallel training of all channels to perform bit correction, word correction and channel correction training in sequence. After the channel calibration training is completed, the first master state machine enters the training completion judgment state to determine whether the training is completed. When the training is determined to be completed, the first master state machine returns to the training idle state and sets the training enable signal to low level. The full-channel serial training mode is suitable for situations where imaging controller resources are limited and the inter-frame redundancy time is sufficient to complete the serial training of all channels. The specific training method for all channels is as follows: After the imaging controller is powered on, the second master state machine for serial training of all channels enters the training idle state to set the initial state. When the area array detector is detected to be powered on or a secondary training command is received, the second main state machine enters the setting bit training start state; when the area array detector is detected to have received a dynamic training command, the second main state machine enters the setting word training start state. In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The second sub-state machine for serial training of all channels is started to perform bit correction training. Then the second main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the second main state machine enters the setting word training start state. In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The second sub-state machine is started to perform word correction training. Then the second main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the second main state machine enters the channel training start state. In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the second sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the second main state machine enters the training idle state. The partial channel serial training mode is suitable for situations where the imaging controller has limited resources and the inter-frame redundancy time is insufficient to complete the serial training of all channels. Only a portion of the channels are trained between each frame, with the channel numbers cyclically increasing between different frames to gradually complete the training of all channels. The specific training method is as follows: After the imaging controller is powered on, the third master state machine for serial training of some channels enters the training idle state to set the initial state. When the area array detector is detected to be powered on or a secondary training command is received, the third main state machine enters the setting position training start state; when the area array detector is detected to have received a dynamic training command, the third main state machine enters the dynamic training start state. In the bit training start state, the bit correction indicator signal is set to high level and the channel number is set to 0. The third sub-state machine for serial training of some channels is started to perform bit correction training. Then the third main state machine enters the bit training end judgment state to judge whether the bit correction training is completed. When the bit correction training is judged to be completed, the channel number is incremented by 1. When the bit correction training of all channels is detected to be completed, the third main state machine enters the setting word training start state. In the word training start state, the word correction indicator signal is set to high level, the bit correction indicator signal is set to low level, and the channel number is set to 0. The third sub-state machine is started to perform word correction training. Then the third main state machine enters the word training end judgment state to judge whether the word correction training is completed. When the word correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the word correction training of all channels is completed, the third main state machine enters the channel training start state. In the channel training start state, the channel correction indicator signal is set to high level, the word correction indicator signal is set to low level, and the channel number is set to 0. Then, the third sub-state machine is started to perform channel correction training. Then, the channel training end judgment state is entered to judge whether the channel correction training is completed. When the channel correction training is judged to be completed, the channel number is incremented by 1. When it is detected that the channel correction training of all channels is completed, the third main state machine enters the training idle state. In the dynamic training start state, the dynamic training enable signal is set to high level, and the third sub-state machine is started to perform dynamic training of the specified channel. The dynamic training includes word correction training and channel correction training performed sequentially. After the dynamic training is completed, the third main state machine enters the dynamic training end judgment state to judge whether the dynamic training is completed. When the dynamic training is judged to be completed, the third main state machine returns to the training idle state and sets the dynamic training enable signal to low level.

2. The dynamic training method for an area array detector according to claim 1, characterized in that, Specify the number of channels m The value of is restricted as follows: ； in, P This is the inter-frame redundancy time for the area array detector; This is the time required for single-channel training.

3. The dynamic training method for an area array detector according to claim 1, characterized in that, The first sub-state machine includes the following states: power-on waiting state, preset period timing setting state before bit correction, reset state before bit correction, stable condition sampling state, stable condition judgment state, bit correction delay state, calculation of sampling position state, reset state after bit correction, delay state after bit correction, word correction state, preset period timing setting state before channel correction, channel correction state, and processing state after single-channel training is complete. After the area array detector is powered on, the first sub-state machine enters the power-on waiting state. After the training enable signal is detected to be high, the first sub-state machine enters the preset cycle timing setting state before bit correction. In the preset period timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the first sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the first sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the first sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the first sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the first sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the first sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the first sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the first sub-state machine enters the word correction state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the first sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the first sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the first sub-state machine enters the processing state after single-channel training is completed. In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the first sub-state machine returns to the power-on waiting state.

4. The dynamic training method for an area array detector according to claim 1, characterized in that, The second sub-state machine includes the following states: power-on waiting state, preset period timing setting state before bit correction, reset state before bit correction, stable condition sampling state, stable condition judgment state, bit correction delay state, calculation of sampling position state, reset state after bit correction, delay state after bit correction, word correction state, preset period timing setting state before channel correction, channel correction state, bit correction completion processing state, word correction completion processing state, and channel correction completion processing state; among which... After the area array detector is powered on, the second sub-state machine first enters the power-on waiting state. When the bit correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before bit correction. When the word correction indication signal is detected to be high, the second sub-state machine enters the word correction sub-state. When the channel correction indication signal is detected to be high, the second sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the second sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the second sub-state machine enters the steady-state sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the second sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the second sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the second sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the second sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the second sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the second sub-state machine enters the bit-correction end processing state. In the bit correction completion processing state, a judgment is made on whether the bit correction is completed. If the bit correction is completed, the second sub-state machine returns to the power-on waiting state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the second sub-state machine enters the word correction end processing state. In the word correction completion processing state, a judgment is made on whether word correction has ended. If it is determined that word correction has ended, the second sub-state machine returns to the power-on waiting state. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the second sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or failed after a preset number of calibrations, the second sub-state machine enters the channel calibration end processing state. In the channel calibration completion processing state, a judgment is made on whether the channel calibration is completed. If the channel calibration is completed, the second sub-state machine returns to the power-on waiting state.

5. The dynamic training method for an area array detector according to claim 1, characterized in that, When the area array detector is detected to be powered on or a secondary training command is received, the third sub-state machine includes the following states: power-on waiting state, preset period timing setting state before bit correction, reset state before bit correction, stable condition sampling state, stable condition judgment state, bit correction delay state, calculation of sampling position state, reset state after bit correction, delay state after bit correction, word correction state, preset period timing setting state before channel correction, channel correction state, bit correction completion processing state, word correction completion processing state, and channel correction completion processing state; among which... After the area array detector is powered on, the third sub-state machine first enters the power-on waiting state. When the bit correction indication signal is detected to be high, the third sub-state machine enters the preset cycle timing setting state before bit correction. When the word correction indication signal is detected to be high, the third sub-state machine enters the word correction sub-state. When the channel correction indication signal is detected to be high, the third sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the third sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the third sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the third sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the third sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the third sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the third sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the third sub-state machine enters the bit-corrected delayed state. In the post-bit correction delay state, the post-bit correction delay is performed. After the delay is completed, the third sub-state machine enters the bit correction end processing state. In the bit correction completion processing state, a judgment is made on whether the bit correction is completed. If the bit correction is completed, the third sub-state machine returns to the power-on waiting state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the third sub-state machine enters the word correction end processing state; In the word correction completion processing state, a judgment is made on whether word correction has ended. If it is determined that word correction has ended, the third sub-state machine returns to the power-on waiting state. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the third sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or failed after a preset number of calibrations, the third sub-state machine enters the channel calibration end processing state. In the channel calibration completion processing state, a judgment is made on whether the channel calibration is completed. If the channel calibration is completed, the third sub-state machine returns to the power-on waiting state.

6. The dynamic training method for an area array detector according to claim 1, characterized in that, When the array detector receives a dynamic training command, the dynamic training also includes bit correction training performed before word correction training. At this time, the third sub-state machine includes the following states: power-on waiting state, preset period timing setting state before bit correction, reset state before bit correction, stable condition sampling state, stable condition judgment state, bit correction delay state, calculation of sampling position state, reset state after bit correction, delay state after bit correction, word correction state, preset period timing setting state before channel correction, channel correction state, and processing state after single-channel training completion. After the area array detector is powered on, the third sub-state machine enters the power-on waiting state. After detecting that the dynamic training enable signal is high, the third sub-state machine enters the preset cycle timing setting state before bit correction. In the preset cycle timing setting state before bit correction, the timing setting before bit correction is performed. After the timing setting is completed, the third sub-state machine enters the reset state before bit correction. In the reset state before bit correction, the bit correction is reset. After the reset is completed, the third sub-state machine enters the stable sampling state. In the stable condition judgment state, the stable condition is judged. When no two transition edges are detected and the number of detections reaches the maximum delay value of the input delay unit inside the imaging controller, the third sub-state machine enters the position correction delay state; when two transition edges are detected or the number of detections reaches the maximum delay value of the input delay unit, the third sub-state machine enters the calculation sampling position state. In the bit correction delay state, the bit correction is delayed. After the delay is completed, the third sub-state machine returns to the stable sampling state. In the process of calculating the sampling position state, the sampling position is calculated. After the calculation is completed, the third sub-state machine enters the reset state after bit correction. In the bit-corrected reset state, a bit-corrected reset is performed. After the reset is completed, the third sub-state machine enters the bit-corrected delayed state. In the bit-corrected delay state, the bit-corrected delay is performed. After the delay is completed, the third sub-state machine enters the word correction state. In the word correction state, when it is determined whether the preset number of corrections is successful or unsuccessful, the third sub-state machine enters the preset cycle timing setting state before channel correction. In the preset cycle timing setting state before channel calibration, the timing setting before channel calibration is performed. After the timing setting is completed, the third sub-state machine enters the channel calibration state. In the channel calibration state, when it is determined whether the channel calibration is successful or unsuccessful after a preset number of times, the third sub-state machine enters the processing state after single-channel training is completed. In the processing state after single-channel training is completed, a judgment is made on whether the training of a single channel is completed. After the judgment is completed, the third sub-state machine returns to the power-on waiting state.

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