Magnetoresistive random access memory and method of making the same

Abstract

A magnetic random access memory and a method of fabricating the same are disclosed. The magnetic random access memory includes a lower electrode layer, a magnetic tunnel junction stack layer above the lower electrode layer, and an upper electrode layer above the magnetic tunnel junction stack layer. The upper electrode layer is made of titanium nitride, and the proportion of nitrogen in the titanium nitride decreases from the top surface to the bottom surface of the upper electrode layer.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201910634906.1, application date: July 15, 2019, invention title: magnetoresistive random access memory and method of manufacturing the same). Technical Field

[0002] The present invention relates to a magnetoresistive random access memory, and more specifically, to a magnetoresistive random access memory having a special upper electrode configuration. Background Technology

[0003] The magnetoresistance (MR) effect is known to be the change in the resistance of a material as a result of an applied magnetic field. Its physical quantity is defined as the resistance difference under and without a magnetic field, divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetoresistive random access memory (MRAM) can be fabricated, which has the advantage of continuously retaining stored data even without power.

[0004] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones integrated with the GPS system, providing users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, current magnetoresistive random access memory (RAM) still suffers from many problems caused by manufacturing processes, such as tail bit failure, necessitating further improvements. Summary of the Invention

[0005] To improve the failure problem of the tail bit in magnetoresistive random access memory, this invention proposes a magnetoresistive random access memory with a special upper electrode composition, which can prevent the etching solution from passing through the upper electrode and damaging the underlying magnetic tunneling junction during the manufacturing process.

[0006] One aspect of the present invention is to provide a magnetoresistive random access memory cell, including a substrate, a lower electrode layer located above the substrate, a magnetic tunneling junction stack located above the lower electrode layer, and an upper electrode layer located above the magnetic tunneling junction stack, wherein the material of the upper electrode layer is titanium nitride, and the proportion of nitrogen in the titanium nitride decreases from the top surface of the upper electrode layer to the bottom surface of the upper electrode layer.

[0007] Another aspect of the present invention is to provide a method for fabricating a magnetoresistive random access memory (MAM), comprising providing a substrate, sequentially forming a lower electrode layer, a magnetic tunneling junction layer, and an upper electrode layer on the substrate, wherein the upper electrode layer is made of titanium nitride, the nitrogen content in the titanium nitride decreases from the top surface of the upper electrode layer to the bottom surface of the upper electrode layer, and patterning the lower electrode layer, the magnetic tunneling junction layer, and the upper electrode layer into a plurality of MAM cells.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figures 1 to 5 This is a cross-sectional schematic diagram of the fabrication method of a magnetoresistive random access memory according to Embodiment 1 of the present invention; and

[0011] Figure 6 This is a cross-sectional schematic diagram of a magnetoresistive random access memory cell according to another embodiment of the present invention.

[0012] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0013] Explanation of main component symbols

[0014] 100 base

[0015] 102 Intermetallic Dielectric Layer

[0016] 104 Stop Layer

[0017] 106 interlayer dielectric layer

[0018] 106a upper surface

[0019] 108 metal layer

[0020] 110 Contact Hole Plug

[0021] 112 Lower electrode layer

[0022] 114 Magnetic tunneling stack

[0023] 116 Upper Electrode Layer

[0024] 118 Magnetoresistive Random Access Memory Units

[0025] 120 Liner

[0026] 122 Dielectric Layer

[0027] 124 Stop Layer

[0028] 126 Intermetallic Dielectric Layer

[0029] 128 Double Inlay Grooves

[0030] 130 Contact Hole Plug

[0031] 132 Dual Mosaic Structure

[0032] 134 Hard mask layers

[0033] 136 Etching Stop Layer Detailed Implementation

[0034] The following detailed description of embodiments of the present invention, illustrated in the accompanying figures, will allow the reader to understand and implement the invention and to appreciate its technical effects. It should be noted that the following description is merely illustrative and does not limit the scope of the invention. Various embodiments and features thereof can be combined and rearranged in many different ways without conflict. Various modifications, counterparts, or improvements to the disclosure of the present invention should be understood by those skilled in the art and are intended to be included within the scope of the present invention, without departing from its spirit and scope.

[0035] It should be readily understood that the meanings of "on top of," "above," and "above" in this text should be interpreted in the broadest sense, such that "on top of" not only means "directly on something," but also includes being on something with an intermediate feature or layer between them, and "above" or "above" not only means being on or above something, but also includes the meaning of not having an intermediate feature or layer between them (i.e., being directly on something).

[0036] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used in the specification to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. In addition to the directions depicted in the drawings, these spatial relative terms are intended to cover different orientations or directions of the device in use or operation. The device may be oriented in other ways (e.g., by rotation of 90 degrees or in other directions), and these can also be interpreted accordingly using the spatially related descriptions used in the specification.

[0037] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a cross-sectional schematic diagram of a method for manufacturing a magnetoresistive random access memory according to Embodiment 1 of the present invention. Figure 1 As shown, a substrate 100 is first provided, such as a substrate 100 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium compounds, silicon carbide, gallium arsenide, etc. A magnetic memory region and a logic region are preferably defined on the substrate 100. However, to avoid obscuring the focus of this case, only the relevant structure of the magnetoresistive random access memory cell on the magnetic memory region is shown in the figure.

[0038] An intermetallic dielectric layer 102, a stop layer 104, and an interlayer dielectric layer 106 are sequentially formed on a substrate 100. The intermetallic dielectric layer 102 is preferably made of an ultra-low dielectric constant (ULK) material, such as porous silicon oxycarbide (SiOC). The stop layer 104 is preferably made of nitrogen-doped carbide (NDC), silicon nitride, or silicon carbide nitride (SiCN), while the interlayer dielectric layer 106 is preferably made of tetraethoxysilane (TEOS), but is not limited thereto. Metal layers 108 and contact hole conductors 110 are formed in the intermetallic dielectric layer 102 and the interlayer dielectric layer 106, respectively. These conductors can be embedded in the intermetallic dielectric layer 102, the stop layer 104, and the interlayer dielectric layer 106 using a single-damascene fabrication process or a double-damascene fabrication process and are electrically connected to each other. The materials of the metal layer 108 and the contact hole conductor 110 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but are not limited to this.

[0039] Rereference Figure 1A lower electrode layer 112, a magnetic tunneling junction stack 114, and an upper electrode layer 116 are sequentially formed on the interlayer dielectric layer 106. The lower electrode layer 112, the magnetic tunneling junction stack 114, and the upper electrode layer 116 can be formed in-situ in the same cavity using physical vapor deposition (PVD). In this embodiment of the invention, the material of the lower electrode layer 112 preferably includes a conductive material, such as tantalum nitride (TaN), but is not limited thereto. According to other embodiments of the invention, the lower electrode layer 112 may also include tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof. The magnetic tunneling junction stack 114 is a multilayer structure, which may include a seed layer, a pinned layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator. In general, the fixed layer can be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The tunneling barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited to these. The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. Since the structure of the magnetic tunneling stack 114 is not the focus of this invention, the above-mentioned multilayer structures are generally referred to as magnetic tunneling stack 114 in the figures.

[0040] In this embodiment, the upper electrode layer 116 is made of titanium nitride (TiN), and preferably contains a compositional gradient, meaning that the compositional ratio of titanium nitride in the entire upper electrode layer 116 is not completely uniform. More specifically, the proportion of nitrogen in the upper electrode layer 116 preferably decreases gradually from the top surface (exposed surface) of the upper electrode layer 116 towards the bottom surface (the side in contact with the magnetic tunneling junction 114), and the proportion of titanium in the upper electrode layer 116 preferably increases gradually from the top surface of the upper electrode layer 116 towards the bottom surface. In other words, there is preferably a higher concentration of titanium atoms or a lower concentration of nitrogen atoms near the bottom surface of the upper electrode layer 116 or at the junction of the upper electrode layer 116 and the magnetic tunneling junction 114, while there is preferably a higher concentration of nitrogen atoms or a lower concentration of titanium atoms near the top surface of the upper electrode layer 116. Preferably, the nitrogen content of titanium nitride in the upper electrode layer 116 is between greater than 0% and less than 50%. The function of the compositional gradient characteristics of titanium nitride in the upper electrode layer 116 will be described in detail in subsequent embodiments.

[0041] Then as Figure 2As shown, the upper electrode layer 116, the magnetic tunneling junction stack 114, and the lower electrode layer 112 are patterned using photolithography and etching processes to define individual magnetoresistive random access memory (RAM) cells 118. Specifically, the upper electrode layer 116 can be patterned first using reactive ion etching (RIE) in conjunction with a silicon oxide hard mask layer, resulting in fewer sidewall byproducts. Next, the magnetic tunneling junction stack 114, the lower electrode layer 112, and the interlayer dielectric layer 106 are patterned using ion beam etching (IBE) to define the RAM cells 118. Due to the characteristics of the ion beam etching process, the upper surface 106a of the remaining interlayer dielectric layer 106 after etching is preferably slightly lower than the upper surface of the contact hole conductor 110, and the upper surface 106a of the interlayer dielectric layer 106 preferably has an arc or curved shape.

[0042] Then as Figure 3 As shown, a conformal substrate 120 is formed on the surface of the magnetoresistive random access memory cell 118 and the interlayer dielectric layer 106. The substrate 120 is preferably made of silicon oxide, but other dielectric materials can be selected depending on the fabrication process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide. Next, a dielectric layer 122, a stop layer 124, and an intermetallic dielectric layer 126 are sequentially formed on the substrate 120. The dielectric layer 122 fills the gaps between the magnetoresistive random access memory cells 118, and a planarization process such as chemical mechanical polishing (CMP) is used to planarize the dielectric layer 122 so that its upper surface is flush with or slightly higher than the magnetoresistive random access memory cells 118. In this embodiment of the invention, the dielectric layer 122 and the intermetallic dielectric layer 126 are preferably made of ultra-low dielectric constant (ULK) materials, and the stop layer 124 is preferably made of nitrogen-doped carbide (NDC), silicon nitride, or silicon carbide.

[0043] Then as Figure 4 As shown, a dual damascene groove 128 is formed in the intermetallic dielectric layer 126, which includes a contact hole and the outline of a metal layer. The dual damascene groove 128 passes through the substrate 120 on the magnetoresistive random access memory cell 118 to expose its upper electrode layer 116. In this embodiment, the dual damascene groove 128 can be formed by forming a patterned photoresist and a patterned hard mask on the intermetallic dielectric layer 126 and performing several etching and wet cleaning processes. Since how this dual damascene groove 128 is formed is not the focus of this invention, the details of the steps will not be disclosed in the specification and figures.

[0044] In this embodiment of the invention, the dual damascene grooves 128 on the magnetic memory region are formed in the same fabrication process as the dual damascene grooves (not shown) on the logic region. For the components in the logic region, a wet etching process is performed after the formation of the dual damascene grooves to remove polymer byproducts and the exposed titanium nitride hard mask layer from the grooves. The etching solution used in this wet etching process, such as DuPont's EKC series etching residue cleaning solution with hydrogen peroxide solution, has a high etching power for titanium nitride and its oxides. In addition, titanium nitride layers are generally grown in a polycrystalline columnar shape, which results in a high surface roughness and often has fine pore defects between the columnars that lead directly to the bottom of the titanium nitride layer. Thus, the wet etching process used to remove the hard mask layer on the logic region will also remove the titanium nitride upper electrode layer 116 on the upper part of the magnetic memory region. Furthermore, the etching solution may further penetrate to the bottom of the upper electrode layer 116 and damage the underlying magnetic tunneling junction stack 114, causing the ferromagnetic layer in the magnetic tunneling junction stack 114 to lose its ferromagnetism. This is particularly prone to causing the tail bits to fail.

[0045] The titanium nitride in the upper electrode layer 116 of this invention has the advantage of a compositional gradient, which prevents damage to the magnetic tunneling junction stack 114 during the wet etching process. The principle is that the lower the nitrogen content in titanium nitride, the closer its crystal form is to a dense metallic state rather than a polycrystalline columnar state. This results in smaller die size and surface roughness, and fewer silicon via defects. By designing the titanium nitride composition in the upper electrode layer 116 to have a lower nitrogen content closer to the magnetic tunneling junction stack 114, the etching solution becomes less likely to penetrate the upper electrode layer 114, thus preventing damage to the underlying magnetic tunneling junction stack 114 from the etching solution.

[0046] Next, as follows Figure 5 As shown, the desired metal material is filled into the dual damascene groove 128, such as a barrier layer containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, for example, by chemical mechanical polishing to remove some of the metal material to form a dual damascene structure 132 containing contact hole plugs 130 and a metal layer, which electrically connects to the upper electrode layer 116 of the lower magnetoresistive random access memory cell 118.

[0047] Based on the manufacturing process described in the preceding embodiments, this invention also proposes a novel magnetoresistive random access memory cell 118, such as... Figure 5As shown, its structure includes a lower electrode layer 112 located above a substrate 100, a magnetic tunneling junction stack 114 located above the lower electrode layer 112, and an upper electrode layer 116 located above the magnetic tunneling junction stack 114. The upper electrode layer 116 is made of titanium nitride, and the nitrogen content of the titanium nitride decreases from the top surface to the bottom surface of the upper electrode layer 116, with the nitrogen ratio between greater than 0% and less than 50%.

[0048] In addition to the titanium nitride composition gradient characteristics mentioned above, other features may be added to the magnetoresistive random access memory in other embodiments to enhance the desired protection effect on the magnetic tunneling junction stack. Please refer to... Figure 6 This is a cross-sectional schematic diagram of a magnetoresistive random access memory cell according to another embodiment of the present invention. Figure 6 As shown, a hard mask layer 134 can be disposed between the upper electrode layer 116 and the contact hole plug 130 of the magnetoresistive random access memory cell 118. The material of the hard mask layer 134 is preferably tantalum (Ta) or tantalum nitride (TaN), which can prevent etchant from penetrating the upper electrode layer 116 to the magnetic tunneling junction stack 114 at the top surface of the upper electrode layer 116. Furthermore, an etch stop layer 136 can also be disposed between the upper electrode layer 116 and the magnetic tunneling junction stack 114. The material of the etch stop layer 136 is preferably a multilayer alternating stack structure of ruthenium (Ru) and ruthenium oxide (RuO), which has good chemical corrosion resistance and can further prevent the magnetic tunneling junction stack 114 from being etched and damaged. The alternating stack design of ruthenium and ruthenium oxide can also avoid peeling problems of the magnetic tunneling junction stack 114 due to etchant corrosion. The aforementioned hard mask layer 134 and etch stop layer 136 can also be formed in the same cavity using physical vapor deposition, along with the lower electrode layer 112, magnetic tunneling junction stack 114, and upper electrode layer 116.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.

Claims

1. A magnetoresistive random access memory cell, characterized in that, include: Base; The lower electrode layer is located above the substrate; A magnetic tunneling stack is located above the lower electrode layer; as well as An upper electrode layer, located above the magnetic tunneling junction stack, is made of titanium nitride, and the nitrogen content in the titanium nitride decreases from the top surface to the bottom surface of the upper electrode layer; and A hard mask layer is disposed on the upper electrode, wherein the material of the hard mask layer is tantalum or tantalum nitride.

2. The magnetoresistive random access memory cell according to claim 1, wherein the nitrogen content in the titanium nitride is between greater than 0% and less than 50%.

3. The magnetoresistive random access memory cell according to claim 1 further includes an etch stop layer disposed between the upper electrode layer and the magnetic tunneling junction stack, wherein the material of the etch stop layer includes ruthenium or ruthenium oxide.

4. The magnetoresistive random access memory cell according to claim 3, wherein the etch stop layer is a multilayered ruthenium oxide and ruthenium alternating stacked structure.

5. The magnetoresistive random access memory cell according to claim 1, wherein the magnetic tunneling junction stack comprises a seed layer, a fixed layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator.

6. A method for manufacturing a magnetoresistive random access memory, comprising: Provide a base; A lower electrode layer, a magnetic tunneling junction stack, an upper electrode layer, and a hard mask layer are sequentially formed on the substrate. The upper electrode layer is made of titanium nitride, and the hard mask layer is made of tantalum or tantalum nitride. The nitrogen content in the titanium nitride decreases from the top surface of the upper electrode layer to its bottom surface. The lower electrode layer, the magnetic tunneling junction stack, the upper electrode layer, and the hard mask layer are patterned into multiple magnetoresistive random access memory cells.

7. The method for manufacturing a magnetoresistive random access memory according to claim 6, wherein the nitrogen content in the titanium nitride is between greater than 0% and less than 50%.

8. The method for fabricating a magnetoresistive random access memory according to claim 6 further includes an etch stop layer disposed between the upper electrode layer and the magnetic tunneling junction stack, wherein the material of the etch stop layer comprises ruthenium or ruthenium oxide.

9. The method for fabricating a magnetoresistive random access memory according to claim 8, wherein the etch stop layer is a multilayered ruthenium oxide and ruthenium alternating stacked structure.

10. The method for fabricating a magnetoresistive random access memory according to claim 6, wherein the magnetic tunneling junction stack comprises a seed layer, a fixed layer, a reference layer, a tunneling barrier layer, a free layer, and a metal separator.

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