Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate and a driving circuit arranged on the substrate; the driving circuit comprises a plurality of noise reduction transistors and a plurality of driving transistors; the noise reduction transistors are electrically connected with a pull-up node; the length of the channel of at least part of the noise reduction transistors is a first length L1; the length of the channel of at least part of the driving transistors is a second length L2; the first length L1 is not equal to the second length L2.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] In related technologies, the charging time for each row of pixels in large-size displays with high refresh rates is shortened, and low-temperature startup difficulties are easily caused during low-temperature reliability testing. Therefore, in the driving circuit, the gate and source of the transistor used to drive the pull-up node are separated to improve this problem. Due to layout space limitations, the driving circuit does not include a transistor for resetting the driving signal; instead, the driving signal output terminal is discharged only through a transistor used to drive it. When the potential of the pull-up node (the gate of the transistor used to drive the driving signal output terminal is electrically connected to the pull-up node) is unstable, it significantly affects the discharge of the driving signal output terminal. During the lamp-on process of large-size displays with high refresh rates, horizontal stripe defects occur due to incorrect charging caused by the slow pull-down of the driving signal potential. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a display substrate, including a substrate and a driving circuit disposed on the substrate; the driving circuit includes a plurality of noise-reducing transistors and a plurality of transistors for driving; the noise-reducing transistors are electrically connected to a pull-up node;

[0004] The channel length of at least a portion of the transistors in the noise reduction transistor is a first length L1;

[0005] The channel length of at least a portion of the plurality of transistors used for driving is a second length L2;

[0006] The first length L1 is not equal to the second length L2.

[0007] Optionally, the first length L1 is greater than the second length L2.

[0008] Optionally, the first length L1 is greater than or equal to 5.5 μm and less than or equal to 9 μm, and the second length L2 is greater than or equal to 2 μm and less than or equal to 5.0 μm; the ratio between the first length L1 and the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5.

[0009] Optionally, the driving circuit further includes a transistor for noise reduction of the carry signal output terminal, and a transistor for noise reduction of the driving signal output terminal;

[0010] The length of the channel of the transistor used for noise reduction of the carry signal output terminal is the third length L3;

[0011] The length of the channel of the transistor used for noise reduction at the drive signal output terminal is the fourth length L4;

[0012] The third length L3 is not equal to the second length L2, and the fourth length L4 is not equal to the second length L2.

[0013] Optionally, the third length L3 is greater than the second length L2, and the fourth length is greater than the second length L2.

[0014] Optionally, the third length L3 is greater than or equal to 5.5 μm and less than or equal to 9 μm, the fourth length L4 is greater than or equal to 5.5 μm and less than or equal to 9 μm, and the second length L2 is greater than or equal to 2 μm and less than or equal to 5.0 μm; the ratio of the third length L3 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5, and the ratio of the fourth length L4 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5.

[0015] Optionally, the transistor for driving includes a transistor for driving the pull-up node, a transistor for driving the carry signal output terminal, and a transistor for driving the drive signal output terminal.

[0016] Optionally, the driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first transistor, the second transistor, the third transistor, and the fourth transistor are the noise reduction transistors.

[0017] The control electrode of the first transistor is electrically connected to the pull-up reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0018] The control electrode of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0019] The control electrode of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal.

[0020] The control electrode of the fourth transistor is electrically connected to the starting voltage terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal.

[0021] Optionally, the driving circuit includes a fifth transistor and a sixth transistor; the fifth transistor and the sixth transistor are the noise reduction transistors;

[0022] The control electrode of the fifth transistor is electrically connected to the pull-up node, the first electrode of the fifth transistor is electrically connected to the first pull-down control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0023] The control electrode of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down control node, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0024] Optionally, at least one of the following lengths—the channel length of the first transistor, the channel length of the second transistor, the channel length of the third transistor, the channel length of the fourth transistor, the channel length of the fifth transistor, and the channel length of the sixth transistor—is a first length L1.

[0025] Optionally, the driving circuit further includes a seventh transistor, an eighth transistor, and a ninth transistor; the seventh transistor, the eighth transistor, and the ninth transistor are driving transistors for driving.

[0026] The control electrode of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal.

[0027] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the carry signal output terminal.

[0028] The control electrode of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node.

[0029] Optionally, at least one of the channel lengths of the seventh transistor, the eighth transistor, and the ninth transistor is a second length L2.

[0030] Optionally, the driving circuit further includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0031] The control electrode of the tenth transistor is electrically connected to the first pull-down node, the first electrode of the tenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal.

[0032] The control electrode of the eleventh transistor is electrically connected to the second pull-down node, the first electrode of the eleventh transistor is electrically connected to the drive signal output terminal, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal.

[0033] The control electrode of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal.

[0034] The control electrode of the thirteenth transistor is electrically connected to the second pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry signal output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

[0035] The tenth and eleventh transistors are transistors used for noise reduction at the drive signal output terminal, and the twelfth and thirteenth transistors are transistors used for noise reduction at the carry signal output terminal.

[0036] The channel lengths of the tenth transistor and the eleventh transistor are a third length L3, and the channel lengths of the twelfth transistor and the thirteenth transistor are a fourth length L4.

[0037] Optionally, the driving circuit further includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a capacitor;

[0038] The control electrode and the first electrode of the fourteenth transistor are electrically connected to the first control voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the first pull-down control node;

[0039] The control electrode and the first electrode of the fifteenth transistor are electrically connected to the second control voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second pull-down control node;

[0040] The control electrode of the sixteenth transistor is electrically connected to the pull-up node, the first electrode of the sixteenth transistor is electrically connected to the first pull-down node, and the second electrode of the sixteenth transistor is electrically connected to the first voltage terminal.

[0041] The control electrode of the seventeenth transistor is electrically connected to the pull-up node, the first electrode of the seventeenth transistor is electrically connected to the second pull-down node, and the second electrode of the seventeenth transistor is electrically connected to the first voltage terminal.

[0042] The control electrode of the eighteenth transistor is electrically connected to the first pull-down control node, the first electrode of the eighteenth transistor is electrically connected to the first control voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first pull-down node.

[0043] The control electrode of the nineteenth transistor is electrically connected to the second pull-down control node, the first electrode of the nineteenth transistor is electrically connected to the second control voltage terminal, and the second electrode of the nineteenth transistor is electrically connected to the second pull-down node.

[0044] The control electrode of the twentieth transistor is electrically connected to the first input terminal, the first electrode of the twentieth transistor is electrically connected to the first pull-down node, and the second electrode of the twentieth transistor is electrically connected to the first voltage terminal.

[0045] The control electrode of the 21st transistor is electrically connected to the first input terminal, the first electrode of the 21st transistor is electrically connected to the second pull-down node, and the second electrode of the 21st transistor is electrically connected to the first voltage terminal.

[0046] Optionally, the aspect ratio of the first transistor is B1, the aspect ratio of the ninth transistor is A1, the aspect ratio of the fourth transistor is B2, the aspect ratios of the second transistor and the third transistor are both B3, and the aspect ratio of the seventh transistor is A2.

[0047] The aspect ratio of the tenth transistor and the eleventh transistor is both B4; the aspect ratio of the twelfth transistor and the thirteenth transistor is both B5.

[0048] B1 / A1 is greater than or equal to 0.1 and less than or equal to 0.8; B2 / A1 is greater than or equal to 0.005 and less than or equal to 0.5; B3 / A1 is greater than or equal to 0.01 and less than or equal to 0.5; B4 / A1 is greater than or equal to 0.04 and less than or equal to 0.4; B5 / A1 is greater than or equal to 0.01 and less than or equal to 0.3.

[0049] B1 / A2 is greater than or equal to 0.02 and less than or equal to 0.08; B2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06; B3 / A2 is greater than or equal to 0.015 and less than or equal to 0.05; B4 / A2 is greater than or equal to 0.004 and less than or equal to 0.048; B5 / A2 is greater than or equal to 0.001 and less than or equal to 0.045.

[0050] Optionally, the aspect ratio of the fifth transistor and the aspect ratio of the sixth transistor are C1, the aspect ratio of the sixteenth transistor is C2, the aspect ratio of the fourteenth transistor and the aspect ratio of the fifteenth transistor are both C3, and the aspect ratio of the eighteenth transistor and the nineteenth transistor are both C4.

[0051] C1 / A1 is greater than or equal to 0.03 and less than or equal to 0.09, C2 / A1 is greater than or equal to 0.08 and less than or equal to 0.6, C3 / A1 is greater than or equal to 0.005 and less than or equal to 0.046, and C4 / A1 is greater than or equal to 0.03 and less than or equal to 0.09.

[0052] C1 / A2 is greater than or equal to 0.005 and less than or equal to 0.02, C2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06, C3 / A2 is greater than or equal to 0.01 and less than or equal to 0.05, and C4 / A2 is greater than or equal to 0.003 and less than or equal to 0.04.

[0053] In a second aspect, embodiments of this disclosure also provide a display device, including the display substrate described above. Attached Figure Description

[0054] Figure 1 This is a circuit diagram of at least one embodiment of the driving circuit in the display substrate described in this disclosure;

[0055] Figure 2 This is a waveform diagram of the potential of the pull-up node PU after each transistor is cut in the relevant technology;

[0056] Figure 3 yes Figure 1 A schematic diagram of the layout of the fifth transistor M5, the sixth transistor M6, the sixteenth transistor M16, and the seventeenth transistor M17 in the transistor.

[0057] Figure 4 yes Figure 3 Layout diagram of the gate metal layer in the middle;

[0058] Figure 5 yes Figure 3 Layout diagram of the active layer in the diagram;

[0059] Figure 6 yes Figure 3 A schematic diagram of the source and drain metal layers in the diagram;

[0060] Figure 7 This is a public announcement Figure 1 A schematic diagram of the active layer of each transistor in at least one embodiment of the driving circuit shown.

[0061] Figure 8 This is a public announcement Figure 1 A schematic diagram of the gates of each transistor in at least one embodiment of the driving circuit shown.

[0062] Figure 9 This is a schematic diagram of channel 10 of M1;

[0063] Figure 10This is a schematic diagram of channel 20 of M2;

[0064] Figure 11 This is a schematic diagram of channel 30 of M3;

[0065] Figure 12 This is a schematic diagram of the M4's channel 40;

[0066] Figure 13 This is a schematic diagram of the M5 channel 50;

[0067] Figure 14 This is a schematic diagram of the M6's channel 60;

[0068] Figure 15 This is a schematic diagram of the channel 100 of the M10;

[0069] Figure 16 This is a schematic diagram of channel 110 of M11;

[0070] Figure 17 This is a schematic diagram of the M12 channel 120;

[0071] Figure 18 This is a schematic diagram of the M13 channel 130;

[0072] Figure 19 This is a schematic diagram of the M7 channel 70;

[0073] Figure 20 This is a schematic diagram of the M8 channel 80;

[0074] Figure 21 This is a schematic diagram of the M9's channel 90. Detailed Implementation

[0075] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0076] The display substrate described in this embodiment includes a substrate and a driving circuit disposed on the substrate; the driving circuit includes a plurality of noise reduction transistors and a plurality of transistors for driving; the noise reduction transistors are electrically connected to a pull-up node;

[0077] The channel length of at least a portion of the transistors in the noise reduction transistor is a first length L1;

[0078] The channel length of at least a portion of the plurality of transistors used for driving is a second length L2;

[0079] The first length L1 is not equal to the second length L2.

[0080] This embodiment of the disclosure improves the leakage current of the pull-up node by setting the channel length of at least some of the transistors in the plurality of noise reduction transistors to be different from the channel length of at least some of the transistors in the plurality of driving transistors, thereby ensuring that the gate of the transistor used to drive the drive signal output terminal is fully opened, thereby reducing the magnitude of the fall time Tf of the drive signal output terminal, and thus improving the horizontal stripe situation.

[0081] In at least one embodiment of this disclosure, the first length L1 is greater than the second length L2.

[0082] In at least one embodiment of this disclosure, the first length L1 is set to be greater than the second length L2, thereby reducing the aspect ratio of at least some of the noise-reducing transistors. This results in a smaller leakage current Ioff, ensuring that the potential of the pull-up node remains high throughout the entire driving circuit operation due to the reduced leakage current of at least some of the noise-reducing transistors. When the driving signal output terminal stops outputting a high-voltage signal, the voltage holding characteristic of the pull-up node can stably maintain the gate of the transistor used to drive the driving signal output terminal in an open state. At this time, when the potential of the clock signal connected to the first terminal of the transistor used to drive the driving signal output terminal becomes low, a good discharge effect can be achieved for the driving signal output terminal without significantly affecting other functions.

[0083] Optionally, the first length L1 is greater than or equal to 5.5 μm and less than or equal to 9 μm; for example, L1 can be 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm or 9 μm.

[0084] The second length L2 is greater than or equal to 2um and less than or equal to 5.0um; for example, L2 can be 2um, 2.5um, 2.8um, 3um, 3.2um, 3.5um, 3.8um, 4um, 4.3um, 4.5um or 5um;

[0085] The ratio between the first length L1 and the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5; for example, the ratio between the first length L1 and the second length L2 can be 1.1, 1.3, 1.627, 1.8, 2, 2.3, 2.5, 2.7, 3, 3.2, 3.5, 3.8, 4, 4.2 or 4.5;

[0086] However, this is not the limit.

[0087] In related technologies, the channel lengths of all thin-film transistors (TFTs) in the driving circuit are designed to be identical to ensure consistent characteristic curves across all TFTs, facilitating control. As display products continue to upgrade, high refresh rates pose a challenge to the charging rate of large-size displays, while narrow bezels impose limitations on the size of TFTs in these products. With the deployment and production of high refresh rate displays, it is necessary to correspondingly increase the aspect ratio of the driving transistors to ensure the charging rate of high refresh rate displays.

[0088] When the gate-source voltage Vgs of the thin-film transistor is greater than Vth, and the drain-source voltage Vds of the thin-film transistor is less than Vgs-Vth, then...

[0089] Where Ids is the drain-source current, μ is the electron mobility, and C ox W / L represents the capacitance per unit area of ​​the MIS (metal-insulator-semiconductor) structure of the thin-film transistor, and represents the ratio of the width of the channel to the length of the channel in the thin-film transistor.

[0090] According to the formula above, to increase the on-state current of the thin-film transistor, μ and C can be increased. ox The parameters W / L, Vgs, and Vds, except for Vgs and Vds, can be controlled through process parameters or structural settings. With a fixed a-Si (amorphous silicon) process, the on-state current Ion and leakage current Ioff can be increased and decreased by adjusting the film thickness. Given fixed process conditions, a larger charge rate and a smaller fall time Tf can be ensured by specifically designing the structure of thin-film transistors with different functions in the drive circuit. That is, while ensuring μ, C... ox With Vgs, Vds, and Vth (Vth being the threshold voltage of the thin-film transistor) remaining constant, the efficiency of the drive circuit can be optimized through the W / L design.

[0091] In at least one embodiment of this disclosure, the driving circuit further includes a transistor for noise reduction of the carry signal output terminal, and a transistor for noise reduction of the driving signal output terminal;

[0092] The length of the channel of the transistor used for noise reduction of the carry signal output terminal is the third length L3;

[0093] The length of the channel of the transistor used for noise reduction at the drive signal output terminal is the fourth length L4;

[0094] The third length L3 is not equal to the second length L2, and the fourth length L4 is not equal to the second length L2.

[0095] At least one embodiment of this disclosure improves the driving capability of the driving transistors by setting the channel length (i.e., the third length L3) of the transistor used for noise reduction at the carry signal output terminal to be unequal to the channel length (i.e., the second length L2) of at least some of the plurality of driving transistors, and setting the channel length (i.e., the fourth length L4) of the transistor used for noise reduction at the drive signal output terminal to be unequal to the channel length (i.e., the second length L2) of at least some of the plurality of driving transistors.

[0096] In at least one embodiment of this disclosure, the third length L3 is greater than the second length L2, and the fourth length is greater than the second length L2, so as to relatively reduce the aspect ratio of the transistor used for noise reduction of the carry signal output terminal, relatively reduce the aspect ratio of the transistor used for noise reduction of the drive signal output terminal, and relatively increase the aspect ratio of the transistor used for driving.

[0097] Optionally, the third length L3 is greater than or equal to 5.5 μm and less than or equal to 9 μm; for example, L3 can be 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm or 9 μm.

[0098] The fourth length L4 is greater than or equal to 5.5 μm and less than or equal to 9 μm; for example, L4 can be 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm or 9 μm;

[0099] The second length L2 is greater than or equal to 2um and less than or equal to 5.0um; for example, L2 can be 2um, 2.5um, 2.8um, 3um, 3.2um, 3.5um, 3.8um, 4um, 4.3um, 4.5um or 5um;

[0100] The ratio of the third length L3 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5; for example, the ratio of the third length L3 to the second length L2 can be 1.1, 1.3, 1.627, 1.8, 2, 2.3, 2.5, 2.7, 3, 3.2, 3.5, 3.8, 4, 4.2 or 4.5;

[0101] The ratio of the fourth length L4 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5; for example, the ratio of the fourth length L4 to the second length L2 can be 1.1, 1.3, 1.627, 1.8, 2, 2.3, 2.5, 2.7, 3, 3.2, 3.5, 3.8, 4, 4.2 or 4.5;

[0102] However, this is not the limit.

[0103] In at least one embodiment of this disclosure, the transistor for driving may include a transistor for driving a pull-up node, a transistor for driving a carry signal output terminal, and a transistor for driving a drive signal output terminal.

[0104] Optionally, the driving circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the first transistor, the second transistor, the third transistor, and the fourth transistor are the noise reduction transistors;

[0105] The control electrode of the first transistor is electrically connected to the pull-up reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0106] The control electrode of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0107] The control electrode of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal.

[0108] The control electrode of the fourth transistor is electrically connected to the starting voltage terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal.

[0109] In at least one embodiment of this disclosure, the first transistor, the second transistor, the third transistor, and the fourth transistor are transistors for noise reduction of the pull-up node, and the first transistor, the second transistor, the third transistor, and the fourth transistor can be the noise reduction transistor.

[0110] Optionally, the driving circuit includes a fifth transistor and a sixth transistor; the fifth transistor and the sixth transistor are the noise reduction transistors;

[0111] The control electrode of the fifth transistor is electrically connected to the pull-up node, the first electrode of the fifth transistor is electrically connected to the first pull-down control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0112] The control electrode of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down control node, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0113] In at least one embodiment of this disclosure, the fifth transistor is a transistor that performs noise reduction for the first pull-down control node under the control of the potential of the pull-up node, and the sixth transistor is a transistor that performs noise reduction for the second pull-down control node under the control of the potential of the pull-up node. Both the fifth transistor and the sixth transistor are electrically connected to the pull-up node. The fifth transistor and the sixth transistor can be the noise reduction transistor.

[0114] In at least one embodiment of this disclosure, at least one of the lengths of the channel of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is a first length L1.

[0115] In specific implementation, at least one of the following can be relatively increased: the channel length of the first transistor, the channel length of the second transistor, the channel length of the third transistor, the channel length of the fourth transistor, the channel length of the fifth transistor, and the channel length of the sixth transistor. This reduces the aspect ratio of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, thereby correspondingly reducing the leakage current Ioff of at least one of these transistors. This improves the leakage current of the pull-up node and ensures that the gate of the transistor used to drive the drive signal output terminal is fully open, thereby reducing the fall time Tf of the drive signal output terminal and improving the horizontal stripe situation.

[0116] In at least one embodiment of this disclosure, the leakage current of the corresponding transistor can be reduced by increasing at least one of the channel lengths of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor from 4.3µm to 7µm.

[0117] Optionally, the driving circuit further includes a seventh transistor, an eighth transistor, and a ninth transistor; the seventh transistor, the eighth transistor, and the ninth transistor are driving transistors for driving.

[0118] The control electrode of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal.

[0119] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the carry signal output terminal.

[0120] The control electrode of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node.

[0121] In a specific implementation, the seventh transistor is a transistor used to drive the drive signal output terminal, the eighth transistor is a transistor used to drive the carry signal output terminal, and the ninth transistor is a transistor used to drive the pull-up node.

[0122] In at least one embodiment of this disclosure, the first input terminal is electrically connected to the carry signal output terminal of the adjacent previous stage driving circuit, the second input terminal is electrically connected to the drive signal output terminal of the adjacent previous stage driving circuit, and the second terminal of the ninth transistor is electrically connected to the pull-up node.

[0123] In at least one embodiment of this disclosure, at least one of the channel lengths of the seventh transistor, the eighth transistor, and the ninth transistor is a second length L2.

[0124] Optionally, the driving circuit further includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0125] The control electrode of the tenth transistor is electrically connected to the first pull-down node, the first electrode of the tenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal.

[0126] The control electrode of the eleventh transistor is electrically connected to the second pull-down node, the first electrode of the eleventh transistor is electrically connected to the drive signal output terminal, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal.

[0127] The control electrode of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal.

[0128] The control electrode of the thirteenth transistor is electrically connected to the second pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry signal output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

[0129] The tenth and eleventh transistors are transistors used for noise reduction at the drive signal output terminal, and the twelfth and thirteenth transistors are transistors used for noise reduction at the carry signal output terminal.

[0130] The channel lengths of the tenth transistor and the eleventh transistor are a third length L3, and the channel lengths of the twelfth transistor and the thirteenth transistor are a fourth length L4.

[0131] Optionally, the driving circuit further includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a capacitor;

[0132] The control electrode and the first electrode of the fourteenth transistor are electrically connected to the first control voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the first pull-down control node;

[0133] The control electrode and the first electrode of the fifteenth transistor are electrically connected to the second control voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second pull-down control node;

[0134] The control electrode of the sixteenth transistor is electrically connected to the pull-up node, the first electrode of the sixteenth transistor is electrically connected to the first pull-down node, and the second electrode of the sixteenth transistor is electrically connected to the first voltage terminal.

[0135] The control electrode of the seventeenth transistor is electrically connected to the pull-up node, the first electrode of the seventeenth transistor is electrically connected to the second pull-down node, and the second electrode of the seventeenth transistor is electrically connected to the first voltage terminal.

[0136] The control electrode of the eighteenth transistor is electrically connected to the first pull-down control node, the first electrode of the eighteenth transistor is electrically connected to the first control voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first pull-down node.

[0137] The control electrode of the nineteenth transistor is electrically connected to the second pull-down control node, the first electrode of the nineteenth transistor is electrically connected to the second control voltage terminal, and the second electrode of the nineteenth transistor is electrically connected to the second pull-down node.

[0138] The control electrode of the twentieth transistor is electrically connected to the first input terminal, the first electrode of the twentieth transistor is electrically connected to the first pull-down node, and the second electrode of the twentieth transistor is electrically connected to the first voltage terminal.

[0139] The control electrode of the 21st transistor is electrically connected to the first input terminal, the first electrode of the 21st transistor is electrically connected to the second pull-down node, and the second electrode of the 21st transistor is electrically connected to the first voltage terminal.

[0140] In practical implementation, transistors fourteen, fifteen, sixteen, seventeen, eighteen, nineteen, twentieth, and twenty-first are used to control the potential of the first pull-down node and the potential of the second pull-down node.

[0141] like Figure 1 As shown, the driving circuit described in at least one embodiment of this disclosure may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a capacitor C1;

[0142] The gate of the first transistor M1 is electrically connected to the pull-up reset terminal R1, the first electrode of the first transistor M1 is electrically connected to the pull-up node PU, and the second electrode of the first transistor M1 is electrically connected to the first low voltage terminal LVSS.

[0143] The gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the first electrode of the second transistor M2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor M2 is electrically connected to the first low voltage terminal LVSS.

[0144] The gate of the third transistor M3 is electrically connected to the second pull-down node PD2, the first electrode of the third transistor M3 is electrically connected to the pull-up node PU, and the second electrode of the third transistor M3 is electrically connected to the first low voltage terminal LVSS.

[0145] The gate of the fourth transistor M4 is electrically connected to the start voltage terminal STV, the first electrode of the fourth transistor M4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor M4 is electrically connected to the first low voltage terminal LVSS.

[0146] The gate of the fifth transistor M5 is electrically connected to the pull-up node PU, the first electrode of the fifth transistor is electrically connected to the first pull-down control node PDCN1, and the second electrode of the fifth transistor M5 is electrically connected to the first low voltage terminal LVSS.

[0147] The gate of the sixth transistor M6 is electrically connected to the pull-up node PU, the first electrode of the sixth transistor M6 is electrically connected to the second pull-down control node PDCN2, and the second electrode of the sixth transistor M6 is electrically connected to the first low voltage terminal LVSS.

[0148] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the first electrode of the seventh transistor M7 is electrically connected to the clock signal terminal K1, and the second electrode of the seventh transistor M7 is electrically connected to the drive signal output terminal GO.

[0149] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor M8 is electrically connected to the clock signal terminal K1, and the second electrode of the eighth transistor M8 is electrically connected to the carry signal output terminal OC.

[0150] The gate of the ninth transistor M9 is electrically connected to the first input terminal I1, the first electrode of the ninth transistor M9 is electrically connected to the second input terminal I2, and the second electrode of the ninth transistor M9 is electrically connected to the pull-up node PU.

[0151] The gate of the tenth transistor M10 is electrically connected to the first pull-down node PD1, the first electrode of the tenth transistor M10 is electrically connected to the drive signal output terminal GO, and the second electrode of the tenth transistor M10 is electrically connected to the second low voltage terminal VSS.

[0152] The gate of the eleventh transistor M11 is electrically connected to the second pull-down node PD2, the first electrode of the eleventh transistor M11 is electrically connected to the drive signal output terminal GO, and the second electrode of the eleventh transistor M11 is electrically connected to the second low voltage terminal VSS.

[0153] The gate of the twelfth transistor M12 is electrically connected to the first pull-down node PD1, the first electrode of the twelfth transistor M12 is electrically connected to the carry signal output terminal OC, and the second electrode of the twelfth transistor M12 is electrically connected to the first low voltage terminal LVSS.

[0154] The gate of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the first electrode of the thirteenth transistor M13 is electrically connected to the carry signal output terminal OC, and the second electrode of the thirteenth transistor M13 is electrically connected to the first low voltage terminal LVSS.

[0155] The gate and first electrode of the fourteenth transistor M14 are electrically connected to the first control voltage terminal VDDO, and the second electrode of the fourteenth transistor M14 is electrically connected to the first pull-down control node PDCN1.

[0156] The gate and first electrode of the fifteenth transistor M15 are electrically connected to the second control voltage terminal VDDE, and the second electrode of the fifteenth transistor M15 is electrically connected to the second pull-down control node PDCN2.

[0157] The gate of the sixteenth transistor M16 is electrically connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, and the second electrode of the sixteenth transistor M16 is electrically connected to the first low voltage terminal LVSS.

[0158] The gate of the seventeenth transistor M17 is electrically connected to the pull-up node PU, the first electrode of the seventeenth transistor M17 is electrically connected to the second pull-down node PD2, and the second electrode of the seventeenth transistor M17 is electrically connected to the first low voltage terminal LVSS.

[0159] The gate of the eighteenth transistor M18 is electrically connected to the first pull-down control node PDCN1, the first electrode of the eighteenth transistor M18 is electrically connected to the first control voltage terminal VDDO, and the second electrode of the eighteenth transistor M18 is electrically connected to the first pull-down node PD1.

[0160] The gate of the nineteenth transistor M19 is electrically connected to the second pull-down control node PDCN2, the first electrode of the nineteenth transistor M19 is electrically connected to the second control voltage terminal VDDE, and the second electrode of the nineteenth transistor M19 is electrically connected to the second pull-down node PD2.

[0161] The gate of the twentieth transistor M20 is electrically connected to the first input terminal I1, the first electrode of the twentieth transistor M20 is electrically connected to the first pull-down node PD1, and the second electrode of the twentieth transistor M20 is electrically connected to the first low voltage terminal LVSS.

[0162] The gate of the 21st transistor M21 is electrically connected to the first input terminal I1, the first electrode of the 21st transistor M21 is electrically connected to the second pull-down node PD2, and the second electrode of the 21st transistor M21 is electrically connected to the first low voltage terminal LVSS.

[0163] exist Figure 1 In at least one embodiment of the driving circuit shown, the first voltage terminal is a first low voltage terminal LVSS and the second voltage terminal is a second low voltage terminal VSS, but this is not a limitation.

[0164] exist Figure 1 In at least one embodiment of the driving circuit shown, the first input terminal I1 is electrically connected to the carry signal output terminal of the adjacent previous stage driving circuit, and the second input terminal I2 is electrically connected to the drive signal output terminal of the adjacent previous stage driving circuit. (Refer to...) Figure 1 That is, the carry signal output terminal OC and the drive signal output terminal GO. It should be noted that the "advance stage" mentioned here is not limited to the stage adjacent to the current stage GOA, but can also be the GO and OC terminals of GOAs that are several stages away from the current stage GOA. It mainly depends on the timing or cascading relationship of the specific GOA circuit, and is not limited here.

[0165] In at least one embodiment of this disclosure, the first electrode may be a source or a drain, and the second electrode may be a drain or a source.

[0166] In at least one embodiment of this disclosure, the channel lengths of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be set as a first length L1, the channel lengths of the tenth transistor M10 and the eleventh transistor M11 can be set as a third length L3, and the channel lengths of the twelfth transistor M12 and the thirteenth transistor M13 can be set as a fourth length L4. The first length L1, the third length L3, and the fourth length L4 can all be 7 μm, but are not limited thereto.

[0167] The channel length of the transistors in the driving circuit, excluding the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13, is set to 4.3 μm.

[0168] However, this is not the limit.

[0169] In related technologies, when conducting cutting experiments for verification, one can... Figure 1 The channel lengths of each transistor in the driving circuit are set to be the same. After cutting M1, the leakage current of PU is slightly reduced. After cutting M9, the leakage current of PU is significantly improved. After cutting M5, the leakage current of PU is further improved. After cutting M4, the leakage current of PU is further improved.

[0170] After each transistor is cut, the width of the transistor's channel becomes smaller.

[0171] exist Figure 2In the diagram, the curves from top to bottom represent the potential of PU before cutting, the potential of PU after cutting M1, the potential of PU after cutting M9, the potential of PU after cutting M5, and the potential of PU after cutting M4.

[0172] In at least one embodiment of this disclosure, since changing the width of the channel of each transistor has a significant impact on the spatial layout, changing the length of the channel of each transistor will not significantly change the layout. Therefore, in at least one embodiment of this disclosure, the length of the channel of some transistors is changed to facilitate the layout.

[0173] Figure 3 yes Figure 1 A schematic diagram of the layout of the fifth transistor M5, the sixth transistor M6, the sixteenth transistor M16, and the seventeenth transistor M17.

[0174] exist Figure 3 In the middle, a gate metal layer, an active layer and a source / drain metal layer are sequentially disposed from bottom to top. The gate metal layer includes the gate of each transistor, the active layer includes the channel of each transistor, and the source / drain metal layer includes the first electrode and the second electrode of each transistor. The gate metal layer, the active layer and the source / drain metal layer are sequentially stacked on the substrate.

[0175] Figure 4 yes Figure 3 Layout diagram of the gate metal layer in the middle. Figure 5 yes Figure 3 Layout diagram of the active layer in the middle. Figure 6 yes Figure 3 A schematic diagram of the source and drain metal layers.

[0176] exist Figure 4 In the diagram, the gate labeled G5 is the gate of M5, the gate labeled G6 is the gate of M6, the gate labeled G16 is the gate of M16, and the gate labeled G17 is the gate of M17.

[0177] exist Figure 5 In the diagram, channel number 50 is M5, channel number 60 is M6, channel number 160 is M16, and channel number 170 is M17.

[0178] The length of channel 50 of M5 and the length of channel 60 of M6 are the first length L1, and L1 is 7um;

[0179] The length of channel 160 of M16 and the length of channel 170 of M17 are the second length L2, which is 4.3um.

[0180] In at least one embodiment of this disclosure, the length of the channel of each transistor is the linewidth of the orthogonal projection of the channel onto the substrate, and the width of the channel is the length of the orthogonal projection of the channel onto the substrate.

[0181] like Figure 5 As shown, the length L05 of the channel 50 of M5 is the linewidth of the orthographic projection of the channel 50 onto the substrate.

[0182] The length L06 of the channel 60 of M6 is the linewidth of the orthographic projection of the channel 60 onto the substrate.

[0183] The length L16 of the channel 160 of M16 is the linewidth of the orthographic projection of the channel 160 onto the substrate.

[0184] The length L17 of the channel 170 of M17 is the linewidth of the orthographic projection of the channel 170 onto the substrate.

[0185] Figure 7 This is a public announcement Figure 1 A schematic diagram of the active layer of each transistor in at least one embodiment of the driving circuit shown.

[0186] exist Figure 7 In the diagram, channel number 10 is M1, channel number 20 is M2, channel number 30 is M3, channel number 40 is M4, channel number 50 is M5, channel number 60 is M6, channel number 70 is M8, channel number 80 is M8, channel number 90 is M9, channel number 100 is M10, and channel number 110 is M11. The channel numbered 120 is M12, 130 is M13, 140 is M14, 150 is M15, 160 is M16, 17 is M17, 180 is M18, 190 is M19, 200 is M4, and 210 is M21.

[0187] Figure 8 This is a public announcement Figure 1 A schematic diagram of the gates of each transistor in at least one embodiment of the driving circuit shown, the gates being contained in a gate metal layer.

[0188] exist Figure 8In the diagram, the gate labeled G1 is the gate of M1, G2 is the gate of M2, G3 is the gate of M3, G4 is the gate of M4, G5 is the gate of M5, G6 is the gate of M6, G7 is the gate of M7, G8 is the gate of M8, G9 is the gate of M9, G10 is the gate of M10, and G11 is the gate of M11. The gate labeled G12 is the gate of M12, the gate labeled G13 is the gate of M13, the gate labeled G14 is the gate of M14, the gate labeled G15 is the gate of M15, the gate labeled G16 is the gate of M16, the gate labeled G17 is the gate of M17, the gate labeled G18 is the gate of M18, the gate labeled G19 is the gate of M19, the gate labeled G20 is the gate of M20, and the gate labeled G21 is the gate of M21.

[0189] like Figure 9 As shown, the length L01 of the channel 10 of M1 is the first length L1;

[0190] The length L01 of the channel 10 of M1 is the linewidth of the orthographic projection of the channel 10 onto the substrate.

[0191] like Figure 10 As shown, the length L02 of the channel 20 of M2 is the first length L1;

[0192] The length L02 of the channel 20 of M2 is the linewidth of the orthographic projection of the channel 20 onto the substrate.

[0193] like Figure 11 As shown, the length L03 of the channel 30 of M3 is the first length L1;

[0194] The length L03 of the channel 30 of M3 is the linewidth of the orthographic projection of the channel 30 onto the substrate.

[0195] like Figure 12 As shown, the length L04 of the channel 40 of M4 is the first length L1;

[0196] The length L04 of the channel 40 of M4 is the linewidth of the orthographic projection of the channel 40 onto the substrate.

[0197] like Figure 12 As shown, the channel 40 of M4 includes two channel portions, and the linewidth of the orthographic projection of each channel portion on the substrate is L04.

[0198] like Figure 13 As shown, the length L05 of the channel 50 of M5 is the first length L1;

[0199] The length L05 of the channel 50 of M5 is the linewidth of the orthographic projection of the channel 50 onto the substrate.

[0200] like Figure 14 As shown, the length L06 of the channel 60 of M6 is the first length L1;

[0201] The length L06 of the channel 60 of M6 is the linewidth of the orthographic projection of the channel 60 onto the substrate.

[0202] exist Figure 7 In at least one of the embodiments shown, the first length L1 can be 7 μm, but is not limited thereto.

[0203] like Figure 15 As shown, the length L10 of the channel 100 of M10 is the third length L3.

[0204] like Figure 16 As shown, the length L11 of the channel 110 of M11 is the third length L3.

[0205] like Figure 17 As shown, the length L12 of the channel 120 of M12 is the fourth length L4.

[0206] like Figure 18 As shown, the length L13 of the channel 130 of M13 is the fourth length L4.

[0207] exist Figure 7 In at least one embodiment shown, the third length L3 can be 7 μm and the fourth length L4 can be 7 μm, but are not limited thereto.

[0208] like Figure 19 As shown, the length L07 of the channel 70 of M7 is the second length L2.

[0209] like Figure 19 As shown, the channel 70 of M7 includes five channel portions, and the linewidth of the orthographic projection of each channel portion on the substrate is L07.

[0210] like Figure 20 As shown, the length L08 of the channel 80 of M8 is the second length L2.

[0211] like Figure 21 As shown, the length L09 of the channel 90 of M9 is the second length L2.

[0212] exist Figure 7 In at least one embodiment shown, the second length L2 can be 4.3 μm, but is not limited thereto.

[0213] exist Figure 7In at least one embodiment shown, the lengths of the channels M14, M15, M16, M17, M18, M19, M20, and M21 can all be 4.3 μm, but are not limited thereto.

[0214] In at least one embodiment of this disclosure, the aspect ratio of the first transistor is B1, the aspect ratio of the ninth transistor is A1, the aspect ratio of the fourth transistor is B2, the aspect ratios of the second transistor and the third transistor are both B3, and the aspect ratio of the seventh transistor is A2.

[0215] The aspect ratio of the tenth transistor and the eleventh transistor is both B4; the aspect ratio of the twelfth transistor and the thirteenth transistor is both B5.

[0216] B1 / A1 is greater than or equal to 0.1 and less than or equal to 0.8; for example, B1 / A1 can be 0.1, 0.13, 0.15, 0.18, 0.22, 0.25, 0.27, 0.3, 0.35, 0.4, 0.45, 0.5, 0.53, 0.58, 0.6, 0.68, 0.75 or 0.8;

[0217] B2 / A1 is greater than or equal to 0.005 and less than or equal to 0.5. For example, B2 / A1 can be 0.005, 0.008, 0.010, 0.015, 0.020, 0.025, 0.026, 0.030, 0.040, 0.050, 0.1, 0.15, 0.2, 0.3, 0.4 or 0.5.

[0218] B3 / A1 is greater than or equal to 0.01 and less than or equal to 0.5. For example, B3 / A1 can be 0.005, 0.008, 0.010, 0.015, 0.020, 0.025, 0.026, 0.030, 0.040, 0.050, 0.1, 0.15, 0.2, 0.3, 0.4 or 0.5.

[0219] B4 / A1 is greater than or equal to 0.04 and less than or equal to 0.4; for example, B4 / A1 can be 0.04, 0.06, 0.08, 0.1, 0.15, 0.2, 0.23, 0.26, 0.3, 0.36 or 0.4;

[0220] B5 / A1 is greater than or equal to 0.01 and less than or equal to 0.3; for example, B5 / A1 can be 0.01, 0.02, 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.26 or 0.3;

[0221] B1 / A2 is greater than or equal to 0.02 and less than or equal to 0.08; for example, B1 / A2 can be 0.02, 0.03, 0.05, 0.06 or 0.08.

[0222] B2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06. For example, B2 / A2 can be 0.01, 0.02, 0.03, 0.05 or 0.06.

[0223] B3 / A2 is greater than or equal to 0.015 and less than or equal to 0.05. For example, B3 / A2 can be 0.015, 0.02, 0.03, 0.04 or 0.05.

[0224] B4 / A2 is greater than or equal to 0.004 and less than or equal to 0.048; for example, B4 / A2 can be 0.004, 0.006, 0.008, 0.01, 0.016, 0.02, 0.03, 0.04 or 0.048;

[0225] B5 / A2 is greater than or equal to 0.001 and less than or equal to 0.045; for example, B5 / A2 can be 0.001, 0.002, 0.005, 0.007, 0.009, 0.013, 0.017, 0.019, 0.024, 0.03, 0.036, 0.04, or 0.045.

[0226] However, this is not the limit.

[0227] In at least one embodiment of this disclosure, the aspect ratio of the fifth transistor and the aspect ratio of the sixth transistor are C1, the aspect ratio of the sixteenth transistor is C2, the aspect ratio of the fourteenth transistor and the aspect ratio of the fifteenth transistor are both C3, and the aspect ratio of the eighteenth transistor and the aspect ratio of the nineteenth transistor are both C4.

[0228] C1 / A1 is greater than or equal to 0.03 and less than or equal to 0.09. For example, C1 / A1 can be 0.03, 0.04, 0.05, 0.06, 0.08 or 0.09.

[0229] C2 / A1 is greater than or equal to 0.08 and less than or equal to 0.6; for example, C2 / A1 can be 0.08, 0.1, 0.12, 0.14, 0.16, 0.2, 0.26, 0.32, 0.4, 0.45, 0.52 or 0.6;

[0230] C3 / A1 is greater than or equal to 0.005 and less than or equal to 0.046; for example, C3 / A1 can be 0.005, 0.01, 0.015, 0.02, 0.022, 0.024, 0.03, 0.04 or 0.046;

[0231] C4 / A1 is greater than or equal to 0.03 and less than or equal to 0.09; for example, C4 / A1 can be 0.03, 0.04, 0.05, 0.06, 0.07, 0.08 or 0.09.

[0232] C1 / A2 is greater than or equal to 0.005 and less than or equal to 0.02; for example, C1 / A1 can be 0.005, 0.006, 0.008, 0.01, 0.015, 0.018 or 0.02;

[0233] C2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06; for example, C2 / A1 can be 0.01, 0.02, 0.03, 0.04, 0.05 or 0.06;

[0234] C3 / A2 is greater than or equal to 0.01 and less than or equal to 0.05; for example, C3 / A1 can be 0.01, 0.02, 0.03, 0.04 or 0.05;

[0235] C4 / A2 is greater than or equal to 0.003 and less than or equal to 0.04; for example, C4 / A1 can be 0.003, 0.006, 0.008, 0.01, 0.016, 0.02, 0.025, 0.03 or 0.04;

[0236] However, this is not the limit.

[0237] By setting the aspect ratio as described above, a high charging rate can be guaranteed for the drive circuit without the need for a transistor to reset the drive signal, and there will be no related defects such as leakage at the pull-up node.

[0238] In at least one embodiment of this disclosure, the width of the channel of M9 can be greater than or equal to 1800 μm and less than or equal to 2400 μm, for example, it can be 2100 μm;

[0239] The width of the M1 channel can be greater than or equal to 700um and less than or equal to 1200um, for example, it can be 900um;

[0240] The width of the M7 channel can be greater than or equal to 17,500 μm and less than or equal to 20,000 μm, for example, it can be 18,500 μm;

[0241] The width of the channel for M18 and the width of the channel for M19 can be greater than or equal to 140um and less than or equal to 180um, for example, it can be 160um;

[0242] The width of the channel for M16 and M17 can be greater than or equal to 700um and less than or equal to 900um, for example, it can be 800um;

[0243] The width of the M4 channel can be greater than or equal to 400um and less than or equal to 600um, for example, it can be 500um;

[0244] The width of the channel for M5 and the width of the channel for M6 can be greater than or equal to 180um and less than or equal to 260um, for example, it can be 225um;

[0245] The width of the channel for M14 and the width of the channel for M15 can be greater than or equal to 25um and less than or equal to 45um, for example, it can be 35um;

[0246] The width of the channel for M2 and the width of the channel for M3 are greater than or equal to 600um and less than or equal to 800um, for example, 700um;

[0247] The width of the channel for M10 and the width of the channel for M11 can be greater than or equal to 1200um and less than or equal to 1600um, for example, it can be 1400um;

[0248] The width of the channel for M12 and the width of the channel for M13 can be greater than or equal to 500um and less than or equal to 700um, for example, it can be 600um;

[0249] The width of the M8 channel can be greater than or equal to 1750um and less than or equal to 2000um, for example, it can be 1900um;

[0250] The width of the channel for M20 and the width of the channel for M21 can be greater than or equal to 500um and less than or equal to 700um, for example, it can be 600um;

[0251] However, this is not the limit.

[0252] The display device described in this disclosure includes the display substrate described above.

[0253] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0254] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes a substrate and a driving circuit disposed on the substrate; the driving circuit includes a plurality of noise reduction transistors and a plurality of transistors for driving; the noise reduction transistors are electrically connected to a pull-up node. The channel length of at least a portion of the transistors in the noise reduction transistor is a first length L1; The channel length of at least a portion of the plurality of transistors used for driving is a second length L2; The first length L1 is not equal to the second length L2; The driving circuit includes a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the pull-up reset terminal, the first electrode of the first transistor is electrically connected to the pull-up node, and the second electrode of the first transistor is electrically connected to the first voltage terminal. The control electrode of the second transistor is electrically connected to the first pull-down node, the first electrode of the second transistor is electrically connected to the pull-up node, and the second electrode of the second transistor is electrically connected to the first voltage terminal. The control electrode of the third transistor is electrically connected to the second pull-down node, the first electrode of the third transistor is electrically connected to the pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal. The driving circuit further includes a fourth transistor; the control terminal of the fourth transistor is electrically connected to the starting voltage terminal, the first terminal of the fourth transistor is electrically connected to the pull-up node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal. The driving circuit also includes a seventh transistor and a ninth transistor; The control electrode of the seventh transistor is electrically connected to the pull-up node, the first electrode of the seventh transistor is electrically connected to the clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the drive signal output terminal. The control electrode of the ninth transistor is electrically connected to the first input terminal, the first electrode of the ninth transistor is electrically connected to the second input terminal, and the second electrode of the ninth transistor is electrically connected to the pull-up node. The driving circuit also includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The control electrode of the tenth transistor is electrically connected to the first pull-down node, the first electrode of the tenth transistor is electrically connected to the drive signal output terminal, and the second electrode of the tenth transistor is electrically connected to the second voltage terminal. The control electrode of the eleventh transistor is electrically connected to the second pull-down node, the first electrode of the eleventh transistor is electrically connected to the drive signal output terminal, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal. The control electrode of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the carry signal output terminal, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal. The control electrode of the thirteenth transistor is electrically connected to the second pull-down node, the first electrode of the thirteenth transistor is electrically connected to the carry signal output terminal, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal. The aspect ratio of the first transistor is B1, the aspect ratio of the ninth transistor is A1, the aspect ratio of the fourth transistor is B2, the aspect ratios of the second transistor and the third transistor are both B3, and the aspect ratio of the seventh transistor is A2. The aspect ratio of the tenth transistor and the eleventh transistor is both B4; the aspect ratio of the twelfth transistor and the thirteenth transistor is both B5. B1 / A1 is greater than or equal to 0.1 and less than or equal to 0.8; B2 / A1 is greater than or equal to 0.005 and less than or equal to 0.5; B3 / A1 is greater than or equal to 0.01 and less than or equal to 0.5; B4 / A1 is greater than or equal to 0.04 and less than or equal to 0.4; B5 / A1 is greater than or equal to 0.01 and less than or equal to 0.

3. B1 / A2 is greater than or equal to 0.02 and less than or equal to 0.08; B2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06; B3 / A2 is greater than or equal to 0.015 and less than or equal to 0.05; B4 / A2 is greater than or equal to 0.004 and less than or equal to 0.048; B5 / A2 is greater than or equal to 0.001 and less than or equal to 0.

045.

2. The display substrate as described in claim 1, characterized in that, The first length L1 is greater than the second length L2.

3. The display substrate as described in claim 1, characterized in that, The first length L1 is greater than or equal to 5.5 μm and less than or equal to 9 μm, and the second length L2 is greater than or equal to 2 μm and less than or equal to 5.0 μm; the ratio between the first length L1 and the second length L2 is greater than or equal to 1.1 and less than or equal to 4.

5.

4. The display substrate as described in claim 1, characterized in that, The driving circuit also includes a transistor for noise reduction at the carry signal output terminal, and a transistor for noise reduction at the driving signal output terminal. The length of the channel of the transistor used for noise reduction at the carry signal output terminal is a third length L3; The length of the channel of the transistor used for noise reduction at the drive signal output terminal is the fourth length L4; The third length L3 is not equal to the second length L2, and the fourth length L4 is not equal to the second length L2.

5. The display substrate as described in claim 4, characterized in that, The third length L3 is greater than the second length L2, and the fourth length is greater than the second length L2.

6. The display substrate as described in claim 5, characterized in that, The third length L3 is greater than or equal to 5.5 μm and less than or equal to 9 μm, the fourth length L4 is greater than or equal to 5.5 μm and less than or equal to 9 μm, and the second length L2 is greater than or equal to 2 μm and less than or equal to 5.0 μm; the ratio of the third length L3 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.5, and the ratio of the fourth length L4 to the second length L2 is greater than or equal to 1.1 and less than or equal to 4.

5.

7. The display substrate according to any one of claims 1 to 6, characterized in that, The driving transistors include a transistor for driving the pull-up node, a transistor for driving the carry signal output terminal, and a transistor for driving the drive signal output terminal.

8. The display substrate according to any one of claims 1 to 6, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are the noise reduction transistors.

9. The display substrate as described in claim 8, characterized in that, The driving circuit includes a fifth transistor and a sixth transistor; the fifth transistor and the sixth transistor are the noise reduction transistors; The control electrode of the fifth transistor is electrically connected to the pull-up node, the first electrode of the fifth transistor is electrically connected to the first pull-down control node, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal. The control electrode of the sixth transistor is electrically connected to the pull-up node, the first electrode of the sixth transistor is electrically connected to the second pull-down control node, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

10. The display substrate as claimed in claim 9, characterized in that, At least one of the following lengths is a first length L1: the channel length of the first transistor, the channel length of the second transistor, the channel length of the third transistor, the channel length of the fourth transistor, the channel length of the fifth transistor, and the channel length of the sixth transistor.

11. The display substrate as claimed in claim 9, characterized in that, The driving circuit further includes an eighth transistor; the seventh transistor, the eighth transistor, and the ninth transistor are driving transistors used for driving. The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the carry signal output terminal.

12. The display substrate as claimed in claim 11, characterized in that, At least one of the channel lengths of the seventh transistor, the eighth transistor, and the ninth transistor is a second length L2.

13. The display substrate as claimed in claim 11, characterized in that, The tenth and eleventh transistors are transistors used for noise reduction at the drive signal output terminal, and the twelfth and thirteenth transistors are transistors used for noise reduction at the carry signal output terminal. The channel lengths of the tenth transistor and the eleventh transistor are a third length L3, and the channel lengths of the twelfth transistor and the thirteenth transistor are a fourth length L4.

14. The display substrate as claimed in claim 13, characterized in that, The driving circuit also includes the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, and a capacitor; The control electrode and the first electrode of the fourteenth transistor are electrically connected to the first control voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the first pull-down control node; The control electrode and the first electrode of the fifteenth transistor are electrically connected to the second control voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second pull-down control node; The control electrode of the sixteenth transistor is electrically connected to the pull-up node, the first electrode of the sixteenth transistor is electrically connected to the first pull-down node, and the second electrode of the sixteenth transistor is electrically connected to the first voltage terminal. The control electrode of the seventeenth transistor is electrically connected to the pull-up node, the first electrode of the seventeenth transistor is electrically connected to the second pull-down node, and the second electrode of the seventeenth transistor is electrically connected to the first voltage terminal. The control electrode of the eighteenth transistor is electrically connected to the first pull-down control node, the first electrode of the eighteenth transistor is electrically connected to the first control voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the first pull-down node. The control electrode of the nineteenth transistor is electrically connected to the second pull-down control node, the first electrode of the nineteenth transistor is electrically connected to the second control voltage terminal, and the second electrode of the nineteenth transistor is electrically connected to the second pull-down node. The control electrode of the twentieth transistor is electrically connected to the first input terminal, the first electrode of the twentieth transistor is electrically connected to the first pull-down node, and the second electrode of the twentieth transistor is electrically connected to the first voltage terminal. The control electrode of the 21st transistor is electrically connected to the first input terminal, the first electrode of the 21st transistor is electrically connected to the second pull-down node, and the second electrode of the 21st transistor is electrically connected to the first voltage terminal.

15. The display substrate as claimed in claim 14, characterized in that, The aspect ratio of the fifth transistor and the aspect ratio of the sixth transistor are C1, the aspect ratio of the sixteenth transistor is C2, the aspect ratio of the fourteenth transistor and the aspect ratio of the fifteenth transistor are both C3, and the aspect ratio of the eighteenth transistor and the nineteenth transistor are both C4. C1 / A1 is greater than or equal to 0.03 and less than or equal to 0.09, C2 / A1 is greater than or equal to 0.08 and less than or equal to 0.6, C3 / A1 is greater than or equal to 0.005 and less than or equal to 0.046, and C4 / A1 is greater than or equal to 0.03 and less than or equal to 0.

09. C1 / A2 is greater than or equal to 0.005 and less than or equal to 0.02, C2 / A2 is greater than or equal to 0.01 and less than or equal to 0.06, C3 / A2 is greater than or equal to 0.01 and less than or equal to 0.05, and C4 / A2 is greater than or equal to 0.003 and less than or equal to 0.

04.

16. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 15.

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