Display panel, driving method thereof, and display device

Abstract

A display panel and its driving method and display device are disclosed. The display panel includes: a plurality of pixel driving circuits (PIX) and a first gate driving circuit (1). The pixel driving circuit (PIX) includes: a driving circuit (33) and a first switching unit (31). The driving circuit (33) is connected to a first node (N1), a second node (N2), and a third node (N3), and is used to input a driving current to the third node (N3) through the second node (N2) in response to a signal from the first node (N1). The first terminal of the first switching unit (31) is connected to the third node (N3), and the second terminal is connected to a sensing signal terminal (Sense), and is used to connect the third node (N3) and the sensing signal terminal (Sense) in response to a signal from its control terminal. The first gate driving circuit... The circuit (1) includes multiple first output terminals (O1), each corresponding to a pixel driving circuit (PIX). Each first output terminal (O1) is connected to the control terminal of the first switching unit (31) in its corresponding pixel driving circuit (PIX). One driving cycle of the pixel driving circuit (PIX) includes a data writing phase (t1), multiple light-emitting phases (t2, t4, t6), and a black-insertion phase (t3, t5) between adjacent light-emitting phases (t2, t4, t6). The first output terminal (O1) is used to output valid level pulses during the data writing phase (t1) and black-insertion phases (t3, t5) of its corresponding pixel driving circuit (PIX). This display panel can improve the technical problem of motion blur in dynamic images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] In related technologies, the dynamic image switching process of the display panel may cause image ghosting, also known as dynamic image ghosting, which can easily lead to display panel flickering.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, comprising: a plurality of pixel driving circuits and a first gate driving circuit. The pixel driving circuit includes: a driving circuit and a first switching unit. The driving circuit is connected to a first node, a second node, and a third node, and is used to input a driving current to the third node through the second node in response to a signal from the first node. A first terminal of the first switching unit is connected to the third node, and a second terminal is connected to a sensing signal terminal, used to connect the third node and the sensing signal terminal in response to a signal from its control terminal. The first gate driving circuit includes a plurality of first output terminals, each corresponding to a pixel driving circuit, and connected to the control terminal of the first switching unit in its corresponding pixel driving circuit. A driving cycle of the pixel driving circuit includes a data writing phase, a plurality of light-emitting phases, and a black-insertion phase between adjacent light-emitting phases. The first output terminal is used to output valid level pulses during the data writing phase and the black-insertion phase of its corresponding pixel driving circuit.

[0005] In one exemplary embodiment of this disclosure, the driving circuit includes: a driving transistor, a first terminal of which is connected to the second node, a second terminal of which is connected to the third node, and a gate of which is connected to the first node; the first switching unit includes: a first transistor, a first terminal of which is connected to the third node, a second terminal of which is connected to the sensing signal terminal, and a gate of which is connected to a first gate driving signal terminal. The pixel driving circuit further includes: a second transistor and a capacitor, a first terminal of which is connected to the first node, a second terminal of which is connected to a data signal terminal, and a gate of which is connected to a second gate driving signal terminal; the capacitor is connected between the first node and the third node.

[0006] In one exemplary embodiment of this disclosure, the first gate driving circuit includes a plurality of cascaded first shift register units. Each first shift register unit includes: a first input circuit, a second input circuit, a first output circuit, a first pull-down circuit, and a second pull-down circuit. The first input circuit is connected to a first power supply terminal, a first clock signal terminal, a fourth node, a fifth node, and a second clock signal terminal. It is used to transmit the signal from the first power supply terminal to the fourth node in response to the signal from the first clock signal terminal, and to transmit the signal from the second clock signal terminal to the fifth node in response to the signal from the fourth node. The second input circuit is connected to the first power supply terminal, the first clock signal terminal, a first signal input terminal, a second power supply terminal, and a sixth node. It is used to transmit the signal from the first power supply terminal to the sixth node in response to the signal from the first clock signal terminal, and to transmit the signal from the second power supply terminal to the sixth node in response to the signals from the first signal input terminal and the first clock signal terminal. The sixth node is described above; a first output circuit is connected to the sixth node, the seventh node, the first power supply terminal, the first signal output terminal, and the second power supply terminal, and is used to transmit the signal of the second power supply terminal to the first signal output terminal in response to the signal of the sixth node, and to transmit the signal of the first power supply terminal to the first signal output terminal in response to the signal of the seventh node, wherein the seventh node is connected to the fifth node; a first pull-down circuit is connected to the seventh node, the sixth node, the second power supply terminal, and the fourth node, and is used to transmit the signal of the second power supply terminal to the seventh node and the fourth node in response to the signal of the sixth node; a second pull-down circuit is connected to the fourth node, the sixth node, the second clock signal terminal, and the second power supply terminal, and is used to transmit the signal of the second power supply terminal to the sixth node in response to the signals of the fourth node and the second clock signal terminal; wherein the first signal output terminal of the first shift register unit forms the first output terminal of the first gate drive circuit.

[0007] In an exemplary embodiment of this disclosure, the first shift register unit further includes: an isolation circuit and a first reset circuit. The isolation circuit is connected to the fifth node, the seventh node, and the second clock signal terminal, and is used to respond to the signal of the second clock signal terminal to connect the fifth node and the seventh node. The first reset circuit is connected to the sixth node, a first power supply terminal, and a first reset signal terminal, and is used to respond to the signal of the first reset signal terminal to transmit the signal of the first power supply terminal to the sixth node.

[0008] In one exemplary embodiment of this disclosure, the first input circuit includes: a third transistor, a fourth transistor, and a first capacitor. The first terminal of the third transistor is connected to the first power supply terminal, the second terminal is connected to the fourth node, and the gate is connected to the first clock signal terminal. The first terminal of the fourth transistor is connected to the second clock signal terminal, the second terminal is connected to the fifth node, and the gate is connected to the fourth node. The first capacitor is connected to the fourth node. The second input circuit includes: a fifth transistor, a sixth transistor, and a seventh transistor. The first terminal of the fifth transistor is connected to the first power supply terminal, and the gate is connected to the first clock signal terminal. The first terminal of the sixth transistor is connected to the second terminal of the fifth transistor, the second terminal is connected to the sixth node, and the gate is connected to the first clock signal terminal. The first terminal of the seventh transistor is connected to the second power supply terminal, the second terminal is connected to the second terminal of the fifth transistor, and the gate is connected to the first signal input terminal.

[0009] In one exemplary embodiment of this disclosure, the first output circuit includes: an eighth transistor, a second capacitor, a ninth transistor, and a third capacitor. The first terminal of the eighth transistor is connected to the first power supply terminal, the second terminal is connected to the first signal output terminal, and the gate is connected to the seventh node. The second capacitor is connected to the seventh node. The first terminal of the ninth transistor is connected to the second power supply terminal, the second terminal is connected to the first signal output terminal, and the gate is connected to the sixth node. The third capacitor is connected to the sixth node.

[0010] In one exemplary embodiment of this disclosure, the first pull-down circuit includes a tenth transistor and an eleventh transistor. The first terminal of the tenth transistor is connected to the seventh node, the second terminal is connected to the second power supply terminal, and the gate is connected to the sixth node. The first terminal of the eleventh transistor is connected to the fourth node, the second terminal is connected to the second power supply terminal, and the gate is connected to the sixth node. The second pull-down circuit includes a twelfth transistor and a thirteenth transistor. The first terminal of the twelfth transistor is connected to the second power supply terminal, and the gate is connected to the fourth node. The first terminal of the thirteenth transistor is connected to the second terminal of the twelfth transistor, the second terminal is connected to the sixth node, and the gate is connected to the second clock signal terminal.

[0011] In one exemplary embodiment of this disclosure, the isolation circuit includes a fourteenth transistor, the first terminal of which is connected to the fifth node, the second terminal of which is connected to the seventh node, and the gate of which is connected to the second clock signal terminal. The first reset circuit includes a fifteenth transistor, the first terminal of which is connected to the first power supply terminal, the second terminal of which is connected to the sixth node, and the gate of which is connected to the first reset signal terminal.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a second transistor, the first terminal of which is connected to the first node, and the second terminal of which is connected to a data signal terminal. The display panel further includes: a second gate driving circuit, the second gate driving circuit including a plurality of second output terminals, each second output terminal corresponding to one of the pixel driving circuits, and the second output terminal being connected to the gate of the second transistor in the corresponding pixel driving circuit; the second output terminal is used to output a valid level pulse during the data writing phase of the corresponding pixel driving circuit.

[0013] In an exemplary embodiment of this disclosure, a frame of the display panel includes a blank period. During the blank period of a frame, at least a portion of the pixel driving circuit is in a sensing phase. The sensing phase of the pixel driving circuit includes a sensing signal writing phase, a charging phase, a sampling phase, and a data signal write-back phase. The second output terminal corresponding to the pixel driving circuit in the sensing phase is further used to output valid level pulses in the sensing signal writing phase and the data signal write-back phase of the pixel driving circuit, respectively. The first output terminal corresponding to the pixel driving circuit in the sensing phase is further used to output valid level pulses in the sensing phase of the pixel driving circuit.

[0014] In one exemplary embodiment of this disclosure, the second gate driving circuit includes a plurality of cascaded second shift register units. Each second shift register unit includes a second output circuit and a first control circuit. The second output circuit is connected to an eighth node, a second signal output terminal, and a third clock signal terminal, and is used to transmit the signal from the third clock signal terminal to the second signal output terminal in response to a signal from the eighth node. The second signal output terminal of the second shift register unit is used to form the second output terminal of the second gate driving circuit. The first control circuit is connected to the eighth node, a fourth clock signal terminal, the second signal output terminal, a tenth node, and an eleventh node. A first control signal terminal is used to transmit the signal from the second signal output terminal to the tenth node in response to a signal from the first control signal terminal, to transmit the signal from the fourth clock signal terminal to the eleventh node in response to a signal from the tenth node, and to transmit the signal from the eleventh node to the eighth node in response to a signal from the fourth clock signal terminal. The first shift register unit further includes a second control circuit, which is connected to the eleventh node, the fourth clock signal terminal, and the fourth node in the corresponding second shift register unit, and is used to transmit the signal of the eleventh node to the fourth node in response to the signal of the fourth clock signal terminal; wherein, the second shift register unit and the first shift register unit corresponding to the same pixel driving circuit correspond to each other, and the second control circuit in the corresponding first shift register unit corresponds to each other.

[0015] In one exemplary embodiment of this disclosure, the second shift register unit further includes: a third input circuit, a third pull-down circuit, a fourth pull-down circuit, a second reset circuit, and a third reset circuit. The third input circuit is connected to a third power supply terminal, an eighth node, and a second signal input terminal, and is used to transmit the signal from the third power supply terminal to the eighth node in response to the signal from the second signal input terminal. The third reset circuit is connected to the eighth node, the fourth power supply terminal, and a third reset signal terminal, and is used to transmit the signal from the fourth power supply terminal to the eighth node in response to the signal from the third reset signal terminal. The third pull-down circuit is connected to the third power supply terminal, the eighth node, the fourth power supply terminal, a ninth node, and a second signal output terminal, and is used to transmit the signal from the third power supply terminal to the ninth node in response to the signal from the third power supply terminal, and to transmit the signal from the fourth power supply terminal to the second signal output terminal and the eighth node in response to the signal from the ninth node. The fourth pull-down circuit is connected to the eighth node, the fourth power supply terminal, and the ninth node, and is used to transmit the signal from the fourth power supply terminal to the ninth node in response to the signal from the eighth node. The second reset circuit is connected to the eighth node, the fourth power supply terminal, and the second reset signal terminal, and is used to transmit the signal from the fourth power supply terminal to the eighth node in response to the information from the second reset signal terminal.

[0016] In one exemplary embodiment of this disclosure, the third input circuit includes a sixteenth transistor, the first terminal of which is connected to the third power supply terminal, the second terminal of which is connected to the eighth node, and the gate of which is connected to the second signal input terminal. The third reset circuit includes a seventeenth transistor, the first terminal of which is connected to the fourth power supply terminal, the second terminal of which is connected to the eighth node, and the gate of which is connected to the third reset signal terminal. The second output circuit includes an eighteenth transistor and a fourth capacitor, the first terminal of which is connected to the third clock signal terminal, the second terminal of which is connected to the second signal output terminal, and the gate of which is connected to the eighth node; the fourth capacitor is connected to the eighth node. The third pull-down circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-seventh transistor, the first terminal of which is connected to the third power supply terminal, the second terminal of which is connected to the ninth node, and the gate of which is connected to the third power supply terminal; the first terminal of which is connected to the eighth node, the second terminal of which is connected to the fourth power supply terminal, and the gate of which is connected to the ninth node; the first terminal of which is connected to the fourth power supply terminal, the second terminal of which is connected to the second signal output terminal, and the gate of which is connected to the ninth node. The fourth pull-down circuit includes a twenty-first transistor, the first terminal of which is connected to the ninth node, the second terminal to the fourth power supply terminal, and the gate to the eighth node. The second reset circuit includes a twenty-second transistor, the first terminal of which is connected to the fourth power supply terminal, the second terminal to the eighth node, and the gate to the second reset signal terminal.

[0017] In one exemplary embodiment of this disclosure, the first control circuit includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a fifth capacitor. The first terminal of the twenty-third transistor is connected to the second signal output terminal, the second terminal is connected to the tenth node, and the gate is connected to the first control signal terminal. The first terminal of the twenty-fourth transistor is connected to the fourth clock signal terminal, the second terminal is connected to the eleventh node, and the gate is connected to the tenth node. The first terminal of the twenty-fifth transistor is connected to the eleventh node, the second terminal is connected to the eighth node, and the gate is connected to the fourth clock signal terminal. The fifth capacitor is connected to the tenth node.

[0018] In one exemplary embodiment of this disclosure, the second control circuit includes a twenty-sixth transistor, the first terminal of which is connected to the eleventh node, the second terminal of which is connected to the fourth node, and the gate of which is connected to the fourth clock signal terminal.

[0019] In one exemplary embodiment of this disclosure, the first power supply terminal and the third power supply terminal share the same power supply terminal, and the second power supply terminal and the fourth power supply terminal share the same power supply terminal.

[0020] In one exemplary embodiment of this disclosure, the display panel further includes: a first clock signal line and a second clock signal line, wherein the first clock signal line is connected to a first clock signal terminal in an odd-level first shift register unit and a second clock signal terminal in an even-level first shift register unit; and the second clock signal line is connected to a second clock signal terminal in an odd-level first shift register unit and a first clock signal terminal in an even-level first shift register unit.

[0021] In one exemplary embodiment of this disclosure, the display panel further includes: a fourth clock signal line and a reset signal line, wherein the fourth clock signal line is connected to the fourth clock signal terminal in the first shift register unit; and the reset signal line is connected to the first reset signal terminal in the first shift register unit and the second reset signal terminal in the second shift register unit.

[0022] According to one aspect of this disclosure, a display panel driving method is provided, wherein the method is used to drive the aforementioned display panel, the driving method comprising:

[0023] The first output terminal outputs valid level pulses during the data writing stage, black insertion stage, and sensing stage of the corresponding pixel driving circuit.

[0024] The second output terminal outputs valid level pulses during the data writing stage, sensing signal writing stage, and data signal write-back stage of the corresponding pixel driving circuit.

[0025] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 This is a schematic diagram of the pixel driving circuit in the display panel of this disclosure;

[0029] Figure 2 for Figure 1 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0030] Figure 3This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0031] Figure 4 This is a schematic diagram of the structure of the first gate driving circuit in an exemplary embodiment of the display panel disclosed herein;

[0032] Figure 5 This is a schematic diagram of the structure of the first shift register unit in an exemplary embodiment of the display panel of this disclosure;

[0033] Figure 6 for Figure 5 The timing diagram of each node in a driving method for the first shift register unit is shown below;

[0034] Figure 7 This is a schematic diagram of the structure of the second gate driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0035] Figure 8 This is a schematic diagram of an exemplary embodiment of the second shift register unit of this disclosure;

[0036] Figure 9 for Figure 8 The timing diagram of each node in a driving method for the second shift register unit is shown below;

[0037] Figure 10 for Figure 7 The timing diagram of each signal line in the second gate drive circuit is shown below.

[0038] Figure 11 for Figure 4 The timing diagram of each signal line in a driving method of the first gate driving circuit is shown. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0040] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0041] like Figure 1The diagram shows a schematic of the pixel driving circuit in the display panel of this disclosure. The pixel driving circuit may include: a driving circuit 33, a first switching unit 31, a second switching unit 32, and a capacitor C. The driving circuit 33 is connected to a first node N1, a second node N2, and a third node N3, and is used to input a driving current to the third node N3 through the second node N2 in response to a signal from the first node N1. The first switching unit 31 has a first terminal connected to the third node N3, a second terminal connected to a sensing signal terminal Sense, and a control terminal connected to a first gate driving signal terminal G1, and is used to connect the third node N3 and the sensing signal terminal Sense in response to a signal from its control terminal. The second switching unit 32 has a first terminal connected to the first node N1, a second terminal connected to a data signal terminal Da, and a control terminal connected to a second gate driving signal terminal G2, and is used to connect the first node N1 and the data signal terminal Da under the action of a signal from its control terminal. The capacitor is connected between the first node N1 and the third node N3. In this embodiment, the second node N2 can be connected to the fifth power supply terminal VDD, the third node N3 can be connected to the first electrode of an OLED light-emitting unit, and the second electrode of the OLED can be connected to the sixth power supply terminal VSS. The fifth power supply terminal VDD can be a high-level signal terminal, and the sixth power supply terminal VSS can be a low-level signal terminal. In this exemplary embodiment, as... Figure 1 As shown, the driving circuit 33 may include: a driving transistor DT, the first terminal of which is connected to the second node N2, the second terminal of which is connected to the third node N3, and the gate of which is connected to the first node N1; the first switching unit 31 may include: a first transistor T1, the first terminal of which is connected to the third node N3, the second terminal of which is connected to the sensing signal terminal Sense, and the gate of which is connected to the first gate driving signal terminal G1. The second switching unit 32 may include: a second transistor T2, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the data signal terminal Da, and the gate of which is connected to the second gate driving signal terminal G2. The first transistor T1, the second transistor T2, and the driving transistor DT may all be N-type transistors. In addition, the sensing signal terminal Sense may be connected to the reference voltage generation circuit 34 through a switch K2, and the sensing signal terminal Sense may also be connected to an analog-to-digital converter 36 through a switch K1 and a sample-and-hold circuit 35.

[0042] like Figure 2 As shown, Figure 1The diagram shows the timing diagrams of each node in a driving method for a pixel driving circuit. Da is the timing diagram for the data signal terminal, Sense is the timing diagram for the sensing signal terminal, G1 is the timing diagram for the first gate driving signal terminal, G2 is the timing diagram for the second gate driving signal terminal, N1 is the timing diagram for the first node, and N3 is the timing diagram for the third node. One driving cycle of the pixel driving circuit may include a data writing phase t1, multiple light-emitting phases t2, t4, t6, and black-insertion phases t3 and t5 located between adjacent light-emitting phases. In the data writing phase t1, the first gate driving signal terminal G1 and the second gate driving signal terminal G2 output valid levels, the first transistor T1 and the second transistor T2 are turned on, the data signal terminal Da writes a data signal to the first node N1 through the second transistor T2, and the sensing signal terminal Sense writes a reset signal to the third node N3. During the light-emitting phases t2, t4, and t6, the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output invalid levels, the first transistor T1 and the second transistor T2 are turned off, and the drive transistor DT provides drive current to the light-emitting unit OLED under the action of the data signal stored in the first node N1. During the black-filling phases t3 and t5, the first gate drive signal terminal G1 outputs an active level, the second gate drive signal terminal G2 outputs an invalid level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the sensing signal terminal Sense writes a black screen signal to the third node N3.

[0043] It should be noted that one driving cycle of the pixel driving circuit is from the start of the current frame data writing phase to the start of the next frame data writing phase. The effective level is the potential that enables the target circuit to operate normally. For example, when the first transistor T1 is an N-type transistor, the effective level output by the first gate driving signal terminal G1 is high. Correspondingly, the invalid level is logically opposite to the effective level. Furthermore, the black screen signal and reset signal output by the sensing signal terminal Sense can be provided by the reference voltage generation circuit 34, and the potentials of the black screen signal and reset signal can be the same or different.

[0044] like Figure 3 The diagram shown illustrates a structural embodiment of the display panel disclosed herein. The display panel may include multiple pixel driving circuits (PIX) and a first gate driving circuit 1. The structure of the pixel driving circuits (PIX) can be as follows: Figure 1 As shown. The first gate driving circuit 1 may include a plurality of first output terminals O1, and the first output terminals O1 are configured corresponding to the pixel driving circuit, such as... Figure 3As shown, the first output terminal O1 can be configured to correspond to a row of pixel driving circuits (PIX). The first output terminal O1 is connected to the control terminal of the first switching unit 31 in the corresponding pixel driving circuit (PIX). It should be understood that the first output terminal O1 can also be configured to correspond to multiple rows of pixel driving circuits. Furthermore, the first output terminal O1 can also be configured to correspond to pixel driving circuits in other ways. In other exemplary embodiments, the pixel driving circuit can also have other structures.

[0045] In this exemplary embodiment, on one hand, the first output terminal O1 can be used to input valid level pulses to the first gate drive signal terminal G1 of the pixel drive circuit during the data writing stage and the black insertion stage of the corresponding pixel drive circuit, so that the pixel drive circuit can realize the aforementioned black insertion drive. This black insertion drive method can solve the technical problem of image ghosting during dynamic screen switching of the display panel. On the other hand, the structure of the pixel drive circuit in the display panel is simple, and the pixel drive circuit occupies a small space, thereby facilitating the design of high-resolution display panels.

[0046] In this exemplary embodiment, as Figure 4 The diagram shown is a schematic representation of the structure of a first gate driving circuit in an exemplary embodiment of the display panel of this disclosure. The first gate driving circuit 1 may include multiple cascaded first shift register units GOA1. As shown... Figure 5The diagram shown is a schematic representation of the structure of the first shift register unit in an exemplary embodiment of the display panel of this disclosure. The first shift register unit GOA1 may include: a first input circuit 11, a second input circuit 12, a first output circuit 13, a first pull-down circuit 14, and a second pull-down circuit 15. The first input circuit 11 is connected to a first power supply terminal VGH1, a first clock signal terminal CLK1, a fourth node N4, a fifth node N5, and a second clock signal terminal CLK2. It is used to transmit the signal of the first power supply terminal VGH1 to the fourth node N4 in response to the signal of the first clock signal terminal CLK1, and to transmit the signal of the second clock signal terminal CLK2 to the fifth node N5 in response to the signal of the fourth node N4. The second input circuit 12 is connected to the first power supply terminal VGH1, the first clock signal terminal CLK1, a first signal input terminal IN1, a second power supply terminal VGL1, and a sixth node N6. It is used to transmit the signal of the first power supply terminal VGH1 to the sixth node N6 in response to the signal of the first clock signal terminal CLK1, and to transmit the signal of the second power supply terminal VGL1 to the sixth node N6 in response to the signals of the first signal input terminal IN1 and the first clock signal terminal CLK1. The first output circuit 13 is connected to the sixth node N6. 6. A seventh node N7, a first power supply terminal VGH1, a first signal output terminal OUT1, and a second power supply terminal VGL1 are used to transmit the signal of the second power supply terminal VGL1 to the first signal output terminal OUT1 in response to the signal of the sixth node N6, and to transmit the signal of the first power supply terminal VGH1 to the first signal output terminal OUT1 in response to the signal of the seventh node N7, wherein the seventh node N7 is connected to the fifth node N5; a first pull-down circuit 14 is connected to the seventh node N7, the sixth node N6, the second power supply terminal VGL1, and the fourth node N4, and is used to transmit the signal of the second power supply terminal VGL1 to the seventh node N7 and the fourth node N4 in response to the signal of the sixth node N6; a second pull-down circuit 15 is connected to the fourth node N4, the sixth node N6, the second clock signal terminal CLK2, and the second power supply terminal VGL1, and is used to transmit the signal of the second power supply terminal VGL1 to the sixth node N6 in response to the signals of the fourth node N4 and the second clock signal terminal CLK2; wherein the first signal output terminal OUT1 of the first shift register unit GOA1 forms the first output terminal O1 of the first gate drive circuit 1.

[0047] In this exemplary embodiment, the first power supply terminal VGH1 is an active level signal terminal, and the second power supply terminal VGL1 is an inactive level signal terminal. The driving method of the first shift register unit GOA1 may include a first stage, a second stage, a third stage, and a fourth stage. In the first stage, the first signal input terminal IN1 and the first clock signal terminal CLK1 output active levels, and the second clock signal terminal CLK2 outputs inactive levels. The first input circuit 11 transmits the active level signal of the first power supply terminal VGH1 to the fourth node N4, while the seventh node N7 and the first signal output terminal OUT1 maintain the inactive level of the previous stage. In the second stage, the first signal input terminal IN1 and the second clock signal terminal CLK2 output active levels, while the first clock signal terminal CLK1 outputs inactive levels. Under the action of the fourth node N4, the first input circuit 11 transmits the active level of the second clock signal terminal to the fifth node, the active level of the fifth node N5 to the seventh node, and the first output circuit, under the action of the seventh node N7, transmits the active level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1. Simultaneously, under the action of the fourth node N4 and the second clock signal terminal CLK2, the second pull-down circuit 15 transmits the invalid level signal of the second power supply terminal VGL1 to the sixth node N6. In the third stage, the first signal input terminal IN1 and the first clock signal terminal CLK1 output invalid levels, while the second clock signal terminal CLK2 outputs an active level. The fourth node N4 maintains the active level of the previous stage. Under the action of the fourth node N4, the first input circuit 11 transmits the active level of the second clock signal terminal CLK2 to the fifth node, the active level of the fifth node N5 to the seventh node, and the first output circuit, under the action of the seventh node N7, transmits the active level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1. In the fourth stage, the first signal input terminal IN1 and the second clock signal terminal CLK2 output invalid levels, while the first clock signal terminal CLK1 outputs an active level. The second input circuit 12 transmits the effective level signal of the first power supply terminal VGH1 to the sixth node N6 under the action of the first clock signal terminal CLK1. The first output circuit 13 transmits the invalid level of the second power supply terminal VGL1 to the first signal output terminal OUT1 under the action of the sixth node N6. At the same time, the first pull-down circuit 14 transmits the invalid level of the second power supply terminal VGL1 to the fourth node N4 and the seventh node N7 under the action of the sixth node N6.

[0048] In this exemplary embodiment, as Figure 5 As shown, the first shift register unit GOA1 may further include: an isolation circuit 17, which is connected to the fifth node N5, the seventh node N7, and the second clock signal terminal CLK2, and is used to respond to the signal of the second clock signal terminal CLK2 to connect the fifth node N5 and the seventh node N7. The isolation circuit 17 can reduce the leakage current of the seventh node N7.

[0049] In this exemplary embodiment, as Figure 5 As shown, the first input circuit 11 may include: a third transistor T3, a fourth transistor T4, and a first capacitor C1. The first terminal of the third transistor T3 is connected to the first power supply terminal VGH1, the second terminal is connected to the fourth node N4, and the gate is connected to the first clock signal terminal CLK1. The first terminal of the fourth transistor T4 is connected to the second clock signal terminal CLK2, the second terminal is connected to the fifth node N5, and the gate is connected to the fourth node N4. The first capacitor C1 is connected between the fourth node N4 and the fifth node N5. The second input circuit 12 may include: a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VGH1, and the gate is connected to the first clock signal terminal CLK1. The first terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, the second terminal is connected to the sixth node N6, and the gate is connected to the first clock signal terminal CLK1. The first terminal of the seventh transistor T7 is connected to the second power supply terminal VGL1, the second terminal is connected to the second terminal of the fifth transistor T5, and the gate is connected to the first signal input terminal IN1.

[0050] In this exemplary embodiment, as Figure 5 As shown, the first output circuit 13 may include: an eighth transistor T8, a second capacitor C2, a ninth transistor T9, and a third capacitor C3. The first terminal of the eighth transistor T8 is connected to the first power supply terminal VGH1, the second terminal is connected to the first signal output terminal OUT1, and the gate is connected to the seventh node N7. The second capacitor C2 is connected between the seventh node N7 and the first signal output terminal OUT1. The first terminal of the ninth transistor T9 is connected to the second power supply terminal VGL1, the second terminal is connected to the first signal output terminal OUT1, and the gate is connected to the sixth node N6. The third capacitor C3 is connected between the sixth node N6 and the second power supply terminal VGL1.

[0051] In this exemplary embodiment, as Figure 5As shown, the first pull-down circuit 14 may include: a tenth transistor T10 and an eleventh transistor T11. The first terminal of the tenth transistor T10 is connected to the seventh node N7, the second terminal is connected to the second power supply terminal VGL1, and the gate is connected to the sixth node N6. The first terminal of the eleventh transistor T11 is connected to the fourth node N4, the second terminal is connected to the second power supply terminal VGL1, and the gate is connected to the sixth node N6. The second pull-down circuit 15 may include: a twelfth transistor T12 and a thirteenth transistor T13. The first terminal of the twelfth transistor T12 is connected to the second power supply terminal VGL1, and the gate is connected to the fourth node N4. The first terminal of the thirteenth transistor T13 is connected to the second terminal of the twelfth transistor T12, the second terminal is connected to the sixth node N6, and the gate is connected to the second clock signal terminal CLK2.

[0052] In this exemplary embodiment, as Figure 5 As shown, the isolation circuit 17 may include: a fourteenth transistor T14, the first terminal of the fourteenth transistor T14 is connected to the fifth node N5, the second terminal is connected to the seventh node N7, and the gate is connected to the second clock signal terminal CLK2.

[0053] In this exemplary embodiment, the third transistor T3 to the fifteenth transistor T15 can all be N-type transistors. The first power supply terminal VGH1 can be a high-level signal terminal, and the second power supply terminal VGL1 can be a low-level signal terminal.

[0054] like Figure 6 As shown, Figure 5 The diagram shows the timing diagrams of each node in a driving method for the first shift register unit. IN1 is the timing diagram for the first signal input terminal, CLK1 is the timing diagram for the first clock signal terminal, CLK2 is the timing diagram for the second clock signal terminal, Trst1 is the timing diagram for the first reset signal terminal, N4 is the timing diagram for the fourth node, N5 is the timing diagram for the fifth node, N6 is the timing diagram for the sixth node, N7 is the timing diagram for the seventh node, and OUT1 is the timing diagram for the first signal output terminal. A frame of the display panel may include a scan period Ts and a blank period Tb. The driving method for the first shift register unit may include: a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4 located during the scan period Ts.

[0055] In the first stage t1, the first signal input terminal IN1 and the first clock signal terminal CLK1 output a high level, while the second clock signal terminal CLK2 outputs a low level. The third transistor T3 is turned on to transmit the high-level signal from the first power supply terminal VGH1 to the fourth node N4. The seventh node N7 and the first signal output terminal maintain the low level of the previous stage.

[0056] In the second stage t2, the first signal input terminal IN1 and the second clock signal terminal CLK2 output high levels, while the first clock signal terminal CLK1 outputs a low level. The fourth transistor T4, under the action of the fourth node N4, conducts, transmitting the high-level signal of the second clock signal terminal CLK2 to the fifth node N5. The voltage of the fourth node N4 is further pulled high under the coupling effect of the first capacitor C1. The fourteenth transistor T14 conducts, transmitting the high-level signal of the fifth node N5 to the seventh node N7. The eighth transistor T8, under the action of the seventh node N7, conducts, transmitting the high-level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1. Simultaneously, the twelfth transistor T12 and the thirteenth transistor T13 conduct, transmitting the low-level signal of the second power supply terminal VGL1 to the sixth node N6.

[0057] In the third stage t3, the first signal input terminal IN1 and the first clock signal terminal CLK1 output a low level, while the second clock signal terminal CLK2 outputs a high level. The fourth node N4 maintains the high level from the previous stage. The fourth transistor T4 is turned on under the action of the fourth node N4, transmitting the high-level signal of the second clock signal terminal CLK2 to the fifth node N5. The voltage of the fourth node N4 is further pulled high under the coupling effect of the first capacitor C1. The fourteenth transistor T14 is turned on to transmit the high-level signal of the fifth node N5 to the seventh node N7. The eighth transistor T8 is turned on under the action of the seventh node N7 to transmit the high-level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1. Simultaneously, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, transmitting the low-level signal of the second power supply terminal VGL1 to the sixth node N6.

[0058] In the fourth stage t4, the first signal input terminal IN1 and the second clock signal terminal CLK2 output a low level, while the first clock signal terminal CLK1 outputs a high level. The fifth transistor T5 and the sixth transistor T6 are turned on by the first clock signal terminal CLK1, transmitting the high-level signal of the first power supply terminal VGH1 to the sixth node N6. The ninth transistor T9 is turned on by the sixth node N6 to transmit the low-level signal of the second power supply terminal VGL1 to the first signal output terminal OUT1. Simultaneously, the eleventh transistor T11 and the tenth transistor T10 are turned on by the sixth node N6, transmitting the low-level signal of the second power supply terminal VGL1 to the fourth node N4 and the seventh node N7.

[0059] The first shift register unit can shift and output the signal from the first signal input terminal IN1 through the first signal output terminal OUT1. For example... Figure 6As shown, the first signal input terminal IN1 can output multiple high-level pulses during the scanning period Ts of the display panel, thereby enabling the first shift register unit to output multiple high-level pulses during the scanning period Ts of the display panel. These multiple high-level pulses can be used to turn on the first transistor T1 during the data writing and black-insertion phases of the pixel driving circuit. It should be noted that, in this exemplary embodiment, the duration of the high-level pulses output by the first signal input terminal IN1 can be adjusted according to actual needs. Specifically, during a single high-level pulse period output by the first signal input terminal IN1, the first clock signal terminal CLK1 outputs at least one high-level pulse signal, and the second clock signal terminal CLK2 outputs at least one high-level pulse signal. When the first clock signal terminal CLK1 outputs a high-level pulse signal, the second clock signal terminal CLK2 outputs a low-level signal, and when the second clock signal terminal CLK2 outputs a high-level pulse signal, the first clock signal terminal CLK1 outputs a low-level signal. That is, as shown... Figure 6 As shown, during a single high-level pulse period output from the first signal input terminal IN1, the shift register unit driving method includes at least a first stage t1 and a second stage t2.

[0060] like Figure 1 , 2As shown, the driving method of this pixel driving circuit may further include a sensing phase Tg during the blank period Tb of the display panel. The sensing phase Tg may include a sensing signal writing phase t7, a charging phase t8, a sampling phase t9, and a data signal write-back phase t10. Specifically, in the sensing signal writing phase t7, the first gate driving signal terminal G1 and the second gate driving signal terminal G2 output high-level signals, the first transistor T1 and the second transistor T2 are turned on, the sensing signal terminal Sense inputs a reset signal to the third node N3, and the data signal terminal Da inputs a sensing data signal to the first node N1. In the charging phase t8, the first gate driving signal terminal G1 outputs a high-level signal, and the second gate driving signal terminal G2 outputs a low-level signal. At this time, the sensing signal terminal Sense is connected to the analog-to-digital converter 36 through the sample-and-hold circuit 35. Simultaneously, during the charging phase t8, the driving transistor DT is turned on under the action of the first node N1 and inputs current to the third node N3. The voltage between the third node N3 and the sensing signal terminal Sense gradually increases. When the gate-source voltage difference of the driving transistor DT equals the threshold voltage of the driving transistor, the driving transistor DT stops inputting current to the third node N3, and the voltage between the third node N3 and the sensing signal terminal Sense no longer increases. During the sampling phase t9, the first gate driving signal terminal G1 outputs a high-level signal, and the second gate driving signal terminal G2 outputs a low-level signal. The driving chip of the display panel can sample the voltage of the sensing signal terminal Sense through the analog-to-digital converter 36, and obtain the threshold and mobility of the driving transistor based on the sampled voltage. The display panel can compensate the data signal during the data writing phase of the pixel driving circuit according to the threshold and mobility of the driving transistor to reduce the display unevenness caused by the difference in the threshold voltage of the driving transistor. During the data signal write-back phase t10, the first gate drive signal terminal G1 and the second gate drive signal terminal G2 output high-level signals, the first transistor T1 and the second transistor T2 are turned on, and the data signal terminal Da rewrites the data signal written in the data writing phase t1 to the first node N1. The sensing signal terminal Sense can also input a reset signal to the third node.

[0061] like Figure 3 As shown, the display panel may further include: a second gate driving circuit 2, the second gate driving circuit 2 including a plurality of second output terminals O2, the second output terminals O2 being configured corresponding to the pixel driving circuit, for example, as... Figure 3As shown, the second output terminal O2 can be configured to correspond to a row of pixel driving circuits. The second output terminal O2 can be connected to the gate of the second transistor T2 in the corresponding pixel driving circuit; the second output terminal O2 can be used to output a valid level pulse during the data writing phase of the corresponding pixel driving circuit. It should be understood that the second output terminal O2 can also be configured to correspond to multiple rows of pixel driving circuits; furthermore, the second output terminal O2 can be configured to correspond to pixel driving circuits in other ways.

[0062] In this exemplary embodiment, during a blank time period Tb of a frame, at least a portion of the pixel driving circuits are in the sensing phase. The display panel can sequentially sense the pixel driving circuits during blank time periods of different frames. For example, it can sense the first row of pixel driving circuits during the blank time period of the first frame and sense the second row of pixel driving circuits during the blank time period of the second frame. The second output terminal O2 corresponding to the pixel driving circuit in the sensing phase can also be used to output valid level pulses during the sensing signal writing phase and the data signal writing back phase of the pixel driving circuit, thereby realizing the sensing of the pixel driving circuit.

[0063] In this exemplary embodiment, as Figure 7 The diagram shown is a schematic representation of the structure of the second gate driving circuit in an exemplary embodiment of the display panel of this disclosure. The second gate driving circuit 2 may include multiple cascaded second shift register units GOA2.

[0064] In this exemplary embodiment, as Figure 8 The diagram shown is a schematic representation of an exemplary embodiment of the second shift register unit of this disclosure. The second shift register unit GOA2 may include: a third input circuit 21, a third pull-down circuit 23, a fourth pull-down circuit 24, a second reset circuit 25, a second output circuit 22, a first control circuit 26, and a third reset circuit 27.

[0065] In this exemplary embodiment, as Figure 8As shown, the third input circuit 21 is connected to the third power supply terminal VGH2, the eighth node N8, and the second signal input terminal IN2, and is used to transmit the signal from the third power supply terminal VGH2 to the eighth node N8 in response to the signal from the second signal input terminal IN2. The second output circuit 22 is connected to the eighth node N8, the second signal output terminal OUT2, and the third clock signal terminal CLK3, and is used to transmit the signal from the third clock signal terminal CLK3 to the second signal output terminal OUT2 in response to the signal from the eighth node N8. The second signal output terminal OUT2 of the second shift register unit GOA2 is used to form the second output terminal O2 of the second gate drive circuit 2. The first control circuit 26 is connected to the eighth node N8, the fourth clock signal terminal CLK4, the second signal output terminal OUT2, the tenth node N10, the eleventh node N11, and the first control signal terminal OE. It is used to transmit the signal of the second signal output terminal OUT2 to the tenth node N10 in response to the signal of the tenth node N10, to transmit the signal of the fourth clock signal terminal CLK4 to the eleventh node N11 in response to the signal of the tenth node N10, and to transmit the signal of the eleventh node N11 to the eighth node N8 in response to the signal of the fourth clock signal terminal CLK4. The third reset circuit 27 is connected to the eighth node N8, the fourth power supply terminal VGL2, and the third reset signal terminal Re3. It is used to transmit the signal of the fourth power supply terminal VGL2 to the eighth node N8 in response to the signal of the third reset signal terminal Re3.

[0066] In this exemplary embodiment, as Figure 8 As shown, the third pull-down circuit 23 is connected to the third power supply terminal VGH2, the eighth node N8, the fourth power supply terminal VGL2, the ninth node N9, and the second signal output terminal OUT2. It is used to transmit the signal of the third power supply terminal VGH2 to the ninth node N9 in response to the signal of the third power supply terminal VGH2, and to transmit the signal of the fourth power supply terminal VGL2 to the second signal output terminal OUT2 and the eighth node N8 in response to the signal of the ninth node N9. The fourth pull-down circuit 24 is connected to the eighth node N8, the fourth power supply terminal VGL2, and the ninth node N9. It is used to transmit the signal of the fourth power supply terminal VGL2 to the ninth node N9 in response to the signal of the eighth node N8. The second reset circuit 25 is connected to the eighth node N8, the fourth power supply terminal VGL2, and the second reset signal terminal Tst2. It is used to transmit the signal of the fourth power supply terminal VGL2 to the eighth node N8 in response to the information of the second reset signal terminal Tst2.

[0067] In this exemplary embodiment, as Figure 7As shown, the second signal output terminal OUT2 of the second shift register unit GOA2 in this stage is connected to the second signal input terminal IN2 of the adjacent next-level second shift register unit GOA2, and the second signal output terminal OUT2 of the second shift register unit GOA2 in this stage is connected to the third reset signal terminal Re3 of the adjacent previous-level second shift register unit GOA2.

[0068] In this exemplary embodiment, as Figure 8 As shown, the third input circuit 21 includes a sixteenth transistor T16, whose first terminal is connected to the third power supply terminal VGH2, second terminal is connected to the eighth node N8, and gate is connected to the second signal input terminal IN2. The third reset circuit 27 may include a seventeenth transistor T17, whose first terminal is connected to the fourth power supply terminal VGL2, second terminal is connected to the eighth node N8, and gate is connected to the third reset signal terminal Re3. The second output circuit 22 includes an eighteenth transistor T18 and a fourth capacitor C4. The first terminal of the eighteenth transistor T18 is connected to the third clock signal terminal CLK3, second terminal is connected to the second signal output terminal OUT2, and gate is connected to the eighth node N8; the fourth capacitor C4 is connected between the eighth node N8 and the second signal output terminal OUT2. The third pull-down circuit 23 includes: a nineteenth transistor T19, a twentieth transistor T20, and a twenty-seventh transistor T27. The first terminal of the nineteenth transistor T19 is connected to the third power supply terminal VGH2, the second terminal is connected to the ninth node N9, and the gate is connected to the third power supply terminal VGH2. The first terminal of the twentieth transistor T20 is connected to the eighth node N8, the second terminal is connected to the fourth power supply terminal VGL2, and the gate is connected to the ninth node N9. The first terminal of the twenty-seventh transistor T27 is connected to the fourth power supply terminal VGL2, the second terminal is connected to the second signal output terminal OUT2, and the gate is connected to the ninth node N9. The fourth pull-down circuit 24 includes: a twenty-first transistor T21. The first terminal of the twenty-first transistor T21 is connected to the ninth node N9, the second terminal is connected to the fourth power supply terminal VGL2, and the gate is connected to the eighth node N8. The second reset circuit 25 includes: a twenty-second transistor T22. The first terminal of the twenty-second transistor T22 is connected to the fourth power supply terminal VGL2, the second terminal is connected to the eighth node N8, and the gate is connected to the second reset signal terminal Trst2.

[0069] In this exemplary embodiment, as Figure 8As shown, the first control circuit 26 includes: a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, and a fifth capacitor C5. The first terminal of the twenty-third transistor T23 is connected to the second signal output terminal OUT2, the second terminal is connected to the tenth node N10, and the gate is connected to the first control signal terminal OE. The first terminal of the twenty-fourth transistor T24 is connected to the fourth clock signal terminal CLK4, the second terminal is connected to the eleventh node N11, and the gate is connected to the tenth node N10. The first terminal of the twenty-fifth transistor T25 is connected to the eleventh node N11, the second terminal is connected to the eighth node N8, and the gate is connected to the fourth clock signal terminal CLK4. The fifth capacitor C5 is connected between the tenth node N10 and the fourth power supply terminal VGL2.

[0070] In this exemplary embodiment, the sixteenth transistor T16 to the twenty-fifth transistor T25 and the twenty-seventh transistor T27 can be N-type transistors, the third power supply terminal VGH2 can be a high-level signal terminal, and the fourth power supply terminal VGL2 can be a low-level signal terminal.

[0071] like Figure 9 As shown, Figure 8 The diagram shows the timing diagrams of each node in a driving method for the second shift register unit. Specifically, IN2 is the timing diagram for the second signal input terminal in the first-stage second shift register unit; OE is the timing diagram for the first control signal terminal OE in any first-stage second shift register unit; CLK3 is the timing diagram for the third clock signal terminal in the first-stage second shift register unit; CLK4 is the timing diagram for the fourth clock signal terminal in any first-stage second shift register unit; OUT2 is the timing diagram for the second signal output terminal in the first-stage second shift register unit; N8 is the timing diagram for the eighth node in the first-stage second shift register unit; OUT2 is the timing diagram for the second signal output terminal in the eleventh-stage second shift register unit; N8 is the timing diagram for the eighth node in the eleventh-stage second shift register unit; and CLK3 is the timing diagram for the third clock signal terminal in the eleventh-stage second shift register unit.

[0072] like Figure 9 As shown, a frame T of the display panel includes a scan period Ts and a blank period Tb. During the scan period Ts, the second gate driving circuit can input gate driving signals line by line to the second gate driving signal terminal of the pixel driving circuit. During the blank period Tb, the second gate driving circuit can also input two high-level pulse signals to the pixel driving circuit in the detection phase.

[0073] like Figure 9 As shown, for the first-stage second shift register unit:

[0074] In the first stage t1, the second signal input terminal IN2 and the first control signal terminal OE of the first-stage second shift register unit output high-level signals, while the third clock signal terminal CLK3 and the fourth clock signal terminal CLK4 output low-level signals. The sixteenth transistor T16 is turned on by the second signal input terminal IN2, and the high-level signal of the third power supply terminal VGH2 is transmitted to the eighth node N8 through the sixteenth transistor T16. The eighteenth transistor T18 is turned on by the eighth node N8 to transmit the low-level signal of the third clock signal terminal CLK3 to the second signal output terminal OUT2. Simultaneously, the twenty-first transistor T21 is turned on, and the low-level signal of the fourth power supply terminal VGL2 is transmitted to the ninth node N9 to turn off the twentieth transistor T20 and the twenty-seventh transistor T27.

[0075] In the second stage t2, the second signal input terminal IN2, the first control signal terminal OE, and the fourth clock signal terminal CLK4 of the first-stage second shift register unit output low-level signals, while the third clock signal terminal CLK3 outputs a high-level signal. The eighteenth transistor T18, under the action of the eighth node N8, transmits the high-level signal of the third clock signal terminal CLK3 to the second signal output terminal OUT2. Simultaneously, the voltage of the eighth node N8 is pulled high by the coupling effect of the fourth capacitor C4. Furthermore, the twenty-first transistor T21 is turned on, and the low-level signal of the fourth power supply terminal VGL2 is transmitted to the ninth node N9 to turn off the twentieth transistor T20 and the twenty-seventh transistor T27.

[0076] In the third stage t3, the second signal input terminal IN2, the first control signal terminal OE, the fourth clock signal terminal CLK4, and the third clock signal terminal CLK3 of the first-stage second shift register unit output low-level signals. The reset signal terminal Re3 outputs a high-level signal under the action of the second signal output terminal OUT2 of the second-stage second shift register unit GOA2. The seventeenth transistor T17 is turned on, and the fourth power supply terminal VGL2 inputs a low-level signal to the eighth node N8. The nineteenth transistor T19 is turned on under the action of the third power supply terminal VGH2 to transmit the high-level signal from VGH2 to the ninth node N9. The twenty-seventh transistor T27 is turned on under the action of the ninth node N9 to transmit the low-level signal from VGL2 to the second signal output terminal OUT2. Simultaneously, the twentieth transistor T20 is turned on under the action of the ninth node N9 to transmit the low-level signal from VGL2 to the eighth node N8.

[0077] For the eleventh stage, second shift register unit:

[0078] In the fourth stage t4, the second signal output terminal of the eleventh-stage second shift register unit GOA2 outputs a high-level signal, and simultaneously, the first control signal terminal OE outputs a high-level signal. The high-level signal output from the second signal output terminal of the eleventh-stage second shift register unit GOA2 is transmitted to the tenth node N10 through the twenty-third transistor T23. That is, the first control signal terminal OE can select to write a high-level signal to the tenth node in any stage of the second shift register unit by controlling the duration of the high-level pulse signal output.

[0079] In the fifth stage t5, which is in the blank period Tb, the fourth clock signal terminal CLK4 outputs a high-level signal, and the twenty-fourth transistor T24 and the twenty-fifth transistor T25 are turned on to transmit the high-level signal of the fourth clock signal terminal CLK4 to the eleventh node N11 and the eighth node N8.

[0080] During the sixth stage t6, which is in the blank period, the third clock signal terminal of the eleventh stage second shift register unit outputs a high-level signal, and the eighteenth transistor T18 is turned on to transmit the high-level signal from the third clock signal terminal to the second signal output terminal of the eleventh stage second shift register unit.

[0081] During the seventh stage t7, which is in a blank period, the third clock signal terminal of the eleventh stage second shift register unit outputs a high-level signal, and the eighteenth transistor T18 is turned on to transmit the high-level signal from the third clock signal terminal to the second signal output terminal of the eleventh stage second shift register unit.

[0082] Subsequently, in the first stage of the next frame, the first control signal terminal OE outputs a high-level signal, and the twenty-third transistor T23 is turned on to transmit the low-level signal of the second signal output terminal OUT2 in the eleventh stage second shift register unit to the tenth node N10.

[0083] In this exemplary embodiment, the second gate driving circuit 2 can select the pixel driving circuit row to be sensed in the current frame through the first control signal terminal OE. Wherein, Figure 9 The sixth stage corresponds to Figure 2 During the sensing signal writing stage, Figure 9 The seventh stage output corresponds to Figure 2 The data signal write-back stage in the process. Specifically, the high-level pulse output by the second shift register unit in the sixth stage is used to turn on the second transistor in the sensing signal writing stage of the pixel driving circuit, and the high-level pulse output by the second shift register unit in the seventh stage is used to turn on the second transistor in the data signal write-back stage of the pixel driving circuit.

[0084] like Figure 7As shown, the second gate drive circuit can adopt a 4CLK architecture, that is, the second gate drive circuit can include four clock signal lines LC31, LC32, LC33, and LC34. These four clock signal lines LC31, LC32, LC33, and LC34 are used to provide clock signals to the third clock signal terminal CLK3 in the second shift register unit. Figure 7 As shown, the third clock signal terminal of the second shift register unit in stage 1+4n is connected to clock signal line LC31, the third clock signal terminal of the second shift register unit in stage 2+4n is connected to clock signal line LC32, the third clock signal terminal of the second shift register unit in stage 3+4n is connected to clock signal line LC33, and the third clock signal terminal of the second shift register unit in stage 4+4n is connected to clock signal line LC34. Here, n is an integer greater than or equal to 0. Figure 7 As shown, the second gate drive circuit may further include: a second signal input line LIN2, a second reset signal line LTrst2, a first control signal line LOE, and a fourth clock signal line LC4. The second signal input line LIN2 is connected to the second signal input terminal IN2 of the first-stage second shift register unit; the second reset signal line LTrst2 is connected to the second reset signal terminal Trst2 of each stage of the second shift register unit; the first control signal line LOE is connected to the first control signal terminal OE of each stage of the second shift register unit; and the fourth clock signal line LC4 is connected to the fourth clock signal terminal CLK4 of each stage of the second shift register unit. It should be understood that in other exemplary embodiments, the second gate drive circuit may also employ other CLK architectures, such as a 3CLK architecture, a 5CLK architecture, etc.

[0085] like Figure 10 As shown, Figure 7 The timing diagrams for each signal line in the second gate drive circuit are shown below. LC31 is the timing diagram for clock signal line LC31, LC32 is the timing diagram for clock signal line LC32, LC33 is the timing diagram for clock signal line LC33, LC34 is the timing diagram for clock signal line LC34, LIN2 is the timing diagram for the second signal input line LIN2, LTrst2 is the timing diagram for the second reset signal line LTrst2, LOE is the timing diagram for the first control signal line LOE, and LC4 is the timing diagram for the fourth clock signal line LC4. Figure 10As shown, the second signal input line LIN2 inputs a high-level signal to the first-stage second shift register unit at the beginning of each frame T. The first control signal line LOE, in addition to providing a high-level signal simultaneously with the second signal input line LIN2 at the beginning of each frame, also outputs a high-level signal during any scan period of that frame to select the transmission of a high-level signal from the output of any second shift register unit to the tenth node N10 of that second shift register unit. The fourth clock signal line LC4 outputs a high-level pulse during the blank period of a frame to write a high-level signal to the eighth node N8 of the second shift register unit selected by the first control signal line LOE. Furthermore, the second reset signal line LTret2 can output a high-level pulse at the end of a frame to reset the eighth node N8.

[0086] In this exemplary embodiment, as Figure 2 As shown, the first output terminal O1 of the pixel driving circuit in the sensing stage Tg is also used to output an effective level pulse in the sensing stage Tg of the pixel driving circuit, where the effective level is a high level.

[0087] Correspondingly, such as Figure 5 As shown, the first shift register unit GOA1 may further include: a first reset circuit 16 and a second control circuit 18. The first reset circuit 16 is connected to the sixth node N6, the first power supply terminal VGH1, and the first reset signal terminal Trst1, and is used to transmit the signal of the first power supply terminal VGH1 to the sixth node N6 in response to the signal of the first reset signal terminal Trst1. The second control circuit 18 is connected to the eleventh node N11 in the corresponding second shift register unit GOA2, the fourth clock signal terminal CLK4 in the corresponding second shift register unit GOA2, and the fourth node N4, and is used to transmit the signal of the eleventh node N11 to the fourth node N4 in response to the signal of the fourth clock signal terminal CLK4. The second shift register unit GOA2 and the first shift register unit GOA1, which correspond to the same pixel driving circuit, correspond to the second control circuit 18 in the first shift register unit GOA1.

[0088] In this exemplary embodiment, the first reset circuit 16 may include a fifteenth transistor T15, the first terminal of which is connected to the first power supply terminal VGH1, the second terminal of which is connected to the sixth node N6, and the gate of which is connected to the first reset signal terminal Trst1. The second control circuit 18 may include a twenty-sixth transistor T26, the first terminal of which is connected to the eleventh node N11, the second terminal of which is connected to the fourth node N4, and the gate of which is connected to the fourth clock signal terminal CLK4. The fifteenth transistor T15 and the twenty-sixth transistor T26 may be N-type transistors.

[0089] like Figure 6 As shown, when the pixel driving circuit corresponding to the first shift register unit is sensed in this frame, the potential of the eleventh node N11 is high during the blank period. The driving method of the first shift register unit may also include a sensing driving stage Tc located in the blank period Tb, which may include a fifth stage t5 and a sixth stage t6. In the fifth stage t5, the second clock signal terminal CLK2 and the fourth clock signal terminal CLK4 output high-level signals, the twenty-sixth transistor T26 is turned on under the action of the fourth clock signal terminal CLK4, the high-level signal of the eleventh node N11 is transmitted to the fourth node, the fourth transistor T4 is turned on under the action of the fourth node N4, the fourteenth transistor T14 is turned on under the action of the second clock signal terminal CLK2, the high-level signal of the second clock signal terminal CLK2 is transmitted to the seventh node N7, and the eighth transistor T8 is turned on under the action of the seventh node N7 to transmit the high-level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1. In the sixth stage t6, the second clock signal terminal CLK2 outputs a high-level signal, the fourth clock signal terminal CLK4 outputs a low-level signal, the seventh node N7 maintains the high-level signal of the fifth stage t5, and the eighth transistor T8 is turned on under the action of the seventh node N7 to transmit the high-level signal of the first power supply terminal VGH1 to the first signal output terminal OUT1.

[0090] like Figure 6 As shown, the first shift register unit driving method may further include a seventh stage t7 located in the blank period Tb. In the seventh stage t7, the first reset signal terminal Trst1 outputs a high-level signal, the fifteenth transistor T15 is turned on, the first power supply terminal VGH1 inputs a high-level signal to the sixth node N6, the eleventh transistor T11, the tenth transistor T10, and the ninth transistor T9 are turned on, and the second power supply terminal VGL1 inputs a low-level signal to the fourth node N4, the seventh node N7, and the first signal output terminal OUT1.

[0091] in, Figure 6 The sensing drive stage Tc corresponds to Figure 2In the sensing stage Tg, the high-level signal output by the first shift transmitter unit in the sensing drive stage Tc can be used to drive the pixel driving circuit in the sensing drive stage Tc.

[0092] like Figure 4 As shown, in the first gate drive circuit, the first signal output terminal OUT1 of the first-stage first shift register unit GOA1 is connected to the first signal input terminal IN1 of the adjacent next-stage first shift register unit GOA1. The display panel may further include: a first clock signal line LC1, a second clock signal line LC2, a first signal input line LIN1, a first reset signal line LTrst1, and a fourth clock signal line LC4. The first clock signal line LC1 is connected to the first clock signal terminal CLK1 in the odd-numbered stage first shift register unit GOA1 and the second clock signal terminal CLK2 in the even-numbered stage first shift register unit GOA1; the second clock signal line LC2 is connected to the second clock signal terminal CLK2 in the odd-numbered stage first shift register unit GOA1 and the first clock signal terminal CLK1 in the even-numbered stage first shift register unit GOA1. The first signal input line LIN1 is connected to the first signal input terminal IN1 of the first-stage first shift register unit GOA1. The first reset signal line LTrst1 is connected to the first reset signal terminal Trst1 of each stage first shift register unit GOA1. The fourth clock signal line LC4 is connected to the fourth clock signal terminal of the first shift register unit GOA1 of each stage.

[0093] like Figure 11 As shown, Figure 4 The diagram shows the timing of each signal line in a driving method of the first gate driving circuit. LC1 is the timing diagram of the first clock signal line, LC2 is the timing diagram of the second clock signal line, LC4 is the timing diagram of the fourth clock signal line, and LTrst1 is the timing diagram of the first reset signal line.

[0094] Among them, such as Figure 11 As shown, during the blank period Tb between adjacent frames, the first clock signal line LC1 and the second clock signal line LC2 alternately output high-level pulse signals. For example, during the blank period Tb in frame T1, the second clock signal line LC2 outputs a high-level pulse signal to enable the second clock signal terminal CLK2 in the odd-numbered stage first shift register unit to output a high-level signal; during the blank period Tb in frame T2, the first clock signal line LC1 outputs a high-level pulse signal to enable the second clock signal terminal CLK2 in the even-numbered stage first shift register unit to output a high-level signal. The first reset signal line LTrst1 can input a reset signal to the first shift register unit GOA1 during the blank period of each frame.

[0095] In this exemplary embodiment, the first power supply terminal VGH1 and the third power supply terminal VGH2 can share the same power supply terminal, and the second power supply terminal VGL1 and the fourth power supply terminal VGL2 can share the same power supply terminal.

[0096] In this exemplary embodiment, the fourth clock signal line in the first gate driving circuit and the fourth clock signal line in the second gate driving circuit can share the same signal line, and the first reset signal line in the first gate driving circuit and the second reset signal line in the second gate driving circuit can share the same signal line.

[0097] This exemplary embodiment also provides a display panel driving method, wherein the method is used to drive the aforementioned display panel, the driving method comprising:

[0098] The first output terminal O1 outputs valid level pulses during the data writing stage, black insertion stage, and sensing stage of the corresponding pixel driving circuit.

[0099] The second output terminal O2 is used to output valid level pulses during the data writing stage, sensing signal writing stage, and data signal write-back stage of the corresponding pixel driving circuit.

[0100] The driving method has been explained in detail above and will not be repeated here.

[0101] This exemplary embodiment also provides a display device, wherein the display device includes the display panel described above. The display device can be a display device for a mobile phone, tablet computer, or television.

[0102] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0103] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Multiple pixel driving circuits, the pixel driving circuits comprising: A driving circuit, connected to a first node, a second node, and a third node, is used to respond to a signal from the first node by inputting a driving current to the third node through the second node. The first switching unit has a first end connected to the third node and a second end connected to the sensing signal terminal, and is used to respond to the signal of its control terminal to connect the third node and the sensing signal terminal. A first gate driving circuit, the first gate driving circuit includes a plurality of first output terminals, the first output terminals are correspondingly configured with the pixel driving circuit, and the first output terminals are connected to the control terminal of the first switching unit in the pixel driving circuit corresponding to them. Wherein, one driving cycle of the pixel driving circuit includes a data writing stage, multiple light emission stages, and a black insertion stage located between adjacent light emission stages. The first output terminal is used to output a valid level pulse during the data writing stage and black insertion stage of the pixel driving circuit corresponding to it. The first gate drive circuit includes multiple cascaded first shift register units, each of which includes: The first input circuit is connected to a first power supply terminal, a first clock signal terminal, a fourth node, a fifth node, and a second clock signal terminal. It is used to transmit the signal from the first power supply terminal to the fourth node in response to the signal from the first clock signal terminal, and to transmit the signal from the second clock signal terminal to the fifth node in response to the signal from the fourth node. The second input circuit is connected to the first power supply terminal, the first clock signal terminal, the first signal input terminal, the second power supply terminal, and the sixth node. It is used to transmit the signal of the first power supply terminal to the sixth node in response to the signal of the first clock signal terminal, and to transmit the signal of the second power supply terminal to the sixth node in response to the signals of the first signal input terminal and the first clock signal terminal. A first output circuit is connected to the sixth node, the seventh node, the first power supply terminal, the first signal output terminal, and the second power supply terminal. It is used to transmit the signal of the second power supply terminal to the first signal output terminal in response to the signal of the sixth node, and to transmit the signal of the first power supply terminal to the first signal output terminal in response to the signal of the seventh node. The seventh node is connected to the fifth node. The first pull-down circuit connects the seventh node, the sixth node, the second power supply terminal, and the fourth node, and is used to transmit the signal from the second power supply terminal to the seventh node and the fourth node in response to the signal from the sixth node. The second pull-down circuit is connected to the fourth node, the sixth node, the second clock signal terminal, and the second power supply terminal, and is used to transmit the signal from the second power supply terminal to the sixth node in response to the signals from the fourth node and the second clock signal terminal. The first signal output terminal of the first shift register unit forms the first output terminal of the first gate drive circuit.

2. The display panel according to claim 1, wherein, The driving circuit includes: A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node; The first switching unit includes: The first transistor has a first electrode connected to the third node, a second electrode connected to the sensing signal terminal, and a gate connected to the first gate drive signal terminal. The pixel driving circuit also includes: The second transistor has a first terminal connected to the first node, a second terminal connected to the data signal terminal, and a gate connected to the second gate drive signal terminal. A capacitor is connected between the first node and the third node.

3. The display panel according to claim 1, wherein, The first shift register unit further includes: An isolation circuit is provided, connecting the fifth node, the seventh node, and the second clock signal terminal, for responding to the signal of the second clock signal terminal to connect the fifth node and the seventh node; A first reset circuit is connected to the sixth node, a first power supply terminal, and a first reset signal terminal, and is used to respond to the signal from the first reset signal terminal to transmit the signal from the first power supply terminal to the sixth node.

4. The display panel according to claim 1, wherein, The first input circuit includes: The third transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the fourth node, and its gate connected to the first clock signal terminal. The fourth transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the fifth node, and its gate connected to the fourth node. The first capacitor is connected to the fourth node; The second input circuit includes: The fifth transistor has its first terminal connected to the first power supply terminal and its gate connected to the first clock signal terminal. The sixth transistor has its first terminal connected to the second terminal of the fifth transistor, the second terminal connected to the sixth node, and its gate connected to the first clock signal terminal. The seventh transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the second terminal of the fifth transistor, and its gate connected to the first signal input terminal.

5. The display panel according to claim 1, wherein, The first output circuit includes: The eighth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the first signal output terminal, and its gate connected to the seventh node. The second capacitor is connected to the seventh node; The ninth transistor has its first terminal connected to the second power supply terminal, its second terminal connected to the first signal output terminal, and its gate connected to the sixth node. The third capacitor is connected to the sixth node.

6. The display panel according to claim 1, wherein, The first pull-down circuit includes: The tenth transistor has its first terminal connected to the seventh node, its second terminal connected to the second power supply terminal, and its gate connected to the sixth node. The eleventh transistor has its first terminal connected to the fourth node, its second terminal connected to the second power supply terminal, and its gate connected to the sixth node. The second pull-down circuit includes: The twelfth transistor has its first terminal connected to the second power supply terminal and its gate connected to the fourth node. The thirteenth transistor has its first terminal connected to the second terminal of the twelfth transistor, the second terminal connected to the sixth node, and its gate connected to the second clock signal terminal.

7. The display panel according to claim 3, wherein, The isolation circuit includes: The fourteenth transistor has its first terminal connected to the fifth node, its second terminal connected to the seventh node, and its gate connected to the second clock signal terminal. The first reset circuit includes: The fifteenth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the sixth node, and its gate connected to the first reset signal terminal.

8. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit also includes: The second transistor has its first terminal connected to the first node and its second terminal connected to the data signal terminal. The display panel also includes: The second gate driving circuit includes a plurality of second output terminals, which are correspondingly configured with respect to the pixel driving circuit. The second output terminals are connected to the gate of the second transistor in the pixel driving circuit to which they correspond. The second output terminal is used to output a valid level pulse during the data writing phase of the corresponding pixel driving circuit.

9. The display panel according to claim 8, wherein, A frame of the display panel includes a blank period. During the blank period of a frame, at least part of the pixel driving circuit is in the sensing phase. The sensing phase of the pixel driving circuit includes a sensing signal writing phase, a charging phase, a sampling phase, and a data signal write-back phase. The second output terminal of the pixel driving circuit in the sensing stage is also used to output valid level pulses in the sensing signal writing stage and the data signal writing back stage of the pixel driving circuit, respectively. The first output terminal of the pixel driving circuit in the sensing phase is also used to output an effective level pulse during the sensing phase of the pixel driving circuit.

10. The display panel according to claim 9, wherein, The second gate drive circuit includes multiple cascaded second shift register units, each of which includes: The second output circuit is connected to the eighth node, the second signal output terminal, and the third clock signal terminal, and is used to transmit the signal of the third clock signal terminal to the second signal output terminal in response to the signal of the eighth node. The second signal output terminal of the second shift register unit is used to form the second output terminal of the second gate drive circuit. A first control circuit is connected to the eighth node, the fourth clock signal terminal, the second signal output terminal, the tenth node, and the eleventh node. The first control signal terminal is used to transmit the signal of the second signal output terminal to the tenth node in response to the signal of the first control signal terminal, to transmit the signal of the fourth clock signal terminal to the eleventh node in response to the signal of the tenth node, and to transmit the signal of the eleventh node to the eighth node in response to the signal of the fourth clock signal terminal. The first shift register unit further includes: The second control circuit is connected to the eleventh node in the corresponding second shift register unit, the fourth clock signal terminal in the corresponding second shift register unit, and the fourth node, and is used to transmit the signal of the eleventh node to the fourth node in response to the signal of the fourth clock signal terminal. The second shift register unit and the first shift register unit, which are corresponding to the same pixel driving circuit, are respectively connected, and the second shift register unit and the second control circuit in the first shift register unit are respectively connected.

11. The display panel according to claim 10, wherein, The second shift register unit further includes: The third input circuit is connected to the third power supply terminal, the eighth node, and the second signal input terminal, and is used to transmit the signal from the third power supply terminal to the eighth node in response to the signal from the second signal input terminal. The third pull-down circuit is connected to the third power supply terminal, the eighth node, the fourth power supply terminal, the ninth node, and the second signal output terminal. It is used to transmit the signal of the third power supply terminal to the ninth node in response to the signal of the third power supply terminal, and to transmit the signal of the fourth power supply terminal to the second signal output terminal and the eighth node in response to the signal of the ninth node. The fourth pull-down circuit is connected to the eighth node, the fourth power supply terminal, and the ninth node, and is used to transmit the signal from the fourth power supply terminal to the ninth node in response to the signal from the eighth node. The second reset circuit is connected to the eighth node, the fourth power supply terminal, and the second reset signal terminal, and is used to transmit the signal from the fourth power supply terminal to the eighth node in response to the information from the second reset signal terminal. The third reset circuit is connected to the eighth node, the fourth power supply terminal, and the third reset signal terminal, and is used to respond to the signal of the third reset signal terminal to transmit the signal of the fourth power supply terminal to the eighth node.

12. The display panel according to claim 11, wherein, The third input circuit includes: The sixteenth transistor has its first terminal connected to the third power supply terminal, its second terminal connected to the eighth node, and its gate connected to the second signal input terminal. The third reset circuit includes: The seventeenth transistor has its first terminal connected to the fourth power supply terminal, its second terminal connected to the eighth node, and its gate connected to the third reset signal terminal. The second output circuit includes: The eighteenth transistor has its first terminal connected to the third clock signal terminal, its second terminal connected to the second signal output terminal, and its gate connected to the eighth node. The fourth capacitor is connected to the eighth node; The third pull-down circuit includes: The nineteenth transistor has its first terminal connected to the third power supply terminal, its second terminal connected to the ninth node, and its gate connected to the third power supply terminal. The twentieth transistor has its first terminal connected to the eighth node, its second terminal connected to the fourth power supply terminal, and its gate connected to the ninth node. The 27th transistor has its first terminal connected to the fourth power supply terminal, its second terminal connected to the second signal output terminal, and its gate connected to the ninth node. The fourth pull-down circuit includes: The twenty-first transistor has its first terminal connected to the ninth node, its second terminal connected to the fourth power supply terminal, and its gate connected to the eighth node. The second reset circuit includes: The 22nd transistor has its first terminal connected to the fourth power supply terminal, its second terminal connected to the eighth node, and its gate connected to the second reset signal terminal.

13. The display panel according to claim 10, wherein, The first control circuit includes: The 23rd transistor has its first terminal connected to the second signal output terminal, its second terminal connected to the 10th node, and its gate connected to the first control signal terminal. The 24th transistor has its first terminal connected to the fourth clock signal terminal, its second terminal connected to the eleventh node, and its gate connected to the tenth node. The 25th transistor has its first terminal connected to the 11th node, its second terminal connected to the 8th node, and its gate connected to the 4th clock signal terminal. The fifth capacitor is connected to the tenth node.

14. The display panel according to claim 10, wherein, The second control circuit includes: The 26th transistor has its first terminal connected to the 11th node, its second terminal connected to the 4th node, and its gate connected to the 4th clock signal terminal.

15. The display panel according to claim 11, wherein, The first power supply terminal and the third power supply terminal share the same power supply terminal, and the second power supply terminal and the fourth power supply terminal share the same power supply terminal.

16. The display panel according to claim 1, wherein, The display panel also includes: The first clock signal line is connected to the first clock signal terminal in the odd-level first shift register unit and the second clock signal terminal in the even-level first shift register unit. The second clock signal line is connected to the second clock signal terminal in the odd-level first shift register unit and the first clock signal terminal in the even-level first shift register unit.

17. The display panel according to claim 10, wherein, The display panel also includes: The fourth clock signal line is connected to the fourth clock signal terminal in each of the first shift register units; A reset signal line is connected to the first reset signal terminal in each of the first shift register units and the second reset signal terminal in each of the second shift register units.

18. A display panel driving method, wherein, The driving method for driving the display panel according to any one of claims 11-17 includes: The first output terminal outputs valid level pulses during the data writing stage, black insertion stage, and sensing stage of the corresponding pixel driving circuit. The second output terminal outputs valid level pulses during the data writing stage, sensing signal writing stage, and data signal write-back stage of the corresponding pixel driving circuit.

19. A display device, wherein, The display device includes the display panel as described in any one of claims 1-17.

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