Semiconductor device structure with micro- and nanostructures for raman characterization

Abstract

The application provides a semiconductor device structure with a micro-nano structure for Raman characterization, comprising: a semiconductor device structure to be measured, comprising: a substrate and a component to be measured; a first test light incident area, a test area and a first test light exit area are formed on the substrate; the component to be measured is formed in the test area; a first optical structure is formed in the first test light incident area and the first test light exit area, so that the component to be measured is embedded in the first optical structure; wherein the first optical structure is used to form a "U" type path for the transmission path of the test light. The technical scheme provided by the application solves the problem of how to change the direction of the test light in the micro-nano structure scale in the Raman test, and more accurately characterizes the information in the component to be measured, while avoiding the noise caused by the background signal of the substrate placed below the sample.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor device structure having micro / nano structures for Raman characterization. Background Technology

[0002] Raman spectroscopy is a rapid, non-destructive optical characterization technique that can provide important information about a sample's material and lattice structure. As a crucial characterization step in the CMOS integrated circuit manufacturing process, it is playing an increasingly critical role. However, with the continuous evolution of CMOS technology nodes, the size of micro- and nano-structures in integrated circuits is constantly shrinking, posing significant challenges to optical characterization techniques like Raman spectroscopy.

[0003] Since CMOS devices are still primarily based on silicon substrates, Raman incident light penetrates deeply into silicon (for example, the penetration depth of commonly used 532nm incident light is about 1µm; the penetration depth of 405nm incident light is about 100nm). CMOS devices are typically fabricated on the surface of a wafer, with a vertical dimension not exceeding 100 nm. The channel layer and dielectric layer, which significantly affect device performance, are even smaller, within the 20nm range. Therefore, within the penetration range of the incident light, the area to be characterized occupies a very small vertical proportion. Using deep ultraviolet incident light (with a penetration depth of about 10nm) can significantly reduce the penetration depth, theoretically increasing the signal proportion of the characterization area in the vertical direction. However, deep ultraviolet incident light has problems such as difficulty in miniaturizing the light spot, poor laser stability, and potential fluorescence signal interference during measurement.

[0004] Furthermore, in common Raman measurements, the incident light is always perpendicular to the sample surface, i.e., in backscattering geometry. In this mode, the incident direction of the light is fixed and immutable. However, for certain anisotropic structures, such as fins, incident light parallel to the fin structure can enhance the response of phonon modes in specific directions, which is beneficial for better characterizing information within the fin structure. However, conventional Raman measurement methods do not meet this requirement. In some advanced testing equipment, the direction of the incident light can be changed by rotating the sample stage, but this mechanical rotation-based adjustment method is relatively crude and difficult to achieve directional changes at the micro / nanoscale.

[0005] Therefore, developing an improved Raman testing system to better characterize the information in the fin structure has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0006] This invention provides a semiconductor device structure with micro / nano structures for Raman characterization, which solves the problem of how to change the direction of the test light at the micro / nano structure scale in Raman testing, and more accurately characterize the information in the device under test, while avoiding noise from the background signal of the substrate below the sample.

[0007] According to a first aspect of the present invention, a semiconductor device structure having micro / nano structures for Raman characterization is provided, comprising: A semiconductor device under test (DUT) structure; the DUT structure includes a substrate and a component under test; the substrate includes a first test light incident region, a test region, and a first test light emitting region; a test light transmission region is located between the first test light incident region and the first test light emitting region; the component under test is formed in the test region; A first optical structure; the first optical structure is formed in the first test light incident region and the first test light emitting region, such that the component under test is embedded in the first optical structure; The first optical structure is used to guide the test light incident on the first test light incident area to the component under test. After passing through the component under test, the test light is emitted from the first test light emitting area to obtain the stress information of the component under test, and is used for the Raman characterization. The transmission path of the test light forms a "U" shaped path.

[0008] Optionally, the first optical structure is a grating structure; the grating structure includes: Waveguide substrate; the waveguide substrate is formed in the first test light incident region and the first test light emitting region; the component under test is embedded in the waveguide substrate; Coupled structure; the coupled structure is formed on the waveguide substrate in the first test light incident region; The coupling structure is formed on the waveguide substrate in the first test light emission region; The grating structure is used to: couple the test light incident on the first test light incident area into the waveguide substrate through the coupling structure, conduct it through the waveguide substrate to the component under test, and then, through the component under test, conduct it through the waveguide substrate to the coupling structure, and then emit the test light from the first test light emitting area through the coupling structure, so that the Raman testing device can obtain the stress information of the component under test for Raman characterization.

[0009] Optionally, a first thin film layer is further included between the waveguide substrate and the substrate. The first thin film layer is used to refract the leaked light emitted from the first surface of the waveguide substrate back into the waveguide substrate, and propagate it through total internal reflection in the waveguide substrate, and finally couple it out through the coupling structure. The first surface of the waveguide substrate represents the side of the waveguide substrate that is close to the substrate.

[0010] Optionally, the material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with said titanium oxide or said niobium oxide.

[0011] Optionally, the grating structure is made of silicon oxide.

[0012] Optionally, the semiconductor device under test is a gate-around device; The component under test is a first process stage structure; the first process stage structure includes a stacked sacrificial material layer and a channel material layer; wherein the first process stage structure is embedded in the grating structure.

[0013] Optionally, the semiconductor device under test is a gate-around device; The component under test is a second process stage structure; the second process stage structure includes several fin structures: each fin structure includes a stacked sacrificial layer and a nanowire-shaped channel layer; wherein the second process stage structure is embedded in the grating structure.

[0014] Optionally, the semiconductor device under test is a gate-around device; The component under test is a third-stage structure; the third-stage structure includes: a stacked sacrificial structure layer and a channel structure layer; a source material layer and a drain material layer, wherein the source material layer and the drain material layer are formed on both sides of the fin structure along a first direction; the first direction is perpendicular to the stacking direction of the sacrificial structure layer and the channel structure layer; wherein the third-stage structure is embedded in the grating structure.

[0015] Optionally, the semiconductor device under test is a gate-around device; The component under test is a fourth-stage process structure; the fourth-stage process structure includes: spaced-stacked channel structure layers; A source region material layer and a drain region material layer are formed on both sides of the fin structure along a first direction; The fourth process stage structure is embedded in the grating structure.

[0016] Optionally, the semiconductor device under test is a gate-around device; The component under test is a fifth-stage process structure; the fifth-stage process structure includes: spaced-stacked channel structure layers; A gate dielectric layer and a gate metal layer; the gate dielectric layer encloses the channel structure layer, and the gate metal layer encloses the gate metal layer; A source region material layer and a drain region material layer are formed on both sides of the fin structure along a first direction; The fifth process stage structure is embedded in the grating structure.

[0017] According to a second aspect of the present invention, a method for fabricating a semiconductor device structure having micro / nano structures for Raman characterization is provided, comprising: A substrate is provided; the substrate includes a first test light incident region, a test region, and a first test light emitting region; A first optical component is formed in the first test light incident area and the first test light emitting area; A component under test (DUT) is formed in the test area; wherein the DUT semiconductor device structure includes the substrate and the DUT; the DUT is embedded in the first optical component; The first optical structure is used to guide the test light incident on the first test light incident area to the component under test, through the component under test, and to emit the test light from the first test light emitting area to obtain the stress information of the component under test for Raman characterization. The transmission path of the test light forms a "U" shaped path.

[0018] According to a third aspect of the present invention, a Raman testing system for a gate-around device is provided, comprising a semiconductor device structure having micro / nano structures for Raman characterization as described in any of the first aspects of the present invention, wherein the Raman testing system for the gate-around device further comprises: A Raman testing apparatus is used to emit test light into the first test light incident area, acquire the test light that passes through the component under test and exits from the first test light exit area, and obtain stress information of the component under test in the ring gate device based on the acquired test light for Raman characterization.

[0019] The semiconductor device structure with micro / nano structures for Raman characterization provided by this invention forms a first optical structure in the semiconductor device structure under test. This first optical structure guides test light incident on the first test light incident region to the device under test. After passing through the device under test, the test light exits from the first test light exit region, resulting in a U-shaped optical path. This allows for the acquisition of stress information of the device under test, which is then used for Raman characterization, thus achieving accurate characterization of the micro / nano structure. As can be seen, the technical solution provided in this application achieves a change in orientation at the micro / nano structure scale, allowing the test light to be incident "parallel" to the direction of the device under test and pass through it. Utilizing the fact that the incident test light is parallel to the direction of the device under test can enhance phonon modes in a specific direction, which is beneficial for better characterizing the information in the device under test. Furthermore, because the perpendicular incident mode of the test light is changed, the test light does not need to penetrate the substrate, avoiding noise from the background signal of the substrate below the sample. In addition, the micro-nano fabrication method used in the grating structure is compatible with CMOS technology; the test light being parallel to the device under test means that the test light is propagated laterally in the device under test, rather than penetrating the device vertically. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a Raman testing system for a ring gate device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the optical path of the test light in the first optical structure and the component under test in a Raman testing system for a ring grating device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a device structure based on the first process stage structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a device structure according to a second process stage structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a device structure based on the third process stage structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a device structure according to the fourth process stage structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a device structure according to the fifth process stage structure provided in an embodiment of the present invention; Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor device structure with micro / nano structures for Raman characterization, according to an embodiment of the present invention. Explanation of reference numerals in the attached figures: 10-grating structure; 101 - Waveguide substrate; 102-Coupled-out structure; 103-coupled structure; 20-substrate; 30 - Component under test; 301 - Sacrificial Material Layer; 302-Channel Material Layer 303 - Sacrificial Layer; 304 - Channel layer; 305 - Sacrificial structural layer; 306 - Channel structure layer; 307 - Source region material layer or drain region material layer; 308 - Gate dielectric layer; 309 - Gate metal layer; 40-Raman test apparatus. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In the Raman spectroscopy characterization stage of CMOS integrated circuit manufacturing, the incident light is always incident perpendicularly to the sample surface, i.e., in backscattering geometry. On the one hand, when the light is incident perpendicularly to the sample surface, the area to be characterized in the longitudinal direction is too small within the penetration range of the incident light, making it impossible to avoid noise from the background signal of the substrate below the sample. On the other hand, when the light is incident perpendicularly to the sample surface, the Raman test information is not ideal for characterizing the sample. However, the incident light parallel to the fin structure can enhance the response of phonon modes in a specific direction, which is beneficial for better characterizing the information in the fin structure. But conventional Raman measurement methods do not meet this requirement. Even in some advanced testing equipment, the direction of the incident light can be changed by rotating the sample stage, but this mechanical rotation-based adjustment method is relatively crude and difficult to achieve directional changes at the micro-nano structure scale.

[0025] In view of this, the inventors of this application propose the following for Raman characterization of micro / nano structures in advanced CMOS nodes: A grating is fabricated within a specific region of the CMOS micro / nano structure to be characterized using a micro / nano fabrication method. The structural characteristics of the grating are utilized to adjust the incident Raman light and its direction at the micro / nano scale, thereby changing the propagation direction of the test light in the CMOS device and altering the exit direction of the emitted light. This allows the Raman testing device to acquire the emitted light, i.e., to make the optical path exhibit a "U"-shaped feature, thus achieving accurate characterization of the micro / nano structure. The micro / nano fabrication method refers to the fabrication method of the grating structure.

[0026] As can be seen, the technical solution provided in this application achieves directional changes at the micro / nano structure scale. It utilizes the fact that incident light parallel to the fin structure can enhance phonon modes in a specific direction, which is beneficial for better characterizing the information in the fin structure. Furthermore, because the perpendicular incident mode of the test light is changed, the test light does not need to penetrate the substrate, avoiding noise from the background signal of the substrate below the sample. In addition, the micro / nano fabrication method used for the grating structure is compatible with CMOS processes.

[0027] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0028] Please refer to Figures 1-8 According to an embodiment of the present invention, a semiconductor device structure having micro / nano structures for Raman characterization is provided, comprising: The semiconductor device under test (DUT) structure includes a substrate 20 and a device under test (DUT) 30. The substrate 20 includes a first test light incident region, a test region, and a first test light emitting region. A test light transmission region is located between the first test light incident region and the first test light emitting region. The DUT 30 is formed in the test region. A first optical structure; the first optical structure is formed in the first test light incident region and the first test light emitting region, such that the component under test 30 is embedded in the first optical structure; the first optical structure is the micro / nano structure used for Raman characterization; The first optical structure is used to guide the test light incident on the first test light incident area to the component under test 30. After passing through the component under test 30, the test light is emitted from the first test light emitting area to obtain the stress information of the component under test 30 and to be used for the Raman characterization. The test light travels in a U-shaped path; please refer to the optical path diagram. Figure 2 .

[0029] The semiconductor device structure with micro / nano structures for Raman characterization provided by the present invention forms a first optical structure in the semiconductor device structure under test, such that the first optical structure transmits the test light incident on the first test light incident region to the component under test, and after passing through the component under test, the test light is emitted from the first test light emitting region, so that the optical path presents a "U" shaped feature, thereby obtaining the stress information of the component under test and using it for Raman characterization; so as to achieve accurate characterization of the micro / nano structure.

[0030] As can be seen, the technical solution provided in this application achieves a change in orientation at the micro / nano structure scale, allowing the test light to be incident "parallel" to the device under test (DUT) and pass through it. Utilizing the fact that the incident test light is parallel to the DUT can enhance phonon modes in a specific direction, which is beneficial for better characterizing the information in the DUT. Furthermore, because the perpendicular incident mode of the test light has been changed, the test light does not need to penetrate the substrate, avoiding noise from the background signal of the substrate below the sample. In addition, the micro / nano fabrication method used for the grating structure is compatible with CMOS technology; "test light parallel to the DUT" means that the test light propagates laterally within the DUT, rather than penetrating it perpendicularly.

[0031] In one embodiment, the first optical structure is a grating structure 10; the grating structure 10 includes: Waveguide substrate 101; the waveguide substrate 101 is formed in the first test light incident region and the first test light emitting region; the component under test 30 is embedded in the waveguide substrate 101; Coupled structure 103; the coupled structure 103 is formed on the waveguide substrate 101 in the first test light incident region; Coupler structure 102; the coupler structure 102 is formed on the waveguide substrate 101 in the first test light emission region; The grating structure 10 is used to: couple the test light incident on the first test light incident area into the waveguide substrate 101 through the coupling structure 103, conduct it through the waveguide substrate 101 to the component under test 30, and conduct it through the waveguide substrate 101 to the coupling structure 102, and emit the test light from the first test light emitting area through the coupling structure 102, so that the Raman testing device 40 can acquire the stress information of the component under test 30 for Raman characterization.

[0032] The incident angle of the test light is greater than the critical angle, so that the test light is totally internally reflected in the grating structure 10.

[0033] The test light consumed by secondary diffraction in the grating structure 10 provided by the present invention is much less than the impact of noise from the vertically incident substrate 20 on the Raman test results.

[0034] In one embodiment, a first thin film layer is further included between the waveguide substrate 101 and the substrate 20, for refracting the leaked light emitted from the first surface of the waveguide substrate 101 back into the waveguide substrate 101, propagating by total internal reflection in the waveguide substrate 101, and finally being coupled out through the coupling structure 102 and captured by the Raman test device 40; the first surface of the waveguide substrate 101 characterizes the side of the waveguide substrate 101 close to the substrate 20.

[0035] The first thin film layer has high and low refractive indices. When the first thin film layer is disposed on the light leakage side of the waveguide substrate 101 (waveguide substrate 101 and the substrate 20), total internal reflection of the test light in the waveguide substrate 101 can be achieved to collect and utilize the energy on the light leakage side of the waveguide substrate 101. This can reduce the light leakage phenomenon caused by secondary diffraction in the waveguide substrate 101, thereby further improving the test accuracy. In one embodiment, the material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with titanium oxide or niobium oxide. Of course, the aforementioned material of the first thin film layer can be composed of other materials, and the present invention is not limited thereto. Any implementation of the material of the first thin film layer is within the protection scope of the present invention.

[0036] In one embodiment, the grating structure 10 is made of silicon oxide. Of course, the grating structure 10 can be made of other materials, and this invention is not limited thereto; any implementation of the grating structure 10 using any material is within the scope of protection of this invention.

[0037] In one embodiment, the semiconductor device under test is a gate-around device; The component under test 30 is a first process stage structure; the first process stage structure includes: a stacked sacrificial material layer 301 and a channel material layer 302; wherein, the first process stage structure is embedded in the grating structure 10; the first process stage structure is as follows: Figure 3 As shown.

[0038] In one embodiment, the semiconductor device under test is a gate-around device; The component under test 30 is a second-stage structure; the second-stage structure includes several fin structures: each fin structure includes a stacked sacrificial layer 303 and a nanowire-shaped channel layer 304; wherein, the second-stage structure is embedded in the grating structure 10; the second-stage structure is as follows Figure 4 As shown.

[0039] In one embodiment, the semiconductor device under test is a gate-around device; The component under test 30 is a third-stage structure; the third-stage structure includes: a stacked sacrificial structure layer 305 and a channel structure layer 306; a source region material layer 307 and a drain region material layer 307, the source region material layer 307 and the drain region material layer 307 being formed on both sides of the fin structure along a first direction; the first direction is perpendicular to the stacking direction of the sacrificial structure layer 305 and the channel structure layer 306; wherein, the third-stage structure is embedded in the grating structure 10; the third-stage structure is as follows Figure 5 As shown.

[0040] In one embodiment, the semiconductor device under test is a gate-around device; The component under test 30 is a fourth process stage structure; the fourth process stage structure includes: a channel structure layer 306 stacked at intervals. Source region material layer 307 and drain region material layer 307 are formed on both sides of the fin structure along the first direction; The fourth process stage structure is embedded in the grating structure 10; the fourth process stage structure is as follows: Figure 6 As shown.

[0041] In one embodiment, the semiconductor device under test is a gate-around device; The component under test 30 is a fifth process stage structure; the fifth process stage structure includes: a channel structure layer 306 stacked at intervals; A gate dielectric layer 308 and a gate metal layer 309; the gate dielectric layer 308 encloses the channel structure layer 306, and the gate metal layer 309 encloses the gate metal layer 309; Source region material layer 307 and drain region material layer 307 are formed on both sides of the fin structure along the first direction; The fifth process stage structure is embedded in the grating structure 10; the fifth process stage structure is as follows: Figure 7 As shown.

[0042] Secondly, according to an embodiment of the present invention, a method for fabricating a semiconductor device structure having a micro / nano structure for Raman characterization is also provided, the process flow diagram of which is shown below. Figure 8 As shown, the method includes: S11: A substrate 20 is provided; the substrate 20 includes a first test light incident area, a test area, and a first test light emitting area; S12: A first optical component is formed in the first test light incident area and the first test light emitting area; wherein, the optical component can be a grating structure 10, and the fabrication process of the grating structure 10 is a process that should be known by those skilled in the art. The innovation of the present invention lies in the compatibility of the grating structure 10 with semiconductor processes, and this combined structure can improve the accuracy of Raman characterization. S13: A device under test (DUT) 30 is formed in the test area; wherein the semiconductor device under test structure includes the substrate 20 and the DUT 30; the DUT 30 is embedded in the first optical component; The first optical structure is used to guide the test light incident on the first test light incident area to the component under test 30, through the component under test 30, and to emit the test light from the first test light emitting area to obtain the stress information of the component under test 30 for Raman characterization. The transmission path of the test light forms a "U" shaped path.

[0043] In the first embodiment, when the component under test 30 is a structure of the first process stage, step S13: forming the component under test 30 in the test area includes: A sacrificial material layer 301 and a channel material layer 302 are formed on the substrate 20; wherein the first process stage structure is embedded in the grating structure 10.

[0044] The structure of the semiconductor device under test includes the substrate 20 and the first process stage; the structure of the first process stage is as follows: Figure 3 As shown.

[0045] In the second embodiment, when the component under test 30 is a structure of the second process stage, step S13: forming the component under test 30 in the test area includes: Several fin structures are formed on the substrate 20: each fin structure includes a stacked sacrificial layer 303 and a nanowire-shaped channel layer 304; wherein the second process stage structure is embedded in the grating structure 10.

[0046] The structure of the semiconductor device under test includes the substrate 20 and the second process stage; the structure of the second process stage is as follows: Figure 4 As shown.

[0047] In the third embodiment, when the component under test 30 is a structure of the third process stage, step S13: forming the component under test 30 in the test area includes: A sacrificial structure layer 305 and a channel structure layer 306, a source region material layer 307 and a drain region material layer 307 are formed on the substrate 20, wherein the third process stage structure is embedded in the grating structure 10.

[0048] The structure of the semiconductor device under test includes the substrate 20 and the third process stage; the structure of the third process stage is as follows: Figure 5 As shown.

[0049] In the fourth embodiment, when the component under test 30 is a fourth-stage process structure, step S13: forming the component under test 30 in the test area includes: A channel structure layer 306, a source region material layer 307, and a drain region material layer 307 are formed on the substrate 20 at intervals; wherein the fourth process stage structure is embedded in the grating structure 10.

[0050] The structure of the semiconductor device under test includes the substrate 20 and the fourth process stage; the structure of the fourth process stage is as follows: Figure 6 As shown.

[0051] In the fifth embodiment, when the component under test 30 is a structure of the fifth process stage, step S13: forming the component under test 30 in the test area includes: The fifth process stage structure formed on the substrate 20 includes: a channel structure layer 306 stacked at intervals, a gate dielectric layer 308 and a gate metal layer 309; the gate dielectric layer 308 encloses the channel structure layer 306, and the gate metal layer 309 encloses the gate metal layer 309; a source region material layer 307 and a drain region material layer 307. The fifth process stage structure is embedded in the grating structure 10.

[0052] The structure of the semiconductor device under test includes the substrate 20 and the fifth process stage; the structure of the fifth process stage is as follows: Figure 7 As shown. In the aforementioned step S13: the fabrication process of the grating structure 10 in each embodiment of forming the component under test 30 in the test area is compatible with the fabrication process of structures at different process stages, and is feasible.

[0053] In addition, according to an embodiment of the present invention, a Raman testing system for a gate-ring device is also provided, such as... Figure 1 As shown, the semiconductor device structure having micro / nano structures for Raman characterization as described in any of the foregoing embodiments of the present invention, the Raman testing system for the gate-around device further includes: Raman testing device 40; the Raman testing device 40 is used to emit test light to the first test light incident area, and acquire the test light that passes through the test component 30 and exits from the first test light exit area, and obtain the stress information of the test component 30 in the ring grid device based on the acquired test light, so as to perform Raman characterization. The test light's transmission path forms a "U" shaped path; the optical path diagram is as follows. Figure 2 As shown.

[0054] The following section uses the structure of the first process stage as an example to explain in detail the process of using a ring gate device Raman testing system to conduct Raman testing on the structure of the first process stage to obtain initial stress information: where the initial stress information characterizes the stress information in the structure of the first process stage. Step S11: Provide a substrate; the substrate includes a first test light incident area, a test area, and a first test light emitting area; Step S12: Form a grating structure in the first test light incident area and the first test light emitting area; Step S13: Form a first process stage structure in the test area; at this time, the gate ring device includes a substrate and the first process stage structure; the first process stage structure is embedded in the grating structure; The grating structure is used to guide the test light incident on the first test light incident area to the component under test, through the first process stage structure, and emit the test light from the first test light emitting area to obtain the initial stress information of the first process stage structure for Raman characterization; wherein the transmission path of the test light forms a "U" shaped path.

[0055] Based on the determined stress information, the impact of corresponding process steps on channel stress is analyzed.

[0056] In addition, different stress information determined by implementing the same process step under different process conditions can be obtained; by comparing the different stress information, the influence of different process conditions on the stress at the corresponding position of the channel can be analyzed. The Raman test process for the ring gate device in the other four stages is similar and will not be described in detail here; the first stress information of the structure in the second process stage, the second stress information of the third process stage, the third stress information of the fourth process stage, and the fourth stress information of the fifth process stage are obtained respectively. Of course, stress information of other process stages can also be obtained, and this application is not limited thereto. The aforementioned stress information can be any information that matches (or can be understood as being able to characterize) the corresponding stress and / or stress change. Finally, based on the stress information determined above, the influence of the corresponding process step on the channel stress is analyzed. Different stress information determined by implementing the same process step under different process conditions can also be obtained; by comparing the different stress information, the influence of different process conditions on the stress at the corresponding position of the channel can be analyzed.

[0057] In summary, the Raman testing scheme provided by this invention can achieve better characterization of information in the fin structure within the constraints of existing Raman architectures (vertical laser incidence, microscopic observation of the laser's impact point and sample position coaxial with the laser), while avoiding noise from the background signal on the substrate below the sample. Furthermore, the micro-nano fabrication method used for the grating structure is compatible with CMOS processes.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device having a micro / nano structure for Raman characterization, characterized in that, include: The semiconductor device under test (DUT) structure includes a substrate and a component under test; the substrate includes a first test light incident region, a test region, and a first test light emitting region. The test light transmission region is located between the first test light incident region and the first test light emitting region; the component under test is formed in the test region; A first optical structure; the first optical structure is formed in the first test light incident region and the first test light emitting region, such that the component under test is embedded in the first optical structure. The first optical structure is a grating structure, the grating structure comprising: a waveguide substrate; the waveguide substrate is formed in the first test light incident region and the first test light emitting region; the component under test is embedded in the waveguide substrate; a coupling structure; the coupling structure is formed on the waveguide substrate in the first test light incident region; and a coupling structure; the coupling structure is formed on the waveguide substrate in the first test light emitting region. The coupling structure and the coupling structure are used to: transmit the test light incident on the first test light incident region to the component under test and transmit it within the component under test; and to emit the test light from the first test light emitting region to obtain stress information of the component under test for Raman characterization. The first optical structure is used to guide the test light incident on the first test light incident area to the component under test, through the component under test, and emit the test light from the first test light emitting area to obtain the stress information of the component under test for Raman characterization; wherein the transmission path of the test light is a "U" shaped path.

2. The semiconductor device having a micro / nano structure for Raman characterization according to claim 1, characterized in that, The waveguide substrate and the substrate further include a first thin film layer, which is used to refract the leaked light emitted from the first surface of the waveguide substrate back into the waveguide substrate, and propagate it through total internal reflection in the waveguide substrate, and finally couple it out through the coupling structure. The first surface of the waveguide substrate characterizes the side of the waveguide substrate closest to the substrate.

3. The semiconductor device having a micro / nano structure for Raman characterization according to claim 2, characterized in that, The material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with titanium oxide or niobium oxide.

4. The semiconductor device having a micro / nano structure for Raman characterization according to claim 3, characterized in that, The grating structure is made of silicon oxide.

5. The semiconductor device having a micro / nano structure for Raman characterization according to claim 4, characterized in that, The semiconductor device under test has a gate-around structure; The component to be tested is: a structure of the first process stage; The structure of the first process stage includes: a stacked sacrificial material layer and a channel material layer; The first process stage structure is embedded in the grating structure.

6. The semiconductor device having a micro / nano structure for Raman characterization according to claim 4, characterized in that, The semiconductor device under test has a gate-around structure; The component to be tested is: a structure of the second process stage; The second process stage structure includes: several fin structures: each fin structure includes a sacrificial layer and a nanowire-shaped channel layer; The second process stage structure is embedded in the grating structure.

7. The semiconductor device having a micro / nano structure for Raman characterization according to claim 6, characterized in that, The semiconductor device under test has a gate-around structure; The component under test is a structure of the third process stage; The third process stage structure includes: a stacked sacrificial structure layer and a channel structure layer; A source region material layer and a drain region material layer are formed on both sides of the fin structure along a first direction; The third process stage structure is embedded in the grating structure.

8. The semiconductor device having a micro / nano structure for Raman characterization according to claim 6, characterized in that, The semiconductor device under test has a gate-around structure; The component to be tested is a fourth-stage process structure; The fourth process stage structure includes: a channel structure layer stacked at intervals; A source region material layer and a drain region material layer are formed on both sides of the fin structure along a first direction; The fourth process stage structure is embedded in the grating structure.

9. The semiconductor device having a micro / nano structure for Raman characterization according to claim 6, characterized in that, The semiconductor device under test has a gate-around structure; The component to be tested is a structure of the fifth process stage; The fifth process stage structure includes: a channel structure layer stacked at intervals; A gate dielectric layer and a gate metal layer; the gate dielectric layer encloses the channel structure layer, and the gate metal layer encloses the gate metal layer; A source region material layer and a drain region material layer are formed on both sides of the fin structure along a first direction; The fifth process stage structure is embedded in the grating structure.

10. A method for fabricating a semiconductor device having a micro / nano structure for Raman characterization, characterized in that, For fabricating a semiconductor device having a micro / nano structure for Raman characterization as described in any one of claims 1 to 9, comprising: A substrate is provided; the substrate includes a first test light incident region, a test region, and a first test light emitting region; A first optical structure is formed in the first test light incident region and the first test light emitting region. The first optical structure is a grating structure, which includes: a waveguide substrate; the waveguide substrate is formed in the first test light incident region and the first test light emitting region; a component under test (DUT) is embedded in the waveguide substrate; a coupling structure; the coupling structure is formed on the waveguide substrate in the first test light incident region; and a coupling structure; the coupling structure is formed on the waveguide substrate in the first test light emitting region. The coupling structure and the coupling structure are used to: transmit the test light incident on the first test light incident region to the DUT and transmit it within the DUT; and the coupling structure is used to emit the test light from the first test light emitting region to obtain stress information of the DUT for Raman characterization. A device under test (DUT) is formed in the test area; wherein the DUT semiconductor device structure includes the substrate and the DUT. The first optical structure is used to horizontally guide the light beam incident on the first test light incident area to the component under test, through the component under test, and emit the test light from the first test light emitting area for Raman characterization to obtain stress information of the component under test.

11. A Raman testing system for a ring-ring gate device, characterized in that, include: The semiconductor device having a micro / nano structure for Raman characterization according to any one of claims 1-9, wherein the Raman testing system for the gate-around device further comprises: Raman testing apparatus; The Raman testing device is used to emit test light into the first test light incident area, acquire the test light that passes through the component under test and exits from the first test light exit area, and obtain the stress information of the component under test in the ring gate device based on the acquired test light for Raman characterization.

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