Power supply timing control method within module, circuit and electronic device thereof

Abstract

The application relates to a module power timing control method, a circuit thereof and electronic equipment. The module power timing control method comprises the following steps: in a power-on stage, a first power chip is controlled to successively start outputting a first power and a third power, and the level of a third control signal is pulled high; the voltage division of the first power is collected and compared with the voltage division of a reference power; and in response to the voltage division of the first power being greater than the voltage division of the reference power, the level of a second control signal is pulled high to control a second power chip to start outputting a second power; in a power-off stage, the first power chip is controlled to successively stop outputting the third power and the first power, and the level of the third control signal is pulled low; the voltage division of the third power is collected and compared with the voltage division of the reference power; and in response to the voltage division of the third power being less than the voltage division of the reference power, the level of the second control signal is pulled low to control the second power chip to stop outputting the second power.

Description

Technical Field

[0001] This invention relates to the field of integrated module technology, and in particular to a power supply timing control method, circuit, and electronic device within a module. Background Technology

[0002] Currently, modular products are widely used in various industries, especially integrated modules such as SOCs (System-on-a-Chip) in automotive and consumer electronics. As system computational demands increase, SOC modules require more and more power supply branches, leading to a gradual increase in overall power consumption, sometimes reaching hundreds of watts. Consequently, the power supply current of the module has increased exponentially from a few amperes to tens of amperes. Taking the automotive field as an example, to improve functional safety levels, a dual-system solution of SOC + MCU (System-on-a-Chip + Microcontroller Unit) is typically used. The power-on and power-off logic of the SOC module is usually controlled by a PMIC (Power Management Chip), but the output current capability of the PMIC is limited by the size of its internal MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), preventing it from outputting currents as high as tens of amperes.

[0003] To address this issue, existing design solutions primarily rely on modular SOC development, using PMIC and MCU to jointly control the overall power-on timing of the SOC module. However, when SOC modules are used on different domain control boards, their power-on cannot be fully controlled internally. Furthermore, the control timing between the SOC module and the MCU cannot be standardized across different customers, hindering the achievement of the original intention of modular SOC design: minimizing control impacts with other devices, completing internal control, and outputting corresponding results to other peripherals according to functional requirements, thus achieving unification and standardization. Summary of the Invention

[0004] One advantage of this invention is that it provides a power supply timing control method, circuit, and electronic equipment within a module, which can realize the power-on and power-off timing control of multiple power supplies in a SOC within the module.

[0005] Another advantage of the present invention is that it provides a power supply timing control method, circuit, and electronic device within a module. In one embodiment of the present invention, the power supply timing control method within the module can compare the power-on or power-off voltage differences between multiple power supplies by using combinational logic circuits, and output control logic levels to realize the power-on and power-off timing logic of each power supply required by the SOC module.

[0006] Another advantage of this invention is that it provides a power supply timing control method, circuit, and electronic equipment within a module, wherein expensive materials or complex structures are not required to achieve the aforementioned objectives. Therefore, this invention successfully and effectively provides a solution that not only offers a simple power supply timing control method, circuit, and electronic equipment within a module, but also increases the practicality and reliability of the method, circuit, and electronic equipment.

[0007] To achieve at least one of the above-mentioned advantages or other advantages and objectives of the present invention, the present invention provides a power supply timing control method within a module, comprising the steps of:

[0008] Power-on phase:

[0009] When the level of the first control signal output by the external chip is pulled high, the first power chip is controlled to start outputting the first power supply and the third power supply to the SOC module in sequence, and pulls the level of the third control signal output through the SOC module high.

[0010] The voltage drop of the first power supply is collected and compared with the voltage drop of the reference power supply to determine whether the voltage drop of the first power supply is greater than the voltage drop of the reference power supply; and

[0011] In response to the voltage division of the first power supply being greater than that of the reference power supply, the level of the second control signal is pulled high to control the second power chip to start outputting the second power supply to the SOC module;

[0012] Power-off phase:

[0013] When the level of the first control signal output by the external chip is pulled low, the first power chip is controlled to stop outputting the third power supply and the first power supply in turn, and the level of the third control signal output by the SOC module is pulled low.

[0014] The voltage drop of the third power supply is collected and compared with the voltage drop of the reference power supply to determine whether the voltage drop of the third power supply is less than the voltage drop of the reference power supply; and

[0015] In response to the voltage division of the third power supply being less than that of the reference power supply, the level of the second control signal is pulled low to control the second power chip to stop outputting the second power supply.

[0016] According to one embodiment of this application, the first power chip sets the power-on time difference and power-off time difference between the first power supply and the third power supply according to OTP, wherein the power-on time difference between the first power supply and the third power supply is greater than the power-on time difference between the first power supply and the second power supply, and the power-off time difference between the third power supply and the first power supply is greater than the power-off time difference between the second power supply and the first power supply.

[0017] According to one embodiment of this application, the power supply timing control method within the module further includes the following steps:

[0018] When the external chip issues a SOC power-on instruction, before raising the level of the first control signal, it first raises the level of the fourth control signal to control the third power chip to start outputting the reference power to the SOC module, causing some modules within the SOC module to start working; and

[0019] When the external chip issues a SOC power-down instruction, it first pulls down the level of the first control signal, and then pulls down the level of the fourth control signal, so as to control the third power chip to stop outputting the reference power after the first power chip stops outputting the first power supply.

[0020] According to another aspect of this application, this application further provides an in-module power supply timing control circuit for controlling the timing of power supply to the SOC module by a first power chip, a second power chip, and a third power chip. The in-module power supply timing control circuit includes:

[0021] The first comparator has two input terminals that are electrically connected to the first power supply output by the first power chip and the reference power supply output by the third power chip, respectively, to compare the magnitude of the voltage division of the first power supply and the voltage division of the reference power supply.

[0022] The second comparator has two input terminals that are electrically connected to the third power supply output by the first power chip and the reference power supply output by the third power chip, respectively, to compare the magnitude of the voltage division of the third power supply and the voltage division of the reference power supply.

[0023] An OR gate device, one input of which is electrically connected to the output of the second comparator, and the other input of which is electrically connected to the output of the SOC module to receive a third control signal from the SOC module, for outputting a signal according to the principle of high-to-high; and

[0024] An AND gate device, one input of which is electrically connected to the output of an OR gate device, and the other input of which is electrically connected to the output of the first comparator. The output of the AND gate device is used to be electrically connected to the second power supply chip, and is used to output a second control signal to the second power supply chip according to the principle of all high to high.

[0025] According to one embodiment of this application, the first comparator includes a first comparator circuit chip, a first voltage divider sampling circuit electrically connected to the positive input terminal of the first comparator circuit chip, a second voltage divider sampling circuit electrically connected to the negative input terminal of the first comparator circuit chip, and a first comparison signal output circuit electrically connected to the output terminal of the first comparator circuit chip; the first voltage divider sampling circuit is used to acquire the voltage division of the first power supply; the second voltage divider sampling circuit is used to acquire the voltage division of the reference power supply; and the first comparison signal output circuit is electrically connected to one input terminal of the AND gate device.

[0026] According to one embodiment of this application, the first voltage divider sampling circuit includes a first resistor for grounding and a second resistor for electrical connection to the first power supply, both of which are electrically connected to the positive input terminal of the first comparator circuit chip; the second voltage divider sampling circuit includes a third resistor for grounding and a fourth resistor for electrical connection to the reference power supply, both of which are electrically connected to the negative input terminal of the first comparator circuit chip; the first comparison signal output circuit includes a fifth resistor electrically connected to the output terminal of the first comparator circuit chip, a first capacitor for grounding, and a first diode, the negative terminal of the first diode being electrically connected to the fifth resistor and the first capacitor, and the positive terminal of the first diode being electrically connected to one input terminal of the AND gate device.

[0027] According to one embodiment of this application, the second comparator includes a second comparator circuit chip, a third voltage divider sampling circuit electrically connected to the positive input terminal of the second comparator circuit chip, a fourth voltage divider sampling circuit electrically connected to the negative input terminal of the second comparator circuit chip, and a second comparator signal output circuit electrically connected to the output terminal of the second comparator circuit chip; the third voltage divider sampling circuit is used to acquire the voltage division of the third power supply; the fourth voltage divider sampling circuit is used to acquire the voltage division of the reference power supply; and the second comparator signal output circuit is electrically connected to one input terminal of the OR gate device.

[0028] According to one embodiment of this application, the third voltage divider sampling circuit includes a sixth resistor for grounding and a seventh resistor for electrical connection to the third power supply, both of which are electrically connected to the positive input terminal of the second comparator circuit chip; the fourth voltage divider sampling circuit includes an eighth resistor for grounding and a ninth resistor for electrical connection to the reference power supply, both of which are electrically connected to the negative input terminal of the second comparator circuit chip; the second comparison signal output circuit includes a tenth resistor electrically connected to the output terminal of the second comparator circuit chip and a second capacitor for grounding, both of which are electrically connected to one input terminal of the OR gate device.

[0029] According to one embodiment of this application, the OR gate device includes an OR gate circuit chip and a second diode. One input terminal of the OR gate circuit chip is electrically connected to the tenth resistor and the second capacitor, and the other input terminal of the OR gate circuit chip is electrically connected to the output terminal of the SOC module. The negative terminal of the second diode is electrically connected to the output terminal of the OR gate circuit chip, and the positive terminal of the second diode is electrically connected to the other input terminal of the AND gate device.

[0030] According to another aspect of this application, this application further provides an electronic device, the electronic device including the power timing control circuit within the module described in any of the above. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the power-on phase of a module-based power timing control method according to an embodiment of the present invention.

[0032] Figure 2 A flowchart illustrating the in-module power timing control method during the power-down phase according to the above embodiment of the present invention is shown.

[0033] Figure 3 A schematic diagram showing the power-on timing requirements of the three power supplies A, B, and C in a SOC module is provided.

[0034] Figure 4 A schematic diagram showing the power-down timing requirements of the three power supplies A, B, and C in a SOC module is provided.

[0035] Figure 5 This is a schematic diagram of the power supply timing control circuit within a module according to an embodiment of the present invention;

[0036] Figure 6 An example of a power supply timing control circuit within a module according to the above embodiments of the present invention is shown.

[0037] Key component symbols: 1. First power supply chip; 2. Second power supply chip; 3. Third power supply chip; 4. SOC module; 10. Power timing control circuit within the module; 11. First comparator; 12. Second comparator; 13. OR gate; 14. AND gate; A. First power supply; B. Second power supply; C. Third power supply; O. Reference power supply; enable1. First control signal; enable2. Second control signal; enable3. Third control signal; enable4. Fourth control signal; R935, first resistor; R930, second resistor; R936, third resistor; R931, fourth resistor; R934, fifth resistor; R2483, sixth resistor; R2480, seventh resistor; R2484, eighth resistor; R2481, ninth resistor; R2482, tenth resistor; C1608, first capacitor; C8398, second capacitor; D95, first diode; D97, second diode; U87, OR gate chip; U91, AND gate chip.

[0038] The above description of the main component symbols, together with the accompanying drawings and specific embodiments, provides a more detailed explanation of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] Considering that existing design schemes are mainly based on SOC modular development, using PMIC and MCU to jointly control the overall power-on timing of the SOC module; however, when the SOC module is used on different domain control boards, the power-on of the SOC module cannot be fully controlled internally, and the control timing development between the SOC module and MCU cannot achieve modular uniformity across different customers, which is not conducive to realizing the original intention of SOC modular design. Therefore, this application provides a power supply timing control method within a module, as well as its circuit and electronic equipment, which can realize the power-on and power-off timing control of multiple power supplies within the SOC module.

[0043] Specifically, see the attached document. Figures 1 to 5 As shown, one embodiment of the present invention provides a power supply timing control method within a module, used to control the timing of three types of power chips supplying power to a SOC module 4. These three types of power chips include a first power chip 1 for outputting multiple power supplies (such as a first power supply A and a third power supply C), a second power chip 2 for outputting a high-current power supply (such as a second power supply B), and a third power chip 3 for outputting a reference power supply (such as a reference power supply O). The second power chip 2 supports OTP (One Time Programmable) functionality, allowing for automatic configuration of the power supply's on / off timing. Furthermore, as... Figure 3 As shown, according to the power-on requirements, the power-on of the second power supply B must be later than that of the first power supply A, and earlier than that of the third power supply C; Figure 4 As shown, according to the power-off requirements, the power-off of the second power supply B must be later than that of the third power supply C, but earlier than that of the first power supply A; that is to say, the first power supply A, the second power supply B, and the third power supply C must be powered on in sequence, and the third power supply C, the second power supply B, and the first power supply A must be powered off in sequence.

[0044] More specifically, such as Figure 1 and Figure 2 As shown, the power supply timing control method within this module may include the following steps:

[0045] Power-on phase:

[0046] S110: When the level of the first control signal enable1 output by the external chip MCU is pulled high, the first power chip 1 is controlled to start outputting the first power supply A and the third power supply C to the SOC module 4 in sequence, and the level of the third control signal enable3 output by the SOC module 4 is pulled high.

[0047] S120: Collect the voltage drop of the first power supply A and compare it with the voltage drop of the reference power supply O to determine whether the voltage drop of the first power supply A is greater than the voltage drop of the reference power supply O; and

[0048] S130: In response to the voltage division of the first power supply A being greater than the voltage division of the reference power supply O, the level of the second control signal enable2 is pulled high to control the second power chip 2 to start outputting the second power supply B to the SOC module.

[0049] Power-off phase:

[0050] S210: When the level of the first control signal enable1 output by the external chip MCU is pulled low, the first power chip 1 is controlled to stop outputting the third power supply C and the first power supply A in sequence, and the level of the third control signal enable3 output by the SOC module 4 is pulled low.

[0051] S220: Collect the voltage drop of the third power supply C and compare it with the voltage drop of the reference power supply O to determine whether the voltage drop of the third power supply C is less than the voltage drop of the reference power supply O; and

[0052] S230: In response to the voltage division of the third power supply C being less than the voltage division of the reference power supply O, the level of the second control signal enable2 is pulled low to control the second power chip 2 to stop outputting the second power supply B.

[0053] It is worth noting that the first power chip 1 of this application sets the power-on time difference and power-off time difference between the first power supply A and the third power supply C according to the OTP. The power-on time difference between the first power supply A and the third power supply C is greater than the power-on time difference between the first power supply A and the second power supply B, and the power-off time difference between the third power supply C and the first power supply A is greater than the power-off time difference between the second power supply B and the first power supply A. It is understandable that since the voltage value of the first power supply A gradually increases before power-on stabilization, and the voltage value of the third power supply C gradually decreases before power-off stabilization, and the second power supply B can only be powered on after the first power supply A has stabilized its output, and can only be powered off after the third power supply C has stabilized its shutdown, this application determines whether the first power supply A is stably outputting by comparing the voltage division of the first power supply A with the voltage division of the reference power supply O during the power-on phase, and determines whether the third power supply C is stably shut down by comparing the voltage division of the third power supply C with the voltage division of the reference power supply O during the power-off phase.

[0054] Thus, during the power-on phase, such as Figure 5As shown, when the first control signal enable1 output by the external chip MCU goes high, the first power chip 1 first starts to output the first power supply A to the SOC module 4. At this time, the voltage division of the first power supply A is compared with the voltage division of the reference power supply O to determine whether the first power supply A has reached a stable value. When the voltage division of the first power supply A is greater than the voltage division of the reference power supply O (indicating that the first power supply A has reached a stable value), the second power chip 2 is controlled to start outputting the second power supply B to the SOC module 4. Finally, the first power chip 1 starts to output the third power supply C to the SOC module 4 after a delay of a set value (i.e., a set power-on time difference), thereby realizing the timing requirement of powering on the first power supply A, the second power supply B, and the third power supply C in sequence.

[0055] During the power-off phase, such as Figure 5 As shown, when the level of the first control signal enable1 output by the external chip MCU is pulled low, the first power chip 1 first stops outputting the third power supply C. At this time, the voltage division of the third power supply C is compared with the voltage division of the reference power supply O to determine whether the third power supply C is stably turned off. When the voltage division of the third power supply C is less than the voltage division of the reference power supply O (indicating that the third power supply C has stopped outputting), the second power chip 2 is controlled to stop outputting the second power supply B. Finally, the first power chip 1 stops outputting the third power supply C again after a delay set value (i.e., the set power-down time difference), thereby realizing the timing requirement of powering down the third power supply C, the second power supply B, and the first power supply A in sequence.

[0056] Furthermore, to ensure that the SOC module 4 operates normally during power-on and power-off processes, the third power chip 3 needs to start outputting the reference power supply O to the SOC module 4 first during the power-on phase and stop outputting the reference power supply O last during the power-off phase; therefore, the power timing control method within the module of this application further includes the following steps:

[0057] When the external MCU issues a SOC power-on instruction, before raising the level of the first control signal, the level of the fourth control signal enable4 is raised first to control the third power chip 3 to start outputting reference power O to the SOC module 4, causing some modules within the SOC module 4 to start working; and

[0058] When the external chip MCU issues a SOC power-down instruction, it first pulls down the level of the first control signal, and then pulls down the level of the fourth control signal enable4, so as to control the third power chip 3 to stop outputting the reference power supply O after the first power chip 1 stops outputting the first power supply A.

[0059] According to another aspect of this application, such as Figure 5 and Figure 6As shown, one embodiment of this application further provides a power supply timing control circuit within a module, used to control the timing of power supply from a first power chip 1, a second power chip 2, and a third power chip 3 to a SOC module 4. The output terminals of the first power chip 1, the second power chip 2, and the third power chip 3 are all electrically connected to the SOC module 4, and the input terminals of the first power chip 1 and the third power chip 3 are all electrically connected to an external MCU chip. When the external MCU chip issues a SOC power-on instruction: firstly, the level of the fourth control signal enable4 input to the third power chip 3 is pulled high to control the third power chip 3 to start outputting reference power O to the SOC module 4; then, the level of the first control signal enable1 input to the first power chip 1 is pulled high to control the first power chip 1 to start outputting the first power supply A and the third power supply C sequentially. When the external chip MCU issues a SOC power-down instruction: first, pull down the level of the first control signal enable1 input to the first power chip 1 to control the first power chip 1 to stop outputting the third power supply C and the first power supply A in sequence; finally, after the first power supply A stops outputting, pull down the level of the fourth control signal enable4 input to the third power chip 3 to control the third power chip 3 to stop outputting the reference power supply O.

[0060] More specifically, such as Figure 5 As shown, the power timing control circuit 10 within this module may include: a first comparator 11, a second comparator 12, an OR gate device 13, and an AND gate device 14; the two input terminals of the first comparator 11 are respectively electrically connected to the first power supply A output by the first power chip 1 and the reference power supply O output by the third power chip 3, to compare the voltage division of the first power supply A with the voltage division of the reference power supply O; the two input terminals of the second comparator 12 are respectively electrically connected to the third power supply C output by the first power chip 1 and the reference power supply O output by the third power chip 3, to compare the voltage division of the third power supply C with the voltage division of the reference power supply O; the OR gate device 14... One input terminal of the OR gate 13 is electrically connected to the output terminal of the second comparator 12, and the other input terminal of the OR gate 13 is electrically connected to the output terminal of the SOC module 4 to receive the third control signal enable3 sent by the SOC module 4, and output the signal according to the logic principle of high as high; one input terminal of the AND gate 14 is electrically connected to the output terminal of the OR gate 13, and the other input terminal of the AND gate 14 is electrically connected to the output terminal of the first comparator 11, and the output terminal of the AND gate 14 is electrically connected to the second power chip 2, and outputs the second control signal enable2 to the second power chip 2 according to the logic principle of all high as high.

[0061] Thus, as Figure 5As shown, when the level of the first control signal enable1 is pulled high to control the first power chip 1 to start outputting the first power supply A, the level of the third control signal enable3 is also pulled high. Therefore, regardless of whether the signal level output by the second comparator 12 to the OR gate device 13 is high or low, the signal level output by the OR gate device 13 will always be high. If the first power supply A does not reach a stable value, the signal level output by the first comparator 11 to the AND gate device 14 will be low. At this time, the level of the second control signal enable2 output by the AND gate device 14 will be low, and the second power chip 2 will not... The first power supply chip 1 outputs the second power supply B to the SOC module 4. Once the first power supply A reaches a stable value, the signal level output from the first comparator 11 to the AND gate 14 will be pulled high. At this time, the level of the second control signal enable2 output by the AND gate 14 will also be pulled high, controlling the second power chip 2 to start outputting the second power supply B to the SOC module 4. Finally, after a period of time since the second power supply B started outputting, the first power chip 1 starts outputting the third power supply C to the SOC module 4, thus achieving the sequential power-on control of the first power supply A, the second power supply B, and the third power supply C.

[0062] like Figure 5 As shown, when the level of the first control signal enable1 is pulled low to control the first power chip 1 to stop outputting the third power supply C, the level of the third control signal enable3 is also pulled low. If the third power supply C does not completely stop outputting, the signal level output by the second comparator 12 to the OR gate device 13 is high. At this time, the signal level output by the OR gate device 13 to the AND gate device 14 is also high, so that the level of the second control signal enable2 output by the AND gate device 14 remains high (since the first power supply A has not stopped outputting, the signal level output by the first comparator 11 to the AND gate device 14 is always high). The second power chip 2 continues to output the second power supply B until the third power supply C completely stops outputting. Only then is the signal level of the second comparator 12 output to the OR gate 13 pulled low. At this time, the signal level of the OR gate 13 output to the AND gate 14 is also pulled low, causing the level of the second control signal enable2 output by the AND gate 14 to be pulled low, thereby controlling the second power chip 2 to stop outputting the second power supply B. Finally, after a period of time when the second power supply B stops outputting, the first power chip 1 stops outputting the third power supply C, thereby realizing the sequential power-down control of the third power supply C, the second power supply B, and the first power supply A.

[0063] It is worth noting that the first power chip 1 mentioned in this application may, but is not limited to, be implemented as a PMIC chip, so as to sequentially output the first power supply A and the third power supply C according to the OTO setting. In addition, the first power supply A may, but is not limited to, be implemented as VDDQ-DDR1-1V1, that is, a power supply with a voltage of 1.1V; the third power supply C may, but is not limited to, be implemented as VDDQ-DDR1-0V8, that is, a power supply with a voltage of 0.8V; and the reference power supply O may, but is not limited to, be implemented as VDD-PERI-3V3, that is, a power supply with a voltage of 3.3V.

[0064] Optionally, such as Figure 6 As shown, the first comparator 11 may include a first comparator circuit chip, a first voltage divider sampling circuit electrically connected to the positive input terminal IN+ of the first comparator circuit chip, a second voltage divider sampling circuit electrically connected to the negative input terminal IN- of the first comparator circuit chip, and a first comparison signal output circuit electrically connected to the output terminal OUT of the first comparator circuit chip. The first voltage divider sampling circuit is used to acquire the voltage division of the first power supply A; the second voltage divider sampling circuit is used to acquire the voltage division of the reference power supply O; and the first comparison signal output circuit is electrically connected to one input terminal of the AND gate device 14.

[0065] For example, such as Figure 6 As shown, the first comparator circuit chip can be, but is not limited to, a chip U64 of model number MAX49140, whose threshold voltage VIN﹣ is equal to 0.627835V. The first voltage divider sampling circuit may include a first resistor R935 for grounding and a second resistor R930 for electrical connection to the first power supply A. Both the first resistor R935 and the second resistor R930 are electrically connected to the positive input terminal IN+ of the first comparator circuit chip. The second voltage divider sampling circuit may include a third resistor R936 for grounding and a fourth resistor R931 for electrical connection to the reference power supply O. Both the third resistor R936 and the fourth resistor R931 are electrically connected to the negative input terminal IN﹣ of the first comparator circuit chip. The first comparison signal output circuit includes a fifth resistor R934 electrically connected to the output terminal OUT of the first comparison circuit chip, a first capacitor C1608 for grounding, and a first diode D95; the negative terminal of the diode D95 is electrically connected to the fifth resistor R934 and the first capacitor C1608, and the positive terminal of the first diode D95 is electrically connected to one input terminal of the AND gate device 14.

[0066] Optionally, such as Figure 6As shown, the resistance value of the first resistor R935 can be 10K; the resistance value of the second resistor R930 can be 1K; the resistance value of the third resistor R936 can be 4.7K; the resistance value of the fourth resistor R931 can be 20K; the resistance value of the fifth resistor R934 can be 22K; the capacitance value of the first capacitor C1608 can be 0.1uF / NC; and the first diode D95 can be implemented as NSRRB751S40T1G.

[0067] Similarly, as Figure 6 As shown, the second comparator 12 may include a second comparator circuit chip, a third voltage divider sampling circuit electrically connected to the positive input terminal IN+ of the second comparator circuit chip, a fourth voltage divider sampling circuit electrically connected to the negative input terminal IN- of the second comparator circuit chip, and a second comparison signal output circuit electrically connected to the output terminal OUT of the second comparator circuit chip. The third voltage divider sampling circuit is used to acquire the voltage division of the third power supply C; the fourth voltage divider sampling circuit is used to acquire the voltage division of the reference power supply O; and the second comparison signal output circuit is electrically connected to one input terminal of the OR gate device 13.

[0068] Optionally, such as Figure 6 As shown, the second comparator circuit chip can be, but is not limited to, a chip U88 of model number MAX49140, with a threshold voltage VIN﹣ equal to 0.61875V. The third voltage divider sampling circuit can include a sixth resistor R2483 for grounding and a seventh resistor R2480 for electrical connection to the third power supply C. Both the sixth and seventh resistors R2483 and R2480 are electrically connected to the positive input terminal IN+ of the second comparator circuit chip. The fourth voltage divider sampling circuit can include an eighth resistor R2484 for grounding and a ninth resistor R2481 for electrical connection to the reference power supply O. Both the eighth and ninth resistors R2484 and R2481 are electrically connected to the negative input terminal IN﹣ of the second comparator circuit chip. The second comparison signal output circuit includes a tenth resistor R2482 electrically connected to the output terminal OUT of the second comparison circuit chip and a second capacitor C8398 for grounding; both the tenth resistor R2482 and the second capacitor C8398 are electrically connected to one input terminal of the OR gate device 13.

[0069] For example, such as Figure 6 As shown, the resistance value of the sixth resistor R2483 can be 10K; the resistance value of the seventh resistor R2480 can be 1K; the resistance value of the eighth resistor R2484 can be 3K; the resistance value of the ninth resistor R2481 can be 13K; the resistance value of the tenth resistor R2482 can be 22K; and the capacitance value of the second capacitor C8398 can be 0.1uF / NC.

[0070] It is understood that the ground terminal GND in the first comparator circuit chip and the second comparator circuit chip of this application are both used for grounding, and the power supply terminal VDD in the first comparator circuit chip and the second comparator circuit chip are both used for electrical connection to the reference power supply O to obtain the reference voltage.

[0071] Optionally, such as Figure 6 As shown, the OR gate device 13 may include an OR gate circuit chip U87 and a second diode D97. One input terminal of the OR gate circuit chip U87 is electrically connected to the tenth resistor R2482 and the second capacitor C8398, and the other input terminal of the OR gate circuit chip U87 is electrically connected to the output terminal of the SOC module 4. The negative terminal of the second diode D97 is electrically connected to the output terminal of the OR gate circuit chip U87, and the positive terminal of the second diode D97 is electrically connected to the other input terminal of the AND gate device 14.

[0072] For example, such as Figure 6 As shown, the OR gate chip U87 mentioned in this application can be, but is not limited to, a chip U87 with the model number 74AUP1G32GM-Q100, and the power supply terminal of the OR gate chip U87 is used to be electrically connected to the reference power supply O. The second diode D97 can be implemented as NSRRB751S40T1G.

[0073] It is worth noting that, such as Figure 6 As shown, the AND gate device 14 may include, but is not limited to, the AND gate circuit chip U91 with model number 74LVC1G08-Q100, as long as it can achieve the required AND gate function, which will not be described in detail in this application.

[0074] It is worth mentioning that, according to another aspect of this application, this application may further provide an electronic device (not shown in the figure), which may include the power timing control circuit within the above-mentioned module.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A power supply timing control method within a module, characterized in that, Including the following steps: Power-on phase: When the level of the first control signal output by the external chip is pulled high, the first power chip is controlled to start outputting the first power supply and the third power supply to the SOC module in sequence, and pulls the level of the third control signal output through the SOC module high. The voltage of the first power supply is collected and compared with the voltage of the reference power supply output by the third power chip to determine whether the voltage of the first power supply is greater than the voltage of the reference power supply. as well as In response to the voltage division of the first power supply being greater than that of the reference power supply, the level of the second control signal is pulled high to control the second power chip to start outputting the second power supply to the SOC module; Power-off phase: When the level of the first control signal output by the external chip is pulled low, the first power chip is controlled to stop outputting the third power supply and the first power supply in turn, and the level of the third control signal output by the SOC module is pulled low. The voltage drop of the third power supply is collected and compared with the voltage drop of the reference power supply to determine whether the voltage drop of the third power supply is less than the voltage drop of the reference power supply. as well as In response to the voltage division of the third power supply being less than that of the reference power supply, the level of the second control signal is pulled low to control the second power chip to stop outputting the second power supply. The first power chip sets the power-on time difference and power-off time difference between the first power supply and the third power supply according to the OTP, wherein the power-on time difference between the first power supply and the third power supply is greater than the power-on time difference between the first power supply and the second power supply, and the power-off time difference between the third power supply and the first power supply is greater than the power-off time difference between the second power supply and the first power supply.

2. The power supply timing control method within a module according to claim 1, characterized in that, It also includes the following steps: When the external chip issues a SOC power-on instruction, before raising the level of the first control signal, it first raises the level of the fourth control signal to control the third power chip to start outputting the reference power to the SOC module, so that some modules in the SOC module start working. and When the external chip issues a SOC power-down instruction, it first pulls down the level of the first control signal, and then pulls down the level of the fourth control signal, so as to control the third power chip to stop outputting the reference power after the first power chip stops outputting the first power supply.

3. A power supply timing control circuit within the module, used to control the timing of the first power chip, the second power chip, and the third power chip supplying power to the SOC module, characterized in that, The power supply timing control circuit within the module is used to implement the power supply timing control method within the module as described in claim 1 or 2, including: The first comparator has two input terminals that are electrically connected to the first power supply output by the first power chip and the reference power supply output by the third power chip, respectively, to compare the magnitude of the voltage division of the first power supply and the voltage division of the reference power supply. The second comparator has two input terminals that are electrically connected to the third power supply output by the first power chip and the reference power supply output by the third power chip, respectively, to compare the magnitude of the voltage division of the third power supply and the voltage division of the reference power supply. An OR gate device, one input of which is electrically connected to the output of the second comparator, and the other input of which is electrically connected to the output of the SOC module to receive a third control signal from the SOC module, for outputting a signal according to the principle of high-to-high; and An AND gate device, one input of which is electrically connected to the output of an OR gate device, and the other input of which is electrically connected to the output of the first comparator. The output of the AND gate device is used to be electrically connected to the second power supply chip, and is used to output a second control signal to the second power supply chip according to the principle of all high to high.

4. The power supply timing control circuit within the module according to claim 3, characterized in that, The first comparator includes a first comparator circuit chip, a first voltage divider sampling circuit electrically connected to the positive input terminal of the first comparator circuit chip, a second voltage divider sampling circuit electrically connected to the negative input terminal of the first comparator circuit chip, and a first comparison signal output circuit electrically connected to the output terminal of the first comparator circuit chip; the first voltage divider sampling circuit is used to acquire the voltage division of the first power supply; the second voltage divider sampling circuit is used to acquire the voltage division of the reference power supply; and the first comparison signal output circuit is electrically connected to one input terminal of the AND gate device.

5. The power supply timing control circuit within the module according to claim 4, characterized in that, The first voltage divider sampling circuit includes a first resistor for grounding and a second resistor for electrical connection to the first power supply. Both the first and second resistors are electrically connected to the positive input terminal of the first comparator circuit chip. The second voltage divider sampling circuit includes a third resistor for grounding and a fourth resistor for electrical connection to the reference power supply. Both the third and fourth resistors are electrically connected to the negative input terminal of the first comparator circuit chip. The first comparison signal output circuit includes a fifth resistor electrically connected to the output terminal of the first comparator circuit chip, a first capacitor for grounding, and a first diode. The negative terminal of the first diode is electrically connected to the fifth resistor and the first capacitor, and the positive terminal of the first diode is electrically connected to one input terminal of the AND gate device.

6. The power supply timing control circuit within the module according to claim 3, characterized in that, The second comparator includes a second comparator circuit chip, a third voltage divider sampling circuit electrically connected to the positive input terminal of the second comparator circuit chip, a fourth voltage divider sampling circuit electrically connected to the negative input terminal of the second comparator circuit chip, and a second comparison signal output circuit electrically connected to the output terminal of the second comparator circuit chip; the third voltage divider sampling circuit is used to acquire the voltage division of the third power supply; the fourth voltage divider sampling circuit is used to acquire the voltage division of the reference power supply; the second comparison signal output circuit is electrically connected to one input terminal of the OR gate device.

7. The power supply timing control circuit within the module according to claim 6, characterized in that, The third voltage divider sampling circuit includes a sixth resistor for grounding and a seventh resistor for electrical connection to the third power supply. Both the sixth and seventh resistors are electrically connected to the positive input terminal of the second comparator circuit chip. The fourth voltage divider sampling circuit includes an eighth resistor for grounding and a ninth resistor for electrical connection to the reference power supply. Both the eighth and ninth resistors are electrically connected to the negative input terminal of the second comparator circuit chip. The second comparator signal output circuit includes a tenth resistor electrically connected to the output terminal of the second comparator circuit chip and a second capacitor for grounding. Both the tenth resistor and the second capacitor are electrically connected to one input terminal of the OR gate device.

8. The power supply timing control circuit within the module according to claim 7, characterized in that, The OR gate device includes an OR gate circuit chip and a second diode. One input terminal of the OR gate circuit chip is electrically connected to the tenth resistor and the second capacitor, and the other input terminal of the OR gate circuit chip is electrically connected to the output terminal of the SOC module. The negative terminal of the second diode is electrically connected to the output terminal of the OR gate circuit chip, and the positive terminal of the second diode is electrically connected to the other input terminal of the AND gate device.

9. An electronic device, characterized in that, The electronic device includes an in-module power timing control circuit as described in any one of claims 3 to 8.

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