Sampling control method and AD sampling chip

Abstract

This invention provides a sampling control method and an AD sampling chip, relating to the field of AD sampling technology. The sampling control method includes: acquiring sampled values ​​of a target sampling channel at a preset sampling interval under different sampling states; wherein the target sampling channel is the next sampling channel after sequential sampling among all sampling channels; determining whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling states; and optimizing the sampling channel if necessary. The method provided by this application avoids the influence of the previous sampling channel on the subsequent sampling channel during sequential scanning, thereby ensuring the sampling accuracy of each sampling channel, and has adaptability and wide applicability.

Description

Technical Field

[0001] This invention relates to the field of AD sampling technology, and more specifically, to a sampling control method and an AD sampling chip. Background Technology

[0002] In existing technologies, when a central processing unit (CPU) performs AD sampling, it often uses a sequential scanning method, that is, switching sampling channels one by one. However, during the switching process of sampling channels, such as switching from the first sampling channel to the next sampling channel, the internal capacitors of the CPU MCU will undergo a charging and discharging process, which will cause the subsequent sampling channel to be affected by the previous sampling channel, thus affecting the sampling accuracy. Summary of the Invention

[0003] The objectives of this invention include, for example, providing a sampling control method and an AD sampling chip that can prevent the subsequent sampling channel from being affected by the previous sampling channel during sequential scanning, thereby ensuring the sampling accuracy of each sampling channel and having adaptability and wide applicability.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, embodiments of this application provide a sampling control method applied to an AD sampling chip, the AD sampling chip including at least two sampling channels, the sampling control method comprising:

[0006] Under different sampling states, the sampled values ​​of the target sampling channel are obtained at a preset sampling interval; wherein, the target sampling channel is the next sampling channel after each sampling channel is sampled sequentially.

[0007] Whether sampling optimization is needed is determined based on the sampled values ​​of the target sampling channel under different sampling conditions;

[0008] If necessary, the sampling channel can be optimized.

[0009] In one feasible embodiment, the step of optimizing the sampling channel includes:

[0010] Increase the sampling interval of the sampling channel;

[0011] Determine if the current sampling interval is less than the maximum sampling interval;

[0012] If it is less than, then the current sampling interval is used as the preset sampling interval, and the process returns to the step of obtaining the sampling value of the target sampling channel at the preset sampling interval under different sampling states.

[0013] In one feasible embodiment, the step of determining whether the current sampling interval is less than the maximum sampling interval further includes:

[0014] If the value is greater than the maximum sampling interval, the maximum sampling interval is used as the preset sampling interval, the sampling number of each sampling channel is increased, and the current sampling number is used to return to the step of obtaining the sampling value of the target sampling channel at the preset sampling interval under different sampling states.

[0015] In one feasible embodiment, the step of returning to the step of obtaining the sampled values ​​of the target sampling channel at a preset sampling interval under different sampling states with the current sampling count includes:

[0016] Under different sampling states, each sampling channel is sampled according to the current sampling number, and each sampling channel is sampled sequentially according to a preset sampling interval. The next sampling channel after sequential sampling between each sampling channel is taken as the target sampling channel, and the last sampling value in the target sampling channel is taken as the sampling value of the target sampling channel.

[0017] In one feasible embodiment, the step of acquiring the sampled value of the target sampling channel at a preset sampling period under different sampling states includes:

[0018] In the first sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the first sampling state, the first channel has the greatest impact on the second channel.

[0019] In the second sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the second sampling state, the first channel has the least impact on the second channel.

[0020] In one feasible embodiment, the step of determining whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling states includes:

[0021] Based on the sampled values ​​of the target sampling channel in the first sampling state and the sampled values ​​of the target sampling channel in the second sampling state, the sampling difference of the target sampling channel is calculated, and the sampling difference is used to determine whether sampling optimization is needed.

[0022] In one feasible embodiment, the AD sampling chip further includes a potential output terminal connected to the first channel, and the step of sequentially sampling the first channel and the second channel at a preset sampling interval in the first sampling state includes:

[0023] The first channel and the second channel sample sequentially at a preset sampling interval when the potential output terminal outputs a high level.

[0024] In one feasible embodiment, the AD sampling chip further includes a potential output terminal connected to the first channel, and the step of sampling the first channel and the second channel sequentially at a preset sampling interval in the second sampling state includes:

[0025] The first channel and the second channel sample sequentially at a preset sampling interval when the potential output terminal outputs a low level.

[0026] This application also provides an AD sampling chip, which is used to perform the sampling control method described in any of the first aspects above.

[0027] In one feasible embodiment, the AD sampling chip includes:

[0028] At least two sampling channels, wherein the sampling channels include at least one target sampling channel;

[0029] At least one level output terminal, wherein the level output port is connected to a sampling channel other than the target sampling channel;

[0030] The AD sampling chip adjusts the sampling state of the sampling channel by adjusting the level output state of the level output terminal.

[0031] The beneficial effects of the embodiments of the present invention include, for example:

[0032] A sampling control method and an AD sampling chip are provided. The sampling control method includes: acquiring the sampled values ​​of a target sampling channel at a preset sampling interval under different sampling states; wherein the target sampling channel is the next sampling channel after sequential sampling among all sampling channels; determining whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling states; and optimizing the sampling channel if necessary. This application can avoid the influence of the previous sampling channel on the subsequent sampling channel during sequential scanning, thereby ensuring the sampling accuracy of each sampling channel, and has adaptability and wide applicability. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram illustrating the steps of a sampling control method provided in an embodiment of this application.

[0035] Figure 2 This is a schematic diagram of step S1 in an embodiment of this application.

[0036] Figure 3 This is a schematic diagram of the structure of an AD sampling chip provided in an embodiment of this application.

[0037] Figure 4 This is one of the schematic diagrams of step S3 in the embodiments of this application.

[0038] Figure 5 This is the second schematic diagram of step S3 in the embodiments of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0042] In the description of this invention, it should be noted that the terms "first" and "second" are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0043] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0044] As described in the background section, when a central processing unit (MCU) performs AD sampling, a sequential scanning method is often used. This means that after the first channel is scanned, the process switches to the next sampling channel sequentially to perform the sampling operation. However, since capacitors are typically used in AD sampling, the inventors further discovered that the capacitors often charge and discharge during channel switching. This causes the AD sampling value of the subsequent sampling channel to be affected by the charging and discharging of the capacitor, thus impacting the sampling accuracy of that channel. For example, if the interval between switching from the first channel to the second channel is too short, the internal capacitor of the MCU may still be in the charging and discharging process, affecting the input voltage of that channel. Consequently, the AD sampling accuracy of the subsequent sampling channel is affected during the switching process.

[0045] Based on this, embodiments of this application provide a sampling control method and an AD sampling chip, which can quantify the impact of the subsequent sampling channel under different sampling states, and then determine whether to perform sampling adjustment based on the quantified impact. If the impact is too large, the impact can be optimized through sampling adjustment, or the impact can be reduced to a reasonable error range, thereby avoiding the subsequent sampling channel being affected by the previous sampling channel during sequential scanning, thus ensuring the sampling accuracy of each sampling channel, and having adaptability and wide applicability.

[0046] Please refer to Figure 1 In a first aspect, embodiments of this application provide a sampling control method applied to an AD sampling chip, the AD sampling chip including at least two sampling channels, the sampling control method including:

[0047] S1. Under different sampling states, obtain the sampled value of the target sampling channel at a preset sampling interval; wherein, the target sampling channel is the next sampling channel after sequential sampling among all sampling channels;

[0048] S2. Determine whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling conditions;

[0049] S3. If necessary, optimize the sampling channel.

[0050] In this embodiment, different sampling states can be set to quantify the sampling impact of a subsequent channel switching in sequential sampling mode. The subsequent sampling channel can be understood as follows: when there are two scanning channels, such as a first sampling channel and a second sampling channel, and the first sampling channel performs sampling first and the second sampling channel performs sampling later in sequential sampling mode, then in this embodiment, the second sampling channel is used as the target sampling channel to quantify the impact of the first channel switching on the subsequent sampling channel through different sampling conditions. In another feasible embodiment, for example, when there are multiple channels, adjacent sampling channels in the sequential sampling mode are used as the first and second sampling channels. Therefore, this embodiment does not limit the selection or number of sampling channels; it only requires that in sequential sampling mode, the subsequent sampling channel is used as the target sampling channel for two adjacent sampling channels that need to be sampled.

[0051] Furthermore, in the embodiments of this application, the different sampling states are adjustments made to quantify the influence of the next sampling channel. That is to say, it is based on the maximum and minimum influence of the previous channel on the next channel, and the error is judged based on the maximum and minimum influence.

[0052] In one feasible embodiment, please refer to Figure 2 Step S1, which involves acquiring the sampled values ​​of the target sampling channel at a preset sampling period under different sampling states, includes:

[0053] S11. In the first sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the first sampling state, the first channel has the greatest influence on the second channel.

[0054] S12. In the second sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the second sampling state, the first channel has the least influence on the second channel.

[0055] In the embodiments of this application, the first sampling state and the second sampling state can be used to quantize the situation of the next channel in the scenarios of the previous channel being at the maximum AD sampling value and the minimum AD sampling value, respectively.

[0056] In one feasible embodiment, the AD sampling chip further includes a potential output terminal connected to the first channel. In the first sampling state, the step of sequentially sampling the first channel and the second channel at a preset sampling interval includes:

[0057] When the first and second channels output a high level at the potential output terminal, they are sampled sequentially at a preset sampling interval.

[0058] In this embodiment, please refer to Figure 3 After the AD sampling chip is powered on, one port P3 on the AD sampling chip can be set as a potential output terminal, and the pin of this potential output terminal can be connected to either of the two sampling channels on the AD sampling chip, such as port P1 or port P2 in the figure. When ports P1 and P2 are performing the acquisition task in a sequential scanning manner, the potential output terminal can be connected to port P1. Furthermore, ports P1 and P2 are connected to the first sampling channel Vin1 and the second sampling channel Vin2 respectively through the first resistor R1 and the second resistor R2.

[0059] When the potential output terminal outputs a high level, the potential of the sampling terminal P1 is pulled high due to the high level output of the potential output terminal. As a result, the AD value sampled by the sampling terminal P1 is at its maximum value under the high level output state. Furthermore, due to the presence of the capacitor inside the chip, the charging and discharging of the capacitor has the greatest impact on the subsequent sampling channel when switching channels under the high level state.

[0060] In one feasible embodiment, the AD sampling chip further includes a potential output terminal connected to the first channel. In the second sampling state, the step of sequentially sampling the first channel and the second channel at a preset sampling interval includes:

[0061] When the first and second channels output a low level at the potential output terminal, they are sampled sequentially at a preset sampling interval.

[0062] When the potential output terminal outputs a low level, the potential of the sampling terminal P1 is pulled low due to the low level output of the potential output terminal. As a result, the AD value sampled by the sampling terminal P1 is at its minimum under the low level output state. Furthermore, due to the presence of the capacitor inside the chip, the charging and discharging of the capacitor has the least impact on the subsequent sampling channel when switching channels under the high level state.

[0063] In summary, the sampled values ​​of the target sampling channel can be obtained in the two states mentioned above. The high-level state has the greatest impact, or leads to the largest error in the AD sampling value, while the low-level state has the least impact, or leads to the smallest error in the AD sampling value. The impact of the quantized AD sampling of the target sampling channel can be obtained through the two sampling states mentioned above.

[0064] In one feasible embodiment, the step of determining whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling states includes:

[0065] Based on the sampled values ​​of the target sampling channel in the first sampling state and the sampled values ​​of the target sampling channel in the second sampling state, the sampling difference of the target sampling channel is calculated, and the sampling difference is used to determine whether sampling optimization is needed.

[0066] In this embodiment, when the potential output terminal P3 outputs a high level, the first sampling channel Vin1 and the second sampling channel Vin2 are sequentially scanned, and the AD sampling values ​​of the first sampling channel Vin1 and the second sampling channel Vin2 are recorded respectively, denoted as AD_Vin1P and AD_Vin2P; when the potential output terminal P3 outputs a low level, the first sampling channel Vin1 and the second sampling channel Vin2 are sequentially scanned, and the AD sampling values ​​of the first sampling channel Vin1 and the second sampling channel Vin2 are recorded respectively, denoted as AD_Vin1N and AD_Vin2N.

[0067] Using the second access point in the sequential sampling as the target sampling channel, the sampling difference of the target sampling channel under different sampling states can be used. This sampling difference is expressed as |AD_Vin2P-AD_Vin2N|. Then, based on this sampling difference and a preset sampling difference, it is determined whether sampling optimization is needed. If the sampling difference does not exceed the preset sampling difference, the current sampling can be maintained, and no sampling adjustment is performed on the sampling channel. If the sampling difference exceeds the preset sampling difference, sampling adjustment is required for the current sampling channel. In one feasible embodiment, the preset sampling difference can be 3, meaning that the allowable AD value can fluctuate within 3.

[0068] In one feasible embodiment, please refer to Figure 4 Step S3, which optimizes the sampling channel, includes:

[0069] S31. Increase the sampling interval of the sampling channel;

[0070] S32. Determine whether the current sampling interval is less than the maximum sampling interval;

[0071] S33. If it is less than, then use the current sampling interval as the preset sampling interval and return to the step of obtaining the sampling value of the target sampling channel with the preset sampling interval under different sampling states.

[0072] For further details, please refer to... Figure 5 In one feasible embodiment, the step of determining whether the current sampling interval is less than the maximum sampling interval further includes:

[0073] S34. If it is greater than the maximum sampling interval, the maximum sampling interval is used as the preset sampling interval, the sampling number of each sampling channel is increased, and the current sampling number is used to return to the step of obtaining the sampling value of the target sampling channel under different sampling states with the preset sampling interval.

[0074] In one feasible embodiment, step S34, which returns the step of obtaining the sampled values ​​of the target sampling channel at a preset sampling interval under different sampling states with the current sampling count, includes:

[0075] Under different sampling states, each sampling channel is sampled according to the current sampling number, and each sampling channel is sampled sequentially according to the preset sampling interval. The next sampling channel after sequential sampling between each sampling channel is taken as the target sampling channel, and the last sampled value in the target sampling channel is taken as the sampled value of the target sampling channel.

[0076] In the embodiments of this application, it is understood that when the potential output terminal P3 outputs a high level, the first sampling channel Vin1 and the second sampling channel Vin2 are scanned sequentially, and the AD sampling values ​​of the first sampling channel Vin1 and the second sampling channel Vin2 are recorded respectively. However, when sampling each sampling channel, sampling must be performed according to the currently set number of samplings. For example, if the current number of samplings is 2, then two consecutive samplings are performed in the first sampling channel Vin1 and the second sampling channel Vin2 respectively. However, the second sampling channel Vin2 is still used as the target sampling channel. The difference between the two sampling values ​​is obtained by taking the difference between the second sampling value in the target sampling channel under the high level and the second sampling value in the target sampling channel under the low level as the sampling value of the target sampling channel.

[0077] In this feasible embodiment, before returning to the step of obtaining the sampled value of the target sampling channel at a preset sampling interval under different sampling states in step S34 with the current sampling count, it is also necessary to determine whether the sampling count meets the maximum sampling count. In one feasible embodiment, the maximum sampling count can be 3. If it is less than 3, the next sampling channel is sampled sequentially between each sampling channel as the target sampling channel, and the last sampled value in the target sampling channel is used as the sampled value of the target sampling channel. If it is greater than 3, the loop is exited and an AD sampling abnormality prompt is output.

[0078] This application also provides an AD sampling chip, which is used to execute a sampling control method including any of the first aspects described above.

[0079] The AD sampling chip provided in this application includes all the technical means and effects described in the first aspect above. It can quantify the impact of subsequent sampling channels under different sampling states, and then determine whether to adjust the sampling based on the quantified impact. If the impact is too large, it can be optimized through sampling adjustment, or reduced to a reasonable error range. This avoids the subsequent sampling channel being affected by the previous sampling channel during sequential scanning, thus ensuring the sampling accuracy of each sampling channel and possessing adaptability and versatility. Although the sampling circuits inside different chips may differ, this method is universal, unaffected by the chip, and automatically adjusts and optimizes.

[0080] In one feasible embodiment, the AD sampling chip includes:

[0081] At least two sampling channels, and each sampling channel includes at least one target sampling channel;

[0082] At least one level output terminal is provided, which is connected to a sampling channel other than the target sampling channel.

[0083] The AD sampling chip adjusts the sampling state of the sampling channel by adjusting the level output state of the level output port.

[0084] This invention provides a sampling control method and an AD sampling chip. The sampling control method includes: acquiring the sampling value of a target sampling channel at a preset sampling interval under different sampling states; wherein the target sampling channel is the next sampling channel after sequential sampling among all sampling channels; determining whether sampling optimization is needed based on the sampling value of the target sampling channel under different sampling states; and optimizing the sampling channel if necessary. In this application, the impact of the next sampling channel under different sampling states can be quantified, and the quantified impact can be used to determine whether sampling adjustment is needed. If the impact is too large, it can be optimized through sampling adjustment, or reduced to a reasonable error range. This avoids the impact of the previous sampling channel on the next sampling channel during sequential scanning, thus ensuring the sampling accuracy of each sampling channel. It also has adaptability and wide applicability.

[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A sampling control method applied to an AD sampling chip, the AD sampling chip comprising at least two sampling channels, characterized in that, The sampling control method includes: Under different sampling states, the sampled values ​​of the target sampling channel are obtained at a preset sampling interval; wherein, the target sampling channel is the next sampling channel after each sampling channel is sampled sequentially. Whether sampling optimization is needed is determined based on the sampled values ​​of the target sampling channel under different sampling conditions; If necessary, the sampling channel can be optimized; The steps for optimizing the sampling channel include: Increase the sampling interval of the sampling channel; Determine if the current sampling interval is less than the maximum sampling interval; If it is less than, then the current sampling interval is used as the preset sampling interval, and the process returns to the step of obtaining the sampled value of the target sampling channel at the preset sampling interval under different sampling states; The step of determining whether sampling optimization is needed based on the sampled values ​​of the target sampling channel under different sampling states includes: Based on the sampled values ​​of the target sampling channel in the first sampling state and the sampled values ​​of the target sampling channel in the second sampling state, the sampling difference of the target sampling channel is calculated, and it is determined whether sampling optimization is needed based on the sampling difference. The step of determining whether the current sampling interval is less than the maximum sampling interval further includes: If the value is greater than the maximum sampling interval, the maximum sampling interval is used as the preset sampling interval, the sampling count of each sampling channel is increased, and the current sampling count is used to return to the step of obtaining the sampling value of the target sampling channel at the preset sampling interval under different sampling states.

2. The sampling control method according to claim 1, characterized in that, The step of returning the sampled value of the target sampling channel at a preset sampling interval under different sampling states, based on the current sampling count, includes: Under different sampling states, each sampling channel is sampled according to the current sampling number, and each sampling channel is sampled sequentially according to a preset sampling interval. The next sampling channel after sequential sampling between each sampling channel is taken as the target sampling channel, and the last sampling value in the target sampling channel is taken as the sampling value of the target sampling channel.

3. The sampling control method according to claim 1, characterized in that, The step of acquiring the sampled values ​​of the target sampling channel at a preset sampling interval under different sampling states includes: In the first sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the first sampling state, the first channel has the greatest impact on the second channel. In the second sampling state, the first channel and the second channel are sampled sequentially at a preset sampling interval. In the second sampling state, the first channel has the least influence on the second channel.

4. The sampling control method according to claim 3, characterized in that, The AD sampling chip further includes a potential output terminal, which is connected to the first channel. The step of sequentially sampling the first channel and the second channel at a preset sampling interval in the first sampling state includes: The first channel and the second channel sample sequentially at a preset sampling interval when the potential output terminal outputs a high level.

5. The sampling control method according to claim 3, characterized in that, The AD sampling chip further includes a potential output terminal, which is connected to the first channel. The step of sequentially sampling the first channel and the second channel at a preset sampling interval in the second sampling state includes: The first channel and the second channel sample sequentially at a preset sampling interval when the potential output terminal outputs a low level.

6. An AD sampling chip, characterized in that, The AD sampling chip is used to execute the sampling control method according to any one of claims 1 to 5.

7. The AD sampling chip according to claim 6, characterized in that, The AD sampling chip includes: At least two sampling channels, wherein the sampling channels include at least one target sampling channel; At least one level output terminal, said level output terminal being connected to a sampling channel other than the target sampling channel; The AD sampling chip adjusts the sampling state of the sampling channel by adjusting the level output state of the level output terminal.

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